SYSTEMS AND METHODS FOR CODE GENERATION FOR A PLURALITY OF ARCHITECTURES
| Registre | Brevet USPTO |
|---|---|
| Numéro d'application | 17950773 |
| Statut | En instance |
| Date de dépôt | 2022-09-22 |
| Date de la première publication | 2023-01-19 |
| Date de publication | 2023-01-19 |
| Propriétaire | Intel Corporation (USA) |
| Inventeur(s) |
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Abrégé
Systems and methods for code generation for a plurality of architectures. At a host architecture, a JIT compile operation is performed for a received JavaScript or Web Assembly file. The JIT compiler references a host library that has been updated to include at least one new JIT instruction. Output from the JIT compile operation is compiled machine code for the host architecture that has new opcodes (OPX) added, responsive to the new JIT instruction. The JIT compiler executes the opcodes (OPX) in XuCode mode, meaning that the host architecture switches into a hardware protected private ISA (Instruction Set Architecture) called XuCode to implement the new JIT opcode instruction in XuCode.