ARCHITECTURAL INTERFACES FOR GUEST SOFTWARE TO SUBMIT COMMANDS TO AN ADDRESS TRANSLATION CACHE IN XPUs

Abrégé

In one embodiment, an apparatus includes a processor comprising an address translation cache (ATC); a shared work queue (SWQ) associated with the ATC, and a port to couple to a host processor over a Peripheral Component Interconnect Express (PCIe)-based link. The apparatus also includes circuitry to receive address translation information from a memory management unit of the host processor that includes virtual memory address to physical memory address translations, store the address translation information in the ATC, receive an invalidation command from the host processor indicating an invalidation of address translation information stored in the ATC, modify the address translation information in the ATC based on the invalidation command, and store completion data in a memory location indicated by the invalidation command.

Classes IPC  ?

• G06F 12/1081 - Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
• G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means