Registre Brevet USPTO
Numéro d'application 17952080
Statut En instance
Date de dépôt 2022-09-23
Date de la première publication 2023-01-19
Date de publication 2023-01-19
Propriétaire Intel Corporation (USA)
  • Darmawaikarta, Kristof
  • May, Robert
  • Kandanur, Sashi
  • Boyapati, Sri Ranga Sai
  • Pietambaram, Srinivas
  • Cho, Steve
  • Han, Jung Kyu
  • Heaton, Thomas
  • Lehaf, Ali
  • Eluri, Ravindranadh
  • Tanaka, Hiroki
  • Aleksov, Aleksandar
  • Seneviratne, Dilan


Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

Classes IPC  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device