High Performance Systems And Methods For Modular Multiplication

Registre Brevet USPTO
Numéro d'application 17952085
Statut En instance
Date de dépôt 2022-09-23
Date de la première publication 2023-01-26
Date de publication 2023-01-26
Propriétaire Intel Corporation (USA)
  • Gribok, Sergey
  • Pasca, Bogdan
  • Langhammer, Martin


A circuit system for performing modular reduction of a modular multiplication includes multiplier circuits that receive a first subset of coefficients that are generated by summing partial products of a multiplication operation that is part of the modular multiplication. The multiplier circuits multiply the coefficients in the first subset by constants that equal remainders of divisions to generate products. Adder circuits add a second subset of the coefficients and segments of bits of the products that are aligned with respective ones of the second subset of the coefficients to generate sums.

Classes IPC  ?

  • G06F 7/72 - Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations using residue arithmetic
  • G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
  • G06F 7/523 - Multiplying only
  • G06F 7/50 - Adding; Subtracting
  • G06F 1/03 - Digital function generators working, at least partly, by table look-up