Retiming and Overclocking of Large Circuits

Registre Brevet USPTO
Numéro d'application 17956565
Statut En instance
Date de dépôt 2022-09-29
Date de la première publication 2023-01-19
Date de publication 2023-01-19
Propriétaire Intel Corporation (USA)
  • Langhammer, Martin
  • Baeckler, Gregg William
  • Gribok, Sergey Vladimirovich
  • Iyer, Mahesh A.


The present disclosure describes techniques for incorporating pipelined DSP blocks or other types of embedded functions into a logic circuit with a slower clock rate without any clock crossing complexities, and at the same time managing the power consumption of the more complex design that results from it. The techniques include generating a faster clock or several faster clocks that may have a faster clock rate than the clock used by the logic circuit and that may be used as clock input to the embedded pipelined DSP blocks. In addition, the present disclosure describes techniques for generating, improving, and using the faster clock to sample the output of a logic circuit using pulses of generated faster clock, which may allow to increase the clock frequency of the circuit to an optimal level, while maintaining functional correctness.

Classes IPC  ?

  • G06F 1/08 - Clock generators with changeable or programmable clock frequency
  • H03K 19/17736 - Structural details of routing resources