METHOD TO ENABLE 30 MICRONS PITCH EMIB OR BELOW
Registre | Brevet USPTO |
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Numéro d'application | 17956769 |
Statut | En instance |
Date de dépôt | 2022-09-29 |
Date de la première publication | 2023-01-26 |
Date de publication | 2023-01-26 |
Propriétaire | Intel Corporation (USA) |
Inventeur(s) |
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Abrégé
A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.Classes IPC ?
- H01L 23/498 - Leads on insulating substrates
- H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
- H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
- H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates