TRANSACTIONAL MEMORY SUPPORT FOR COMPUTE EXPRESS LINK (CXL) DEVICES

Abrégé

In one embodiment, an apparatus couples to a host processor over a Compute Express Link (CXL)-based link. The apparatus includes a transaction queue to queue memory transactions to be completed in an addressable memory coupled to the apparatus, a transaction cache, conflict detection circuitry to determine whether a conflict exists between memory transactions, and transaction execution circuitry. The transaction execution circuitry may access a transaction from the transaction queue, the transaction to implement one or more memory operations in the memory, store data from the memory to be accessed by the transaction operations in the transaction cache, execute operations of the transaction, including modifying data from the memory location stored in the transaction cache, and based on completion of the transaction, cause the modified data from the transaction cache to be stored in the memory.

Classes IPC  ?

• G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
• G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
• G06F 9/46 - Multiprogramming arrangements