Management of microservices failover
| Registre | Brevet USPTO |
|---|---|
| Numéro d'application | 17560857 |
| Numéro de brevet | 11561868 |
| Statut | Délivré - en vigueur |
| Date de dépôt | 2021-12-23 |
| Date de la première publication | 2023-01-24 |
| Date de publication | 2023-01-24 |
| Date d'octroi | 2023-01-24 |
| Propriétaire | Intel Corporation (USA) |
| Inventeur(s) |
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Abrégé
Embodiments described herein are generally directed to intelligent management of microservices failover. In an example, responsive to an uncorrectable hardware error associated with a processing resource of a platform on which a task of a service is being performed by a primary microservice, a failover trigger is received by a failover service. A secondary microservice is identified by the failover service that is operating in lockstep mode with the primary microservice. The secondary microservice is caused by the failover service to takeover performance of the task in non-lockstep mode based on failover metadata persisted by the primary microservice. The primary microservice is caused by the failover service to be taken offline.Classes IPC ?
- G06F 11/00 - Error detection; Error correction; Monitoring
- G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements