Abrégé

A semiconductor structure and a method for forming same. The structure comprises: a substrate; a vertical stack structure, which comprises a channel region, and source and drain regions positioned at two sides of the channel region, wherein the channel region comprises a first stack region, an isolation region, and a second stack region, which are positioned on the substrate, the first stack region comprising several first channel layers, and the second stack region comprising several second channel layers; a first isolation layer, which is positioned in the isolation region; a gate structure, which is positioned on the substrate and surrounds the first channel layer and the second channel layer; first source-drain doped regions, which are positioned in the source and drain regions on the two sides of the first stack region; first contact layers, which are positioned on the surfaces of the first source-drain doped regions and are provided with first projections on the surface of the substrate; second source-drain doped regions, which are positioned on the first contact layers; second contact layers, which are positioned on the surfaces of the second source-drain doped regions and are provided with second projections on the surface of the substrate, wherein the areas of the first projections are greater than or equal to those of the second projections; second connection layers, which are positioned on two sides of the gate structure; and first connection layers, which are positioned in the second source-drain doped regions. By means of the structure, the performance of the semiconductor structure is improved.

Classes IPC  ?

• H01L 29/94 - Dispositifs à métal-isolant-semi-conducteur, p.ex. MOS
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS

Abrégé

A semiconductor structure and a method for forming same. The semiconductor structure comprises: a substrate; a surrounding gate transistor, which is located on the substrate, the surrounding gate transistor comprising protrusion portions which are separately located on the substrate, and a channel structure layer which is arranged spaced apart from the protrusion portions in a suspended manner, wherein the channel structure layer comprises a plurality of channel layers sequentially arranged at intervals, the channel layers are vertically stacked in a direction perpendicular to a surface of the substrate, and in the direction perpendicular to the surface of the substrate, the distance between a protrusion portion and a channel layer adjacent to the protrusion portion is greater than the distance between adjacent channel layers; and a gate structure, which comprises work function layers surrounding surfaces of the channel layers, wherein the work function layers are filled between a protrusion portion and a channel layer adjacent to the protrusion portion, and between adjacent channel layers. When an NMOS transistor is formed, the material of the work function layers is a P-type work function material; and when a PMOS transistor is formed, the material of the work function layers is an N-type work function material. The embodiments of the present invention favour reduction in device current leakage.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

A semiconductor structure and a method for forming same. The structure comprises: a substrate, which comprises at least one cell region, the cell region comprising a first region and a second region which are adjacent and arranged in a first direction, the first region comprising a first isolation region, the second region comprising a second isolation region, and the central axis of the first isolation region parallel to the first direction not coinciding with the central axis of the second isolation region; a first gate structure located on the first region, and a first metal layer and second metal layer respectively located at two sides of the first gate structure; a second gate structure located on the second region, and a third metal layer and fourth metal layer respectively located at two sides of the second gate structure, wherein the first gate structure, the first metal layer, the second metal layer, the second gate structure, the third metal layer, and the fourth metal layer are parallel to a second direction; a first isolation structure, which is located on the first isolation region and penetrates the first metal layer and the second metal layer in the first direction; and a second isolation structure, which is located on the second isolation region and penetrates the third metal layer and the fourth metal layer in the first direction.

Classes IPC  ?

• H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/762 - Régions diélectriques

Abrégé

A photoelectric sensor, a method for forming same, and an electronic device, the photoelectric sensor comprising: an isolation structure, which is located in a pixel substrate between photosensitive units, the isolation structure comprising a conductive layer; a plurality of interconnecting structures, which are distributed in the pixel substrate, and the end parts of which are exposed on a second surface, wherein the interconnecting structures comprise a first interconnecting structure located in a first lead region and a second interconnecting structure located in a second lead region, and the second interconnecting structure is electrically connected to the first interconnecting structure; a metal grid, which is located on the second surface and which is in contact with the conductive layer; a connection layer, which is located on a second surface of the first lead region and which is in contact with the metal grid and the first interconnecting structure; and a pad layer, which is located on the second surface of a lead region, the thickness of the pad layer being greater than the thicknesses of the connection layer and the metal grid. The pad layer comprises a first pad layer located in the second lead region, and is in contact with the end part of the second interconnecting structure facing the second surface. According to embodiments of the present invention, the performance of the photoelectric sensor is improved.

Classes IPC  ?

• H01L 27/146 - Structures de capteurs d'images
• H01L 31/0352 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails caractérisés par leurs corps semi-conducteurs caractérisés par leur forme ou par les formes, les dimensions relatives ou la disposition des régions semi-conductrices

Abrégé

A semiconductor structure and a forming method therefor. The forming method comprises: providing a substrate, wherein a first sacrificial layer is formed on the substrate, a channel structure is formed on the first sacrificial layer and comprises one or more stacked channel stacks, and each channel stack comprises a second sacrificial layer and a channel layer located on the second sacrificial layer, and a dummy gate structure crossing the channel structure is further formed on the substrate, wherein the etching resistance of the first sacrificial layer is less than that of the second sacrificial layer; removing the channel structure and the first sacrificial layer on both sides of the dummy gate structure to form a first trench penetrating through the channel structure and the first sacrificial layer; removing the first sacrificial layer at the bottom of the channel structure by means of the first trench, and forming a second trench communicated with the first trench at the bottom of the channel structure; forming an isolation layer in the second trench; and forming a source/drain doped layer in the first trench after the isolation layer is formed. The isolation layer effectively isolates the gate structure from the substrate, thereby reducing the probability of leakage current generated between the gate structure and the substrate.

Classes IPC  ?

• H01L 21/336 - Transistors à effet de champ à grille isolée
• H01L 29/786 - Transistors à couche mince
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS

Abrégé

A photoelectric sensor and a forming method thereof, and an electronic device, the photoelectric sensor comprising: a substrate, the substrate having a light receiving surface, the substrate comprising a photosensitive pixel region, and the photosensitive pixel region comprising a plurality of pixel unit regions distributed in a matrix; a plurality of light trapping grooves positioned in the substrate in part of the thickness of the pixel unit region and positioned on one side of the light receiving surface of the substrate, the plurality of light trapping grooves being distributed in a matrix along the row direction and the column direction; the row direction and the column direction being perpendicular, adjacent light trapping grooves in the row direction being in communication, adjacent light trapping grooves in the column direction being in communication, the side walls of the light trapping grooves enclosing a plurality of adjoining bosses, and the shape of the bosses being octagonal. In the pixel unit region, the eight side surfaces and the top surface of each boss may be used as the photosensitive surface of a photosensor, significantly increasing the photosensitive area of the photoelectric sensor, which is beneficial to improving the optical local area capability of the photoelectric sensor, thereby enhancing the photosensitive performance of the photoelectric sensor.

Classes IPC  ?

• H01L 27/146 - Structures de capteurs d'images
• H01L 31/00 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails
• H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
• H01L 31/18 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives

Abrégé

A semiconductor structure and a formation method therefor. The formation method comprises: providing a substrate, wherein gate structures are formed on the substrate, source-drain doped regions are formed in the substrate at two sides of each gate structure, and bottom dielectric layers which are located between adjacent gate structures are formed on the source-drain doped regions; forming, on the top face of each gate structure, a liner metal layer which is in contact with the gate structure, wherein the material of the liner metal layer is pure metal; forming a top dielectric layer on each bottom dielectric layer, wherein the top dielectric layer covers the liner metal layer; and forming, by using a first selective deposition process, a gate plug which penetrates through the top dielectric layer and is in contact with the liner metal layer. A liner metal layer can provide a good formation interface and a good deposition substrate for forming a gate plug by using a first selective deposition process, thereby facilitating the deposition and growth of the material of the gate plug on the liner metal layer, and thus reducing the difficulty of forming the gate plug by using the first selective deposition process, and improving the formation quality of the gate plug.

Classes IPC  ?

• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS

Abrégé

A semiconductor structure and a forming method therefor. The method comprises: forming an auxiliary layer on the surface of a covering layer by means of a first selective deposition process; forming a first medium layer on the surfaces of a substrate and the auxiliary layer; forming an electrically conductive structure in the first medium layer; forming a second medium layer on the surfaces of the first medium layer and the electrically conductive structure; forming a first opening and a second opening, with the first opening being located in the second medium layer and the first medium layer and being exposed from the auxiliary layer, and the second opening being located in the second medium layer and being exposed from the top surface of the electrically conductive structure; forming a first electrically conductive layer in the first opening; and forming a second electrically conductive layer in the second opening, wherein the growth rate of a material of the electrically conductive layer on the surface of the auxiliary layer is greater than that of the material of the electrically conductive layer on the surface of the covering layer, which improves the performance of the formed semiconductor structure.

Classes IPC  ?

• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

A semiconductor structure, a forming method therefor and a working method thereof. The semiconductor structure comprises: a substrate, comprising a first region that comprises a plurality of first active regions arranged in a first direction and first isolation regions located between adjacent first active regions; several first fin portions located on the substrate, the several first fin portions being arranged parallel to the first direction and in a second direction that is perpendicular to the first direction, and the first fin portions being arranged across the adjacent first active regions and the first isolation regions between the first active regions; a plurality of first gate structures located on the first isolation regions, the first gate structures being arranged across the first fin portions in the second direction; and several first electrical interconnection structures electrically connected to the first gate structures. By means of the present invention, electrical isolation between adjacent active regions is achieved in a semiconductor structure with high integration, which is conducive to improving the performance of the semiconductor structure.

Classes IPC  ?

• H01L 21/336 - Transistors à effet de champ à grille isolée
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus

Abrégé

A semiconductor structure and a forming method therefor, and a mask layout. The semiconductor structure comprises: a base comprising a substrate and a plurality of fins arranged on the substrate in parallel, wherein the substrate comprises a transistor cell region, and in the transistor cell region, in a direction perpendicular to the fin extension direction, the fin closest to the boundary of the transistor cell region is an edge fin, and the edge fin has an outer sidewall facing the boundary of the transistor cell region; and a gate structure that spans the fin and covers a part of the top portion and a part of the sidewall of the fin, the gate structure exposing at least a part of an outer sidewall of any edge fin. According to the present invention, the gate structure exposes at least a part of the outer sidewall of any edge fin, to reduce the area of the sidewall of the edge fin covered by the gate structure, such that the normal operation of the transistor can be ensured, and the effective channel width is reduced by adjusting the etching quantity of the gate structure on the outer sidewall, thereby improving the flexibility of adjusting the effective channel width of the transistor.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

A mask plate, an alignment mark and a photolithography system. The alignment mark comprises a plurality of alignment patterns arranged at intervals, wherein each alignment pattern comprises a first pattern extending in a first direction and a second pattern extending in a second direction. In the first direction, the first pattern comprises a first end and a second end, which are opposite each other; and in the second direction, the second pattern comprises a third end and a fourth end, which are opposite each other, wherein the second end is connected to the third end, and the fourth end is connected to the first end. The alignment patterns are two-dimensional linear patterns. Comparing the embodiments of the present invention and a case where the alignment mark is a one-dimensional linear pattern, during the process of performing alignment by using the alignment mark provided by the embodiments of the present invention, the alignment mark macroscopically constitutes moiré patterns which are arranged periodically, the moiré patterns enable an alignment system to obtain a greater first-order diffraction signal strength, and a corresponding alignment signal strength is greater, thereby improving the overlay (OVL) accuracy and reducing the rework rate and production costs.

Classes IPC  ?

• G03F 9/00 - Mise en registre ou positionnement d'originaux, de masques, de trames, de feuilles photographiques, de surfaces texturées, p.ex. automatique
• G03F 7/20 - Exposition; Appareillages à cet effet
• G03B 27/32 - Appareils de tirage par projection, p.ex. agrandisseur, appareil photographique de reproduction

Abrégé

A method for forming a semiconductor structure. The method comprises: providing a first substrate, wherein the first substrate comprises a first surface and a second surface which are opposite each other, the first substrate is internally provided with first ions, and the first ions have a first concentration; forming a first epitaxial layer on the first surface of the first substrate, wherein the first epitaxial layer is internally provided with second ions, the second ions have a second concentration, and the second concentration is less than the first concentration; forming a second epitaxial layer on the first epitaxial layer and forming a third epitaxial layer located on the second epitaxial layer, wherein the second epitaxial layer is internally provided with third ions, the third ions have a third concentration, the third epitaxial layer is internally provided with fourth ions, the fourth ions have a fourth concentration, and the fourth concentration is less than the third concentration; and performing thinning processing from the second surface of the first substrate on the first substrate, until the surface of the second epitaxial layer is exposed. By means of the present invention, the uniformity of thinning thickness is ensured, and requirements for manufacturing a substrate of a semiconductor structure can also be satisfied, thereby facilitating the improvement of the performance of the semiconductor structure.

Classes IPC  ?

• H01L 27/146 - Structures de capteurs d'images

Abrégé

A semiconductor structure and a formation method therefor. The formation method comprises: providing a substrate and a fin protruding from the substrate, wherein the fin comprises a plurality of groups of stacked structures which are stacked together, and each group of stacked structures comprises a sacrificial layer and a semiconductor layer located on the top portion of the sacrificial layer; forming a dummy gate across the fin, wherein the dummy gate covers part of the top portion and part of a sidewall of the fin; etching the fin on two sides of the dummy gate, so as to form a source/drain groove; etching a sacrificial layer of the fin that is exposed by the source/drain groove and is located at the bottom portion of the dummy gate, so as to form additional slots on two sides of the etched sacrificial layer in the extension direction of the fin, wherein the additional slot has an opening that faces the source/drain groove, and side walls on the two sides of the etched sacrificial layer in the extension direction of the fin form the bottom portion of the additional slot; forming an isolation layer on the bottom portion of the additional slot, wherein the additional slot is not fully filled with the isolation layer; and forming a source/drain doped layer, with which the source/drain groove is fully filled, wherein the source/drain doped layer and the isolation layer define a gap. The gap helps to reduce the parasitic capacitance between the source/drain doped layer and a metal gate.

Classes IPC  ?

• H01L 21/336 - Transistors à effet de champ à grille isolée
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

A semiconductor structure and a method for forming a semiconductor structure. The method comprises: providing a substrate, wherein the substrate is provided with a dielectric layer, the dielectric layer comprising a second area and a first area located on the second area, the first area is internally provided with several initial first nanowires that are separated from each other, and the second area is internally provided with several initial second nanowires that are separated from each other; etching the dielectric layer and the initial first nanowires of the first area, so as to form a first opening in the first area, and form first nanowires from the initial first nanowires; etching the dielectric layer and the initial second nanowires at the bottom of the first opening, so as to form a second opening in the second area, and form second nanowires from the initial second nanowires; forming a second source-drain layer in the second opening; forming an isolation layer on the surface of the second source-drain layer; and forming a first source-drain layer in the first opening. A semiconductor structure formed by means of the method has relatively good performance.

Classes IPC  ?

• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS

Abrégé

A semiconductor structure and a forming method therefor. The forming method comprises: providing a substrate comprising a target layer, wherein the substrate comprises a target region used for forming a target pattern layer, and a cutting region corresponding to a cutting position; forming a mask sidewall on the substrate; using the mask sidewall as a mask, and patterning the target layer to form discrete initial pattern layers, wherein the initial pattern layers extend along a transverse direction, a direction perpendicular to the transverse direction is a longitudinal direction, and a groove is formed between adjacent initial pattern layers along the longitudinal direction; forming a boundary defining groove passing through the initial pattern layer that is located at a junction position between the target region and the cutting region; forming spacer layers that are filled in the groove and the boundary defining groove; and enabling the spacer layer located in the boundary defining groove and the spacer layer located in the groove to respectively correspond to a transverse stop layer and a longitudinal stop layer, etching the initial pattern layer located in the cutting region, and using the remaining initial pattern layer located in the target region as the target pattern layer. The embodiments of the present invention facilitates the increasing of a process window for etching the initial pattern layer of the cutting region.

Classes IPC  ?

• H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques

Abrégé

A semiconductor structure and a forming method therefor. The forming method comprises: providing a substrate, a gate structure, source and drain doped regions in the substrate at two sides of the gate structure, and a bottom dielectric layer located on the substrate at the sides of the gate structure; forming a source/drain interconnect layer penetrating through the bottom dielectric layer at the top of the source and drain doped regions; forming a top dielectric layer on the bottom dielectric layer; forming a gate contact hole penetrating through the top dielectric layer at the top of the gate structure, and a source/drain contact hole penetrating through the top dielectric layer at the top of the source/drain interconnect layer; forming sacrificial sidewall layers on sidewalls of the gate contact hole and the source/drain contact hole; forming a gate plug filling the gate contact hole and a source/drain plug filling the source/drain contact hole; removing the sacrificial sidewall layers to form first gaps; and forming a sealing layer which seals the first gaps, and enabling the sealing layer and at least one of the first gap located on the sidewall of the source/drain plug and the first gap located on the sidewall of the gate plug to define a first air gap. Embodiments of the present invention reduce parasitic capacitance between a gate plug and a source/drain plug.

Classes IPC  ?

• H01L 21/336 - Transistors à effet de champ à grille isolée
• H01L 21/8234 - Technologie MIS
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 21/764 - Espaces d'air

Abrégé

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, forming a gate structure on the substrate, forming a fake sidewall on a sidewall of the gate structure, forming a contact hole etch stop layer on the fake sidewall, and forming a source-drain doped region in the substrate on the two sides of the gate structure; forming a sacrificial dielectric layer above the top of the source-drain doped region and the gate structure; forming source-drain plugs which penetrate the sacrificial dielectric layer above the top of the source-drain doped region and are in contact with the source-drain doped region; etching the sacrificial dielectric layer until the top of the fake sidewall is exposed; after the top of the fake sidewall is exposed, removing the fake sidewall and forming a gap between the contact hole etch stop layer and the sidewall of the gate structure; and forming a top dielectric layer which fills the space between the source-drain plugs and the gap, or seals the top of the gap, the dielectric constant of the top dielectric layer being smaller than the dielectric constant of the fake sidewall. According to the present disclosure, the effective capacitance between the gate structure and the source-drain plugs can be reduced.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/336 - Transistors à effet de champ à grille isolée