Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Chiu, Tzu-Yin
Lu, Juilin
Cai, Jianxiang
Abrégé
Various embodiments provide semiconductor structures and their fabrication methods. An SRAM memory cell can include at least one semiconductor structure, and an SRAM memory can include at least one SRAM memory cell. An exemplary semiconductor structure can include at least two adjacent transistors formed on a semiconductor substrate. An opening can be formed and surrounded by gates of the two adjacent transistors and a doped region formed between the gates of the two adjacent transistors. A conductive layer can be formed to at least partially cover a bottom and a sidewall of the opening to electrically connect a gate of one transistor with the doped region of the other transistor of the two adjacent transistors.
H01L 27/11 - Structures de mémoires statiques à accès aléatoire
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP. (Chine)
Inventeur(s)
He, Qiyang
Abrégé
A method is provided for fabricating small pitch patterns. The method includes providing a semiconductor substrate, and forming a target material layer having a first region and a second region on the semiconductor substrate. The method also includes forming a plurality of discrete first sacrificial layers on the first region of the target material layer and a plurality of discrete second sacrificial layers on the second region of the target material layer, and forming first sidewall spacers on both sides of the discrete first sacrificial layers and the discrete second sacrificial layers. Further, the method includes removing the first sacrificial layers and the second sacrificial layers, and forming second sidewall spacers. Further, the method also includes forming discrete repeating patterns in the first region of the target material layer and a continuous pattern in the second region of the target material layer.
H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP. (Chine)
Inventeur(s)
Chang, Jianguang
Abrégé
Various embodiments provide transistors and fabrication methods. An exemplary transistor can include a silicon nitride layer disposed between a gate dielectric layer and a gate electrode layer. The silicon nitride layer can have a first surface in contact with the gate dielectric layer and a second surface in contact with the gate electrode layer. The second surface can include silicon atoms having a concentration higher than the first surface. A sidewall spacer can be formed on the semiconductor substrate along sidewalls of each of the gate electrode layer, the silicon nitride layer, and the gate dielectric layer. The disclosed transistor can have a reduced turn-on voltage with reduced power consumption.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 29/51 - Matériaux isolants associés à ces électrodes
4.
Method for forming fin FET structure with dual-stress spacers
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP. (Chine)
Inventeur(s)
Bao, Wayne
Abrégé
This application discloses a Fin FET structure and a method for forming the same. In the Fin FET structure, there are lower stress spacers disposed over the lower portion of the fin's opposite sidewalls, asserting one stress type to suppress the carrier mobility; there are also upper stress spacers disposed over the upper portion of the fin's opposite sidewalls, asserting an opposite stress type to increase the carrier mobility. Therefore, the leakage current in the fin FET is reduced and the device performance is improved. In the method, the stress spacers are formed by depositing stress layers and etching back the stress layers, where stress types and magnitudes are controllable, resulting in a simple process.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/283 - Dépôt de matériaux conducteurs ou isolants pour les électrodes
H01L 21/31 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour former des couches isolantes en surface, p.ex. pour masquer ou en utilisant des techniques photolithographiques; Post-traitement de ces couches; Emploi de matériaux spécifiés pour ces couches
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 21/84 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant autre chose qu'un corps semi-conducteur, p.ex. étant un corps isolant
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
5.
Exposure apparatus, photolithographical reticles and exposure methods thereof
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (Chine)
Inventeur(s)
Wu, Qiang
Liu, Chang
Hao, Jing'An
Hu, Huayong
Liu, Yang
Abrégé
An exposure apparatus is provided for performing a column scan-exposure process. The exposure apparatus includes a base for supporting the exposure apparatus; and a reticle stage configured for holding a reticle having at two mask pattern regions and carrying the reticle to move reciprocally along a scanning direction. The exposure apparatus also includes a wafer stage configured for holding a wafer and carrying the wafer to move reciprocally along the scanning direction. Further, the exposure apparatus includes a control unit configured to control the reticle stage and the wafer stage to cooperatively move to cause the at least two mask pattern regions of the reticle on the reticle stage to be continuously and sequentially projected on at least two corresponding exposure shots of the wafer on the wafer stage along the scanning direction to perform a column scan-exposure process.
G03B 27/42 - Appareils de tirage par projection, p.ex. agrandisseur, appareil photographique de reproduction pour la reproduction automatique répétée d'un même original
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (Chine)
Inventeur(s)
Zhang, Haiyang
Ren, Jia
Abrégé
Methods for fabricating semiconductor devices are provided. Gate structures are formed on a top surface of a substrate to form semiconductor devices. Trenches are formed in the substrate on both sides of each gate structure of each semiconductor device. The trenches on the both sides of each gate structure are filled with stress layers, the stress layers in the substrate protruding over the top surface of the substrate. The stress layers are ion-doped and annealed on the both sides of each gate structure, and are pulse-etched to form a source region and a drain region of each gate structure. The pulse-etching is controlled such that the source regions and the drain regions of the plurality of semiconductor devices have a top surface coplanar with the top surface of the substrate.
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP (Chine)
Inventeur(s)
Hong, Zhongshan
Abrégé
A fabrication process of a semiconductor device is disclosed. The method includes providing a semiconductor substrate with a first insulation layer formed on the semiconductor substrate and a fin formed on the surface of the first insulation layer, and forming a fully-depleted semiconductor layer on sidewalls of the fin, and the fully-depleted semiconductor layer having a material different from that of the fin. The method also includes forming a second insulation layer covering the fully-depleted semiconductor layer, and removing the fin to form an opening exposing sidewalls of the fully-depleted semiconductor layer. Further, the method includes forming a gate dielectric layer on part of the sidewalls of the fully-depleted semiconductor layer such that the part of the sidewalls of the fully-depleted semiconductor layer form channel regions of the semiconductor device, and forming a gate electrode layer covering the gate dielectric layer.
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/36 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/161 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/51 - Matériaux isolants associés à ces électrodes
H01L 29/66 - Types de dispositifs semi-conducteurs
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP (Chine)
Inventeur(s)
Zhao, Neil
Fumitake, Mieno
Abrégé
Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate.
H01L 29/15 - Structures avec une variation de potentiel périodique ou quasi périodique, p.ex. puits quantiques multiples, superréseaux
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/161 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en
H01L 29/165 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en dans différentes régions semi-conductrices
Semiconductor Manufacturing International Corp (Chine)
Inventeur(s)
Cheng, Jenhao
Wang, Xining
Liu, Ling
Abrégé
Various embodiments provide inductor devices and fabrication methods. An exemplary inductor device can include a plurality of planar spiral wirings isolated by a dielectric layer. The planar spiral wirings can be connected by conductive pads formed over the dielectric layer and by conductive plugs formed in the dielectric layer. In one embodiment, a third planar spiral wiring can be formed over a second planar spiral wirings that is formed over a first planar spiral wiring. The third planar spiral wiring can be configured in parallel with the first third planar spiral wiring. The second planar spiral wiring can be configured in series with the first and third planar spiral wirings configured in parallel.
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP (Chine)
Inventeur(s)
Hong, Zhongshan
Abrégé
A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a plurality of first doped regions and second doped regions; and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a first gate dielectric layer and a second gate dielectric layer; and forming a first metal gate and a second metal gate on the first gate dielectric layer and the second gate dielectric layer, respectively. Further, the method includes forming a third dielectric layer on the second metal gate; and forming a second dielectric layer on the first dielectric layer. Further, the method also includes forming at least one opening exposing at least one first metal gate and one first doped region; and forming a contact layer contacting with the first metal gate and the first doped region to be used as a share contact structure.
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP. (Chine)
Inventeur(s)
Song, Hualong
Abrégé
A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having an oxide layer on a surface of the semiconductor substrate, and removing the oxide layer to expose the surface of the semiconductor substrate. The method also includes performing a thermal annealing process on the semiconductor substrate using an inert gas as a thermal annealing protective gas after removing the oxide layer, and forming an insulating layer on the semiconductor substrate after performing the thermal annealing process. Further, the method includes forming a high-K gate dielectric layer on a surface of the insulating layer, and forming a protective layer on a surface of the high-K gate dielectric layer.
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP (Chine)
Inventeur(s)
Fumitake, Mieno
Yin, Huaxiang
Abrégé
A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate, and forming a plurality of fins with hard mask layers and an isolation structure. The process also includes forming a first dummy gate layer on the fins and the isolation structure, and polishing the first dummy gate layer until the hard mask layer is exposed. Further, the method includes removing the hard mask layer to expose a top surface of the fins, and forming a second dummy gate material layer on the first dummy gate material layer. Further, the method also includes etching the second dummy gate layer and the first dummy gate layer to form a dummy gate on each of the fins.
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Zhao, Neil
Abrégé
A method is provided for fabricating an MOS transistor. The method includes providing a semiconductor substrate, and forming a gate structure having a gate dielectric layer and a gate metal layer on the semiconductor substrate. The method also includes forming offset sidewall spacers at both sides of the gate structure, and forming lightly doped regions in semiconductor substrate at both sides of the gate structure. Further, the method includes forming a first metal silicide region in each of the lightly doped regions, and forming main sidewall spacers at both sides of the gate structure. Further, the method includes forming heavily doped regions in semiconductor substrate at both sides of the gate structure and the main sidewall spacers, and forming a second metal silicide region in each of the heavily doped regions.
Semiconductor Manufacturing International Corp (Chine)
Inventeur(s)
Hong, Zhongshan
Abrégé
A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a plurality of first doped regions and second doped regions; and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a first gate dielectric layer and a second gate dielectric layer; and forming a first metal gate and a second metal gate on the first gate dielectric layer and the second gate dielectric layer, respectively. Further, the method includes forming a third dielectric layer on the second metal gate; and forming a second dielectric layer on the first dielectric layer. Further, the method also includes forming at least one opening exposing at least one first metal gate and one first doped region; and forming a contact layer contacting with the first metal gate and the first doped region to be used as a share contact structure.
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Wang, Dongjiang
Zhang, Steven
Abrégé
A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate; and configuring a channel region along a first direction. The method also includes forming trenches at both sides of the channel region along a second direction; and forming a magnetic material layer in each of the trenches. Further, the method includes magnetizing the magnetic material layers to form a magnetic field in the channel region between adjacent magnetic material layers; and forming source/drain regions at both ends of the channel region along the first direction.
Semiconductor Manufacturing International Corp (Chine)
Inventeur(s)
Xiao, Deyuan
Abrégé
A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate, and forming a quantum well layer on the semiconductor substrate. The method also includes forming a potential energy barrier layer on the semiconductor substrate, and forming an isolation structure to isolate different transistor regions. Further, the method includes patterning the transistor region to form trenches by removing portions of the quantum well layer and the potential energy barrier layer corresponding to a source region and a drain region, and filling trenches with a semiconductor material to form a source and a drain. Further, the method also includes forming a gate structure on a portion of the quantum well layer and the potential energy barrier layer corresponding to a gate region.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
17.
Nanowires, nanowire fielde-effect transistors and fabrication method
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Xiao, Deyuan
Hong, James
Abrégé
A method is provided for fabricating a nanowire-based semiconductor structure. The method includes forming a first nanowire with a first polygon-shaped cross-section having a first number of sides. The method also includes forming a semiconductor layer on surface of the first nanowire to form a second nanowire with a second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number. Further, the method includes annealing the second nanowire to remove a substantial number of vertexes of the second polygon-shaped cross-section to form the nanowire with a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section.
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP (Chine)
Inventeur(s)
Xiao, Deyuan
Shu, Emily
Abrégé
A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate, and forming a metal layer on the semiconductor substrate. The method also includes forming a silicon layer having at least one layer of graphene-like silicon on the metal layer, and forming a metal oxide layer by oxidizing a portion of the metal layer underneath the silicon layer. Further, the method includes forming a source region and a drain region connecting with the silicon layer.
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
19.
System for making and cleaning semiconductor device
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP. (Chine)
Inventeur(s)
Yuan, Zhugen
Abrégé
Various embodiments provide methods and systems for making and/or cleaning semiconductor devices. In one embodiment, a semiconductor device can be formed including a metal layer and a photoresist polymer. During formation, the semiconductor device can be cleaned in a cleaning chamber by a first cleaning solution provided from a solution supply device. After this cleaning process, a second cleaning solution containing metal ions and/or polymer residues can be produced and processed in a solution processing device to at least partially remove the metal ions and/or polymer residues to produce a third cleaning solution for re-use. In an exemplary fabrication or cleaning system, the solution processing device may be configured connecting to either an inlet or an outlet of the cleaning chamber. After cleaning, the semiconductor device can be processed to include a metal plug or an interconnect wiring.
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP. (Chine)
Inventeur(s)
He, Qiyang
Abrégé
A method is provided for fabricating small pitch patterns. The method includes providing a semiconductor substrate, and forming a target material layer having a first region and a second region on the semiconductor substrate. The method also includes forming a plurality of discrete first sacrificial layers on the first region of the target material layer and a plurality of discrete second sacrificial layers on the second region of the target material layer, and forming first sidewall spacers on both sides of the discrete first sacrificial layers and the discrete second sacrificial layers. Further, the method includes removing the first sacrificial layers and the second sacrificial layers, and forming second sidewall spacers. Further, the method also includes forming discrete repeating patterns in the first region of the target material layer and a continuous pattern in the second region of the target material layer.
H01L 21/461 - Traitement de corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour changer les caractéristiques physiques ou la forme de leur surface, p.ex. gravure, polissage, découpage
H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP. (Chine)
Inventeur(s)
Chiu, Tzu-Yin
Lu, Juilin
Cai, Jianxiang
Abrégé
Various embodiments provide semiconductor structures and their fabrication methods. An SRAM memory cell can include at least one semiconductor structure, and an SRAM memory can include at least one SRAM memory cell. An exemplary semiconductor structure can include at least two adjacent transistors formed on a semiconductor substrate. An opening can be formed and surrounded by gates of the two adjacent transistors and a doped region formed between the gates of the two adjacent transistors. A conductive layer can be formed to at least partially cover a bottom and a sidewall of the opening to electrically connect a gate of one transistor with the doped region of the other transistor of the two adjacent transistors.
H01L 27/11 - Structures de mémoires statiques à accès aléatoire
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP. (Chine)
Inventeur(s)
Li, Aileen
Ni, Jinghua
Abrégé
Various embodiments provide transistors and their fabrication methods. An exemplary method for forming a transistor includes removing a dummy gate to form a trench over a semiconductor substrate. A high-k dielectric layer can be conformally formed on surface of the trench and then be fluorinated to form a fluorinated high-k dielectric layer. A functional layer can be formed on the fluorinated high-k dielectric layer and a metal layer can be formed on the functional layer to fill the trench with the metal layer. Due to fluorination of the high-k dielectric layer, negative bias temperature instability of the formed transistor can be reduced and oxygen vacancies can be passivated to reduce positive bias temperature instability of the transistor.
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Yuan, Zhugen
Abrégé
Various embodiments provide methods and systems for making and/or cleaning semiconductor devices. In one embodiment, a semiconductor device can be formed including a metal layer and a photoresist polymer. During formation, the semiconductor device can be cleaned in a cleaning chamber by a first cleaning solution provided from a solution supply device. After this cleaning process, a second cleaning solution containing metal ions and/or polymer residues can be produced and processed in a solution processing device to at least partially remove the metal ions and/or polymer residues to produce a third cleaning solution for re-use. In an exemplary fabrication or cleaning system, the solution processing device may be configured connecting to either an inlet or an outlet of the cleaning chamber. After cleaning, the semiconductor device can be processed to include a metal plug or an interconnect wiring.
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Deng, Hao
Zhang, Bin
Abrégé
A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate, and forming a shallow trench isolation structure in the semiconductor substrate. The method also includes forming a plurality of parallel gate structures on the semiconductor substrate surrounded by the shallow trench isolation structure. Further, the method includes forming a plurality of first trenches in the semiconductor substrate at least one side of the gate structures proximity to the shallow trench isolation structure, and forming a first silicon germanium layer with a first germanium concentration in each of the first trenches. Further the method also includes forming a plurality second trenches in semiconductor substrate at least one side of the gate structures farther from the shallow trench isolation structure, and forming a second silicon germanium layer with a second germanium concentration greater than the first germanium concentration in each of the second trenches.
H01L 21/70 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun, ou de parties constitutives spécifiques de ceux-ci; Fabrication de dispositifs à circuit intégré ou de parties constitutives spécifiques de ceux-ci
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP (Chine)
Inventeur(s)
Wu, Qiang
Hao, Jing'An
Liu, Chang
Yao, Xin
Li, Tianhui
Shu, Qiang
Gu, Yiming
Abrégé
An exposure method and an exposure device are provided. An exemplary exposure device includes a stage, a first clamp holder, a second clamp holder, an optical projection unit, a first alignment detection unit, and/or a second alignment detection unit. The stage includes a first region and a second region. The first clamp holder is located in the first region and adapted for holding a first substrate, and the second clamp holder is located in the second region and adapted for holding a second substrate. The optical projection unit is located above the stage and adapted for exposure of the first substrate or the second substrate. The first alignment detection unit is adapted for detecting alignment marks of the first substrate. The second alignment detection unit is adapted for detecting alignment marks of the second substrate. The exposure device can accurately position the stage and improve production yield.
G03F 9/00 - Mise en registre ou positionnement d'originaux, de masques, de trames, de feuilles photographiques, de surfaces texturées, p.ex. automatique
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP. (Chine)
Inventeur(s)
Chen, Aries
Abrégé
Various embodiments provide semiconductor devices including high-K dielectric layer(s) and fabrication methods. An exemplary high-K dielectric layer can be formed by providing a semiconductor substrate including a first region and a second region, and forming a first silicon oxide layer on the semiconductor substrate in the first region. The semiconductor substrate can then be placed in an atomic layer deposition (ALD) chamber to repeatedly perform a selective ALD process. The selective ALD process can include an etching process and/or a purging process in the ALD chamber. By repeatedly performing the selective ALD process, a first high-K dielectric layer can be selectively formed on the first silicon oxide layer in the first region, exposing the semiconductor substrate in the second region.
Semiconductor Manufacturing International Corp (Chine)
Inventeur(s)
Li, Aileen
Ni, Jinghua
Abrégé
A method is provided for fabricating a through silicon via packaging structure. The method includes providing a first type substrate, and forming a second type substrate deferent from the first type substrate on the first type substrate. The method also includes forming a semiconductor device on a first surface of the second type substrate, and forming an interlayer dielectric layer on the first surface of the second type substrate. Further, the method includes forming a metal interconnection structure in the interlayer dielectric layer, and forming a through silicon via structure perforating the second type substrate and electrically connecting with the metal interconnection structure. Further, the method also includes removing the first type substrate using a gas etching process or a wet etching process to expose a second surface of the second type substrate and a bottom surface of the through silicon via structure.
H01L 21/44 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP. (Chine)
Inventeur(s)
Chang, Jianguang
Abrégé
Various embodiments provide transistors and fabrication methods. An exemplary transistor can include a silicon nitride layer disposed between a gate dielectric layer and a gate electrode layer. The silicon nitride layer can have a first surface in contact with the gate dielectric layer and a second surface in contact with the gate electrode layer. The second surface can include silicon atoms having a concentration higher than the first surface. A sidewall spacer can be formed on the semiconductor substrate along sidewalls of each of the gate electrode layer, the silicon nitride layer, and the gate dielectric layer. The disclosed transistor can have a reduced turn-on voltage with reduced power consumption.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 29/51 - Matériaux isolants associés à ces électrodes
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Chen, Yong
Abrégé
A method is provided for fabricating a PMOS transistor. The method includes providing a semiconductor substrate, and forming a dummy gate structure at least having a dummy gate, a high-K dielectric layer, and a sidewall spacer surrounding the high-K dielectric layer and the dummy gate on the semiconductor substrate. The method also includes forming a source region and a drain region in the semiconductor substrate at both sides of the dummy gate structure by an ion implantation process, and performing a first annealing process to enhance the ion diffusion. Further, the method includes forming an interlayer dielectric layer leveling with the surface of the dummy gate, and forming a trench by removing the dummy gate. Further, the method also includes performing a second annealing process, and forming a metal gate in the trench.
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Chen, Yong
He, Yonggen
Abrégé
A method is provided for fabricating a High-K layer. The method includes providing a substrate, applying a first precursor gas on the substrate such that the substrate absorbs first precursor gas molecules in a chemical absorption process, and removing the unabsorbed first precursor gas using a first inert gas. The method also includes applying a second precursor gas on the substrate, and forming a first thin film on the substrate as a reaction product of the second precursor gas and the absorbed first precursor gas molecules. Further, the method includes removing unreacted second precursor gas and byproducts using a second inert gas, and forming a high-K layer on the substrate by forming a plurality of the first thin films layer-by-layer.
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 21/31 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour former des couches isolantes en surface, p.ex. pour masquer ou en utilisant des techniques photolithographiques; Post-traitement de ces couches; Emploi de matériaux spécifiés pour ces couches
H01L 21/469 - Traitement de corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour changer les caractéristiques physiques ou la forme de leur surface, p.ex. gravure, polissage, découpage pour y former des couches isolantes, p.ex. pour masquer ou en utilisant des techniques photolithographiques; Post-traitement de ces couches
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/66 - Types de dispositifs semi-conducteurs
C23C 16/455 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c. à d. procédés de dépôt chimique en phase vapeur (CVD) caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour introduire des gaz dans la chambre de réaction ou pour modifier les écoulements de gaz dans la chambre de réaction
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 29/51 - Matériaux isolants associés à ces électrodes
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
31.
IC device including package structure and method of forming the same
Semiconductor Manufacturing International Corp (Chine)
Inventeur(s)
Gan, Zhenghao
Chen, Fang
Abrégé
Various embodiments provide semiconductor devices including a package structure and methods of forming the semiconductor devices. In one embodiment, the package structure can include a through-hole at least partially filled by one or more layers of material(s) to form a through-hole interconnect between semiconductor devices in the package structure. The through-hole can be filled by an insulating layer, a diffusion barrier layer, a metal interconnect layer, and/or a protective layer having a total thickness from the sidewall of the through-hole of less than or equal to the radius of the through-hole.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/52 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Bu, Weihai
Wang, Wenbo
Yu, Shaofeng
Wu, Hanming
Abrégé
A method is provided for fabricating a CMOS device. The method includes providing a semiconductor substrate having a first active region and a second active region. The method also includes forming a first trench on the first active region using a first barrier layer and a second substitute gate electrode layer to protect a gate region on the second active region, followed by forming a first work function layer and a first metal gate in the first trench. Further, the method includes forming a second trench on the second active region using a second barrier layer to protect the first metal gate structure, followed by forming a second work function layer and a second metal gate in the second trench.
H01L 21/70 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun, ou de parties constitutives spécifiques de ceux-ci; Fabrication de dispositifs à circuit intégré ou de parties constitutives spécifiques de ceux-ci
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Liu, Leo
He, Allan
Abrégé
Various embodiments provide complementary metal-oxide-semiconductor (CMOS) devices and their fabrication methods. A semiconductor substrate is provided to include a first region to form a PMOS transistor and a second region to form an NMOS transistor. One of the first and second regions can include a metal gate structure having a metal top layer. The other of the first and second regions can include an interfacial oxide layer formed on a high-k dielectric layer. A surface of the metal top layer can be oxidized to form a metal oxide top layer covering the metal top layer. The metal oxide top layer and the interfacial oxide layer can be removed by wet etching. A metal gate can be formed on the high-k dielectric layer.
H01L 21/70 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun, ou de parties constitutives spécifiques de ceux-ci; Fabrication de dispositifs à circuit intégré ou de parties constitutives spécifiques de ceux-ci
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
Semiconductor Manufacturing International Corp (Chine)
Inventeur(s)
Zhao, Neil
Fumitake, Mieno
Abrégé
Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate.
H01L 29/15 - Structures avec une variation de potentiel périodique ou quasi périodique, p.ex. puits quantiques multiples, superréseaux
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/267 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, des éléments couverts par plusieurs des groupes , , , , dans différentes régions semi-conductrices
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/161 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en
H01L 29/165 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en dans différentes régions semi-conductrices
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
Semiconductor Manufacturing International Corp (Chine)
Inventeur(s)
Hong, Zhongshan
Abrégé
Various embodiments provide complementary metal-oxide-semiconductor (CMOS) devices and fabrication methods. An exemplary CMOS device can be formed by providing a first dummy gate over a semiconductor substrate in a first region, providing a second dummy gate over the semiconductor substrate in a second region, and amorphizing a surface portion of the first dummy gate to form a first amorphous silicon layer. The first amorphous silicon layer can be used to protect the first dummy gate in the first region, when a second opening is formed in the second region by wet etching at least the second dummy gate. A second metal gate can then be formed in the second opening, followed by removing the first amorphous silicon layer and at least the first dummy gate to form a first opening in the first region. A first metal gate can be formed in the first opening.
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Wang, Wenbo
Bu, Weihai
Abrégé
A method is provided for fabricating an integrated semiconductor device. The method includes providing a semiconductor substrate having a first active region, a second active region and a plurality of isolation regions; forming a first gate dielectric layer on one surface of the semiconductor substrate; and forming a plurality of substituted gate electrodes, a layer of interlayer dielectric and sources/drains. The method also includes forming a first trench and a second trench; and covering the first gate dielectric layer on the bottom of the first trench. Further, the method includes removing the first dielectric layer on the bottom of the second trench; subsequently forming a second gate dielectric layer on the bottom of the second trench; and forming metal gates by filling the first trench and second trench using a high-K dielectric layer, followed by completely filling the first trench and the second trench using a gate metal layer.
Semiconductor Manufacturing International Corp (Chine)
Inventeur(s)
Xiao, Haibo
Bao, Wayne
Ping, Yanlei
Abrégé
Exemplary embodiments provide materials and methods for forming a metal silicide layer and/or an NMOS transistor. The metal silicide layer can be formed by heating a metal layer containing at least a tellurium element on a semiconductor substrate. The metal silicide layer can thus contain at least the tellurium element on the semiconductor substrate. The metal silicide layer can be formed in an NMOS transistor. With the addition of tellurium element in the metal silicide layer, Schottky barrier height between the metal silicide layer and the underling semiconductor substrate can be reduced. Contact resistance of the NMOS transistor can also be reduced.
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Gan, Zhenghao
Feng, Junhong
Abrégé
Various embodiments provide an MOS transistor, a formation method thereof, and an SRAM memory cell circuit. An exemplary MOS transistor can include a semiconductor substrate including a first groove on one side of a gate structure and a second groove on the other side of the gate structure. The first groove can have a sidewall perpendicular to a surface of the semiconductor substrate. The second groove can have a sidewall protruding toward a channel region under the gate structure. A stressing material can be disposed in the first groove to form a drain region and in the second groove to form a source region. Stress generated in the channel region of the MOS transistor can be asymmetric. The MOS transistor can be used as a transfer transistor in an SRAM memory cell circuit to increase both read and write margins of the SRAM memory.
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP (Chine)
Inventeur(s)
Zhou, Shicong
Yu, Edward
Zheng, Xiao
Yang, Josh
Yang, Michael
Abrégé
Various embodiments provide voltage regulator circuitry and devices. An exemplary voltage regulator circuitry can include a current comparing unit configured to convert an output voltage from a charge pump to a current and to compare the current with at least two different reference currents to generate a comparison result. A logic controller can be configured to generate a clock frequency adjustment signal based on the comparison result. A programmable clock unit can be configured to adjust a frequency of a clock signal according to the clock frequency adjustment signal to send the clock signal to the charge pump. Accordingly, the disclosed voltage regulator device can have reduced power consumption and improved reliability.
G05F 1/153 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type alternatif utilisant des transformateurs à prises ou des inductances à changement de prises comme dispositifs de réglage final avec un commutateur à prises entraîné par un moteur commandé par des dispositifs à tubes à décharge ou a semi-conducteurs
H02M 3/156 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation
H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p.ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
40.
MOS transistor, fabrication method thereof, and SRAM memory cell circuit
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP. (Chine)
Inventeur(s)
Gan, Zhenghao
Hong, Zhongshan
Feng, Junhong
Abrégé
Various embodiments provide an MOS transistor, a formation method thereof, and an SRAM memory cell circuit. An exemplary MOS transistor can include a channel region including an asymmetric stressing layer having a stress gradually varied from a compressive stress to a tensile stress or from a tensile stress to a compressive stress from a first end of the channel region adjacent to a source region to a second end of the channel region adjacent to a drain region. The MOS transistor can be used as a transfer transistor in an SRAM memory cell circuit to increase a source-drain saturation current in a write operation and to reduce a source-drain saturation current in a read operation. Read and write margins of the SRAM can be increased.
H01L 29/15 - Structures avec une variation de potentiel périodique ou quasi périodique, p.ex. puits quantiques multiples, superréseaux
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/165 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en dans différentes régions semi-conductrices
H01L 27/11 - Structures de mémoires statiques à accès aléatoire
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Fumitake, Mieno
Zhou, Meisheng
Abrégé
A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a first region and an adjacent second region, and etching the semiconductor substrate to form a plurality of first trenches in the first region and a second trench in the second region. Fins are formed in between the adjacent first trenches. The width of the second trench is greater than the width of the first trench. The method also includes filling the first trenches with a first isolation material to form first insolation structures, and form sidewall spacers inside the second trench. Further, the method includes forming a third trench in the second trench by etching the exposed semiconductor substrate on the bottom of the second trench using the sidewall spacers as an etching mask, and filling the second trench and the third trench using a second isolation material to form a second isolation structure.
Semiconductor Manufacturing International Corp (Chine)
Inventeur(s)
Cheng, Jenhao
Wang, Xining
Liu, Ling
Abrégé
Various embodiments provide inductor devices and fabrication methods. In one embodiment, an inductor device can include a first dielectric layer disposed on a semiconductor substrate; a first planar spiral wiring disposed on the first dielectric layer, and optionally one or more second planar spiral wirings disposed over the first planar spiral wiring. Each of the first and the optional second planar spiral wirings can include a first spiral metal wiring and a second spiral metal wiring connected to the first spiral metal wiring. The second spiral metal wiring can include at least two sub-metal-lines isolated with one another.
H01L 27/08 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type
H01L 49/02 - Dispositifs à film mince ou à film épais
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Cheng, Jenhao
Wang, Xining
Liu, Ling
Abrégé
Various embodiments provide inductor devices and fabrication methods. An exemplary inductor device can include a plurality of planar spiral wirings isolated by a dielectric layer. The planar spiral wirings can be connected by conductive pads formed over the dielectric layer and by conductive plugs formed in the dielectric layer. In one embodiment, a third planar spiral wiring can be formed over a second planar spiral wirings that is formed over a first planar spiral wiring. The third planar spiral wiring can be configured in parallel with the first third planar spiral wiring. The second planar spiral wiring can be configured in series with the first and third planar spiral wirings configured in parallel.
H01L 27/08 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type
H01L 49/02 - Dispositifs à film mince ou à film épais
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
44.
Fin field-effect-transistor (FET) structure and manufacturing method
Semiconductor Manufacturing International Corp (Chine)
Inventeur(s)
Fumitake, Mieno
Abrégé
A method for fabricating a semiconductor structure includes providing a semiconductor substrate having a first region and a second region, and doping top of the semiconductor substrate to form a doped layer at top surface of the semiconductor substrate over the first region and the second region. The method also includes etching the doped layer to form a first sub-fin in the first region and a first sub-fin in the second region, and forming an insulating layer over the semiconductor substrate including the first sub-fin in the first region and the first sub-fin in the second region. Further, the method includes removing top portions of the first sub-fin in the first region and the first sub-fin in the second region and forming corresponding second sub-fins.
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP. (Chine)
Inventeur(s)
Li, Aileen
Ni, Jinghua
Abrégé
A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate, forming a first dielectric layer on a surface of the semiconductor substrate based on a first-type oxidation, and forming a high-K dielectric layer on a surface of the first dielectric layer. The method also includes performing a first thermal annealing process to remove the first dielectric layer between the semiconductor substrate and the high-K dielectric layer such that the high-K dielectric layer is on the surface of the semiconductor substrate. Further, the method includes performing a second thermal annealing process to form a second dielectric layer on the surface of the semiconductor substrate between the semiconductor substrate and the high-K dielectric layer, based on a second-type oxidation different from the first-type oxidation, such that high-K dielectric layer is on the second dielectric layer instead of the first dielectric layer.
Semiconductor Manufacturing International Corp (Chine)
Inventeur(s)
Hong, Zhongshan
Abrégé
A fabrication process of a semiconductor device is disclosed. The method includes providing a semiconductor substrate with a first insulation layer formed on the semiconductor substrate and a fin formed on the surface of the first insulation layer, and forming a fully-depleted semiconductor layer on sidewalls of the fin, and the fully-depleted semiconductor layer having a material different from that of the fin. The method also includes forming a second insulation layer covering the fully-depleted semiconductor layer, and removing the fin to form an opening exposing sidewalls of the fully-depleted semiconductor layer. Further, the method includes forming a gate dielectric layer on part of the sidewalls of the fully-depleted semiconductor layer such that the part of the sidewalls of the fully-depleted semiconductor layer form channel regions of the semiconductor device, and forming a gate electrode layer covering the gate dielectric layer.
H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/36 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale
H01L 29/66 - Types de dispositifs semi-conducteurs
47.
Method for correcting layout pattern and mask thereof
Semiconductor Manufacturing International Corp (Chine)
Inventeur(s)
Zhang, Jasmine
Abrégé
A method for correcting layout pattern and a mask having the corrected layout pattern thereon are provided. In an exemplary method, a first layout pattern including a plurality of first hole patterns can be provided to form an auxiliary pattern in each first hole pattern and to obtain a second layout pattern. The auxiliary pattern can have a dimension smaller than an exposure resolution in a photolithography process. The second layout pattern can then be processed by an optical proximity correction (OPC) to obtain a first modified layout pattern. The first modified layout pattern can include a plurality of modified first hole patterns modified by the OPC. The first modified layout pattern can be simulated to obtain an actual layout pattern such that the actual layout pattern and the first layout pattern have an edge placement error (EPE) within a predetermined range.
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP. (Chine)
Inventeur(s)
Huang, Yibin
Liu, Winnie
Abrégé
An alignment method includes dividing a wafer into a plurality of regions including a first region and a second region, and each region contains a plurality chip areas. The method also includes obtaining alignment offset values for the first region, and determining a first alignment compensation equation for the first region. The method also includes obtaining alignment offset values for the second region, and determining a second alignment compensation equation for the second region. Further, the method includes determining whether a chip area to be exposed is in the first region or the second region, when the chip area is in the first region, using the first alignment compensation equation to adjust alignment of the wafer and, when the chip area is in the second region, using the second alignment compensation equation to adjust the alignment of the wafer.
G03F 9/00 - Mise en registre ou positionnement d'originaux, de masques, de trames, de feuilles photographiques, de surfaces texturées, p.ex. automatique
49.
Semiconductor device including contact holes and method for forming the same
A semiconductor device including contact holes and method for forming the same are provided. A dual-stress liner is formed on a substrate. A first, second and third dielectric layers are then formed over the dual-stress liner. The second dielectric layer has a top surface leveling with that of an overlapping portion of the dual-stress liner. The third dielectric layer is etched to form first openings to have the etching stop at the second dielectric layer and at the upper stress liner of the overlapping portion. The second dielectric layer, the first dielectric layer and the upper stress liner are etched along the first openings to form second openings having the etching stop at the lower stress liner of the overlapping portion and the dual-stress liner in other regions. The stress liners are etched to form contact holes.
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Chen, Aries
Abrégé
An SOI substrate and a method for forming the SOI substrate are provided. An SOI substrate can be formed by forming a silicon-germanium layer on a first baseplate. A top silicon layer can be formed on the silicon-germanium layer. A first insulating layer can be formed on the top silicon layer. An ion implanted layer can be formed in one of the silicon-germanium layer and the first baseplate. A second baseplate can be bonded to the first insulating layer. A first annealing process can be performed to anneal and split the one of the silicon-germanium layer and the first baseplate at the ion implanted layer. The silicon-germanium layer can be removed from the top silicon layer to expose the top silicon layer and to form the SOI substrate comprising the first insulating layer formed between the top silicon layer and the second baseplate.
H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Hu, Daniel
Wu, Ken
Gu, Yiming
Abrégé
A semiconductor structure including a double patterned structure and a method for forming the semiconductor structure are provided. A positive photoresist layer is formed on a negative photoresist layer, which is formed over a substrate. An exposure process is performed to form a first exposure region in the positive photoresist layer and to form a second exposure region in the negative photoresist layer in response to a first and a second intensity thresholds of the exposure energy. A positive-tone development process is performed to remove the first exposure region from the positive photoresist layer to form first opening(s). The second exposure region in the negative photoresist layer is then etched along the first opening(s) to form second opening(s) therein. A negative-tone development process is performed to remove portions of the negative photoresist layer outside of remaining second exposure region to form a double patterned negative photoresist layer.
G03F 7/00 - Production par voie photomécanique, p.ex. photolithographique, de surfaces texturées, p.ex. surfaces imprimées; Matériaux à cet effet, p.ex. comportant des photoréserves; Appareillages spécialement adaptés à cet effet
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Song, Hualong
Abrégé
A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having an oxide layer on a surface of the semiconductor substrate, and removing the oxide layer to expose the surface of the semiconductor substrate. The method also includes performing a thermal annealing process on the semiconductor substrate using an inert gas as a thermal annealing protective gas after removing the oxide layer, and forming an insulating layer on the semiconductor substrate after performing the thermal annealing process. Further, the method includes forming a high-K gate dielectric layer on a surface of the insulating layer, and forming a protective layer on a surface of the high-K gate dielectric layer.
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP. (Chine)
Inventeur(s)
Hu, Daniel
Wu, Ken
Gu, Yiming
Abrégé
A semiconductor structure including a double patterned structure and a method for forming the semiconductor structure are provided. A negative photoresist layer is formed on a positive photoresist layer, which is formed over a substrate. An exposure process is performed to form a first exposure region in the positive photoresist layer and to form a second exposure region in the negative photoresist layer in response to a first and a second intensity thresholds of the exposure energy. A negative-tone development process is performed to remove portions of the negative photoresist layer to form first opening(s). The positive photoresist layer is then etched along the first opening(s) to form second opening(s) therein. A positive-tone development process is performed to remove the first exposure region therefrom to form a double patterned positive photoresist layer.
H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
H01L 33/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails
H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
54.
Fin field effect transistor and fabrication method
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP. (Chine)
Inventeur(s)
Wang, Wenbo
Abrégé
A fin field effect transistor (FET) including a fin structure and a method for forming the fin FET are provided. In an exemplary method, the fin FET can be formed by forming at least one fin seed, including a top surface and sidewalls, on a substrate. A first semiconductor layer can then be formed at least on the sidewalls of the at least one fin seed. A second semiconductor layer can be formed on the first semiconductor layer. The second semiconductor layer and the at least one fin seed can be made of a same material. The first semiconductor layer can be removed to form a fin structure including the at least one fin seed and the second semiconductor layer.
H01L 21/20 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 21/84 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant autre chose qu'un corps semi-conducteur, p.ex. étant un corps isolant
55.
Fin field effect transistor and fabrication method
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Mieno, Fumitake
Abrégé
A fin field effect transistor and a method for forming the fin field effect transistor are provided. In an exemplary method, the Fin FET can be formed by forming a dielectric layer and a fin on a semiconductor substrate. The fin can be formed throughout an entire thickness of the dielectric layer and a top surface of the fin is higher than a top surface of the dielectric layer. The fin can be annealed using a hydrogen-containing gas and a repairing gas containing at least an element corresponding to a material of the fin. A gate structure can be formed on the top surface of the dielectric layer and at least on sidewalls of a length portion of the fin after the annealing process.
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Liu, Leo
Abrégé
A transistor and a method for forming the transistor are provided. The transistor can be formed over a substrate including a first region and second regions on opposite sides of the first region. On the substrate, a first SiGe layer can be formed, followed by forming a first silicon layer on the first SiGe layer and forming a second SiGe layer on the first silicon layer. The second SiGe layer and the first silicon layer within the second regions are removed. The first silicon layer within the first region is removed to form a cavity such that the second SiGe layer is floated. An isolating layer is formed in the cavity. Second silicon layers are formed in the second regions. A gate structure is formed on the second SiGe layer within the first region and the second silicon layers are doped to form a source and a drain.
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP (Chine)
Inventeur(s)
Wu, Qiang
Hao, Jing'An
Liu, Chang
Yao, Xin
Li, Tianhui
Shu, Qiang
Gu, Yiming
Abrégé
The present disclosure provides a lithography machine and a scanning and exposing method thereof. According to the scanning and exposing method, the scanning and exposing process for a whole wafer includes two alternately circulated motions: a scanning and exposing motion and a stepping motion; and the scanning and exposing motion is a sinusoidal motion rather than a rapid-acceleration uniform-speed rapid-deceleration scanning and exposing motion in the conventional techniques. During the scanning of a single exposure shot, it may begin to scan the exposure shot once a wafer stage and a reticle stage begin to accelerate from zero speed. And the scanning and exposing may not end until the speeds of the wafer stage and the reticle decrease to zero. Therefore, the effective time of the scanning and exposing in the scanning and exposing motion is greatly increased and the production efficiency of the wafer is improved.
G03B 27/42 - Appareils de tirage par projection, p.ex. agrandisseur, appareil photographique de reproduction pour la reproduction automatique répétée d'un même original
G03B 27/68 - Appareils de tirage par projection, p.ex. agrandisseur, appareil photographique de reproduction - Détails permettant de faire ou de corriger la distorsion, p.ex. en permettant la projection oblique
SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP. (Chine)
Inventeur(s)
Bao, Wayne
Abrégé
This application discloses a Fin FET structure and a method for forming the same. In the Fin FET structure, there are lower stress spacers disposed over the lower portion of the fin's opposite sidewalls, asserting one stress type to suppress the carrier mobility; there are also upper stress spacers disposed over the upper portion of the fin's opposite sidewalls, asserting an opposite stress type to increase the carrier mobility. Therefore, the leakage current in the fin FET is reduced and the device performance is improved. In the method, the stress spacers are formed by depositing stress layers and etching back the stress layers, where stress types and magnitudes are controllable, resulting in a simple process.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/20 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 21/84 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant autre chose qu'un corps semi-conducteur, p.ex. étant un corps isolant
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 29/66 - Types de dispositifs semi-conducteurs
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Cao, Junzhu
Jiang, Lily
Li, Cindy
Zhu, Creek
Abrégé
A method for forming metal gates is provided. In the method, a substrate with a first region and a second region is provided. Dummy gate structures and an ILD layer is formed on the substrate. Dummy gates of the dummy gate structures are removed to form openings respectively within the two regions. Work function layers are respectively formed to overlay the openings. A metal layer is formed on the work function layers and then a CMP process is performed until the ILD layer is exposed, thereby forming the metal gates within the two regions at the same time. Only one CMP process is performed to the metal layer, so that over polishing of the ILD layer may be reduced and thickness of metal gates may be more accurately controlled.
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Wei, Jingheng
Liu, Zheqiu
Abrégé
A method is provided for inspecting a chip layout. The method includes providing a chip layout having a plurality of patterns designed according to a design rule and performing a first inspection to the plurality of patterns according to the design rule. The method also includes determining patterns violating the design rule, as violating patterns, and corresponding violation values, and determining violating patterns having a minimum violation value among the violating patterns. Further, the method includes classifying the violating patterns having the minimum violation value into at least one sub-category based on characteristics of the violating patterns having the minimum violation value, and performing a second inspection on a selected violating pattern from the sub-category to determine whether the selected violating pattern and other violating patterns in the sub-category satisfy fabrication process conditions.
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
Semiconductor Manufacturing International Corporation (Chine)
Semiconductor Manufacturing International Corporation (Chine)
Inventeur(s)
Fumitake, Mieno
Abrégé
A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate and surrounding the fin. The fin has a semiconductor layer that has a source region portion and a drain region portion. The fin includes a first channel control region, a second channel control region, and a channel region between the two channel control regions, all of which are positioned between the source region portion and the drain region portion. The two channel control regions may have the same conductivity type, different from the channel region.
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Shu, Emily
Abrégé
An apparatus and a method for holding a wafer are provided in this disclosure. The wafer holding apparatus includes: an electrostatic chuck, the electrostatic chuck having a plurality of concentric zones; a plurality of power supply units, each adapted for applying a voltage to one of the zones of the electrostatic chuck independently; and a control unit, adapted for controlling each of the power supply units independently to start or stop applying the voltage to a corresponding zone of the electrostatic chuck. Surface flatness is improved when the wafer is chucked on the wafer holding apparatus according to the disclosure, and the risk of particle contamination can be reduced when the wafer is flattened and gets back into warpage from flatness.
H01T 23/00 - Appareils pour la production d'ions destinés à être introduits dans des gaz à l'état libre, p.ex. dans l'atmosphère
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Shu, Emily
Abrégé
An apparatus and a method for holding a wafer are provided in this disclosure. The wafer holding apparatus includes: an electrostatic chuck which has a plurality of zones arranged in a matrix; a plurality of power supply units, each of which is adapted to apply a voltage to the plurality of zones of the electrostatic chuck independently; and a control unit which is adapted to control each of the power supply units independently to start or stop applying the voltage to a corresponding zone of the electrostatic chuck. Surface flatness is improved when the wafer is chucked on the wafer holding apparatus according to the disclosure, and the risk of particles contamination can be reduced when the wafer is flattened and gets back into warpage from flatness.
H01T 23/00 - Appareils pour la production d'ions destinés à être introduits dans des gaz à l'état libre, p.ex. dans l'atmosphère
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
Semiconductor Manufacturing International Corporation (Chine)
Inventeur(s)
He, Yonggen
Wu, Jingang
Yao, Haibiao
Abrégé
A manufacturing method for manufacturing a semiconductor device includes depositing a spacer material on a semiconductor substrate, the substrate includes an NMOS region and a PMOS region, each region has a gate formed thereon. The method further includes covering the NMOS region with a first mask, forming a spacer for the PMOS gate by etching the spacer material, forming a recess in the PMOS region by etching, and growing SiGe or SiGe with in-situ-doped B in the recess of the PMOS region to form a PMOS source/drain region. The method further includes performing an anisotropic wet etching on the recess. After growing SiGE or SiGe with in-situ-doped B, the method further includes covering the PMOS region with a second mask and forming a spacer for the NMOS gate by etching the spacer material. The spacer for the PMOS and NMOS gate has a different critical dimension.
H01L 21/4763 - Dépôt de couches non isolantes, p.ex. conductrices, résistives sur des couches isolantes; Post-traitement de ces couches
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Hong, Zhongshan
Abrégé
A method for forming a TSV structure includes providing a silicon substrate with an interlayer dielectric layer formed thereon, forming a hard mask structure including a first hard mask layer including a metal element on the interlayer dielectric layer and a second hard mask layer on the first hard mask layer; forming an opening through the hard mask structure and the interlayer dielectric layer, the opening has a bottom and sidewalls in the silicon substrate. The method further includes depositing an insulating material on the hard mask structure and on the bottom and the sidewalls of the opening, subsequently removing the insulating material and the second hard mask layer until the first hard mask layer is exposed, and filling a conductive material into the opening. The method also includes removing the conductive material and the first hard mask layer by a CMP process until the interlayer dielectric layer is exposed.
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Zhou, Ming
He, Yonggen
Abrégé
A method for forming an interconnect structure includes providing a semiconductor substrate having a barrier layer, a low dielectric constant (Low K) inter-dielectric layer and a cap dielectric layer sequentially formed thereon; etching the cap dielectric layer and the Low K inter-dielectric layer sequentially until the barrier layer is exposed and a groove is formed; removing the cap dielectric layer until the Low K inter-dielectric layer is exposed; and doping a carbon element into the Low K inter-dielectric layer. The advantages of the method includes a decrease of the dielectric constant of the Low K inter-dielectric layer, thus, reduces the resistive-capacitive (RC) delay of interconnect layers of a semiconductor device and improve its operating speed and performance.
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Zhao, Feng
Deng, Wufeng
Zhao, Jingmin
Chen, Feng
Liu, Chunliang
Abrégé
A chemical mechanical polishing method includes providing a device layer having a surface to be polished, polishing the surface using an alkaline grinding slurry, removing a residual layer that is been formed on the polished surface using an acid buffer, forming a passivation layer covering the polished surface of the device layer after the residual layer has been removed, and cleaning the passivation layer using deionized water. A semiconductor device thus fabricated has surfaces with excellent flatness, good manufacturing yield and long-term reliability.
H01L 21/302 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour changer leurs caractéristiques physiques de surface ou leur forme, p.ex. gravure, polissage, découpage
69.
Semiconductor device and method for manufacturing the same
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Xi, Minwei
Zhu, Hong
Abrégé
A semiconductor device includes a first substrate and a second substrate being bonded to each other, a posterior interconnect layer interposed between the first and second substrates, a weld pad disposed in the posterior interconnect layer, and a first annular opening disposed in the first substrate. The device further includes a dielectric layer formed in the first opening, a via surrounded by the first annular opening, and an interconnect layer disposed in the via. The device also includes a conductive bump disposed on the interconnect layer and electrically connected to the weld pad through the interconnect layer.
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Shao, Qun
Hong, Zhongshan
Abrégé
The invention provides a method for manufacturing a transistor which includes: providing a substrate having a plurality of transistors formed thereon, wherein each transistor includes a gate; forming a stressed layer and a first oxide layer on the transistors and on the substrate successively; forming a sacrificial layer on the first oxide layer; patterning the sacrificial layer to remove a part of the sacrificial layer which covers on the gates of the transistors; forming a second oxide layer on the residual sacrificial layer and on a part of the first oxide layer which is exposed after the part of the sacrificial layer is removed; performing a first planarization process to remove a part of the second oxide layer located on the gates of the transistors; performing a second planarization process to remove the residual second oxide layer; and performing a third planarization process to remove the stressed layer.
H01L 21/461 - Traitement de corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour changer les caractéristiques physiques ou la forme de leur surface, p.ex. gravure, polissage, découpage
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Liu, Huanxin
Abrégé
A method for manufacturing a semiconductor device includes providing a substrate having an NMOS transistor and a PMOS transistor formed thereon, forming a stressed layer that covers the transistors, and selectively removing the stressed layer on the PMOS transistor. The method further includes annealing the substrate, removing the remaining stressed layer, forming a dielectric layer structure on the transistors; and performing a first planarization process on the dielectric layer structure. The method also includes forming a corrosion-resistant insulating structure on a rear surface of the substrate, and performing a second planarization process on the dielectric layer structure. The semiconductor device thus formed can withstand high voltages while maintaining gate oxide integrity.
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Mieno, Fumitake
Abrégé
The invention provides a method for forming a transistor, which includes: providing a substrate, a semiconductor layer being formed on the substrate; forming a dummy gate structure on the semiconductor layer; forming a source region and a drain region in the substrate and the semiconductor layer and at opposite sides of the dummy gate structure; forming an interlayer dielectric layer on the semiconductor layer; removing the dummy gate structure for forming an opening in the interlayer dielectric layer; non-crystallizing the semiconductor layer exposed in the opening for forming a channel layer; annealing the channel layer so that the channel layer and the substrate have same crystal orientation; and forming a metal gate structure in the opening, the metal gate being formed on the channel layer. Saturation current of the transistor is raised, and the performance of a semiconductor device is promoted.
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 21/322 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour modifier leurs propriétés internes, p.ex. pour produire des défectuosités internes
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Mieno, Fumitake
He, Youfeng
Abrégé
The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, peripheral shallow trench isolation (STI) units in the peripheral substrate, and MOS transistors on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, vertical LEDs on the on the N-type ion buried layer, storage shallow trench isolation (STI) units between the vertical LEDs, and phase change layers on the vertical LEDs and between the storage STI units. The storage STI units have thickness equal to thickness of the vertical LEDs. Each vertical LED comprises an N-type conductive region on the N-type ion buried layer, and a P-type conductive region on the N-type conductive region. The P-type conductive region contains SiGe. The peripheral STI units have thickness equal to thickness of the storage STI units. A top of P-type conductive region is flush with a top of the peripheral substrate. The P-type conductive region containing SiGe reduces drain current through the vertical LED and raises current efficiency of the vertical LED. The peripheral circuit region can work normally without adverse influence on performance of the phase change memory.
H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
74.
Phase change memory and method for fabricating the same
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Mieno, Fumitake
He, Youfeng
Abrégé
The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, a plurality of peripheral shallow trench isolation (STI) units in the peripheral substrate, and at least one MOS transistor on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, a plurality of vertical LEDs on the N-type ion buried layer, a plurality of storage shallow trench isolation (STI) units between the vertical LEDs, and a plurality of phase change layers on the vertical LED and between the storage STI units. The storage STI units have thickness substantially equal to thickness of the vertical LEDs. The peripheral STI units have thickness substantially equal to thickness of the storage STI units. The N-type conductive region contains SiC. A top of P-type conductive region is flush with a top of the peripheral substrate. The N-type conductive region containing SiC reduces drain current through the vertical LED and raises current efficiency of the vertical LED. The peripheral circuit region can work normally without adverse influence on performance of the phase change memory.
H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
Semiconductor Manufacturing International Corp (Chine)
Inventeur(s)
Jiang, Li
Li, Mingqi
Abrégé
A method is provided for fabricating a high-K metal gate MOS device. The method includes providing a semiconductor substrate having a surface region, a gate oxide layer on the surface region, a sacrificial gate electrode on the gate oxide layer, and a covering layer on the sacrificial gate electrode, an inter-layer dielectric layer on the semiconductor substrate and the sacrificial gate electrode. The method also includes planarizing the inter-layer dielectric layer to expose a portion of the covering layer atop the sacrificial gate electrode, implanting nitrogen ions into the inter-layer dielectric layer until a depth of implantation is deeper than a thickness of the portion of the covering layer atop the sacrificial gate electrode and polishing the inter-layer dielectric layer to expose a surface of the sacrificial gate electrode, removing the sacrificial gate electrode, and depositing a metal gate.
Semiconductor Manufacturing International Corp. (Chine)
Inventeur(s)
Hong, Zhongshan
Abrégé
A method for forming a gate electrode includes: providing a substrate; forming a gate dielectric layer and forming a sacrificial layer, the sacrificial layer including doping ions, a density of the doping ions in the sacrificial layer decreasing with increasing distance from the substrate; forming a hard mask layer; patterning the sacrificial layer and the hard mask layer; removing part of the patterned sacrificial layer by wet etching with the patterned hard mask layer as a mask, to form a dummy gate electrode which has a top width bigger than a bottom width, and removing the patterned hard mask layer; removing the dummy gate electrode and filling a gate trench with gate material to form a gate electrode which has a top width bigger than a bottom width, which facilitates the filling of the gate material and can avoid or reduce cavity forming in the gate material.