Abrégé

Semiconductor structure and method of forming semiconductor structure are provided. The semiconductor structure includes a substrate, a first isolation structure, and a first nanostructure and a second nanostructure on two sides of the first isolation structure. The semiconductor structure also includes a second isolation structure, and a third nanostructure and a fourth nanostructure on two sides of the second isolation structure. A top of the second isolation structure is lower than a top of the first isolation structure. The semiconductor structure also includes a first gate structure and a second gate structure. The first gate structure and the second gate structure expose a top surface of the first isolation structure. The semiconductor structure also includes a third gate structure and a fourth gate structure. The third gate structure and the fourth gate structure are in contact with each other on a top surface of the second isolation structure.

Classes IPC  ?

• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 21/8234 - Technologie MIS
• H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant

Abrégé

A semiconductor structure includes a substrate; a first electrode layer over the substrate; a dielectric layer on a sidewall surface of the first electrode layer; and a second electrode layer over the substrate. The first electrode layer, the dielectric layer, and the second electrode layer are arranged in a direction parallel to a surface of the substrate.

Classes IPC  ?

• H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

A semiconductor structure includes a substrate that includes a first region, a second region, and a third region; a first electrode layer disposed over the first region and the second region; a first dielectric layer disposed over the substrate; a second electrode layer disposed on the first dielectric layer over the third region and the second region; a second dielectric layer disposed over the substrate; a third electrode layer disposed on the second dielectric layer over the second region and over a portion of each of the third and first regions; and a first plug disposed over the first region and a second plug disposed over the third region. The first plug is electrically connected with one of the first, second and third electrode layers, and the second plug is electrically connected with the other two electrode layers.

Classes IPC  ?

• H01L 21/283 - Dépôt de matériaux conducteurs ou isolants pour les électrodes
• H01L 21/3213 - Gravure physique ou chimique des couches, p.ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable

Abrégé

A semiconductor structure includes a substrate that includes a base, a plurality of channel layers on the base, and an isolation layer between each of the channel layers. The semiconductor structure also includes a gate on the substrate, spanning a top and a portion of sidewalls of the channel layers. The semiconductor structure also includes a sidewall structure on sidewalls at two sides of the gate, a source/drain region in the substrate at two sides of the gate and the sidewall structure, a source/drain electrical connection layer on the source/drain region, and an isolation structure between the source/drain electrical connection layer and the gate. The isolation structure includes a cavity, including a first cavity region and a second cavity region located on the first cavity region. A width of the second cavity region is smaller than a width of the first cavity region.

Classes IPC  ?

• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/40 - Electrodes
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

Method for forming a semiconductor structure includes: providing a first substrate including a first surface and second surface opposite to each other, where the first substrate includes first ions with a first concentration; forming a first epitaxial layer on the first surface of the first substrate, where the first epitaxial layer includes second ions with a second concentration smaller than the first concentration; forming a second epitaxial layer on the first epitaxial layer and a third epitaxial layer located on the second epitaxial layer, where the second epitaxial layer includes third ions with a third concentration and the third epitaxial layer includes fourth ions with a fourth concentration smaller than the third concentration; and thinning the first substrate from the second surface of the first substrate until the surface of the second epitaxial layer is exposed.

Classes IPC  ?

• H01L 31/18 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives

Abrégé

A semiconductor structure includes a plurality of composite layers formed on a portion of a substrate. An interlayer dielectric layer is formed on the substrate and the plurality of composite layers. A first gate trench is formed on the interlayer dielectric layer, and a gate sidewall is formed on a side surface of the first gate trench. The composite layer includes stacked channel layers and a second gate trench between neighboring channel layers. The first gate trench and the gate sidewall cross over a portion of a sidewall and a portion of a top surface of the composite layer, and the first gate trench communicates with the second gate trench. A gate is formed in the first and second gate trenches. The doping region is formed in a channel layer. The source-drain layer is formed in the composite layer on two sides of the gate structure.

Classes IPC  ?

• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

A semiconductor device includes a substrate, a metal layer formed on the substrate, a dielectric layer formed on the substrate and covering the metal layer, a first contact hole formed in the dielectric layer, a conductive layer filled in the first contact hole, a thin film resistor layer formed on a portion of the dielectric layer, and a cover layer located on the thin film resistor layer. A bottom of the first contact hole exposes a surface of the metal layer. A bottom of the thin film resistor layer contacts a top surface of the conductive layer.

Classes IPC  ?

• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

A semiconductor structure and fabrication method are provided. The fabrication method includes providing a substrate and a fin protruding from the substrate, the fin including stacked structures and each stacked structure including a sacrificial layer and a semiconductor layer on the sacrificial layer; forming a dummy gate across the fin; etching the fin on two sides of the dummy gate to form source/drain recesses; etching the sacrificial layer of the fin at the bottom of the dummy gate exposed by the source/drain recesses to form auxiliary recesses along an extension direction of the fin; forming an isolation layer on the bottoms of the auxiliary recesses without completely filling the auxiliary recesses; and forming a source/drain doped layer completely filling the source/drain recesses, the source/drain doped layer and the isolation layer enclosing an air gap.

Classes IPC  ?

• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus

Abrégé

A mask plate, an alignment mark and a photolithography system are provided. In one form, an alignment mark includes a plurality of alignment patterns arranged at intervals, where the alignment pattern includes a first pattern extending in a first direction and a second pattern extending in a second direction, the first pattern includes a first end and a second end which are opposite to each other in the first direction, the second pattern includes a third end and a fourth end which are opposite to each other in the second direction, the second end is connected to the third end, the fourth end is connected to the first end, and the alignment pattern is a two-dimensional linear pattern.

Classes IPC  ?

• G03F 9/00 - Mise en registre ou positionnement d'originaux, de masques, de trames, de feuilles photographiques, de surfaces texturées, p.ex. automatique

Abrégé

Provided are a semiconductor structure and a forming method thereof, and a photomask layout. One form of a semiconductor structure includes: a base, including a substrate and a plurality of fins arranged in parallel on the substrate, the substrate including a transistor cell area, and in the transistor cell area, in a direction perpendicular to an extending direction of the fin, the fin closest to a boundary of the transistor cell area being used as an edge fin, and the edge fin having an outer side wall facing the boundary of the transistor cell area; and a gate structure, spanning the fin and covering a part of a top and a part of a side wall of the fin, and the gate structure exposing at least a part of an outer side wall of any of the edge fins.

Classes IPC  ?

• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS

Abrégé

Semiconductor structure and formation method are provided. A method of forming a semiconductor structure includes providing a dielectric layer on a substrate, the dielectric layer including a first region and a second region under the first region, the first region including discrete first initial nanowires, and the second region including discrete second initial nanowires; etching the dielectric layer and the first initial nanowires in the first region to form a first opening in the first region, and forming first nanowires from the first initial nanowires; etching the dielectric layer at a bottom of the first opening and the second initial nanowires to form a second opening in the second region, and forming second nanowires from the second initial nanowires; forming a second source/drain layer in the second opening; forming an isolation layer on the second source/drain layer; and forming a first source/drain layer in the first opening.

Classes IPC  ?

• H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
• H01L 21/84 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant autre chose qu'un corps semi-conducteur, p.ex. étant un corps isolant

Abrégé

A semiconductor structure and a method for forming same are provided. The forming method includes: forming a second electrode layer on a first dielectric layer, where the second electrode layer covers the first dielectric layer in a first region; forming a second dielectric layer on a second electrode layer and in a second region; forming a third electrode layer on the second dielectric layer, where on a projection plane parallel to the base, the third electrode layer has an overlapping region with each of the first region and the second region; and forming a first electrically connecting structure in contact with the second electrode layer, and forming, in the second region, a second electrically connecting structure in contact with the third electrode layer and the first electrode layer; or forming a third electrically connecting structure in contact with the first electrode layer, and forming a fourth electrically connecting structure in contact with the second electrode layer and the third electrode layer. By adjusting a connection relationship between different electrode layers, different equivalent capacitance densities can be obtained, thereby satisfying demands of different types of capacitors.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion

Abrégé

Semiconductor structures and methods for forming the same are provided. One form of a method includes: forming a sidewall structure layer on a sidewall of an interconnecting trench, and forming a source/drain interconnecting layer on a sidewall of the sidewall structure layer, filling the interconnecting trench, and in contact with a source/drain doped region, where the sidewall structure layer includes: a sacrificial spacer, arranged on a sidewall of a first spacer and suspended and spaced apart from the source/drain doped region, where along a direction perpendicular to the sidewall of the first spacer, a width of a part of the sacrificial spacer away from the base is greater than a width of a part of the sacrificial spacer close to the base; and a second spacer, filling a gap between a bottom of the sacrificial spacer and the source/drain doped region and arranged between the sacrificial spacer and the source/drain interconnecting layer; removing the sacrificial spacer to form an air gap defined by the second spacer and the first spacer; and forming a sealing layer sealing a top of the air gap, so that the sealing layer, the first spacer, and the second spacer form an air spacer.

Classes IPC  ?

• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter

Abrégé

The present disclosure relates to a semiconductor structure and a method for forming the semiconductor structure. The semiconductor structure includes: a first wafer, including a first substrate and a first dielectric layer on the first substrate, a pad groove and a pad structure in the pad groove are formed in the first substrate and the first dielectric layer, and the pad groove extends through the first substrate along a direction from the first substrate to the first dielectric layer and extends into a partial thickness of the first dielectric layer; and an isolation ring structure, arranged in the first substrate around the pad groove and extending through the first substrate along the direction from the first substrate to the first dielectric layer.

Classes IPC  ?

• H01L 21/762 - Régions diélectriques
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/60 - Protection contre les charges ou les décharges électrostatiques, p.ex. écrans Faraday

Abrégé

The present disclosure relates to a semiconductor structure and a method for forming the semiconductor structure. The semiconductor structure includes: a first wafer, including a first substrate and a first dielectric layer on the first substrate, a plurality of through-silicon via (TSV) structures in an array arrangement are formed in the first substrate, and the TSV structures extend through the first substrate along a direction from the first substrate to the first dielectric layer and extend into a partial thickness of the first dielectric layer; and an isolation ring structure, arranged in the first substrate around the plurality of TSV structures and extending through the first substrate along the direction from the first substrate to the first dielectric layer.

Classes IPC  ?

• H01L 27/146 - Structures de capteurs d'images

Abrégé

A semiconductor structure includes a substrate, a body region and a drift region in the substrate, a first gate structure over the body region and the drift region, a second gate structure over the drift region, a source in the body region, and a drain in the drift region. The first gate structure is between the source and the drain. The second gate structure is between the first gate structure and the drain.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

A semiconductor structure includes a substrate, a first electrode plate over the substrate, a second electrode plate over the first electrode plate, and a sidewall structure. The sidewall structure is attached to a side of the second electrode plate. A dielectric constant of the sidewall structure decreases in a direction away from the second electrode plate.

Classes IPC  ?

• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

A photoelectric sensor and a method for forming same and an electronic device are provided. The photoelectric sensor includes: a base, having a light receiving surface and including a pixel unit region; and a plurality of light trapping grooves, arranged in a part of the base in a thickness direction in the pixel unit region and arranged on a side of the light receiving surface of the base, where a surface shape of each of the light trapping grooves is arcuate. The present disclosure helps improve photosensitive performance of the photoelectric sensor.

Classes IPC  ?

• H01L 27/146 - Structures de capteurs d'images

Abrégé

A semiconductor structure includes a substrate, a first isolation layer in the substrate, composite layers over the substrate, and a second isolation layer between adjacent composite layers. Each composite layer includes channel layers, an insulating wall isolating two parts of each channel layer electrically, and a first gate electrode between adjacent channel layers. The second isolation layer penetrates into the first isolation layer.

Classes IPC  ?

• H01L 21/8234 - Technologie MIS
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices

Abrégé

A semiconductor structure and a method for forming the same are provided. The method includes: removing a partial thickness of a first channel layer in an N-type region along a direction parallel to the substrate, to form a first trench, where the first trench is defined by the remaining first channel layer and an adjacent sacrificial layer or by the remaining first channel layer and the adjacent sacrificial layer and a limiting layer; filling the first trench with a sidewall channel film; removing the remaining first channel layer in the N-type region, so that a second trench is defined between the sidewall channel film and the adjacent sacrificial layer or between the sidewall channel film and the adjacent sacrificial layer and the limiting layer; and filling the second trench with a center channel film, where the center channel film and the sidewall channel film are in contact with each other to form a second channel layer, and the second channel layer is configured to improve carrier mobility in a channel of an NMOS transistor. Embodiments of the present disclosure improve performance of a semiconductor structure.

Classes IPC  ?

• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

A semiconductor structure includes a substrate. The substrate includes a shielding region and a device region. The shielding region includes a first active region parallel to a first direction. The device region includes a second active region parallel to the first direction. The semiconductor structure also includes first isolation structures located on the shielding region. The first isolation structures run through the first active region along the second direction. The semiconductor structure also includes first gate structures located on the device region. The first gate structures cross the second active region along the second direction. The semiconductor structure also includes a second isolation structure located on the device region. The second isolation structure runs through the second active region along the second direction. The semiconductor structure also includes a dielectric layer on the substrate and an inductance coil on the dielectric layer.

Classes IPC  ?

• H01L 27/08 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type

Abrégé

This disclosure relates to a packaging structure and a packaging method. The packaging structure includes: a substrate; an interconnecting structure, bonded to the substrate, the interconnecting structure is electrically connected to the substrate; a chipset, including a plurality of first chips stacked along a longitudinal direction, the first chip adjacent to the interconnecting structure is used as a bottom chip, each of the rest of the first chips is used as a top chip, the bottom chip is electrically connected to the interconnecting structure, adjacent first chips along the longitudinal direction are electrically connected, and a portion of the bottom chip is exposed from the top chip; a conductive post, arranged on the interconnecting structure on a side of the chipset and electrically connected to the interconnecting structure; and a second chip, bonded to the bottom chip exposed from the top chip and to the conductive post.

Classes IPC  ?

• H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
• H01L 23/498 - Connexions électriques sur des substrats isolants
• H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
• H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe

Abrégé

This disclosure relates to a packaging structure and a packaging method. The structure includes: a substrate; a first chip, including a first surface and a second surface opposite to each other; a second chip, including a third surface, where the third surface includes a third bonding region bonded to the second bonding region, and a remaining region of the third surface is used as a fourth bonding region; a conductive post, arranged in the fourth bonding region; and a chipset, bonded to the first bonding region of the first chip, where the second bonding region is exposed from a projection of the chipset on the first chip. The chipset includes one or more third chips stacked along a longitudinal direction, adjacent third chips along the longitudinal direction are electrically connected, and the third chip adjacent to the first chip is electrically connected to the first chip.

Classes IPC  ?

• H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
• H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
• H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p.ex. dissipateurs de chaleur
• H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide

Abrégé

This disclosure relates to packaging method and a packaging structure. The packaging structure includes: a substrate, including a bonding surface, a chipset, bonded to the bonding surface and including a plurality of first chips stacked along a longitudinal direction, where the first chip adjacent to the substrate is used as a bottom chip, each of the rest of the first chips is used as a top chip; and a second chip, bonded to the bottom chip exposed from the top chip and to the bonding surface on a side of the chipset, where the second chip, the bottom chip, the top chip, and the substrate are electrically connected, and a projection of the second chip and a projection of the bottom chip on a projection plane parallel to the bonding surface partially overlap. The present disclosure helps improve a speed of communication between chips.

Classes IPC  ?

• H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
• H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
• H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
• H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
• H01L 23/42 - Choix ou disposition de matériaux de remplissage ou de pièces auxiliaires dans le conteneur pour faciliter le chauffage ou le refroidissement
• H01L 23/053 - Conteneurs; Scellements caractérisés par la forme le conteneur étant une structure creuse ayant une base isolante qui sert de support pour le corps semi-conducteur
• H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide

Abrégé

A semiconductor structure includes a substrate, a bottom metal structure located on the substrate, a first dielectric layer located on the bottom metal structure, first plug structures, second plug structures, and first metal structures. The substrate includes a base, a device structure located on the base, and conductive layers located on the device structure. The bottom metal structure is electrically connected to the conductive layers. The first dielectric layer includes a first opening structure and a second opening structure. The first opening structure includes first grooves and second grooves on top of the first grooves, and the second opening structure includes third grooves and fourth grooves on top of the third grooves. The first plug structures are located in the first grooves, and the second plug structures are located in the third grooves. The first metal structures are located in the second grooves and the fourth grooves.

Classes IPC  ?

• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives

Abrégé

An inductor coil includes: a substrate, including a base, a device layer on the base, a conductive layer, and an electrical interconnect structure; a plurality of stacked coil layers being on the substrate, each of the plurality of stacked coil layers including a plurality of sub-coil structures on a same layer; and a plurality of electrical connection layers between two adjacent coil layers, a projection pattern of each electrical connection layer on a surface of the substrate being within a range of projection patterns of two adjacent coil layers that are in contact with the plurality of electrical connection layers on the surface of the substrate, and all the plurality of coil layers being connected in parallel through all the plurality of electrical connection layers.

Classes IPC  ?

• H01F 17/00 - Inductances fixes du type pour signaux

Abrégé

A semiconductor structure includes: a substrate; channel structures on the substrate, a channel structure of the channel structures including a plurality of channel layers stacked along a direction perpendicular to a surface of the substrate and a plurality of gate grooves between adjacent channel layers; gate structures spanning the channel structure, the gate structures being also in the plurality of gate grooves; source/drain regions on the substrate on two sides of the gates and the channel layers, the source/drain regions being in contact with sidewalls of a plurality of channel layers; and inner spacer layers between adjacent channel layers, and first dielectric layers between the inner spacer layers and the gate structures, the inner spacer layers being between the source/drain regions and the gate structures.

Classes IPC  ?

• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/786 - Transistors à couche mince

Abrégé

An optical device and its fabrication method are provided. The method includes: providing a substrate including a coupling region; forming a first dielectric layer on the substrate; forming an initial waveguide groove in the first dielectric layer on the coupling region; forming a patterned layer on a surface of the first dielectric layer and in the initial waveguide groove, exposing at least a portion of a bottom of the initial waveguide groove; and using the patterned layer as a mask to etch the first dielectric layer, to form a waveguide structure on the substrate. The waveguide structure includes a waveguide end structure on the coupling region.

Classes IPC  ?

• G02B 6/30 - Moyens de couplage optique pour usage entre fibre et dispositif à couche mince

Abrégé

A semiconductor structure and its fabrication method are provided. The semiconductor structure includes: a substrate, composite layers, a gate structure crossing the composite layers; inner spacers, source/drain layers, and insulating layers. Each composite layer includes channel layers, first openings between the channel layers and the substrate, and second openings between adjacent channel layers. The gate structure is located on sidewalls and top surfaces of the composite layers, and is also located in the second openings and surrounds the channel layers. The inner spacers are located between adjacent channel layers, and between the channel layers and the substrates. The source/drain layers are located in the composite layers on two sides of the gate structure. Sidewalls of the source/drain layers are coplanar with the sidewalls of adjacent inner spacers and end faces of adjacent channel layers. The insulating layers are located in the first openings.

Classes IPC  ?

• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/306 - Traitement chimique ou électrique, p.ex. gravure électrolytique
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate including a first region and a second region, a first gate structure over the first region, and first source-drain doped layers in the first region of the substrate on both sides of the first gate structure. The semiconductor structure also includes a second gate structure over the second region, and second source-drain doped layers in the second region of the substrate on both sides of the second gate structure. Further, the semiconductor structure includes a first protection layer over the second gate structure, a first conductive structure over a first source-drain doped layer, and an isolation layer over the first conductive structure. The first conductive structure is also formed on the first gate structure, and the first conductive structure has a top surface lower than the first protection layer.

Classes IPC  ?

• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 21/8234 - Technologie MIS
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

A semiconductor structure and its fabrication method are provided. The semiconductor structure includes: a substrate including a base substrate with a first device region and a second device region; a first active region on the first device region and a second active region on the second device region; an isolation layer between the first active region and the second active region; and a first gate electrode and a second gate electrode on the substrate. The first active region includes a first functional region and a first shared region. The first gate electrode is located on the device region and on a portion of a surface of the first active region. The second gate electrode is located on the second device region and on a portion of a surface of the second active region; and the second gate electrode also extends to a surface of the first shared area.

Classes IPC  ?

• H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
• H01L 29/40 - Electrodes
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 23/528 - Configuration de la structure d'interconnexion

Abrégé

A semiconductor structure and a forming method thereof are provided. In one form, a forming method includes: providing a base, including a device region and a zero mark region; forming a zero mark trench inside the base in the zero mark region; filling the zero mark trench, to form a dielectric layer; forming a fin mask material layer covering the base and the dielectric layer; forming a mandrel layer on the fin mask material layer above the dielectric layer and the base in the device region, where the mandrel layer covers a top portion of the dielectric layer; forming a mask spacer on a side wall of the mandrel layer; removing the mandrel layer; etching the fin mask material layer by using the mask spacer as a mask after the mandrel layer is removed, to form a fin mask layer; and etching a partial thickness of the base using the fin mask layer as a mask, where the remaining base after etching is used as a substrate, and a protrusion located over the substrate in the device region is used as a fin, and etching a partial thickness of the dielectric layer during the etching of the base. In the present disclosure, after a fin is formed by filling a zero mark trench with a dielectric layer, a probability that a residue defect or a peeling defect occurs is relatively low.

Classes IPC  ?

• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 21/8234 - Technologie MIS
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

Semiconductor structures and methods for forming the same are provided. In one form, a semiconductor structure includes: a substrate; a bottom dielectric layer, located on the substrate; a bottom interconnect layer, located in the bottom dielectric layer; a top dielectric layer, located on the bottom dielectric layer and the bottom interconnect layer; a conductive plug, located in the top dielectric layer on a top of the bottom interconnect layer and having a bottom in direct contact with the bottom interconnect layer and a sidewall in direct contact with the top dielectric layer; a top interconnect layer, located in the top dielectric layer above the conductive plug and in contact with the conductive plug; and a top adhesion layer, located between the top interconnect layer and the top dielectric layer. By means of embodiments and implementations of the present disclosure, electrical connection performance of a semiconductor structure is optimized.

Classes IPC  ?

• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

A method for forming a semiconductor structure is provided. The method includes providing a substrate, where the substrate includes a conductive layer therein, and a surface of the substrate exposes a surface of the conductive layer; forming a groove adjacent to the conductive layer in the substrate, where the groove exposes a portion of a sidewall surface of the conductive layer; and forming a lower electrode layer in the groove and on a top surface of the conductive layer.

Classes IPC  ?

• H10N 50/01 - Fabrication ou traitement
• H10N 50/80 - Dispositifs galvanomagnétiques - Détails de structure

Abrégé

A memory structure is provided in the present disclosure. The memory structure includes a substrate, a plurality of discrete memory gate structures on the substrate where each of the plurality of memory gate structures includes a floating gate layer and a control gate layer on the floating gate layer, an isolation layer formed between adjacent memory gate structures where a top surface of the isolation layer is lower than a top surface of the control gate layer and higher than a bottom surface of the control gate layer, an opening is formed on an exposed sidewall of the control gate layer, and a bottom of the opening is lower than or coplanar with the top surface of the isolation layer, and a metal silicide layer on an exposed surface of the control gate layer and the top surface of the isolation layer.

Classes IPC  ?

• H10B 41/30 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire
• H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
• H10B 41/60 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes la grille de commande étant une région dopée, p.ex. cellules de mémoire en couche unique de polysilicium

Abrégé

A semiconductor structure includes a substrate, a plurality of gates, a cut isolation structure, and an interlayer dielectric layer. The plurality of gates are formed on the substrate. The plurality of gates extend along a first direction. The cut isolation structure is formed on the substrate. The cut isolation structure passes through the gates in a second direction. A size of the cut isolation structure in the first direction is equal to a predetermined size. The second direction is different from the first direction. The interlayer dielectric layer is formed on the substrate. The interlayer dielectric layer surrounds the gates and the cut isolation structure.

Classes IPC  ?

• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

A semiconductor structure and a forming method therefor are provided. The forming method includes: providing a base, a gate structure, a source/drain doped area, and a bottom dielectric layer; forming a source/drain interconnect layer running through the bottom dielectric layer on a top of the source/drain doped area; forming a top dielectric layer on the bottom dielectric layer; forming a gate contact running through the top dielectric layer on a top of the gate structure and a source/drain contact running through the top dielectric layer on a top of the source/drain interconnect layer; forming a sacrificial side wall layer on side walls of the gate contact and the source/drain contact; forming a gate plug filling the gate contact and a source/drain plug filling the source/drain contact; removing the sacrificial side wall layer to form a first gap; and forming a sealing layer sealing the first gap.

Classes IPC  ?

• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 21/311 - Gravure des couches isolantes

Abrégé

Semiconductor structures and forming methods are disclosed. One form of a method includes: forming mask spacers on a base; patterning a target layer using the mask spacers as masks, to form discrete initial pattern layers, where the initial pattern layers extend along a lateral direction and grooves are formed between a longitudinal adjacent initial pattern layers; forming boundary defining grooves that penetrate through the initial pattern layers located at boundary positions of the target areas and cutting areas along the lateral direction; forming spacing layers filled into the grooves and the boundary defining grooves; and using the spacing layers located in boundary defining grooves and the spacing layers located in the grooves as stop layers along the lateral and the longitudinal directions respectively, etching the initial pattern layers located in the cutting areas, and using the remaining initial pattern layers located in the target areas as the target pattern layers.

Classes IPC  ?

• H01L 21/308 - Traitement chimique ou électrique, p.ex. gravure électrolytique en utilisant des masques
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 21/8234 - Technologie MIS

Abrégé

A semiconductor structure and a forming method thereof are provided. One form of a semiconductor structure includes: a first device structure, including a first substrate and a first device formed on the first substrate, the first device including a first channel layer structure located on the first substrate, a first device gate structure extending across the first channel layer structure, and a first source-drain doping region located in the first channel layer structure on two sides of the first device gate structure; and a second device structure, located on a front surface of the first device structure, including a second substrate located on the first device structure and a second device formed on the second substrate, the second device including a second channel layer structure located on the second substrate, a second device gate structure extending across the second channel layer structure, and a second source-drain doping region located in the second channel layer structure on two sides of the second device gate structure, where projections of the second channel layer structure and the first channel layer structure onto the first substrate intersect non-orthogonally. The electricity of the first device can be led out according to the present disclosure.

Classes IPC  ?

• H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
• H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
• H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

A semiconductor structure and a forming method thereof are provided. The method includes: providing a substrate, a dummy spacer being formed on a side wall of the gate structure, a contact etch stop layer being formed on a side wall of the dummy spacer, and a source/drain doped area being formed in the substrate on two sides of the gate structure; forming a sacrificial dielectric layer above tops of the source/drain doped area and the gate structure; forming a source/drain plug running through the sacrificial dielectric layer; etching the sacrificial dielectric layer until a top of the dummy spacer is exposed; removing, after the top of the dummy spacer is exposed, the dummy spacer to form a gap between the contact etch stop layer and the side wall of the gate structure; and forming a top dielectric layer filling between the source/drain plugs.

Classes IPC  ?

• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

A semiconductor structure is provided. The semiconductor structure includes: a substrate; discrete channel structures on the substrate in device regions; a power rail line, located in the substrate of a power rail region; a gate structure, extending across the channel structures; source/drain doped regions, located in the channel structures on two sides of the gate structure; an interlayer dielectric layer, located at a side portion of the gate structure; a power rail contact plug, penetrating a partial thickness of the interlayer dielectric layer at a top of the power rail line, the power rail contact plug is in full contact with a top surface of the power rail line in a longitudinal direction; and a source/drain contact layer, located in the interlayer dielectric layer and in contact with the source/drain doped region, on a projection surface parallel to the substrate, the source/drain contact layer extends across the power rail line.

Classes IPC  ?

• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/40 - Electrodes
• H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p.ex. structures d'interconnexions enterrées
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
• H01L 23/528 - Configuration de la structure d'interconnexion

Abrégé

A semiconductor structure and a method for forming same. The structure comprises: a substrate; a vertical stack structure, which comprises a channel region, and source and drain regions positioned at two sides of the channel region, wherein the channel region comprises a first stack region, an isolation region, and a second stack region, which are positioned on the substrate, the first stack region comprising several first channel layers, and the second stack region comprising several second channel layers; a first isolation layer, which is positioned in the isolation region; a gate structure, which is positioned on the substrate and surrounds the first channel layer and the second channel layer; first source-drain doped regions, which are positioned in the source and drain regions on the two sides of the first stack region; first contact layers, which are positioned on the surfaces of the first source-drain doped regions and are provided with first projections on the surface of the substrate; second source-drain doped regions, which are positioned on the first contact layers; second contact layers, which are positioned on the surfaces of the second source-drain doped regions and are provided with second projections on the surface of the substrate, wherein the areas of the first projections are greater than or equal to those of the second projections; second connection layers, which are positioned on two sides of the gate structure; and first connection layers, which are positioned in the second source-drain doped regions. By means of the structure, the performance of the semiconductor structure is improved.

Classes IPC  ?

• H01L 29/94 - Dispositifs à métal-isolant-semi-conducteur, p.ex. MOS
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS

Abrégé

The present disclosure relates to a semiconductor packaging method. The method includes: providing a first wafer; and performing a wafer stacking operation a plurality of times. The wafer stacking operation includes: forming a first to-be-bonded wafer in the shape of a boss, where the first to-be-bonded wafer includes a base and a protrusion from the base, and orientating the protrusion toward a second to-be-bonded wafer and bonding the protrusion to the second to-be-bonded wafer; forming a first dielectric layer on a surface of the protrusion; and performing second trimming on an edge region of the protrusion and an edge region of the second to-be-bonded wafer, so that the remainder of the second to-be-bonded wafer after the second trimming is in the shape of a boss, and using the remainder of the wafer stack after the second trimming as the first to-be-bonded wafer for next wafer stacking.

Classes IPC  ?

• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
• H01L 21/3105 - Post-traitement

Abrégé

The present disclosure relates to an optical proximity correction method and system. The correction method may include providing main patterns and setting a forbidden edge rule according to a spacing between adjacent main patterns. The method may further include adding an auxiliary pattern to a side portion of the main patterns. A quantity of auxiliary patterns added to side portions of the main patterns is obtained based on the forbidden edge rule. The forbidden edge rule defines whether an edge of the main patterns is a forbidden edge, and an auxiliary pattern is not added to a side portion of the forbidden edge.

Classes IPC  ?

• G03F 1/38 - Masques à caractéristiques supplémentaires, p.ex. marquages pour l'alignement ou les tests, ou couches particulières; Leur préparation
• G03F 1/70 - Adaptation du tracé ou de la conception de base du masque aux exigences du procédé lithographique, p.ex. correction par deuxième itération d'un motif de masque pour l'imagerie
• G06F 30/398 - Vérification ou optimisation de la conception, p.ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]

Abrégé

A semiconductor structure is provided in the present disclosure. The semiconductor structure includes a substrate, a plurality of fins on the substrate, a plurality of isolation structures on the substrate, each formed on a top surface of the substrate between adjacent fins, and a power rail formed in at least one isolation structure of the plurality of isolation structures and further in the substrate, where a top surface of the power rail is lower than a top surface of the plurality of fins.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

A semiconductor structure and a fabrication method of the semiconductor structure are provided. The semiconductor structure includes a substrate, and the substrate includes a scribe line region. The semiconductor structure also includes a device layer over the substrate. The device layer includes multiple devices, an interconnection structure electrically connected to the devices, and a dielectric layer surrounding the devices and the interconnection structure. Further, the device layer includes a passivation layer over the device layer, and an alignment mark in the passivation layer over the scribe line region. The alignment mark includes two or more sub-alignment marks, the two or more sub-alignment marks are arranged along an extension direction of the scribe line region, and adjacent sub-alignment marks of the two or more sub-alignment marks are spaced apart from each other.

Classes IPC  ?

• H01L 23/544 - Marques appliquées sur le dispositif semi-conducteur, p.ex. marques de repérage, schémas de test
• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
• H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
• H01L 23/10 - Conteneurs; Scellements caractérisés par le matériau ou par la disposition des scellements entre les parties, p.ex. entre le couvercle et la base ou entre les connexions et les parois du conteneur
• H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
• H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium

Abrégé

Semiconductor device is provided. The semiconductor device includes a base substrate including a first region, a second region, and a third region, a first doped layer in the base substrate at the first region and a second doped layer in the base substrate at the third region, a first gate structure on the base substrate at the second region, a first dielectric layer on the base substrate, a first conductive layer on the first conductive layer and the second doped layer, a second conductive layer on a surface of the first conductive layer, and a third conductive layer on a contact region of the first gate structure. The second region is between the first region and the third region. The contact region is at a top of the first gate structure. A minimum distance between the second conductive layer and the third conductive layer is greater than zero.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 21/3213 - Gravure physique ou chimique des couches, p.ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
• H01L 21/8234 - Technologie MIS

Abrégé

A semiconductor device is provided in the present disclosure. The semiconductor device includes a substrate, a plurality of fins formed on the substrate, a dummy gate structure formed across the plurality of fins and on the substrate, a first sidewall spacer formed on a sidewall of the dummy gate structure, an interlayer dielectric layer formed on a surface portion of each fin adjacent to the first sidewall spacer to cover a lower portion of a sidewall of the first sidewall spacer, and a second sidewall spacer formed on a top of the interlayer dielectric layer and covering a remaining portion of the sidewall of the first sidewall spacer. The top of the second sidewall spacer is coplanar with a top of the first sidewall spacer and the top of the dummy gate structure.

Classes IPC  ?

• H01L 21/8234 - Technologie MIS
• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

Semiconductor structure and forming method thereof are provided. The forming method includes: providing a substrate; forming a plurality of initial composite layers on a portion of the substrate; forming a plurality of source and drain layers on surfaces of the plurality of channel layers exposed by a first opening and grooves by using a selective epitaxial growth process, the plurality of source and drain layers being parallel to a first direction and distributed along a second direction, the second direction being parallel to a normal direction of the substrate, and gaps being between adjacent source and drain layers; forming contact layers on surfaces of the plurality of source and drain layers and in the gaps; and forming a conductive structure on a surface of a contact layer on a source and drain layer of the plurality of source and drain layers.

Classes IPC  ?

• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/311 - Gravure des couches isolantes
• H01L 21/285 - Dépôt de matériaux conducteurs ou isolants pour les électrodes à partir d'un gaz ou d'une vapeur, p.ex. condensation

Abrégé

Semiconductor structure and forming method thereof are provided. The forming method includes: forming a substrate including a power rail region, the power rail region including a first area and a second area, the power rail region having a first fin and a second fin spanning the second area; forming sidewall spacers on sidewall surfaces of the first fin and the second fin after forming the first fin and the second fin; forming a first patterned layer on the substrate, the first patterned layer having a first opening in the first patterned layer exposing the power rail region; etching the substrate using the first patterned layer as a mask to form power rail openings in the substrate; forming isolation films on inner wall surfaces of the power rail openings; and forming buried power rails in the power rail openings after forming the isolation films.

Classes IPC  ?

• H01L 27/11 - Structures de mémoires statiques à accès aléatoire
• H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 21/8234 - Technologie MIS

Abrégé

A semiconductor structure and its fabrication method are provided. The semiconductor structure includes: a substrate including a base substrate, fins, and an isolation structure; a first dielectric layer; gate structures in the first dielectric layer, where each gate structure includes a gate electrode layer and a gate dielectric layer; air spacers and second spacers on sidewalls of gate electrode layers, where the air spacers are located between the gate electrode layers and the second spacers to expose the sidewalls of the gate electrode layers and the second spacers; source/drain layers in the fins at sides of each gate structure; first conductive structures in the first dielectric layer and on the source/drain layers; and a second dielectric layer on the first dielectric layer and the gate structures, located on the air spacers. The air spacers are also located between the first conductive structures and the gate electrode layers.

Classes IPC  ?

• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 21/8234 - Technologie MIS

Abrégé

A semiconductor structure and a method for forming same. The semiconductor structure comprises: a substrate; a surrounding gate transistor, which is located on the substrate, the surrounding gate transistor comprising protrusion portions which are separately located on the substrate, and a channel structure layer which is arranged spaced apart from the protrusion portions in a suspended manner, wherein the channel structure layer comprises a plurality of channel layers sequentially arranged at intervals, the channel layers are vertically stacked in a direction perpendicular to a surface of the substrate, and in the direction perpendicular to the surface of the substrate, the distance between a protrusion portion and a channel layer adjacent to the protrusion portion is greater than the distance between adjacent channel layers; and a gate structure, which comprises work function layers surrounding surfaces of the channel layers, wherein the work function layers are filled between a protrusion portion and a channel layer adjacent to the protrusion portion, and between adjacent channel layers. When an NMOS transistor is formed, the material of the work function layers is a P-type work function material; and when a PMOS transistor is formed, the material of the work function layers is an N-type work function material. The embodiments of the present invention favour reduction in device current leakage.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

A semiconductor structure and a method for forming same. The structure comprises: a substrate, which comprises at least one cell region, the cell region comprising a first region and a second region which are adjacent and arranged in a first direction, the first region comprising a first isolation region, the second region comprising a second isolation region, and the central axis of the first isolation region parallel to the first direction not coinciding with the central axis of the second isolation region; a first gate structure located on the first region, and a first metal layer and second metal layer respectively located at two sides of the first gate structure; a second gate structure located on the second region, and a third metal layer and fourth metal layer respectively located at two sides of the second gate structure, wherein the first gate structure, the first metal layer, the second metal layer, the second gate structure, the third metal layer, and the fourth metal layer are parallel to a second direction; a first isolation structure, which is located on the first isolation region and penetrates the first metal layer and the second metal layer in the first direction; and a second isolation structure, which is located on the second isolation region and penetrates the third metal layer and the fourth metal layer in the first direction.

Classes IPC  ?

• H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/762 - Régions diélectriques

Abrégé

A semiconductor structure and a method for forming the same are provided. One form of a method includes: forming a source/drain groove in the channel structure on two sides of a gate structure; forming a sacrificial epitaxial layer on a bottom of the source/drain groove; forming, on the sacrificial epitaxial layer, a source/drain doped layer in the source/drain groove; and removing the sacrificial epitaxial layer, to form a gap between a bottom of the source/drain doped layer and the protrusion. After the sacrificial epitaxial layer is formed, the source/drain doped layer located in the source/drain groove may be formed on the sacrificial epitaxial layer using the epitaxy process on the basis of the sacrificial epitaxial layer. Therefore, the epitaxy process for forming the source/drain doped layer is prevented from adverse effects, the epitaxial growth quality of the source/drain doped layer is ensured, and a performance of the semiconductor structure is optimized.

Classes IPC  ?

• H01L 29/786 - Transistors à couche mince
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

A photoelectric sensor, a method for forming same, and an electronic device, the photoelectric sensor comprising: an isolation structure, which is located in a pixel substrate between photosensitive units, the isolation structure comprising a conductive layer; a plurality of interconnecting structures, which are distributed in the pixel substrate, and the end parts of which are exposed on a second surface, wherein the interconnecting structures comprise a first interconnecting structure located in a first lead region and a second interconnecting structure located in a second lead region, and the second interconnecting structure is electrically connected to the first interconnecting structure; a metal grid, which is located on the second surface and which is in contact with the conductive layer; a connection layer, which is located on a second surface of the first lead region and which is in contact with the metal grid and the first interconnecting structure; and a pad layer, which is located on the second surface of a lead region, the thickness of the pad layer being greater than the thicknesses of the connection layer and the metal grid. The pad layer comprises a first pad layer located in the second lead region, and is in contact with the end part of the second interconnecting structure facing the second surface. According to embodiments of the present invention, the performance of the photoelectric sensor is improved.

Classes IPC  ?

• H01L 27/146 - Structures de capteurs d'images
• H01L 31/0352 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails caractérisés par leurs corps semi-conducteurs caractérisés par leur forme ou par les formes, les dimensions relatives ou la disposition des régions semi-conductrices

Abrégé

A semiconductor structure and a forming method therefor. The forming method comprises: providing a substrate, wherein a first sacrificial layer is formed on the substrate, a channel structure is formed on the first sacrificial layer and comprises one or more stacked channel stacks, and each channel stack comprises a second sacrificial layer and a channel layer located on the second sacrificial layer, and a dummy gate structure crossing the channel structure is further formed on the substrate, wherein the etching resistance of the first sacrificial layer is less than that of the second sacrificial layer; removing the channel structure and the first sacrificial layer on both sides of the dummy gate structure to form a first trench penetrating through the channel structure and the first sacrificial layer; removing the first sacrificial layer at the bottom of the channel structure by means of the first trench, and forming a second trench communicated with the first trench at the bottom of the channel structure; forming an isolation layer in the second trench; and forming a source/drain doped layer in the first trench after the isolation layer is formed. The isolation layer effectively isolates the gate structure from the substrate, thereby reducing the probability of leakage current generated between the gate structure and the substrate.

Classes IPC  ?

• H01L 21/336 - Transistors à effet de champ à grille isolée
• H01L 29/786 - Transistors à couche mince
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS

Abrégé

A photoelectric sensor and a forming method thereof, and an electronic device, the photoelectric sensor comprising: a substrate, the substrate having a light receiving surface, the substrate comprising a photosensitive pixel region, and the photosensitive pixel region comprising a plurality of pixel unit regions distributed in a matrix; a plurality of light trapping grooves positioned in the substrate in part of the thickness of the pixel unit region and positioned on one side of the light receiving surface of the substrate, the plurality of light trapping grooves being distributed in a matrix along the row direction and the column direction; the row direction and the column direction being perpendicular, adjacent light trapping grooves in the row direction being in communication, adjacent light trapping grooves in the column direction being in communication, the side walls of the light trapping grooves enclosing a plurality of adjoining bosses, and the shape of the bosses being octagonal. In the pixel unit region, the eight side surfaces and the top surface of each boss may be used as the photosensitive surface of a photosensor, significantly increasing the photosensitive area of the photoelectric sensor, which is beneficial to improving the optical local area capability of the photoelectric sensor, thereby enhancing the photosensitive performance of the photoelectric sensor.

Classes IPC  ?

• H01L 27/146 - Structures de capteurs d'images
• H01L 31/00 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails
• H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
• H01L 31/18 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives

Abrégé

A semiconductor structure and a formation method therefor. The formation method comprises: providing a substrate, wherein gate structures are formed on the substrate, source-drain doped regions are formed in the substrate at two sides of each gate structure, and bottom dielectric layers which are located between adjacent gate structures are formed on the source-drain doped regions; forming, on the top face of each gate structure, a liner metal layer which is in contact with the gate structure, wherein the material of the liner metal layer is pure metal; forming a top dielectric layer on each bottom dielectric layer, wherein the top dielectric layer covers the liner metal layer; and forming, by using a first selective deposition process, a gate plug which penetrates through the top dielectric layer and is in contact with the liner metal layer. A liner metal layer can provide a good formation interface and a good deposition substrate for forming a gate plug by using a first selective deposition process, thereby facilitating the deposition and growth of the material of the gate plug on the liner metal layer, and thus reducing the difficulty of forming the gate plug by using the first selective deposition process, and improving the formation quality of the gate plug.

Classes IPC  ?

• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS

Abrégé

A semiconductor structure and a forming method therefor. The method comprises: forming an auxiliary layer on the surface of a covering layer by means of a first selective deposition process; forming a first medium layer on the surfaces of a substrate and the auxiliary layer; forming an electrically conductive structure in the first medium layer; forming a second medium layer on the surfaces of the first medium layer and the electrically conductive structure; forming a first opening and a second opening, with the first opening being located in the second medium layer and the first medium layer and being exposed from the auxiliary layer, and the second opening being located in the second medium layer and being exposed from the top surface of the electrically conductive structure; forming a first electrically conductive layer in the first opening; and forming a second electrically conductive layer in the second opening, wherein the growth rate of a material of the electrically conductive layer on the surface of the auxiliary layer is greater than that of the material of the electrically conductive layer on the surface of the covering layer, which improves the performance of the formed semiconductor structure.

Classes IPC  ?

• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

A semiconductor structure, a forming method therefor and a working method thereof. The semiconductor structure comprises: a substrate, comprising a first region that comprises a plurality of first active regions arranged in a first direction and first isolation regions located between adjacent first active regions; several first fin portions located on the substrate, the several first fin portions being arranged parallel to the first direction and in a second direction that is perpendicular to the first direction, and the first fin portions being arranged across the adjacent first active regions and the first isolation regions between the first active regions; a plurality of first gate structures located on the first isolation regions, the first gate structures being arranged across the first fin portions in the second direction; and several first electrical interconnection structures electrically connected to the first gate structures. By means of the present invention, electrical isolation between adjacent active regions is achieved in a semiconductor structure with high integration, which is conducive to improving the performance of the semiconductor structure.

Classes IPC  ?

• H01L 21/336 - Transistors à effet de champ à grille isolée
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus

Abrégé

A method of forming a semiconductor structure includes: providing an initial substrate having a first region and a second region; forming a first substrate on the initial substrate; forming a first insulating layer on the first substrate; forming a second substrate on the first insulating layer; removing the second substrate in the second region to form a second insulating layer on the first insulating layer in the second region; and forming a plurality of passive devices on the second insulating layer in the second region and forming a plurality of active devices on the second substrate in the first region.

Classes IPC  ?

• G02B 6/124 - Lentilles géodésiques ou réseaux intégrés
• G02B 6/12 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES - Détails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p.ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
• G02B 6/13 - Circuits optiques intégrés caractérisés par le procédé de fabrication

Abrégé

A mask pattern for forming the semiconductor structure is provided. The mask pattern includes a first mask pattern and a second mask pattern. The first mask pattern includes a plurality of first target patterns, and the plurality of first target patterns are arranged along a first direction. The second mask pattern includes a plurality of second target patterns, and the plurality of second target patterns are arranged along the first direction. When the first mask pattern overlaps the second mask pattern, one of the plurality of first target patterns partially overlaps a corresponding one of the plurality of second target patterns.

Classes IPC  ?

• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
• G03F 1/70 - Adaptation du tracé ou de la conception de base du masque aux exigences du procédé lithographique, p.ex. correction par deuxième itération d'un motif de masque pour l'imagerie
• H01L 21/311 - Gravure des couches isolantes
• H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques

Abrégé

A semiconductor structure and a method for forming the same are provided. In one form, a semiconductor structure includes: a substrate and protruding portions protruding from the substrate in sub-device regions; channel structure layers located on the protruding portions and spaced apart from the protruding portions, where each of the channel structure layers includes one or more channel layers spaced apart from each other; a dielectric wall located on the substrate between adjacent sub-device regions in a longitudinal direction, where the dielectric wall includes a main dielectric wall portion protruding from the substrate and dielectric wall protrusions protruding from the main dielectric wall portion in the longitudinal direction, where the dielectric wall protrusions are in contact with side walls of the channel layers; gate structures located on the sub-device regions, spanning tops of the channel structure layers in the sub-device regions, and surrounding the channel layers exposed from the dielectric wall; and source/drain doped layers located on the protruding portions on two sides of the gate structures and in contact with the channel structure layers. In forms of the present disclosure, an influence of the dielectric wall on a stress applied by the source/drain doped layers to the channel layers is reduced, and performance of the semiconductor structure is optimized.

Classes IPC  ?

• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/786 - Transistors à couche mince
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS

Abrégé

A semiconductor structure is provided. The semiconductor structure including: a substrate, where the substrate includes a first region and a second region adjacent to the first region; a plurality of fins formed over the first region of the substrate; an isolation layer over the substrate between adjacent fins of the plurality of fins, where a top of the isolation layer is lower than a top surface of a fin of the plurality of fins, the isolation layer over the second region and the second region of the substrate together contain a power rail opening, and the substrate contains a through-hole at a bottom of the power rail opening; and a first metal layer in the power rail opening and the through-hole, where a back surface of the first metal layer is above a back surface of the substrate.

Classes IPC  ?

• H01L 29/76 - Dispositifs unipolaires
• H01L 29/94 - Dispositifs à métal-isolant-semi-conducteur, p.ex. MOS
• H01L 31/062 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails adaptés comme dispositifs de conversion photovoltaïque [PV] caractérisés par au moins une barrière de potentiel ou une barrière de surface les barrières de potentiel étant uniquement du type métal-isolant-semi-conducteur
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 21/8234 - Technologie MIS
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

Semiconductor device is provided. The semiconductor device includes a to-be-etched layer having a plurality of first regions and a plurality of second regions that are alternately arranged along a first direction, where the second region includes a second trench region; a first mask layer on the plurality of first regions and the plurality of second regions of the to-be-etched layer; a second mask layer on the first mask layer; a first trench penetrating the first mask layer and the second mask layer over a first region of the plurality of first regions; a mask sidewall spacer on sidewall surfaces of the first trench; and second trenches over the plurality of second trench regions of the plurality of second regions, where a sidewall surface of the second trench exposes a corresponding mask sidewall spacer of an adjacent first trench.

Classes IPC  ?

• H01L 21/311 - Gravure des couches isolantes
• H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques

Abrégé

A semiconductor structure and a forming method therefor, and a mask layout. The semiconductor structure comprises: a base comprising a substrate and a plurality of fins arranged on the substrate in parallel, wherein the substrate comprises a transistor cell region, and in the transistor cell region, in a direction perpendicular to the fin extension direction, the fin closest to the boundary of the transistor cell region is an edge fin, and the edge fin has an outer sidewall facing the boundary of the transistor cell region; and a gate structure that spans the fin and covers a part of the top portion and a part of the sidewall of the fin, the gate structure exposing at least a part of an outer sidewall of any edge fin. According to the present invention, the gate structure exposes at least a part of the outer sidewall of any edge fin, to reduce the area of the sidewall of the edge fin covered by the gate structure, such that the normal operation of the transistor can be ensured, and the effective channel width is reduced by adjusting the etching quantity of the gate structure on the outer sidewall, thereby improving the flexibility of adjusting the effective channel width of the transistor.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

A mask plate, an alignment mark and a photolithography system. The alignment mark comprises a plurality of alignment patterns arranged at intervals, wherein each alignment pattern comprises a first pattern extending in a first direction and a second pattern extending in a second direction. In the first direction, the first pattern comprises a first end and a second end, which are opposite each other; and in the second direction, the second pattern comprises a third end and a fourth end, which are opposite each other, wherein the second end is connected to the third end, and the fourth end is connected to the first end. The alignment patterns are two-dimensional linear patterns. Comparing the embodiments of the present invention and a case where the alignment mark is a one-dimensional linear pattern, during the process of performing alignment by using the alignment mark provided by the embodiments of the present invention, the alignment mark macroscopically constitutes moiré patterns which are arranged periodically, the moiré patterns enable an alignment system to obtain a greater first-order diffraction signal strength, and a corresponding alignment signal strength is greater, thereby improving the overlay (OVL) accuracy and reducing the rework rate and production costs.

Classes IPC  ?

• G03F 9/00 - Mise en registre ou positionnement d'originaux, de masques, de trames, de feuilles photographiques, de surfaces texturées, p.ex. automatique
• G03F 7/20 - Exposition; Appareillages à cet effet
• G03B 27/32 - Appareils de tirage par projection, p.ex. agrandisseur, appareil photographique de reproduction

Abrégé

The semiconductor structure includes a substrate; a dielectric layer formed on the substrate; an opening, formed through the dielectric layer; a contact layer formed at bottom of the opening; a blocking layer formed on a sidewall surface of the opening; and a plug formed in the opening. The plug is formed on a sidewall surface of the blocking layer and in contact with the contact layer.

Classes IPC  ?

• H01L 21/285 - Dépôt de matériaux conducteurs ou isolants pour les électrodes à partir d'un gaz ou d'une vapeur, p.ex. condensation
• H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p.ex. structures d'interconnexions enterrées
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

Semiconductor structures is provided. The semiconductor structure includes a semiconductor substrate having at least one first region, a plurality of second regions and a plurality of third regions; at least one second fin formed on one second region of the plurality of second region; at least one third fin formed on one third region of the plurality of third regions; a first epitaxial layer formed in the at least one first fin; and a second epitaxial layer formed in the at least one second fin and the at least one third fin.

Classes IPC  ?

• H01L 27/11 - Structures de mémoires statiques à accès aléatoire
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
• H01L 29/165 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en dans différentes régions semi-conductrices
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

Semiconductor structures is provided. The semiconductor structure includes a semiconductor substrate having a first region and a second region. A surface of the first region of the semiconductor substrate contains a gate structure, a surface of the second region of the semiconductor substrate contains a dummy gate structure, and the semiconductor substrate under the dummy gate structure contains an isolation structure. The semiconductor structure further includes a bulk layer having a substantially flat reshaped surface formed in the semiconductor substrate at each of two sides of the gate structure; and a protective layer formed on the reshaped surface of the bulk layer.

Classes IPC  ?

• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires

Abrégé

Disclosed are a semiconductor structure and a forming method thereof. In one form, a semiconductor structure includes: a base; gate structures arranged discretely on the base, including gate contact regions used for contact with gate plugs; source/drain doped regions, including source/drain contact regions and source/drain connection regions; dielectric structure layers, located on the base on sides of the gate structures and covering the source/drain doped regions and the gate structures; source/drain contact structures, being in contact with the source/drain doped regions, where the source/drain contact structures are an integrated structure, and include source/drain plugs penetrating dielectric structure layers of the source/drain contact regions and source/drain contact layers located in dielectric structures of the source/drain connection regions, top surfaces of the source/drain contact layers are lower than top surfaces of the source/drain plugs, and the source/drain contact structures and the dielectric structure layers enclose spaced openings; spaced dielectric layers, filling the spaced openings; and gate plugs, located on tops of the gate structures in the gate contact regions and in contact with the gate structures. The source/drain contact structures of implementations of the present disclosure are an integrated structure, which improves performance of electrical connection between the source/drain plugs and the source/drain contact layers.

Classes IPC  ?

• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/40 - Electrodes

Abrégé

A semiconductor structure and a fabrication method are provided. The semiconductor structure includes: a base substrate; gate structures and source/drain plugs over the base substrate; source/drain contact structures on the source/drain plugs; gate contact structures on the gate structures; and a dielectric layer on the gate structures and the source/drain plugs. Cavities are formed between the gate structures and the source/drain plugs along a surface of the base substrate. The dielectric layer encloses tops of the cavities.

Classes IPC  ?

• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/40 - Electrodes
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

A semiconductor structure and a fabrication method of the semiconductor structure are provided. The semiconductor structure includes a substrate including a first region and a second region, first gate structures, second gate structures, first source-drain doped layers, second source-drain doped layers, and a first dielectric layer. A top surface of the first dielectric layer disposed over the first region is lower than a top surface of the first dielectric layer disposed over the second region. The semiconductor structure also includes a first barrier layer disposed over the first dielectric layer disposed over the first region. The first barrier layer and the first dielectric layer disposed over the first region include a first opening exposing the first source-drain doped layer, and the first dielectric layer disposed over the second region includes a second opening exposing the second source-drain doped layer.

Classes IPC  ?

• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 21/8234 - Technologie MIS
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 21/321 - Post-traitement

Abrégé

A semiconductor structure and a fabrication method of the semiconductor structure are provided. The semiconductor structure includes a substrate. The substrate includes a first region, a second region, and an isolation region between the first region and the second region. The semiconductor structure also includes a first fin, a second fin and a third fin disposed over the first region, the second region, and the isolation region, respectively. Further, the semiconductor structure includes a gate structure. The gate structure includes a first work function layer over the first region and a first portion of the isolation region, and a second work function layer over the second region and a second portion of the isolation region. An interface where the first work function layer is in contact with the second work function layer is located over a top surface of the third fin.

Classes IPC  ?

• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS

Abrégé

Semiconductor fabrication method for manufacturing an interconnect structure is provided. The semiconductor fabrication method for manufacturing an interconnect structure includes providing a substrate structure comprising a substrate, a first dielectric layer on the substrate, and a metal interconnect line extending through the first dielectric layer; removing a portion of the first dielectric layer on the metal interconnect line to form a recess exposing a surface of the metal interconnect line; forming a graphene layer on the exposed surface of the metal interconnect line; and forming a second dielectric layer filling the recess and covering the graphene layer.

Classes IPC  ?

• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 21/3205 - Dépôt de couches non isolantes, p.ex. conductrices ou résistives, sur des couches isolantes; Post-traitement de ces couches
• H01L 23/528 - Configuration de la structure d'interconnexion

Abrégé

A semiconductor structure includes a base substrate including a first region and a second region. The semiconductor further includes a first fin member located over the first region, a second fin member located over the second region, a first dummy gate across a surface of the first fin member, and a second dummy gate across a surface of the second fin member. A first opening is formed in the first fin member located on each side of the first dummy gate, a second opening is formed between two adjacent first channel layers, a third opening is formed in the second fin member located at each side of the second dummy gate, and a fourth opening is formed between two second channel layers. The semiconductor structure still further includes a first inner spacer located in the second opening, and a second inner spacer located in the fourth opening.

Classes IPC  ?

• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/786 - Transistors à couche mince
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

A method for forming a semiconductor structure is provided. In one form, a method includes: providing a to-be-processed base structure, where the to-be-processed base structure includes a base layer and pattern structures protruding from the base layer, and a surface of the base structure has adsorption groups; performing plasma treatment on the surface of the base structure by using a reaction gas, where the reaction gas chemically reacts with the adsorption group to cause quantities of precursor adsorption nucleation points on the surface of the base structure to tend to be same; and after the plasma treatment, forming, by using an atomic layer deposition (ALD) process, a target layer conformally covering the surface of the base structure. The plasma treatment is performed on the surface of the base structure, so that the quantities of the precursor adsorption nucleation on top surfaces and sidewalls of the pattern structures and on the surface of the base layer are the same, achieving the modification to the surface of the base structure. Therefore, the thickness uniformity of the target layer is improved, thereby enhancing the performance of a semiconductor.

Classes IPC  ?

• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives

Abrégé

A semiconductor structure and a fabrication method of the semiconductor structure are provided. The semiconductor structure includes a substrate, a gate structure over the substrate, and a sidewall spacer structure located on a sidewall surface of the gate structure. The sidewall spacer structure includes a first sidewall spacer, a second sidewall spacer, and a cavity located between the first sidewall spacer and the second sidewall spacer. The first sidewall spacer is located on the sidewall surface of the gate structure. A top surface of the cavity is above a top surface of the gate structure, and a bottom surface of the cavity is coplanar with a bottom surface of the gate structure. The semiconductor structure also includes a source and drain plug located over the substrate on each side of the gate structure. The source and drain plug is located on a sidewall surface of the second sidewall spacer.

Classes IPC  ?

• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/40 - Electrodes

Abrégé

A semiconductor structure and a method for forming the same are provided. One form of the method includes: providing a base, where a channel stack and a tear-off structure span the channel stack being formed on the base, and the channel stack including a sacrificial layer and a channel layer; forming a groove in channel stacks on both sides of a gate structure; laterally etching the sacrificial layer exposed from the groove to form a remaining sacrificial layer; forming a source/drain doped region in the channel layer exposed from the remaining sacrificial layer; forming an interlayer dielectric layer on the base; etching the interlayer dielectric layer on one side of the source region to expose a surface of the channel layer corresponding to the source region; etching the interlayer dielectric layer on one side of the drain region to expose the surface of the channel layer corresponding to the drain region; forming a first metal silicide layer on a surface of the channel layer corresponding to the source region; forming a second metal silicide layer on a surface of the channel layer corresponding to the drain region; forming a first conductive plug covering the first metal silicide layer and a second conductive plug covering the second metal silicide layer. In the present disclosure, contact resistance of the first conductive plug, the second conductive plug, and the source/drain doped region is reduced.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 21/8234 - Technologie MIS
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices

Abrégé

A semiconductor structure and a fabrication method are provided. The semiconductor structure includes: a base substrate, an optical waveguide layer over the base substrate; a first dielectric layer over the base substrate; a cavity between the first dielectric layer and the optical waveguide layer; and a second dielectric layer on the first dielectric layer and the optical waveguide layer. The cavity is located on sidewall surfaces of the optical waveguide layer and has a bottom coplanar with a bottom of the optical waveguide layer. The second dielectric layer is located on a top of the cavity and seals the cavity.

Classes IPC  ?

• G02B 6/12 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES - Détails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p.ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
• G02B 6/10 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES - Détails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p.ex. des moyens de couplage du type guide d'ondes optiques
• G02B 6/122 - Elements optiques de base, p.ex. voies de guidage de la lumière
• G02B 6/136 - Circuits optiques intégrés caractérisés par le procédé de fabrication par gravure

Abrégé

A method for forming a semiconductor structure. The method comprises: providing a first substrate, wherein the first substrate comprises a first surface and a second surface which are opposite each other, the first substrate is internally provided with first ions, and the first ions have a first concentration; forming a first epitaxial layer on the first surface of the first substrate, wherein the first epitaxial layer is internally provided with second ions, the second ions have a second concentration, and the second concentration is less than the first concentration; forming a second epitaxial layer on the first epitaxial layer and forming a third epitaxial layer located on the second epitaxial layer, wherein the second epitaxial layer is internally provided with third ions, the third ions have a third concentration, the third epitaxial layer is internally provided with fourth ions, the fourth ions have a fourth concentration, and the fourth concentration is less than the third concentration; and performing thinning processing from the second surface of the first substrate on the first substrate, until the surface of the second epitaxial layer is exposed. By means of the present invention, the uniformity of thinning thickness is ensured, and requirements for manufacturing a substrate of a semiconductor structure can also be satisfied, thereby facilitating the improvement of the performance of the semiconductor structure.

Classes IPC  ?

• H01L 27/146 - Structures de capteurs d'images

Abrégé

Disclosed are a semiconductor structure and a forming method thereof. In one form, a forming method includes: providing a base, including a substrate and a plurality of fins protruding from the substrate, an interlayer dielectric layer formed on the substrate, a gate opening formed in the interlayer dielectric layer, the gate opening spanning the fin and exposing a part of a top and a part of a sidewall of the fin, and a source/drain doped region formed in the fins on two sides of the gate opening, where the substrate includes a first region and a second region adjacent to each other, to respectively form transistors, the gate opening located in either of the first region and the second region extends to the other region and exposes the fin of the other region, and a position of the exposed fin of the other region is used as an interconnect position; forming a gate dielectric layer covering a bottom and a sidewall of the gate opening and the fin in the gate opening conformally; removing the gate dielectric layer on a surface of the fin at the interconnect position, to expose the surface of the fin at the interconnect position; and forming a gate structure in the gate opening after the surface of the fin at the interconnect position is exposed. The present disclosure enlarges a process window for electrical connection.

Classes IPC  ?

• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 27/11 - Structures de mémoires statiques à accès aléatoire
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/45 - Electrodes à contact ohmique
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 21/285 - Dépôt de matériaux conducteurs ou isolants pour les électrodes à partir d'un gaz ou d'une vapeur, p.ex. condensation
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

A method for forming a semiconductor structure is provided. In one form, a method includes: providing a base, a dummy gate structure, a source-drain doped region, and an interlayer dielectric layer; removing the dummy gate structure located at an isolation region to form an isolation opening; performing first ion doping on a fin below the isolation opening, to form an isolation doped region, where a doping type of the isolation doped region is different from a doping type of the source-drain doped region; filling an isolation structure in the isolation opening; removing the remaining dummy gate structure, to form a gate opening; and forming a gate structure in the gate opening. In embodiments and implementations of the present disclosure, the isolation doped region with a doping type different from that of the source-drain doped region is formed, so that a doping concentration of opposite-type ions in the fin of the isolation region can be improved, thereby accordingly improving a potential energy barrier of a P-N junction formed by the source-drain doped region and the fin of the isolation region, to prevent a conduction current from being generated in the fin of the isolation region when a device is working, and implementing isolation between the fin in the isolation region and the fin in other regions. Moreover, there is no need to perform a fin cut process, so that the fin is a continuous structure, to prevent stress release in the fin.

Classes IPC  ?

• H01L 21/762 - Régions diélectriques
• H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
• H01L 21/8234 - Technologie MIS
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

A semiconductor structure and a method for forming the same are provided. In one form, a forming method includes: providing a base, a gate structure, a source-drain doping region, and an interlayer dielectric layer; removing the gate structure located in an isolation region to form an isolation opening and expose the top and side walls of a fin located in the isolation region; performing first ion-doping on the fin under the isolation opening to form an isolation doped region, a doping type of the isolation doped region being different from a doping type of the source-drain doping region; and filling the isolation opening with an isolation structure after the doping, the isolation structure straddling the fin of the isolation region. In embodiments and implementations of the present disclosure, the isolation doped region is formed, a doping concentration of inversion ions in the fin of the isolation region can thus be increased, and a barrier of a P-N junction formed by the source-drain doping region and the fin of the isolation region can be increased accordingly, to prevent the device from generating a conduction current in the fin of the isolation region during operation, thereby implementing isolation between the fin of the isolation region and the fin of other regions. Moreover, there is no need to perform a fin cut process. Hence the fin is made into a continuous structure, which helps prevent stress relief in the fin.

Classes IPC  ?

• H01L 29/76 - Dispositifs unipolaires
• H01L 29/94 - Dispositifs à métal-isolant-semi-conducteur, p.ex. MOS
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 21/8234 - Technologie MIS
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

A cleaning method of a semiconductor structure is provided. The method includes providing a substrate, where the substrate includes a functional surface and a back surface that is opposite to the functional surface. The method also includes forming a fluid passivation film on the functional surface of the substrate. In addition, the method includes after forming the fluid passivation film, performing a first charge removal treatment on the functional surface of the substrate through a wet cleaning process. Further, the method includes after performing the first charge removal treatment, performing a main cleaning treatment on the functional surface and the back surface of the substrate.

Classes IPC  ?

• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• C01C 1/02 - Préparation ou séparation d'ammoniac

Abrégé

Semiconductor structure and fabrication method are provided. The semiconductor structure includes a substrate, including a first region and a second region; a plurality of fins, formed on the first region of the substrate; a first isolation structure, formed on the first region between adjacent fins and on the second region of the substrate; a second isolation structure, formed in each fin and in the first isolation structure, over the first region of the substrate; and a power rail, formed in the isolation structure and partially in the substrate of the second region.

Classes IPC  ?

• H01L 29/76 - Dispositifs unipolaires
• H01L 29/94 - Dispositifs à métal-isolant-semi-conducteur, p.ex. MOS
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter

Abrégé

A semiconductor structure and a forming method thereof are provided. In one form, a forming method includes: providing a base, including a device region and a zero mark region; forming a zero mark trench inside the base in the zero mark region; filling the zero mark trench, to form a dielectric layer; forming a fin mask material layer covering the base and the dielectric layer; forming a mandrel layer on the fin mask material layer above the dielectric layer and the base in the device region, where the mandrel layer covers a top portion of the dielectric layer; forming a mask spacer on a side wall of the mandrel layer; removing the mandrel layer; etching the fin mask material layer by using the mask spacer as a mask after the mandrel layer is removed, to form a fin mask layer; and etching a partial thickness of the base using the fin mask layer as a mask, where the remaining base after etching is used as a substrate, and a protrusion located over the substrate in the device region is used as a fin, and etching a partial thickness of the dielectric layer during the etching of the base. In the present disclosure, after a fin is formed by filling a zero mark trench with a dielectric layer, a probability that a residue defect or a peeling defect occurs is relatively low.

Classes IPC  ?

• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 21/8234 - Technologie MIS
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, having a plurality of fins on a surface of the substrate; a gate structure across the plurality of fins. The gate structure is located on a portion of a top surface and sidewall surfaces of the plurality of fins. The gate structure includes a first region and a second region on the first region. A bottom boundary of the second region is higher than the top surface of the plurality of fins. A size of the first region in an extending direction of the plurality of fins is smaller than a size of the second region in the extending direction of the plurality of fins.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/3065 - Gravure par plasma; Gravure au moyen d'ions réactifs
• H01L 21/3213 - Gravure physique ou chimique des couches, p.ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

A semiconductor structure and a formation method therefor. The formation method comprises: providing a substrate and a fin protruding from the substrate, wherein the fin comprises a plurality of groups of stacked structures which are stacked together, and each group of stacked structures comprises a sacrificial layer and a semiconductor layer located on the top portion of the sacrificial layer; forming a dummy gate across the fin, wherein the dummy gate covers part of the top portion and part of a sidewall of the fin; etching the fin on two sides of the dummy gate, so as to form a source/drain groove; etching a sacrificial layer of the fin that is exposed by the source/drain groove and is located at the bottom portion of the dummy gate, so as to form additional slots on two sides of the etched sacrificial layer in the extension direction of the fin, wherein the additional slot has an opening that faces the source/drain groove, and side walls on the two sides of the etched sacrificial layer in the extension direction of the fin form the bottom portion of the additional slot; forming an isolation layer on the bottom portion of the additional slot, wherein the additional slot is not fully filled with the isolation layer; and forming a source/drain doped layer, with which the source/drain groove is fully filled, wherein the source/drain doped layer and the isolation layer define a gap. The gap helps to reduce the parasitic capacitance between the source/drain doped layer and a metal gate.

Classes IPC  ?

• H01L 21/336 - Transistors à effet de champ à grille isolée
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

A semiconductor structure and a method for forming a semiconductor structure. The method comprises: providing a substrate, wherein the substrate is provided with a dielectric layer, the dielectric layer comprising a second area and a first area located on the second area, the first area is internally provided with several initial first nanowires that are separated from each other, and the second area is internally provided with several initial second nanowires that are separated from each other; etching the dielectric layer and the initial first nanowires of the first area, so as to form a first opening in the first area, and form first nanowires from the initial first nanowires; etching the dielectric layer and the initial second nanowires at the bottom of the first opening, so as to form a second opening in the second area, and form second nanowires from the initial second nanowires; forming a second source-drain layer in the second opening; forming an isolation layer on the surface of the second source-drain layer; and forming a first source-drain layer in the first opening. A semiconductor structure formed by means of the method has relatively good performance.

Classes IPC  ?

• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS

Abrégé

A semiconductor structure and a forming method thereof are provided. In one form, a semiconductor structure includes: a substrate; discrete channel structures on the substrate in device regions; a power rail line, located in the substrate of a power rail region; a gate structure, extending across the channel structures; source/drain doped regions, located in the channel structures on two sides of the gate structure; an interlayer dielectric layer, located at a side portion of the gate structure; a power rail contact plug, penetrating a partial thickness of the interlayer dielectric layer at a top of the power rail line, where the power rail contact plug is in full contact with a top surface of the power rail line in a longitudinal direction; and a source/drain contact layer, located in the interlayer dielectric layer and in contact with the source/drain doped region, where on a projection surface parallel to the substrate, the source/drain contact layer extends across the power rail line. The power rail contact plug is in full contact with the top surface of the power rail line in the longitudinal direction, and a dimension of the power rail contact plug in the longitudinal direction and a contact area between the power rail contact plug and the power rail line are increased, to further help to reduce a resistance of the power rail contact plug and a contact resistance between the power rail line and the power rail contact plug.

Classes IPC  ?

• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/40 - Electrodes
• H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p.ex. structures d'interconnexions enterrées
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
• H01L 23/528 - Configuration de la structure d'interconnexion

Abrégé

A semiconductor structure and a method for fabricating the semiconductor structure are provided in the present disclosure. The method includes providing a substrate, wherein the substrate includes a plurality of first regions to-be-etched extending along a first direction; a first region to-be-etched includes a central region and an edge region adjacent to each of two sides of the central region; and a material layer to-be-etched is on the substrate; forming a plurality of discrete initial mask structures on the material layer to-be-etched; etching initial mask structures at the edge region till a surface of the material layer to-be-etched is exposed to form a plurality of mask structures; using the plurality of mask structures as a mask, etching the material layer to-be-etched to form a plurality of discrete layers to-be-etched; and removing layers to-be-etched at the central region till a surface of the substrate is exposed.

Classes IPC  ?

• H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques

Abrégé

A method for forming a semiconductor structure is provided. In one form, a method includes: providing a base, where the base includes first regions and a second region located between the first regions; forming a pattern definition layer on the base; forming discrete mask layers on the pattern definition layer, the mask layers and the base defining openings, where openings of the first regions serve as first openings, and an opening of the second region serves as a second opening; forming a filling layer in the second opening; and etching, using the mask layers and the filling layer as masks, the pattern definition layer exposed from the first openings, to form target patterns. In embodiments and implementations of this application, the filling layer is formed between the mask layers of the second region, to obtain a mask that finally etches the pattern definition layer, so that the formed target patterns meet process requirements, which is conducive to improving electrical performance of the semiconductor structure.

Classes IPC  ?

• H01L 21/308 - Traitement chimique ou électrique, p.ex. gravure électrolytique en utilisant des masques

Abrégé

A wet etching method is provided in the present disclosure. The method includes providing a substrate, where a layer to-be-etched is on a surface of the substrate; and performing etching treatments on the layer to-be-etched till a thickness of the layer to-be-etched reaches a target thickness. Each etching treatment includes performing a first etching process, where the substrate is at a first rotation speed; after the first etching process, performing a second etching process, where a rotation speed of the substrate is reduced from the first rotation speed to a second rotation speed, and a liquid film of a chemical solution on the surface of the substrate is increased to a first thickness; and after the second etching process, performing a third etching process, where the substrate is at a third rotation speed, and the third rotation speed is lower than or equal to the first rotation speed.

Classes IPC  ?

• H01L 21/3213 - Gravure physique ou chimique des couches, p.ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
• C09K 13/04 - Compositions pour l'attaque chimique, la gravure, le brillantage de surface ou le décapage contenant un acide inorganique
• C09K 13/08 - Compositions pour l'attaque chimique, la gravure, le brillantage de surface ou le décapage contenant un acide inorganique contenant un composé du fluor
• C09K 13/00 - Compositions pour l'attaque chimique, la gravure, le brillantage de surface ou le décapage

Abrégé

A semiconductor structure is provided. The semiconductor structure includes: a fin heat-dissipation region on a substrate; a fin channel part on the fin heat-dissipation region, and an isolation structure on the substrate. A width of the fin channel part is smaller than a width of the fin heat-dissipation region. A top surface of the isolation structure is coplanar with a top surface of the fin heat-dissipation region.

Classes IPC  ?

• H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/76 - Réalisation de régions isolantes entre les composants
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 23/367 - Refroidissement facilité par la forme du dispositif

Abrégé

A semiconductor structure formation method and a mask are provided. One form of the formation method includes: providing a base, including a target layer; forming a mandrel material layer on the base, the mandrel material layer including a first region and a second region encircling the first region; performing ion doping on the mandrel material layer in the second region, the ion doping being suitable for increasing the etching resistance of the mandrel material layer, where the mandrel material layer in the second region serves as an anti-etching layer, and the mandrel material layer in the first region serves as a mandrel layer; forming a first trench that runs through, along a first direction, at least part of the mandrel material layer in the first region, where part of the mandrel material layer in the first region remains at two sides of the first trench along a second direction; forming spacers on side walls of the first trench, so that the spacers form a first groove by encircling; removing the mandrel layer to form second grooves; and etching, using the anti-etching layer and the spacers as masks, the target layer below the first groove and the second grooves, to form the target pattern. In embodiments and implementations of the present disclosure, a pitch between target patterns is further compressed.

Classes IPC  ?

• H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
• H01L 21/311 - Gravure des couches isolantes
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 21/3215 - Dopage des couches
• H01L 21/3115 - Dopage des couches isolantes

Abrégé

A method for forming a semiconductor structure in provided. The method includes providing a substrate, forming a gate electrode layer on the substrate, and performing a defluorination treatment on the gate electrode layer. The method also includes, after performing the defluorination treatment, forming a barrier layer on a portion of a surface of the gate electrode layer. The barrier layer is made of a material including titanium element.

Classes IPC  ?

• H01L 21/285 - Dépôt de matériaux conducteurs ou isolants pour les électrodes à partir d'un gaz ou d'une vapeur, p.ex. condensation
• H01L 21/477 - Traitement thermique pour modifier les propriétés des corps semi-conducteurs, p.ex. recuit, frittage
• H01L 21/8234 - Technologie MIS
• H01L 21/321 - Post-traitement
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives

Abrégé

A semiconductor structure and a forming method thereof are provided. One form of a semiconductor structure includes: a first device structure, including a first substrate and a first device formed on the first substrate, the first device including a first channel layer structure located on the first substrate, a first device gate structure extending across the first channel layer structure, and a first source-drain doping region located in the first channel layer structure on two sides of the first device gate structure; and a second device structure, located on a front surface of the first device structure, including a second substrate located on the first device structure and a second device formed on the second substrate, the second device including a second channel layer structure located on the second substrate, a second device gate structure extending across the second channel layer structure, and a second source-drain doping region located in the second channel layer structure on two sides of the second device gate structure, where projections of the second channel layer structure and the first channel layer structure onto the first substrate intersect non-orthogonally. The electricity of the first device can be led out according to the present disclosure.

Classes IPC  ?

• H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
• H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
• H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

A capacitor structure and a forming method thereof are provided. The capacitor structure includes a substrate and a bottom electrode composite layer on the substrate. The bottom electrode composite layer includes a first electrode layer and a second electrode layer on the first electrode layer. An oxidation rate of a material of the second electrode layer is lower than an oxidation rate of a material of the first electrode layer. The capacitor structure also includes a dielectric structure layer on the bottom electrode composite layer.

Classes IPC  ?

• H01L 49/02 - Dispositifs à film mince ou à film épais
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 27/08 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type

Abrégé

A semiconductor structure and a forming method therefor. The forming method comprises: providing a substrate comprising a target layer, wherein the substrate comprises a target region used for forming a target pattern layer, and a cutting region corresponding to a cutting position; forming a mask sidewall on the substrate; using the mask sidewall as a mask, and patterning the target layer to form discrete initial pattern layers, wherein the initial pattern layers extend along a transverse direction, a direction perpendicular to the transverse direction is a longitudinal direction, and a groove is formed between adjacent initial pattern layers along the longitudinal direction; forming a boundary defining groove passing through the initial pattern layer that is located at a junction position between the target region and the cutting region; forming spacer layers that are filled in the groove and the boundary defining groove; and enabling the spacer layer located in the boundary defining groove and the spacer layer located in the groove to respectively correspond to a transverse stop layer and a longitudinal stop layer, etching the initial pattern layer located in the cutting region, and using the remaining initial pattern layer located in the target region as the target pattern layer. The embodiments of the present invention facilitates the increasing of a process window for etching the initial pattern layer of the cutting region.

Classes IPC  ?

• H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques