Silicon Motion, Inc.

Taïwan, Province de Chine

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Type PI
        Brevet 1 008
        Marque 22
Juridiction
        États-Unis 1 026
        Europe 4
Date
Nouveautés (dernières 4 semaines) 13
2024 juin (MACJ) 9
2024 mai 13
2024 avril 11
2024 mars 8
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Classe IPC
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement 442
G06F 12/02 - Adressage ou affectation; Réadressage 309
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11 156
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires 111
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence 96
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Classe NICE
09 - Appareils et instruments scientifiques et électriques 21
42 - Services scientifiques, technologiques et industriels, recherche et conception 12
Statut
En Instance 85
Enregistré / En vigueur 945
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1.

METHOD AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM AND APPARATUS FOR EXECUTING HOST WRITE COMMANDS

      
Numéro d'application 18383063
Statut En instance
Date de dépôt 2023-10-24
Date de la première publication 2024-06-20
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Chiu, Shen-Ting

Abrégé

The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for executing host write commands. The method performed by a processing unit includes: providing a sequential-write command queue (SCQ), a random-write command queue (RCQ) and a mark queue; receiving a host write command from a host side; and pushing a record into the mark queue and pushing the host write command into the SCQ or the RCQ according to a length of the first logical address range carried in the host write command when detecting that a first logical address range carried in the host write command conflicts with a second logical address range carried in at least one sequential write command and/or a third logical address range carried in at least one random write command, where the record indicates that a conflicting sequential write command and/or a conflicting random write command needs to be processed earlier than the host write command.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage

2.

Data storage device and method for performing error recovery

      
Numéro d'application 18219714
Statut En instance
Date de dépôt 2023-07-10
Date de la première publication 2024-06-20
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Shih, Fu-Jen

Abrégé

A data storage device includes an interface circuit to process reception signals received from a peer device and transmission signals to be transmitted to the peer device. The interface circuit includes at least one signal processing circuit to perform an error recovery procedure when an error has occurred in the data storage device. When performing the error recovery procedure, the signal processing circuit performs an operation of periodic line reset to repeatedly transmit a line reset signal to the peer device within a predetermined period until the predetermined period expires or another line reset signal representing an acknowledgment of the line reset signal has been received from the peer device.

Classes IPC  ?

  • G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
  • G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p.ex. en utilisant différentes séquences d'opérations aboutissant au même résultat

3.

Data storage device and method for dynamically determining a buffer size

      
Numéro d'application 18218014
Statut En instance
Date de dépôt 2023-07-04
Date de la première publication 2024-06-20
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Wu, Po-Wei

Abrégé

A data storage device includes a memory device and a memory controller. The memory device has a corresponding total storage capacity and includes multiple memory blocks. The total storage capacity is set to a maximum storage capacity provided by the memory blocks by default. The memory blocks include one or more predetermined memory blocks configured as a buffer to receive data from a host device. The memory controller is coupled to the memory device to access the memory device. In response to setting of a maximum amount of write data, the memory controller determines a value of the total storage capacity according to the maximum amount of write data, and determines a number of said one or more predetermined memory blocks according to the value of the total storage capacity and the maximum storage capacity.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

4.

METHOD AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM AND APPARATUS FOR EXECUTING HOST WRITE COMMANDS

      
Numéro d'application 18383239
Statut En instance
Date de dépôt 2023-10-24
Date de la première publication 2024-06-20
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Chiu, Shen-Ting

Abrégé

The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for executing host write commands. The method performed by a processing unit includes: providing a sequential-write command queue (SCQ), a random-write command queue (RCQ) and a mark queue; when a specific condition is met, obtaining a first logical address range carried in the conflicting sequential write command and second logical address ranges carried in the sequential write commands earlier than the conflicting sequential write command from the SCQ, and/or a third logical address range carried in the conflicting random write command and fourth logical address ranges carried in the random write commands earlier than the conflicting random write command from the RCQ according to content of the record; reading user data of the first logical address range from a first address of the RAM and user data of the second logical address ranges from second addresses of the RAM, and/or user data of the third logical address range from a third address of the RAM and user data of the fourth logical address ranges from fourth addresses of the RAM; and programming the user data of the first logical address range and the second logical address ranges, and/or the user data of the third logical address range and the fourth logical address ranges into the flash module.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

5.

Data storage device and method for performing error recovery

      
Numéro d'application 18219087
Statut En instance
Date de dépôt 2023-07-06
Date de la première publication 2024-06-20
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Shih, Fu-Jen

Abrégé

A data storage device includes at least one signal processing circuit to perform an error recovery procedure when an error has occurred in the data storage device. When performing the error recovery procedure, the signal processing circuit determines which type of line reset is to be performed according to a device identifier. When the device identifier satisfies a predetermined condition, the signal processing circuit performs an operation of periodic line reset to repeatedly transmit a line reset signal to the peer device in a predetermined period until the predetermined period expires or another line reset signal representing an acknowledgment of the line reset signal is received from the peer device; and when the device identifier does not satisfy the predetermined condition, the signal processing circuit performs an operation of one-shot line reset to transmit the line reset signal to the peer device for only one time.

Classes IPC  ?

  • G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
  • G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts

6.

FLASH MEMORY MODULE TESTING METHOD AND ASSOCIATED MEMORY CONTROLLER AND MEMORY DEVICE

      
Numéro d'application 18236409
Statut En instance
Date de dépôt 2023-08-22
Date de la première publication 2024-06-13
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Chang, Chiu-Han
  • Chen, Yu-Ting

Abrégé

A method for performing a test upon a flash memory module includes: performing data writing upon a plurality of first blocks of a first group in the flash memory module; reading the plurality of first blocks of the first group to determine whether there is any abnormal block in the plurality of first blocks and generating a first test result; after the plurality of first blocks are read, performing data writing upon a plurality of second blocks of a second group in the flash memory module; and reading the plurality of second blocks of the second group to determine whether there is any abnormal block in the plurality of second blocks and generating a second test result.

Classes IPC  ?

  • G11C 29/10 - Algorithmes de test, p.ex. algorithmes par balayage de mémoire [MScan]; Configurations de test, p.ex. configurations en damier

7.

METHOD OF MANAGING INDEPENDENT WORD LINE READ OPERATION IN FLASH MEMORY AND RELATED MEMORY CONTROLLER AND STORAGE DEVICE

      
Numéro d'application 18078077
Statut En instance
Date de dépôt 2022-12-08
Date de la première publication 2024-06-13
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tzu-Yi

Abrégé

A method of managing operation commands for a flash memory includes: providing a first command queue for receiving and storing a plurality of normal operation commands; providing at least one word line read (IWLR) command queue for receiving and storing a plurality of IWLR operation commands; issuing a lock state command between each two consecutive IWLR operation commands to the at least one second command queue; determining a selected command queue from the first command queue and the at least one IWLR command queues according to the lock state command; and delivering an operation command from the selected command queue to the flash memory.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

8.

FLASH MEMORY CONTROLLER AND ASSOCIATED MEMORY DEVICE AND CONTROL METHOD

      
Numéro d'application 18233897
Statut En instance
Date de dépôt 2023-08-15
Date de la première publication 2024-06-06
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Tsai, Ming-Yu

Abrégé

A flash memory controller is arranged to access a flash memory module, and includes a transmission interface circuit, a buffer memory, and a microprocessor. The transmission interface circuit is coupled to a host device, wherein the transmission interface circuit includes a command processing circuit, the command processing circuit is arranged to receive a command from the host device and convert the command to generate a converted command of a specific format, the command supports multiple formats, and the specific format is different from the multiple formats. The buffer memory is arranged to store the converted command. The microprocessor is arranged to read the converted command from the buffer memory, and access the flash memory module according to the converted command.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

9.

FLASH MEMORY CONTROLLER AND ASSOCIATED MEMORY DEVICE AND CONTROL METHOD

      
Numéro d'application 18236398
Statut En instance
Date de dépôt 2023-08-21
Date de la première publication 2024-06-06
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Tsai, Ming-Yu

Abrégé

A flash memory controller is arranged to access a flash memory module, and includes a transmission interface circuit a buffer memory, and a microprocessor. The transmission interface circuit is coupled to a host device, wherein the transmission interface circuit includes a command processing circuit, and the command processing circuit is arranged to: receive a command from the host device; utilize multiple check items to check the command to generate at least one check result; and convert the command to generate a converted command of a specific format, wherein the converted command comprises an error state field for recording the at least one check result. The buffer memory is arranged to store the converted command. The microprocessor is arranged to read the converted command from the buffer memory, and access the flash memory module according to the converted command.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

10.

FLASH MEMORY CONTROLLER THAT CAN QUICKLY ENTER POWER SAVING MODE AFTER ENTERING IDLE STATE, ASSOCIATED FLASH MEMORY DEVICE, AND ASSOCIATED CONTROL METHOD

      
Numéro d'application 18220240
Statut En instance
Date de dépôt 2023-07-10
Date de la première publication 2024-05-30
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Lin, Wen-Sheng

Abrégé

A control method of a memory device includes: controlling a flash memory controller to transmit a command to a flash memory module; determining whether the flash memory controller is in an idle state; in response to the flash memory controller being in the idle state, determining whether an idle time of the idle state exceeds a threshold value, wherein the threshold value is less than a time required for the flash memory module to complete executing a write command or an erase command; and in response to the idle time exceeding the threshold value, controlling the flash memory controller to enter a power saving mode to turn off a part of components in the flash memory controller.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

11.

METHOD AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM AND APPARATUS FOR EXECUTING HOST COMMANDS

      
Numéro d'application 18368890
Statut En instance
Date de dépôt 2023-09-15
Date de la première publication 2024-05-30
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Chiu, Shen-Ting

Abrégé

The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for executing host commands. The method performed by a processing unit includes: setting a first start register and a first end register to store a first logical address range from a first start logical address to a first end logical address for an execution of a host command; providing a sequential update queue including multiple entries; setting an activation register to drive a search engine; checking values of a matching register and a resulting address register of the search engine to determine whether a whole or a portion of data of the first logical address range is temporarily stored in the RAM after a time period; and if so, manipulating the whole or a portion of data of the first logical address range that is temporarily stored in the RAM.

Classes IPC  ?

  • G11C 16/10 - Circuits de programmation ou d'entrée de données

12.

APPARATUS AND METHOD FOR SEARCHING FOR LOGICAL ADDRESS RANGES OF HOST COMMANDS

      
Numéro d'application 18369046
Statut En instance
Date de dépôt 2023-09-15
Date de la première publication 2024-05-30
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Chen, Chun-Yu

Abrégé

The invention relates to an apparatus for searching for logical address ranges of host commands. The first comparator outputs logic “0” to the NOR gate when a first end logical address is not smaller than a second start logical address. The second comparator outputs logic “0” to the NOR gate when a second end logical address is not smaller than a first start logical address. The NOR gate outputs logic “1” to a matching register and an output circuitry when receiving logic “0” from both the first and the second comparators. The output circuitry outputs a memory address of a random access memory (RAM) storing a second logical address range from the second start logical address to the second end logical address to a resulting address register when receiving logic “1” from the NOR gate.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
  • H03K 3/037 - Circuits bistables

13.

DATA STORAGE DEVICE AND DATA PROTECTION METHOD THEREOF

      
Numéro d'application 18389227
Statut En instance
Date de dépôt 2023-11-14
Date de la première publication 2024-05-23
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Chien, Jieh-Hsin
  • Pao, Yi-Hua

Abrégé

A data protection method applied to a data storage device including a volatile memory and a non-volatile flash memory is provided. The data protection method includes, executing a protection program after the data storage device is coupled to a host, to perform following steps: shielding a refresh command from the host; monitoring a working voltage of the data storage device through a voltage sensing module; determining whether the working voltage is lower than a threshold; when it is determined that the working voltage is lower than the threshold, providing the data storage device with power to trigger the refresh command to write the data in the volatile memory into the non-volatile flash memory. Therefore, the writing times of the data storage device are reduced, the performance degradation of the data storage device is avoided, and the service life of the data storage device is extended.

Classes IPC  ?

  • G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
  • G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p.ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation

14.

VIDEO WALL SYSTEM

      
Numéro d'application 18487324
Statut En instance
Date de dépôt 2023-10-16
Date de la première publication 2024-05-16
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Qian, Xiaobing

Abrégé

A video wall system with software running on a host computer and a video wall control device is shown. Using the software, the user inputs the size of each screen of a video wall and, accordingly, the delay time for each row of screens of the video wall is calculated. The video wall control device couples the host computer to the screens. The video wall control device outputs a plurality of split videos to the different screens through separated output ports, and drives each row of screens to display according to the delay time calculated for the row of screens.

Classes IPC  ?

  • G06F 3/14 - Sortie numérique vers un dispositif de visualisation
  • G06F 3/147 - Sortie numérique vers un dispositif de visualisation utilisant des panneaux de visualisation

15.

Firmware updating method and data storage device utilizing the same

      
Numéro d'application 18219114
Statut En instance
Date de dépôt 2023-07-07
Date de la première publication 2024-05-09
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Wang, Te-Kai

Abrégé

A data storage device includes a memory device and a memory controller. The memory controller executes a first firmware, sets a value of a lock indicator to a first value and receives a first firmware update command in the first firmware. In response to the first firmware update command, the memory controller receives a file of a second firmware. When a version number of the second firmware is a specific version number, the memory controller sets the value of the lock indicator to a second value. When the version number of the second firmware is not a specific version number, the memory controller performs an unlocked firmware update procedure when the value of the lock indicator is set to the second value, and performs a locked firmware update procedure when the value of the lock indicator is not set to the second value.

Classes IPC  ?

16.

METHOD AND APPARATUS FOR EXECUTING STRUCTURAL QUERY LANGUAGE INSTRUCTION IN SOLID-STATE STORAGE DEVICE

      
Numéro d'application 18384515
Statut En instance
Date de dépôt 2023-10-27
Date de la première publication 2024-05-09
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lai, Bo-Cheng
  • Kuo, Yen-Shi

Abrégé

The invention relates to a method and an apparatus for executing Structural Query Language (SQL) instructions in a Solid-state Storage Device (SSD). The apparatus includes: a processing unit; and a database accelerator. The processing unit is arranged operably to obtain an SQL query from a host side. The database accelerator is arranged operably to parse the SQL query according an SQL syntax tree to generate a series of table tasks to execute; and during the execution of the table tasks, read tables from a flash module through the processing unit, generate intermediate tables and sub-tables based on the read tables, and perform an arithmetic computation, a logical computation or both on a specific field in one intermediate table to generate a final dataset. The processing unit is arranged operably to reply to the host side with the final dataset.

Classes IPC  ?

  • G06F 16/2455 - Exécution des requêtes
  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G06F 16/22 - Indexation; Structures de données à cet effet; Structures de stockage

17.

Firmware updating method and data storage device utilizing the same

      
Numéro d'application 18218600
Statut En instance
Date de dépôt 2023-07-06
Date de la première publication 2024-05-09
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Wang, Te-Kai

Abrégé

A data storage device includes a memory device and a memory controller. The memory controller executes a first firmware, sets a value of a lock indicator to a first value in the first firmware, and sequentially receive a first firmware update command and a second firmware update command. In response to the first firmware update command, the memory controller receives file of a second firmware. When determining that a version number of the second firmware is set to a specific version number, the memory controller sets the value of the lock indicator to a second value. In response to the second firmware update command, the memory controller receives a file of a third firmware. When the value of the lock indicator is set to the second value, the memory controller performs a firmware update procedure to the first firmware with the third firmware.

Classes IPC  ?

18.

Flash memory controller

      
Numéro d'application 18412635
Statut En instance
Date de dépôt 2024-01-15
Date de la première publication 2024-05-09
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Yang, Tsung-Chieh
  • Kuo, Chun-Chieh
  • Lin, Ching-Hui
  • Shen, Yang-Chih

Abrégé

A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence

19.

FLASH MEMORY APPARATUS AND STORAGE MANAGEMENT METHOD FOR FLASH MEMORY

      
Numéro d'application 18413007
Statut En instance
Date de dépôt 2024-01-15
Date de la première publication 2024-05-09
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Yang, Tsung-Chieh
  • Hsu, Hong-Jung

Abrégé

A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

Classes IPC  ?

  • H03M 13/09 - Détection d'erreurs uniquement, p.ex. utilisant des codes de contrôle à redondance cyclique [CRC] ou un seul bit de parité
  • G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
  • G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
  • G11C 16/10 - Circuits de programmation ou d'entrée de données
  • H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
  • H03M 13/15 - Codes cycliques, c. à d. décalages cycliques de mots de code produisant d'autres mots de code, p.ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]

20.

APPARATUS AND METHOD FOR DETECTING ERRORS DURING DATA ENCRYPTION

      
Numéro d'application 18203305
Statut En instance
Date de dépôt 2023-05-30
Date de la première publication 2024-05-02
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Wu, Wun-Jhe
  • Chen, Po-Hung
  • Cheng, Chiao-Wen
  • Yu, Jiun-Hung
  • Liu, Chih-Wei

Abrégé

The invention introduces an apparatus for detecting errors during data encryption. The apparatus includes a search circuitry and a substitution check circuitry. The key generation circuitry is arranged operably to convert a first value of one byte corresponding to a plaintext, an intermediate encryption result, or a round key into a second value of a K-bit according to an 8-to-K lookup table, where K is an integer ranging from 10 to 15 and the second value comprises (K minus 8) bits of a Hamming parity. The substitution check circuitry is arranged operably to employ check formulae corresponding to the 8-to-K lookup table to determine whether an error is occurred during a conversion of the first value of the one byte into the second value of the K-bit, and output an error signal when finding the error, where a total amount of the formulae is K minus 8.

Classes IPC  ?

  • G06F 21/60 - Protection de données
  • H03M 13/15 - Codes cycliques, c. à d. décalages cycliques de mots de code produisant d'autres mots de code, p.ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]

21.

Data storage device and method for determining buffer size of the data storage device

      
Numéro d'application 18219101
Statut En instance
Date de dépôt 2023-07-07
Date de la première publication 2024-05-02
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Wu, Po-Lin

Abrégé

A data storage device includes a memory device and a memory controller. The memory device includes multiple memory blocks which include one or more spare memory blocks not written with data and one or more predetermined memory blocks that are configured as a buffer for receiving data from a host device. The memory controller obtains a total number of remaining erasable count of the memory blocks and determines a setting value of a number of said one or more predetermined memory blocks according to a number of currently remaining spare memory block(s), a number of the predetermined memory block(s) that has/have been written with data among said one or more predetermined memory blocks, a predetermined threshold and the total number of remaining erasable count of the memory blocks, and configures the number of the predetermined memory block(s) as the buffer according to the setting value.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

22.

Data storage device and method for managing a write buffer

      
Numéro d'application 18220293
Statut En instance
Date de dépôt 2023-07-11
Date de la première publication 2024-05-02
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Wu, Po-Lin

Abrégé

A data storage device includes a memory device and a memory controller. The memory device includes multiple predetermined memory blocks that are configured as a buffer for receiving data from a host device. The memory controller performs a write operation in response to a write command, and during the write operation, the memory controller maintains a first quantity count value for counting a number of the predetermined memory block(s) that has/have been written with data, determine a number of the predetermined memory block(s) which is/are released in response to the write operation and maintains a second quantity count value based on this number. After the write operation, the memory controller performs a garbage collection and updates the first quantity count value based on the second quantity count value when determining that the host device has requested to perform a flush operation on the predetermined memory blocks.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

23.

MEMORY OPERATION METHOD AND MEMORY DEVICE

      
Numéro d'application 18330349
Statut En instance
Date de dépôt 2023-06-05
Date de la première publication 2024-04-25
Propriétaire SILICON MOTION INC. (Taïwan, Province de Chine)
Inventeur(s)
  • Chou, Po-Sheng
  • Huang, Hsiang-Yu
  • Wang, Yan-Wen

Abrégé

A memory operation method, comprising: when a first super block of a memory device is a open block (or in programming state), obtaining a first read count of one of a plurality of first memory blocks in the first super block, wherein the first read count is a number of times that data of one of the first memory blocks is read out; determining whether the first read count is larger than a first threshold; and when the first read count is larger than the first threshold, moving a part of the data in the first super block to a safe area in the memory device, wherein the part of the data comprises data in the first memory block.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

24.

Data storage device and method for determining buffer size of the data storage device

      
Numéro d'application 18219705
Statut En instance
Date de dépôt 2023-07-10
Date de la première publication 2024-04-18
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Wu, Po-Lin

Abrégé

A data storage device includes a memory device and a memory controller. The memory device includes multiple memory blocks. The memory blocks includes one or more spare memory blocks that are not written with data and one or more predetermined memory blocks that are configured as a buffer for receiving data from a host device. The memory controller is coupled to the memory device and configured to access the memory device. The memory controller is configured to determine a setting value of a number of said one or more predetermined memory blocks according to a number of currently remaining spare memory block(s), a number of the predetermined memory block(s) that has/have been written with data among said one or more predetermined memory blocks and a predetermined threshold, and configure the number of the predetermined memory block(s) as the buffer according to the setting value.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 12/02 - Adressage ou affectation; Réadressage

25.

Data storage device and method for managing a write buffer

      
Numéro d'application 18220288
Statut En instance
Date de dépôt 2023-07-11
Date de la première publication 2024-04-18
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Wu, Po-Lin

Abrégé

A data storage device includes a memory device and a memory controller. The memory device includes multiple predetermined memory blocks that are configured as a buffer for receiving data from a host device. The memory controller performs a write operation in response to a write command issued by the host device, and during the write operation, the memory controller maintains a first quantity count value for counting a number of the predetermined memory block(s) that has/have been written with data, determines a number of the predetermined memory block(s) which is/are released in response to the write operation and maintains a second quantity count value based on this number. After the write operation, the memory controller updates the first quantity count value based on the second quantity count value when determining that the host device has requested to perform a flush operation on the predetermined memory blocks.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

26.

Method for Reading Data Stored in a Flash Memory According to a Voltage Characteristic and Memory Controller Thereof

      
Numéro d'application 18515691
Statut En instance
Date de dépôt 2023-11-21
Date de la première publication 2024-04-18
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tsung-Chieh

Abrégé

A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage. The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.

Classes IPC  ?

  • G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
  • G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
  • G11C 16/06 - Circuits auxiliaires, p.ex. pour l'écriture dans la mémoire
  • G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention

27.

METHOD AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM AND APPARATUS FOR SCHEDULING AND EXECUTING HOST DATA-UPDATE COMMANDS

      
Numéro d'application 18230364
Statut En instance
Date de dépôt 2023-08-04
Date de la première publication 2024-04-11
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yao, Yu-Hsien

Abrégé

The invention introduces a method for scheduling and executing host data-update commands. A first queue and a second queue are provided. The first queue includes first host data-update commands each including a first logical address. The second queue includes second host data-update commands each including a second logical address. A third host data-update command including a third logical address is generated and is labeled as a first type of host data-update command according to a host command received from a host side. All the first host data-update commands of the first queue are popped out and executed in response that the third logical address is the same as any first logical address. All the second host data-update commands of the second queue are popped out and executed in response that the third logical address is the same as any second logical address.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

28.

BRIDGE CONTROL CHIP AND ASSOCIATED SIGNAL PROCESSING METHOD

      
Numéro d'application 18109269
Statut En instance
Date de dépôt 2023-02-14
Date de la première publication 2024-04-11
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Huang, Guo-Rung
  • Chang, Chun-Chieh
  • Huang, Hsing-Lang

Abrégé

A bridge control chip includes a first interface, a second interface, and a processor, wherein the first interface is coupled to a host device, the second interface is coupled to a memory device, and the memory device is a flash memory device. The processor is arranged to execute commands in a queue in sequence, to transmit the commands in the queue to the memory device through the second interface in sequence, wherein when the processor receives one or more received commands from the host device, the processor sorts the one or more received commands and commands which are currently and temporarily stored in the queue according to a distance between a logical address of each of the one or more received commands and a logical address of a current command in the queue that is currently executed by the processor.

Classes IPC  ?

  • G06F 13/18 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire avec commande prioritaire
  • G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
  • G06F 13/40 - Structure du bus

29.

METHOD AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM AND APPARATUS FOR SCHEDULING AND EXECUTING HOST DATA-UPDATE COMMANDS

      
Numéro d'application 18230391
Statut En instance
Date de dépôt 2023-08-04
Date de la première publication 2024-04-11
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yao, Yu-Hsien

Abrégé

The invention introduces a method for scheduling and executing host data-update commands. A first queue and a second queue are provided. The first queue includes first host data-update commands each including a first logical address. The second queue includes second host data-update commands each including a second logical address. A third host data-update command including a third logical address is generated and is labeled as a first type of host data-update command according to a host command received from a host side. A redundant first logical address is removed from a matched one of the first host data-update commands in response that the third logical address is the same as any first logical address. A redundant second logical address is removed from a matched one of the second host data-update commands in response that the third logical address is the same as any second logical address.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

30.

FLASH MEMORY SCHEME CAPABLE OF AUTOMATICALLY GENERATING OR REMOVING DUMMY DATA PORTION OF FULL PAGE DATA BY USING FLASH MEMORY DEVICE

      
Numéro d'application 17956855
Statut En instance
Date de dépôt 2022-09-30
Date de la première publication 2024-04-04
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lu, Tsu-Han
  • Yen, Hsiao-Chang

Abrégé

A method of a flash memory controller includes: controlling an I/O circuit using a set-feature signal, which carries a set-feature command, feature address, and parameter information, and transmitting the set-feature signal to a flash memory device; the feature address corresponds to a valid data portion or a dummy data portion following the valid data portion, and both the valid data portion and dummy data portion are comprised in a full page data which is to be written into a physical page unit of the flash memory device or to be read out from the physical page unit; the corresponding parameter information is used to record the valid data portion's column address and data length, the dummy data portion's column address and data length, the dummy data portion's column address and the valid data portion's, or the dummy data portion's data length and the valid data portion's data length.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

31.

STORAGE DEVICE CONTROLLER AND METHOD CAPABLE OF ALLOWING INCOMING OUT-OF-SEQUENCE WRITE COMMAND SIGNALS

      
Numéro d'application 17958430
Statut En instance
Date de dépôt 2022-10-02
Date de la première publication 2024-04-04
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Chen, Li-Chi
  • Jou, Yen-Yu

Abrégé

A method of a storage device controller includes: using an interface circuit for receiving and storing different write address information of different write command signals sent from a host device, the different write address information being out of sequence; and, using multiple processor cores to rearrange the different write address information in sequence and then write data into at least one storage zone according to the different write address information rearranged in sequence.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

32.

Method and apparatus for performing access management of memory device in host performance booster architecture with aid of device side table information encoding and decoding

      
Numéro d'application 17959320
Numéro de brevet 11994985
Statut Délivré - en vigueur
Date de dépôt 2022-10-04
Date de la première publication 2024-04-04
Date d'octroi 2024-05-28
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Lin, Yu-Chih

Abrégé

A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information encoding and decoding are provided. The method may include: encoding internal information of the memory device and sending encoded result thereof to a host device, to allow the host device to store the encoded result in a memory within the host device as host-owned encoded device side table information at the host device; generating and storing multiple entries of address mapping control table into a RAM as at least one portion of device side table information at the memory device; decoding partial information of the host-owned encoded device side table information, performing checking operation on decoded result thereof, and selectively using the decoded result to determine physical address associated with logical address; and reading data from the NV memory according to the physical address.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage

33.

Method and apparatus for performing access management of memory device in host performance booster architecture with aid of device side table information encoding and decoding

      
Numéro d'application 17959308
Numéro de brevet 11995349
Statut Délivré - en vigueur
Date de dépôt 2022-10-04
Date de la première publication 2024-04-04
Date d'octroi 2024-05-28
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Lin, Yu-Chih

Abrégé

A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information encoding and decoding are provided. The method may include: encoding internal information of the memory device and sending encoded result thereof to a host device, to allow the host device to store the encoded result in a memory within the host device as host-owned encoded device side table information at the host device; generating and storing multiple entries of address mapping control table into a RAM as at least one portion of device side table information at the memory device; decoding partial information of the host-owned encoded device side table information, performing checking operation on decoded result thereof, and selectively using the decoded result to determine physical address associated with logical address; and reading data from the NV memory according to the physical address.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

34.

Data processing method for efficiently processing data stored in the memory device by splitting data flow and the associated data storage device

      
Numéro d'application 18223558
Statut En instance
Date de dépôt 2023-07-19
Date de la première publication 2024-03-28
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Chen, Yu-Ta

Abrégé

A data storage device includes a memory device and a memory controller. The memory controller uses a first predetermined memory block as a buffer to receive data from a host device. In response to a write command received from the host device, the memory controller determines a sub-region corresponding to the write command, determines whether the sub-region is a hot-write sub-region according to a write count corresponding to the sub-region and accordingly determines whether to use a second predetermined memory block as another buffer to receive data from the host device. When the memory controller determines that the sub-region corresponding to the write command is a hot-write sub-region, the memory controller writes the data into the second predetermined memory block. When the memory controller determines that the sub-region is not a hot-write sub-region, the memory controller writes the data into the first predetermined memory block.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 12/1009 - Traduction d'adresses avec tables de pages, p.ex. structures de table de page

35.

Data processing method for improving continuity of data corresponding to continuous logical addresses as well as avoiding excessively consuming service life of memory blocks and the associated data storage device

      
Numéro d'application 18142579
Statut En instance
Date de dépôt 2023-05-02
Date de la première publication 2024-03-28
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Chen, Yu-Ta

Abrégé

A data storage device includes a memory device and a memory controller. When a sub-region of the memory device is selected based on a predetermined rule to perform a data rearrangement procedure, the memory controller determines whether the selected sub-region is a system data sub-region. When determining that the selected sub-region is not a system data sub-region, the memory controller performs the data rearrangement procedure on the selected sub-region to move data corresponding to logical addresses belonging to the selected sub-region to a memory space of the memory device having continuous physical addresses, and when determining that the selected sub-region is a system data sub-region, the memory controller does not perform the data rearrangement procedure on the selected sub-region.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

36.

Data processing method for efficiently processing data stored in the memory device by splitting data flow and the associated data storage device

      
Numéro d'application 18204386
Statut En instance
Date de dépôt 2023-05-31
Date de la première publication 2024-03-28
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Chen, Yu-Ta

Abrégé

A data storage device includes a memory device and a memory controller. The memory controller uses a first predetermined memory block as a buffer to receive data from a host device. In response to a write command received from the host device, the memory controller determines a sub-region corresponding to the write command, determines whether the sub-region is a system data sub-region and accordingly determines whether to use a second predetermined memory block as another buffer to receive data from the host device. When the memory controller determines that the sub-region corresponding to the write command is a system data sub-region, the memory controller writes the data into the second predetermined memory block. When the memory controller determines that the sub-region corresponding to the write command is not a system data sub-region, the memory controller writes the data into the first predetermined memory block.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

37.

Data processing method for improving continuity of data corresponding to continuous logical addresses as well as avoiding excessively consuming service life of memory blocks and the associated data storage device

      
Numéro d'application 18142590
Statut En instance
Date de dépôt 2023-05-03
Date de la première publication 2024-03-28
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Chen, Yu-Ta

Abrégé

A data storage device includes a memory device and a memory controller. The memory controller maintains a write count for each sub-region of the memory device. When the memory controller has selected one or more sub-regions to perform a data rearrangement procedure, the memory controller further determines whether a selected sub-region is a hot-write sub-region according to the write count corresponding to the selected sub-region. When the memory controller determines that the selected sub-region is not a hot-write sub-region, the memory controller performs the data rearrangement procedure on the selected sub-region to move data corresponding to logical addresses belonging to the selected sub-region to a memory space of the memory device having continuous physical addresses. When the memory controller determines that the selected sub-region is a hot-write sub-region, the memory controller does not perform the data rearrangement procedure on the selected sub-region.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

38.

MEMORY ACCESS MODULE FOR PERFORMING A PLURALITY OF SENSING OPERATIONS TO GENERATE DIGITAL VALUES OF A STORAGE CELL IN ORDER TO PERFORM DECODING OF THE STORAGE CELL

      
Numéro d'application 18522128
Statut En instance
Date de dépôt 2023-11-28
Date de la première publication 2024-03-21
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Yang, Tsung-Chieh
  • Chang, Hsiao-Te
  • Wang, Wen-Long

Abrégé

A method for performing memory access of a Flash cell of a Flash memory includes: performing a series of sensing operations respectively corresponding to a plurality of sensing voltages, wherein a sensing voltage of a specific sensing operation of the series of sensing operations has a sensing voltage determined according to a result of an initial sensing operation of the series of sensing operations; determining a threshold voltage of the Flash cell according to at least a digital value generated by the series of sensing operations; and using the determined threshold voltage to perform soft decoding of the Flash cell.

Classes IPC  ?

  • G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
  • G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données

39.

METHOD FOR ACCESSING FLASH MEMORY MODULE, FLASH MEMORY CONTROLLER, AND MEMORY DEVICE

      
Numéro d'application 17976901
Statut En instance
Date de dépôt 2022-10-31
Date de la première publication 2024-03-21
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Liang, Chia-Chi
  • Yen, Hsiao-Chang
  • Lu, Tsu-Han

Abrégé

A method for accessing a flash memory module includes: selecting a block in the flash memory module; selecting a specific encoding/decoding setting from a plurality of sets of encoding/decoding settings at least according to an erase count of the block, wherein the plurality of sets of encoding/decoding settings include different error correction code (ECC) lengths, respectively; utilizing the specific encoding/decoding setting to encode a data to generate an encoded data; and writing the encoded data into the block.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

40.

METHOD FOR ACCESSING FLASH MEMORY MODULE, FLASH MEMORY CONTROLLER, AND MEMORY DEVICE

      
Numéro d'application 17993896
Statut En instance
Date de dépôt 2022-11-24
Date de la première publication 2024-03-21
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Liang, Chia-Chi
  • Yen, Hsiao-Chang
  • Lu, Tsu-Han

Abrégé

A method for accessing a flash memory module includes: determining a type of data to be written into the flash memory module; selecting a specific encoding/decoding setting from a plurality of sets of encoding/decoding settings at least according to the type of data, wherein the plurality of sets of encoding/decoding settings correspond to different data lengths, respectively; utilizing the specific encoding/decoding setting to encode the data to generate encoded data; and writing the encoded data into a block of the flash memory module.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

41.

FRACTIONAL FREQUENCY DIVIDER AND FLASH MEMORY CONTROLLER

      
Numéro d'application 18498054
Statut En instance
Date de dépôt 2023-10-31
Date de la première publication 2024-03-07
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Yao, Tien-Hsing
  • Lee, Chun-Cheng
  • Hsu, Sheng-L

Abrégé

The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

Classes IPC  ?

  • H03K 21/02 - Circuits d'entrée
  • G06F 1/3234 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise
  • H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe
  • H03K 21/10 - Circuits de sortie comprenant des circuits logiques
  • H03K 21/40 - Surveillance; Détection d'erreurs; Empêchement ou correction d'un fonctionnement incorrect du compteur

42.

FLASH MEMORY APPARATUS AND STORAGE MANAGEMENT METHOD FOR FLASH MEMORY

      
Numéro d'application 18498069
Statut En instance
Date de dépôt 2023-10-31
Date de la première publication 2024-02-22
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Yang, Tsung-Chieh
  • Hsu, Hong-Jung
  • Du, Jian-Dong

Abrégé

A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Classes IPC  ?

  • G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
  • G11C 29/52 - Protection du contenu des mémoires; Détection d'erreurs dans le contenu des mémoires
  • G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
  • G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
  • G11C 16/10 - Circuits de programmation ou d'entrée de données

43.

MEMORY CONTROLLER AND METHOD FOR BIT FLIPPING OF LOW-DENSITY PARITY-CHECK CODES

      
Numéro d'application 17933183
Statut En instance
Date de dépôt 2022-09-19
Date de la première publication 2024-02-22
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Kuo, Shiuan-Hao

Abrégé

A memory controller for use in a data storage device is provided. The memory controller includes a variable-node circuit and a check-node circuit. The check-node circuit obtains a codeword difference from the variable-node circuit, and calculates a syndrome according to the codeword difference. The variable-node circuit includes a threshold-tracking circuit which is configured to track a threshold used by the variable-node circuit during a low-density parity check (LDPC) decoding process to determine whether the variable-node circuit has entered a trapping status. In response to determining that the variable-node circuit has entered the trapping status during the LDPC decoding process, the variable-node circuit switches a bit-flipping algorithm used by the variable-node circuit during the LDPC decoding process from a first flipping strategy to a post-processing flipping strategy to bring the variable-node circuit out of the trapping status. The first flipping strategy is different from the post-processing flipping strategy.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

44.

DATA STORAGE DEVICE AND NON-VOLATILE MEMORY CONTROL METHOD

      
Numéro d'application 18361150
Statut En instance
Date de dépôt 2023-07-28
Date de la première publication 2024-02-15
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Ou, Hsu-Ping
  • Tai, Kuang-Ting

Abrégé

A technique for signal deskew at the non-volatile memory side. The non-volatile memory includes a plurality of dies and a signal timing adjustment circuit. The dies are grouped into storage zones. A controller is coupled to the non-volatile memory through a plurality of data lines. Through the data lines, the controller issues a plurality of commands to provide zone delay parameters to the non-volatile memory to drive the signal timing adjustment circuit at the non-volatile memory side to separately adjust data-line timing of the different storage zones.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

45.

DATA STORAGE DEVICE AND NON-VOLATILE MEMORY CONTROL METHOD

      
Numéro d'application 18364542
Statut En instance
Date de dépôt 2023-08-03
Date de la première publication 2024-02-15
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Ou, Hsu-Ping
  • Lee, Chien-Hung

Abrégé

A technique for accurate communication between a non-volatile memory and its controller. The controller accesses a storage area of the non-volatile memory through data lines, wherein the controller transmits a command through the data lines to access the storage area of the non-volatile memory. The command is further returned from the non-volatile memory to the controller through the data lines for comparison, to determine whether the command is correctly received by the non-volatile memory.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

46.

Memory controller and method of accessing flash memory

      
Numéro d'application 17933195
Numéro de brevet 11901912
Statut Délivré - en vigueur
Date de dépôt 2022-09-19
Date de la première publication 2024-02-13
Date d'octroi 2024-02-13
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Kuo, Shiuan-Hao
  • Liu, Zhen-U

Abrégé

A memory controller for use in a data storage device is provided. A low-density parity check (LDPC) process performed by the memory controller includes an initial phase, a decoding phase, and an output phase. The memory controller includes a variable-node circuit and a check-node circuit. During the initial phase, the variable-node circuit performs the following steps: obtaining a channel value, that is read from a flash memory, from a channel-value memory; transmitting the channel value to the check-node circuit to calculate a syndrome; and in response to the syndrome not being 0, setting a value of a register corresponding to each entry of a plurality of entries in a variable-node memory, and entering the decoding phase.

Classes IPC  ?

  • H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
  • H03M 13/15 - Codes cycliques, c. à d. décalages cycliques de mots de code produisant d'autres mots de code, p.ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]

47.

FLASH MEMORY CONTROLLER, SD CARD DEVICE, METHOD USED IN FLASH MEMORY CONTROLLER, AND HOST DEVICE COUPLED TO SD CARD DEVICE

      
Numéro d'application 18380568
Statut En instance
Date de dépôt 2023-10-16
Date de la première publication 2024-02-08
Propriétaire SILICON MOTION INC. (Taïwan, Province de Chine)
Inventeur(s) Hsieh, Chao-Kuei

Abrégé

A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G11C 7/20 - Circuits d'initialisation de cellules de mémoire, p.ex. à la mise sous ou hors tension, effacement de mémoire, mémoire d'image latente
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 3/08 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement à partir de, ou vers des supports d'enregistrement distincts, p.ex. carte perforée
  • G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
  • G11C 16/16 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p.ex. des réseaux, des mots, des groupes
  • G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données

48.

METHOD, MEMORY CONTROLLER, AND MEMORY SYSTEM FOR READING DATA STORED IN FLASH MEMORY

      
Numéro d'application 18379154
Statut En instance
Date de dépôt 2023-10-11
Date de la première publication 2024-02-01
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tsung-Chieh

Abrégé

An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.

Classes IPC  ?

  • G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
  • G11C 29/52 - Protection du contenu des mémoires; Détection d'erreurs dans le contenu des mémoires
  • G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p.ex. compteurs de rafraîchissement défectueux
  • G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
  • G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
  • H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité

49.

Method and apparatus for performing link management of memory device in predetermined communications architecture with aid of handshaking phase transition control

      
Numéro d'application 17874270
Numéro de brevet 11972113
Statut Délivré - en vigueur
Date de dépôt 2022-07-26
Date de la première publication 2024-02-01
Date d'octroi 2024-04-30
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Ye, Bo-Chang
  • Kuo, Kuo-Cyuan
  • Chen, Chih-Chiang

Abrégé

A method for performing link management of a memory device in predetermined communications architecture with aid of handshaking phase transition control and associated apparatus are provided. The method may include: utilizing at least one upper layer controller of a transmission interface circuit to turn on a physical layer (PHY) circuit of the transmission interface circuit, for starting establishing a link between a host device and the memory device; before entering a first handshaking phase, utilizing the PHY circuit to receive any first incoming data sent from the host device to determine whether the any first incoming data indicates that the host device is in a corresponding first handshaking phase; and in response to the any first incoming data indicating that the host device is in the corresponding first handshaking phase, utilizing the PHY circuit to send first outgoing data that is equal to first predetermined data to the host device.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

50.

METHOD AND APPARATUS FOR PERFORMING DATA FRAGMENTATION REDUCTION CONTROL OF MEMORY DEVICE IN PREDETERMINED COMMUNICATIONS ARCHITECTURE WITH AID OF FRAGMENTATION INFORMATION DETECTION, AND ASSOCIATED COMPUTER-READABLE MEDIUM

      
Numéro d'application 17974546
Statut En instance
Date de dépôt 2022-10-27
Date de la première publication 2024-02-01
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Shih, Po-Yi

Abrégé

A method for performing data fragmentation reduction control of a memory device in a predetermined communications architecture with aid of fragmentation information detection, associated apparatus and computer-readable medium are provided. The method may include: utilizing a memory controller to receive a first command from a host device through a transmission interface circuit of the memory controller; utilizing the memory controller to perform discontinuity-related calculation to generate a discontinuity-related calculation result for generating a data fragmentation degree, and send a first response; utilizing the memory controller to receive a second command from the host device through the transmission interface circuit; and utilizing the memory controller to send a second response to the host device through the transmission interface circuit to return the data fragmentation degree to the host device, for selectively performing data fragmentation reduction according to a determination result of the host device.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

51.

Memory controller and method for controlling output of debug messages

      
Numéro d'application 18213899
Statut En instance
Date de dépôt 2023-06-26
Date de la première publication 2024-01-25
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Fang, Hong-Ren
  • Wang, Hao-Hsuan

Abrégé

A memory controller coupled to a memory device for accessing the memory device and includes a Universal Asynchronous Receiver/Transmitter (UART) and a microprocessor. The microprocessor is coupled to the UART and configured to control access operations of the memory device. The microprocessor is configured to perform an interrupt service routine in response to an interrupt. When performing the interrupt service routine, the microprocessor is configured to determine whether a predetermined signal has been received by a specific pin and when determining that the predetermined signal has been received by the specific pin, the microprocessor is configured to output a debug message through a transmitting terminal of the UART.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage

52.

METHOD AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM AND APPARATUS FOR DECODING LOW-DENSITY PARITY-CHECK (LDPC) CODE

      
Numéro d'application 18220464
Statut En instance
Date de dépôt 2023-07-11
Date de la première publication 2024-01-25
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Teng, Duen-Yih

Abrégé

The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for decoding a Low-Density Parity-Check (LDPC) code. The method, which is performed by a processing unit in an LDPC decoder, includes the following steps: determining whether a bit flipping algorithm when decoding a codeword enters a trapping state after an observation period during which a sequential selection strategy is used; and modifying a scheduling strategy to a non-sequential selection strategy and performing the bit flipping algorithm on the codeword under the non-sequential selection strategy when the bit flipping algorithm enters the trapping state. The codeword is divided into chunks in fixed-length and the sequential selection strategy indicates sequentially selecting the chunks in the codeword, so that the bit flipping algorithm is performed on one selected chunk only each time. The non-sequential selection strategy indicates an arbitrary selection combination of the chunks in the codeword, which is different from that under the sequential selection strategy.

Classes IPC  ?

  • H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité

53.

METHOD AND APPARATUS FOR PERFORMING DATA RETENTION MANAGEMENT OF MEMORY DEVICE WITH AID OF PRE-SHUTDOWN CONTROL

      
Numéro d'application 17870861
Statut En instance
Date de dépôt 2022-07-22
Date de la première publication 2024-01-25
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tsung-Chieh

Abrégé

A method for performing data retention management of a memory device with aid of pre-shutdown control and associated apparatus are provided. The method may include: receiving a predetermined host command from a host device; in response to the predetermined host command, performing a re-programming procedure on the NV memory, for enhancing data storage reliability of the memory device, for example, reading stored data from at least one source location within the at least one NV memory element to prepare re-programming data according to the stored data, and programming the re-programming data into at least one destination location within the at least one NV memory element to be replacement of the stored data; and in response to the re-programming procedure being completed, sending completion information of the predetermined host command to the host device, to allow the host device to trigger the shutdown of the memory device.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

54.

Method and apparatus for performing data management of memory device with aid of targeted protection control

      
Numéro d'application 17869735
Numéro de brevet 12014087
Statut Délivré - en vigueur
Date de dépôt 2022-07-20
Date de la première publication 2024-01-25
Date d'octroi 2024-06-18
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tsung-Chieh

Abrégé

A method for performing data management of a memory device with aid of targeted protection control and associated apparatus are provided. The method may include: receiving a first host command from a host device; sending a first operating command to a non-volatile (NV) memory to read first stored data from a first location within the NV memory; monitoring a read count of the first location to determine whether the read count of the first location reaches a read count threshold; monitoring at least one error bit count of other stored data of at least one other location within the NV memory to determine whether the at least one error bit count reaches an error bit count threshold; and starting a targeted protection procedure to process second stored data, for preventing the second stored data from being damaged by at least one reading behavior of the host device.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

55.

Memory controller and method for controlling data in decoding pipeline

      
Numéro d'application 17933190
Numéro de brevet 11876535
Statut Délivré - en vigueur
Date de dépôt 2022-09-19
Date de la première publication 2024-01-16
Date d'octroi 2024-01-16
Propriétaire SILICON MOTION, INC. (Taïwan, Province de Chine)
Inventeur(s) Kuo, Shiuan-Hao

Abrégé

A memory controller, for use in a data storage device, is provided. A low-density parity-check (LDPC) decoding procedure performed by the memory controller includes an initial phase, a decoding phase, and an output phase in sequence. The memory controller includes a memory-index control circuit and a decoder. The decoder includes a decoding pipeline to perform the decoding phase of the LDPC decoding procedure. After the data storage device is booted up, the decoder reads a plurality of first codewords from a variable-node memory using a first order via the memory-index control circuit for LDPC decoding. In response to the decoder determining that a specific codeword among the first codewords has decoding failure, the decoder is reset to read a plurality of second codewords from the variable-node memory using a second order via the memory-index control circuit for LDPC decoding. The first order is different from the second order.

Classes IPC  ?

  • H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
  • H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
  • H03M 13/15 - Codes cycliques, c. à d. décalages cycliques de mots de code produisant d'autres mots de code, p.ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]

56.

FLASH MEMORY CONTROLLER AND METHOD CAPABLE OF USING ONE SET-FEATURE SIGNAL AS A MACRO EXECUTION SIGNAL TO EXECUTE MULTIPLE SET-FEATURE OPERATIONS FOR FLASH MEMORY DEVICE

      
Numéro d'application 17852385
Statut En instance
Date de dépôt 2022-06-29
Date de la première publication 2024-01-04
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lu, Tsu-Han
  • Yen, Hsiao-Chang

Abrégé

A method of a flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface includes: using a set-feature signal, which carries a set-feature command, a macro execution feature address, and corresponding macro execution parameter information, as a macro execution signal and transmitting the macro execution signal to the flash memory device to make the flash memory device execute multiple set-feature operations respectively having unique information defined by the corresponding macro execution parameter information carried in the macro execution signal.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

57.

Flash memory controller and method capable of transmitting multiple set-feature signals and macro settings to flash memory device

      
Numéro d'application 17852403
Numéro de brevet 11914901
Statut Délivré - en vigueur
Date de dépôt 2022-06-29
Date de la première publication 2024-01-04
Date d'octroi 2024-02-27
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lu, Tsu-Han
  • Yen, Hsiao-Chang

Abrégé

A method of a flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface includes: using a set-feature signal, which carries a set-feature command, a macro execution feature address, and corresponding macro execution parameter information, as a macro execution signal and transmitting the macro execution signal to the flash memory device to make the flash memory device execute multiple set-feature operations respectively having unique information defined by the corresponding macro execution parameter information carried in the macro execution signal.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

58.

APPARATUS AND METHOD FOR GENERATING LOW-DENSITY PARITY-CHECK (LDPC) CODE

      
Numéro d'application 18207233
Statut En instance
Date de dépôt 2023-06-08
Date de la première publication 2023-12-28
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Kuo, Shiuan-Hao

Abrégé

The invention relates to an apparatus and a method for generating a Low-Density Parity-Check (LDPC) code. The apparatus includes: a LDPC encoder, a look-ahead circuitry and an exclusive-OR (XOR) calculation circuitry. The LDPC encoder is arranged operably to encode a front part of a user data using a 2-stage encoding algorithm with a parity check matrix to generate a first calculation result. The look-ahead circuitry is arranged operably to perform a dot product operation on a rear part of the user data and one of a plurality of feature rows corresponding to the parity check matrix to generate a second calculation result in each iteration. The XOR calculation circuitry is arranged operably to perform an XOR operation on the first calculation result and the second calculation result to generate a front part of the LDPC code.

Classes IPC  ?

  • H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
  • H03K 19/21 - Circuits OU EXCLUSIF, c. à d. donnant un signal de sortie si un signal n'existe qu'à une seule entrée; Circuits à COÏNCIDENCES, c. à d. ne donnant un signal de sortie que si tous les signaux d'entrée sont identiques
  • H03K 19/173 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants

59.

METHOD AND APPARATUS FOR DECODING LOW-DENSITY PARITY-CHECK (LDPC) CODE

      
Numéro d'application 18143343
Statut En instance
Date de dépôt 2023-05-04
Date de la première publication 2023-12-28
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Kuo, Shiuan-Hao
  • Huang, Hung-Jen

Abrégé

The invention relates to a method and an apparatus for decoding a Low-Density Parity-Check (LDPC) code. The method includes the following steps, which is performed by an LDPC decoder including a variable-node calculation circuitry and a check-node calculation circuitry: A first-stage state entering when a codeword has been stored in a static random access memory (SRAM) is detected. The check-node calculation circuitry is arranged operably to perform a modulo 2 multiplication on the codeword and a parity check matrix to calculate a plurality of first syndromes in the first-stage state. A second-stage state is entered when the first syndromes indicate that the codeword obtained in the first-stage state is incorrect. The variable-node calculation circuitry is arranged operably to perform a bit flipping algorithm accordingly to generate variable nodes, and calculate second soft bits for the variable nodes in the second-stage state. The check-node calculation circuitry is arranged operably to perform the modulo 2 multiplication on the variable nodes and the parity check matrix to calculate second syndromes in the second-stage stage. A third-stage state is repeatedly entered when the second syndromes indicate that the variable nodes generated in the second-stage state are incorrect until a decoding succeeds or a total number of iterations of the third-stage state exceeds a threshold.

Classes IPC  ?

  • H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
  • H03M 13/37 - Méthodes ou techniques de décodage non spécifiques à un type particulier de codage prévu dans les groupes
  • H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes

60.

Encoder and flash memory controller

      
Numéro d'application 17945110
Numéro de brevet 11929764
Statut Délivré - en vigueur
Date de dépôt 2022-09-15
Date de la première publication 2023-12-21
Date d'octroi 2024-03-12
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Teng, Duen-Yih

Abrégé

For an encoder for use in a flash memory controller, partial parity blocks generated in the encoder are divided into two parts for further operations, wherein a number of partial parity block(s) of the first part generated earlier is less than a number of partial parity block(s) of the second part. The encoder can reduce the hardware required for the circulant convolution calculation in the encoder, and has high efficiency. In addition, by converting a parity-check matrix to generate an isomorphic matrix, some components in the encoder and the decoder can be further omitted, so as to further reduce the manufacturing cost.

Classes IPC  ?

  • H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
  • H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
  • H03M 13/15 - Codes cycliques, c. à d. décalages cycliques de mots de code produisant d'autres mots de code, p.ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]

61.

STORAGE DEVICE CAPABLE OF DYNAMICALLY DETERMINING WHETHER TO AND WHEN TO SEND NEXT INTERRUPT EVENT TO HOST DEVICE

      
Numéro d'application 17743485
Statut En instance
Date de dépôt 2022-05-13
Date de la première publication 2023-11-16
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tzu-Yi

Abrégé

A method of a storage device to be externally coupled to a host device via a specific communication interface includes: providing a flash memory unit comprising at least one flash memory; counting an outstanding command number for at least one submission queue which is used for storing information of unfinished commands; counting a completion command number for at least one completion queue which is used for storing information of finished commands; and, generating and outputting an interrupt event from the storage device to the host device when a comparison result of the counted outstanding command number with the counted completion command number matches a specific condition.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

62.

Method and apparatus for performing data access management of memory device with aid of randomness-property control

      
Numéro d'application 17863383
Numéro de brevet 11809713
Statut Délivré - en vigueur
Date de dépôt 2022-07-12
Date de la première publication 2023-11-07
Date d'octroi 2023-11-07
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tsung-Chieh

Abrégé

A method for performing data access management of a memory device with aid of randomness-property control and associated apparatus are provided. The method may include: receiving a plurality of host commands from a host device and performing data access on the NV memory according to the plurality of host commands, for example, in response to at least one host write command, programming data into at least one single level cell (SLC) block to be first stored data corresponding to a data reception stage; and performing a seed-aware garbage collection (GC) procedure to collect valid data among the first stored data of the at least one SLC block into at least one non-SLC block to be second stored data corresponding to a data storage stage, for example, performing a randomness-property checking operation on multiple seeds to selectively determine respective data of multiple pages within the SLC block as target data.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 12/02 - Adressage ou affectation; Réadressage

63.

METHOD AND APPARATUS FOR READING DATA STORED IN FLASH MEMORY BY REFERRING TO BINARY DIGIT DISTRIBUTION CHARACTERISTICS OF BIT SEQUENCES READ FROM FLASH MEMORY

      
Numéro d'application 18219083
Statut En instance
Date de dépôt 2023-07-06
Date de la première publication 2023-11-02
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tsung-Chieh

Abrégé

A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Classes IPC  ?

  • G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
  • G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
  • G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
  • G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
  • G11C 29/52 - Protection du contenu des mémoires; Détection d'erreurs dans le contenu des mémoires
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
  • H03M 13/15 - Codes cycliques, c. à d. décalages cycliques de mots de code produisant d'autres mots de code, p.ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]

64.

INITIALIZATION METHODS AND ASSOCIATED CONTROLLER, MEMORY DEVICE AND HOST

      
Numéro d'application 18214427
Statut En instance
Date de dépôt 2023-06-26
Date de la première publication 2023-11-02
Propriétaire SILICON MOTION INC. (Taïwan, Province de Chine)
Inventeur(s) Hsieh, Chao-Kuei

Abrégé

The present invention provides a method performed by a secure digital (SD) card supporting both an SD mode and a peripheral component interconnect express (PCIe) mode for initializing the SD card. The method includes: (a) after receiving a first supply voltage through a first voltage supply pin from a host coupled to the SD card, entering the SD mode if the SD card is not in the PCIe mode and a CMD0 command for entering the SD mode is received through a command pin from the host coupled to the SD card; and (b) after receiving the first supply voltage through the first voltage supply pin from the host coupled to the SD card, performing a PCIe linkup process if the SD card is not in the SD mode and a second supply voltage is received through a second voltage supply pin from the host coupled to the SD card. The SD card enters the PCIe mode if the PCIe linkup process succeeds.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation

65.

METHOD FOR MANAGING A MEMORY APPARATUS

      
Numéro d'application 18218122
Statut En instance
Date de dépôt 2023-07-05
Date de la première publication 2023-11-02
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lin, Tsai-Cheng
  • Lee, Chun-Kun

Abrégé

A method for managing a memory apparatus including a plurality of physical blocks, and a volatile memory includes: obtaining a first host address and first data, and obtaining a second host address and second data; linking the first host address and second host address to a first page and second page of the physical block, and storing the first data and second data into the physical block; building a valid/invalid page count table according to a valid/invalid page count of the physical block; building a valid page position table according to the valid/invalid page count table, and storing the valid/invalid page count table in the volatile memory; and when a valid/invalid page count of the physical block indicates the physical block should be erased, using the valid page position table to move valid pages of the physical block to another physical block.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage

66.

Method for accessing flash memory module and associated flash memory controller and electronic device

      
Numéro d'application 17725531
Numéro de brevet 11947818
Statut Délivré - en vigueur
Date de dépôt 2022-04-20
Date de la première publication 2023-10-26
Date d'octroi 2024-04-02
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Chen, Ching-Ke
  • Hsu, Wei-Chih

Abrégé

The present invention provides a method for accessing a flash memory module, wherein the method includes the steps of: writing data into a plurality of pages of a specific block, and establishes or updates a F2H mapping table based on physical addresses of the plurality of pages and logical addresses of the data; using the F2H mapping table to update a H2F mapping table; initializing a flush-bitmap, wherein the flush-bitmap records a plurality of flush bits corresponding to the physical addresses of the plurality of pages, respectively; receiving a trim command from a host device, wherein the trim command asks to mark at least one of the logical addresses of the data as invalid; updating the H2F mapping data according to the trim command; updating the flush-bitmap according to the trim command; and writing the updated H2F mapping table and the updated flush-bitmap into the flash memory module.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G06F 12/10 - Traduction d'adresses

67.

CONTROL METHOD OF FLASH MEMORY CONTROLLER AND ASSOCIATED FLASH MEMORY CONTROLLER AND STORAGE DEVICE

      
Numéro d'application 18215185
Statut En instance
Date de dépôt 2023-06-28
Date de la première publication 2023-10-26
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Lin, Ching-Hui

Abrégé

The present invention provides a control method of the flash memory controller. In the control method, after receiving a deallocate command from a host device, the flash memory controller will update a valid page count table, a detailed valid page count table and/or a zone valid page count table according to deallocate command, for the flash memory controller to efficiently and quickly determine if any one of the zones does not have any valid data, so that the flash memory controller can recommend the host device to send a reset command to reset the zone.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

68.

METHOD FOR PERFORMING ACCESS MANAGEMENT IN A MEMORY DEVICE, ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF, AND ASSOCIATED ELECTRONIC DEVICE

      
Numéro d'application 18218576
Statut En instance
Date de dépôt 2023-07-05
Date de la première publication 2023-10-26
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lee, Jie-Hao
  • Yu, Cheng-Yu

Abrégé

A method for performing access management in a memory device, the associated memory device and the controller thereof, and the associated electronic device are provided. The method may include: receiving a host command and a logical address from a host device; performing at least one checking operation to obtain at least one checking result, for determining whether to load a logical-to-physical (L2P) table from the NV memory to a random access memory (RAM) of the memory device, wherein the L2P table includes address mapping information for accessing the target data, and performing the at least one checking operation to obtain at least one checking result includes checking whether a first L2P-table index pointing toward the L2P table and a second L2P-table index sent from the host device are equivalent to each other; and reading the target data from the NV memory, and sending the target data to the host device.

Classes IPC  ?

  • G06F 12/1009 - Traduction d'adresses avec tables de pages, p.ex. structures de table de page
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G06F 12/14 - Protection contre l'utilisation non autorisée de mémoire

69.

Data storage device and method for rewriting parameters thereof

      
Numéro d'application 18336316
Numéro de brevet 12008235
Statut Délivré - en vigueur
Date de dépôt 2023-06-16
Date de la première publication 2023-10-12
Date d'octroi 2024-06-11
Propriétaire SILICON MOTION, INC. (Taïwan, Province de Chine)
Inventeur(s)
  • Wang, Te-Kai
  • Chen, Yu-Da

Abrégé

A data storage device with flash memory. The controller receives a mode selection command from a host. In response to the mode selection command, the controller sends a ready-to-transfer message to the host, to further receive a data out message from the host that is sent by the host in response to the ready-to-transfer message. The ready-to-transfer message and the data out message are UFS protocol information unit (UPIU) messages. The data out message is arranged to rewrite a first mode page setting among a plurality of mode page settings of firmware stored in the flash memory. In response to the data out message, the controller determines whether the data out message will change mode parameters which cannot be rewritten in the first mode page setting, to adopt or refuse new mode parameters issued through the data out message for the first mode page setting.

Classes IPC  ?

  • G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G11C 16/10 - Circuits de programmation ou d'entrée de données
  • G11C 16/22 - Circuits de sécurité ou de protection pour empêcher l'accès non autorisé ou accidentel aux cellules de mémoire
  • G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données

70.

Method and apparatus for performing data access performance shaping of memory device

      
Numéro d'application 17706645
Numéro de brevet 11816360
Statut Délivré - en vigueur
Date de dépôt 2022-03-29
Date de la première publication 2023-10-05
Date d'octroi 2023-11-14
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Wang, Kaihong
  • Yi, Cheng

Abrégé

A method for performing data access performance shaping of a memory device and associated apparatus are provided. The method may include: receiving a plurality of host commands from a host device, for performing data access on the NV memory according to the plurality of host commands; and monitoring the plurality of host commands to control respective performance metrics of a plurality of access control groups of the memory device with a dual-state leaky bucket (LB) model, wherein regarding any access control group, for example: determining at least one first performance metric according to at least one first command to be a first LB fill level of a dual-state LB; in response to the first LB fill level being below a state threshold, determining the dual-state LB to be in a first predetermined state, and configuring the dual-state LB to have a first predetermined drain rate, for dynamically adjusting performance quota.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

71.

METHOD AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM AND APPARATUS FOR DATA ACCESS IN RESPONSE TO HOST DISCARD COMMANDS

      
Numéro d'application 18110747
Statut En instance
Date de dépôt 2023-02-16
Date de la première publication 2023-10-05
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Chiu, Shen-Ting

Abrégé

The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for data access in response to a host discard command. The method includes: allocating space in a random access memory (RAM) for an expanded discard table; receiving the host discard command from a host side; appending new entries each including one first logical address to the expanded discard table; and setting a start-address register and/or an end-address register in a performance engine for redefining an address range in the RAM that stores the expanded discard table, thereby enabling the performance engine to search the expanded discard table in the address range in the RAM for determining whether a specific logical address of user data is no longer used.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire

72.

Memory controller and data processing method for processing disordered read-out data

      
Numéro d'application 18116801
Statut En instance
Date de dépôt 2023-03-02
Date de la première publication 2023-09-28
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Ye, Bo-Chang
  • Chen, I-Ta
  • Chen, Wen-Shu
  • Kuo, Kuo-Cyuan

Abrégé

A data processing method includes reading a memory device in response to a read command to respectively read multiple portions of predetermined data; respectively writing the portions in a buffer memory to complete data transfers of the portions of the predetermined data; sequentially providing access information corresponding to each portion of the predetermined data in response to completion of the data transfer of the corresponding portion; obtaining the access information of the predetermined data and accordingly generating multiple descriptors in chronological order of obtaining the access information; receiving and buffering the descriptors in a descriptor pool; sequentially selecting a latest descriptor from the descriptor pool according to a tag value and providing the latest descriptor to a direct memory access engine; and reading the buffer memory according to the latest descriptor to obtain at least a portion of the predetermined data by the direct memory access engine.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

73.

Data storage system and parameter margin evaluation method

      
Numéro d'application 18074527
Statut En instance
Date de dépôt 2022-12-05
Date de la première publication 2023-09-28
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Shih, Po-Yi

Abrégé

A method for evaluating a margin of at least one parameter utilized by a transmission interface includes: step (A) setting a value of a first parameter utilized by a host device to a first test value selected from a first group; (B) setting a value of a second parameter utilized by a data storage device to a second test value selected from a second group; (C) controlling the data storage device to perform a predetermined testing procedure to test whether the data storage device functions normally when the first test value and the second test value are applied; and (D) changing the first test value or the second test value and re-performing steps (A) to (C), wherein step (D) is repeatedly performed until all the test values in the first group and the second group have been tested.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

74.

Control method of flash memory controller and associated flash memory controller and electronic device

      
Numéro d'application 17692121
Numéro de brevet 11809748
Statut Délivré - en vigueur
Date de dépôt 2022-03-10
Date de la première publication 2023-09-14
Date d'octroi 2023-11-07
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Liang, Chia-Chi
  • Lu, Tsu-Han
  • Yen, Hsiao-Chang

Abrégé

The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, the flash memory module includes a plurality of planes, and each plane includes a plurality of blocks; and the control method includes the steps of: after the flash memory controller is powered on, reading a first code bank from a specific block of the plurality of blocks; storing the first code bank into a buffer memory; executing the first code bank to manage the flash memory module; when the flash memory controller starts a code bank swapping operation, trying to read a second code bank from a super block; if the second code bank is read successfully, storing the second code bank into the buffer memory to replace the first code bank; and executing the second code bank to manage the flash memory module.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

75.

Method and apparatus for performing access management of memory device with aid of serial number assignment timing control

      
Numéro d'application 17691137
Numéro de brevet 11899977
Statut Délivré - en vigueur
Date de dépôt 2022-03-10
Date de la première publication 2023-09-14
Date d'octroi 2024-02-13
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Hong, Wen-Chi
  • Tseng, Hsin-Hsiang

Abrégé

A method for performing access management of a memory device with aid of serial number assignment timing control and associated apparatus are provided. The method includes: managing a plurality of spare blocks with a spare pool; popping a first block from the spare pool to be a host data block, and performing first subsequent operations, wherein the host data block is arranged to receive data from a host device, and serial number assignment of the host data block corresponds to a timing of fully programing the host data block; and popping a second block from the spare pool to be a garbage collection (GC) destination block, and performing second subsequent operations, wherein the GC destination block is arranged to receive data from a GC source block during a GC procedure, and serial number assignment of the GC destination block corresponds to a timing of starting using the GC destination block.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

76.

Method and apparatus for caching address mapping information in flash memory based storage device

      
Numéro d'application 17693431
Numéro de brevet 11977767
Statut Délivré - en vigueur
Date de dépôt 2022-03-14
Date de la première publication 2023-09-14
Date d'octroi 2024-05-07
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Pai, Yi-Kai

Abrégé

A method of caching mapping table for use in a flash memory device having a flash memory controller and a flash memory is provided. The method includes: in response to a host read command, determining whether a group of a logical-to-physical (L2P) required by handling the host read command has been loaded to a DRAM of the flash memory controller; if the required group of the L2P mapping table has not been loaded to the DRAM, loading the required group of the L2P mapping table from the flash memory to a SRAM of the flash memory controller; directly accessing the SRAM to obtain an L2P address associated with the host read command from the required group of the L2P mapping table; and performing a read operation on the flash memory in response to the host read command according to the obtained L2P address.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 12/02 - Adressage ou affectation; Réadressage

77.

Flash memory controller and method capable of sending read command or data toggle command to ask for flash memory device return more plane data of different planes

      
Numéro d'application 17679103
Numéro de brevet 11972146
Statut Délivré - en vigueur
Date de dépôt 2022-02-24
Date de la première publication 2023-09-07
Date d'octroi 2024-04-30
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lu, Tsu-Han
  • Yen, Hsiao-Chang

Abrégé

A method of a flash memory controller includes: providing an input/output (I/O) circuit coupled to a flash memory device through a specific communication interface; and, controlling a processor sending a specific read command or a data toggle command through the I/O circuit and the specific communication interface into the flash memory device, to make the flash memory device perform a data toggle operation to control the flash memory device's data register selecting and transferring a first data unit and a second data unit to the flash memory device's I/O control circuit to make the I/O control circuit sequentially transmit the first data unit and the second data unit to the flash memory controller through the specific communication interface in response to the specific read command or the data toggle command.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

78.

Flash memory device, controller, and method capable of performing access operation upon data unit(s) of multiple planes of flash memory device in response one simplified command sequence

      
Numéro d'application 17679120
Numéro de brevet 11861212
Statut Délivré - en vigueur
Date de dépôt 2022-02-24
Date de la première publication 2023-09-07
Date d'octroi 2024-01-02
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lu, Tsu-Han
  • Yen, Hsiao-Chang

Abrégé

A flash memory scheme simplifies the command sequences transmitted between a flash memory device and a flash memory controller into a simplified command sequence so as to reduce the waiting time period of the command transmission and improve the performance of flash memory.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

79.

FLASH MEMORY DEVICE, CONTROLLER, AND METHOD CAPABLE OF PERFORMING ACCESS OPERATION UPON DATA UNIT(s) OF MULTIPLE PLANES OF FLASH MEMORY DEVICE IN RESPONSE ONE SIMPLIFIED COMMAND SEQUENCE

      
Numéro d'application 17679116
Statut En instance
Date de dépôt 2022-02-24
Date de la première publication 2023-08-24
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lu, Tsu-Han
  • Yen, Hsiao-Chang

Abrégé

A flash memory scheme simplifies the command sequences transmitted between a flash memory device and a flash memory controller into a simplified command sequence so as to reduce the waiting time period of the command transmission and improve the performance of flash memory.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 12/02 - Adressage ou affectation; Réadressage

80.

Flash memory device, controller, and method capable of performing access operation upon data unit(s) of multiple planes of flash memory device in response one simplified command sequence

      
Numéro d'application 17679125
Numéro de brevet 11935595
Statut Délivré - en vigueur
Date de dépôt 2022-02-24
Date de la première publication 2023-08-24
Date d'octroi 2024-03-19
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lu, Tsu-Han
  • Yen, Hsiao-Chang

Abrégé

A flash memory scheme simplifies the command sequences transmitted between a flash memory device and a flash memory controller into a simplified command sequence so as to reduce the waiting time period of the command transmission and improve the performance of flash memory.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
  • G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
  • G11C 16/10 - Circuits de programmation ou d'entrée de données
  • G11C 16/14 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement
  • G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données

81.

Data storage device and control method for non-volatile memory

      
Numéro d'application 17835206
Numéro de brevet 11775386
Statut Délivré - en vigueur
Date de dépôt 2022-06-08
Date de la première publication 2023-08-24
Date d'octroi 2023-10-03
Propriétaire SILICON MOTION, INC. (Taïwan, Province de Chine)
Inventeur(s)
  • Chang, Yu-Hao
  • Hsiao, Yu-Han
  • Chou, Po-Sheng

Abrégé

A solution for deteriorated non-volatile memory is shown. When determining that raw data read from the non-volatile memory is undesirable data, the controller updates a deterioration table to record a deteriorated logical address of the raw data that is the undesirable data. When performing garbage collection from a source block associated with the deteriorated logical address to a destination block and determining that the deteriorated logical address is listed in the deterioration table, the controller invalidates target data stored in the source block and mapped to the deteriorated logical address, without moving the target data from the source block to the destination block in the garbage collection.

Classes IPC  ?

  • G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
  • G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
  • G06F 12/02 - Adressage ou affectation; Réadressage

82.

Flash memory controller and method capable of sending read command or data toggle command to ask for flash memory device return more plane data of different planes

      
Numéro d'application 17679111
Numéro de brevet 11977776
Statut Délivré - en vigueur
Date de dépôt 2022-02-24
Date de la première publication 2023-08-24
Date d'octroi 2024-05-07
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lu, Tsu-Han
  • Yen, Hsiao-Chang

Abrégé

A flash memory device is disclosed. The memory cell array has a first plane and a second plane and stores a first data unit and a second data unit. The data register buffers the first data unit and the second data unit transmitted from the memory cell array when a read command or a data toggle command is received and stored by the command register. The control circuit performs a data toggle operation to control the data register selecting and transferring the first data unit and the second data unit to the I/O control circuit to make the I/O control circuit sequentially transmit the first data unit and the second data unit to the flash memory controller through a specific communication interface in response to the read command or the data toggle command. The transmission of the first data unit is followed by the transmission of the second data unit.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

83.

Flash memory controller and method capable of sending data toggle set-feature signal to enable, disable, or configure data toggle operation of flash memory device

      
Numéro d'application 17679136
Numéro de brevet 11977752
Statut Délivré - en vigueur
Date de dépôt 2022-02-24
Date de la première publication 2023-08-24
Date d'octroi 2024-05-07
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lu, Tsu-Han
  • Yen, Hsiao-Chang

Abrégé

A method of a flash memory controller includes: providing an input/output (I/O) circuit coupled to the flash memory device; and sending a data toggle set-feature signal to the flash memory device to enable, disable, or configure a data toggle operation of the flash memory device; the data toggle operation of the flash memory device is arranged to make the flash memory device control the flash memory device's data register selecting and transferring a first data unit and a second data unit to the flash memory device's I/O control circuit to make the I/O control circuit sequentially transmit the first data unit and the second data unit to the flash memory controller through the specific communication interface in response to a specific read command or a data toggle command transmitted by the flash memory controller.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

84.

Data storage device and control method for non-volatile memory

      
Numéro d'application 17835183
Numéro de brevet 11922044
Statut Délivré - en vigueur
Date de dépôt 2022-06-08
Date de la première publication 2023-08-24
Date d'octroi 2024-03-05
Propriétaire SILICON MOTION, INC. (Taïwan, Province de Chine)
Inventeur(s)
  • Chang, Yu-Hao
  • Hsiao, Yu-Han
  • Chou, Po-Sheng

Abrégé

A solution for deteriorated non-volatile memory is shown. When a controller determines that raw data read from the non-volatile memory is undesirable data, the controller performs safety moving of valid data of an erasure unit that contains the raw data to safely move the valid data of the erasure unit, wherein the erasure unit is a high-risk block, and the raw data in the non-volatile memory is regarded as being in a deteriorated physical address. Prior to being moved in the safety moving, the raw data is changed so that it is different from the undesirable data. In an exemplary embodiment, the undesirable data is all-1's data or all-0's data.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

85.

Data storage device and control method for non-volatile memory

      
Numéro d'application 17835198
Numéro de brevet 12008258
Statut Délivré - en vigueur
Date de dépôt 2022-06-08
Date de la première publication 2023-08-24
Date d'octroi 2024-06-11
Propriétaire SILICON MOTION, INC. (Taïwan, Province de Chine)
Inventeur(s)
  • Chang, Yu-Hao
  • Hsiao, Yu-Han
  • Chou, Po-Sheng

Abrégé

A solution for deteriorated non-volatile memory is shown. When determining that raw data read from the non-volatile memory is undesirable data, the controller updates a deterioration table to record a deteriorated logical address of the raw data that is the undesirable data. In response to a read request that a host issues to read the non-volatile memory for data of the deteriorated logical address, the controller obtains the deteriorated logical address from the deterioration table and informs the host that deterioration has happened at the deteriorated logical address.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

86.

Flash memory scheme capable of decreasing waiting time of trim command

      
Numéro d'application 17578380
Numéro de brevet 11809711
Statut Délivré - en vigueur
Date de dépôt 2022-01-18
Date de la première publication 2023-07-20
Date d'octroi 2023-11-07
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Hong, Wen-Chi
  • Ciou, Huang-Jhih

Abrégé

A method of a flash memory controller used to be externally coupled to a host device and a flash memory, comprising: providing a multi-processor having a plurality of processing units; receiving a trim command and a logical block address (LBA) range sent from the host device; separating multiple operations of the trim command into N threads according to at least one of a number of the processing units, types of the multiple operations, numbers of execution cycles of the multiple operations, and portions of the LBA range; using the processing units to execute the N threads individually; and maximizing a number of execution cycles during which the processing units are busy.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

87.

Method and apparatus for accessing L2P address without searching group-to-flash mapping table

      
Numéro d'application 17693420
Numéro de brevet 11704238
Statut Délivré - en vigueur
Date de dépôt 2022-03-14
Date de la première publication 2023-07-18
Date d'octroi 2023-07-18
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Pai, Yi-Kai

Abrégé

A method of caching mapping table for use in a flash memory device having a flash memory controller and a flash memory is provided. The method includes: in response to a host read/write command, checking a G2F mapping table to determine whether a required group of a L2P mapping table has been loaded to a DRAM of the flash memory controller and accordingly obtain a node index indicating which memory node of the DRAM the group is stored in; recording the node index to a first region of a SRAM of the flash memory controller; accessing the DRAM to obtain an L2P address indicating a physical address that is associated with the host read/write command from the group of the L2P mapping table by referencing the node index stored in the first region of the SRAM; and performing a read/write operation on the flash memory according to the L2P address.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage

88.

METHOD AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM AND APPARATUS FOR DYNAMICALLY UPDATING OPTIMIZATION READ VOLTAGE TABLE

      
Numéro d'application 18080852
Statut En instance
Date de dépôt 2022-12-14
Date de la première publication 2023-07-13
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Chen, Chun-Yi
  • Chang, Hsiao-Te

Abrégé

The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for dynamically updating an optimization read voltage (RV) table. The method includes: obtaining a data-read transaction and replying with the data-read transaction to a host side after listening to a first request for read-performance data, which is issued by the host side, thereby enabling the data-performance transaction to be used in an update of the optimization RV table for a designated memory-cell type; and programming multiple records of an updated optimization RV table for the designated memory-cell type into a designated location of the NAND-flash module after listening to a second request for updating the optimization RV table for the designated memory-cell type, which is issued by the host side. The data-read transaction includes a current environmental parameter of a NAND-flash module, the designated memory-cell type and a bit error rate (BER). Each record includes one set of RV parameters and an environmental parameter associated with the set of RV parameters.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

89.

METHOD AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM AND APPARATUS FOR READING DATA WITH OPTIMIZATION READ VOLTAGE TABLE

      
Numéro d'application 18080842
Statut En instance
Date de dépôt 2022-12-14
Date de la première publication 2023-07-13
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Chen, Chun-Yi
  • Chang, Hsiao-Te

Abrégé

The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for reading data with an optimization read voltage (RV) table. The method includes: determining one set of RVs for a designated memory-cell type according to a current environmental parameter of a NAND-flash module and content of the optimization RV table; and reading data on a page corresponding to the designated memory-cell type from the NAND-flash module with the set of RVs. The optimization RV table includes multiple records and each record includes one set of RV parameters and an environmental parameter associated with the set of RV parameters.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

90.

Method and apparatus for performing access management of memory device with aid of buffer usage reduction control

      
Numéro d'application 17569451
Numéro de brevet 11704054
Statut Délivré - en vigueur
Date de dépôt 2022-01-05
Date de la première publication 2023-07-06
Date d'octroi 2023-07-18
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Li, An-Pang

Abrégé

A method for performing access management of a memory device with aid of buffer usage reduction control and associated apparatus are provided. The method includes: determining whether any host command among a plurality of host commands from a host device is a trim-related read command, wherein the trim-related read command represents a read command indicating that reading from at least one trimmed location is required; in response to the any host command being the trim-related read command, determining an estimated trim-related read operation count regarding a data buffer according to a trimmed range of the at least one trimmed location and a predetermined unit size of accessing the data buffer; writing predetermined trimmed data having the predetermined unit size into the data buffer; and controlling a transmission interface circuit to read the predetermined trimmed data from the data buffer multiple times, for being returned to the host device.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 12/02 - Adressage ou affectation; Réadressage

91.

APPARATUS AND METHOD FOR DRIVING REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) ENGINE

      
Numéro d'application 17984691
Statut En instance
Date de dépôt 2022-11-10
Date de la première publication 2023-06-29
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lee, Lien-Yu
  • Chiu, Shen-Ting

Abrégé

The invention is related to an apparatus and a method for driving redundant array of independent disks (RAID) engine. The method, performed by a RAID controller in a RAID pre-processor, including: completing a driving operation for performing a series of physical-layer signal interactions with a RAID engine according to a driving value in the configuration register. The driving value corresponds to a command issued by a processing unit. The processing unit performs an operation irrelevant from an encoding or a decoding of a parity of a page group in parallel of the driving operation by the RAID controller in coordination with the RAID engine.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

92.

Method for improve read disturbance phenomenon of flash memory module and associated flash memory controller and electronic device

      
Numéro d'application 17574579
Numéro de brevet 11687290
Statut Délivré - en vigueur
Date de dépôt 2022-01-13
Date de la première publication 2023-06-27
Date d'octroi 2023-06-27
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Huang, Cheng-Hao

Abrégé

The present invention provides a control method of a flash memory controller wherein the control method includes the steps of: selecting a first block; reading pages of the first block and determining a bit error rate or a bit error count of each page; for each of the pages, if the bit error rate or the bit error count of the page is not greater than a first threshold value, moving the data of the page into a second block; and for each of the pages, if the bit error rate or the bit error count of the page is greater than the first threshold value, moving the data of the page into a third block; wherein a number of pages corresponding to a word line of the second block is less than a number of pages corresponding to a word line of the third block.

Classes IPC  ?

  • G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

93.

Method and apparatus for performing access control of memory device with aid of additional physical address information

      
Numéro d'application 17568690
Numéro de brevet 11687447
Statut Délivré - en vigueur
Date de dépôt 2022-01-04
Date de la première publication 2023-06-27
Date d'octroi 2023-06-27
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tsung-Chieh

Abrégé

A method and apparatus for performing access control of a memory device with aid of additional physical address information are provided. The method includes: during a garbage collection procedure, reading valid data from a source block and writing the valid data into a destination block; updating at least one logical-to-physical address mapping table; receiving a first read request from a host device, wherein the first read request indicates reading at a first logical address; in response to the first read request, reading the valid data of the destination block according to the second physical address associated with the first logical address; receiving a second read request from the host device, wherein the second read request indicates reading at the first logical address; and in response to the second read request, reading the valid data of the source block according to the first physical address associated with the first logical address.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

94.

APPARATUS AND METHOD FOR DETECTING ERRORS DURING DATA ENCRYPTION

      
Numéro d'application 18076615
Statut En instance
Date de dépôt 2022-12-07
Date de la première publication 2023-06-22
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Wu, Wun-Jhe
  • Chen, Po-Hung
  • Cheng, Chiao-Wen
  • Yu, Jiun-Hung
  • Liu, Chih-Wei

Abrégé

The invention introduces an apparatus for detecting errors during data encryption. The apparatus includes a key generation circuitry and a key-error detection circuitry. The key generation circuitry is arranged operably to realize a key expansion operation for generating multiple round keys based on a root key in an encryption algorithm, where the encryption algorithm encodes plaintext or an intermediate encryption result with one round key in a corresponding round. The error detection circuitry is arranged operably to: calculate redundant data corresponding to each round key; and output an error signal to a processing unit when finding that any round key does not match corresponding redundant data at a check point during the key expansion operation.

Classes IPC  ?

  • H04L 9/08 - Répartition de clés
  • H04L 9/06 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p.ex. système DES

95.

APPARATUS AND METHOD FOR DETECTING ERRORS DURING DATA ENCRYPTION

      
Numéro d'application 18076899
Statut En instance
Date de dépôt 2022-12-07
Date de la première publication 2023-06-22
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Wu, Wun-Jhe
  • Chen, Po-Hung
  • Cheng, Chiao-Wen
  • Yu, Jiun-Hung
  • Liu, Chih-Wei

Abrégé

The invention introduces an apparatus for detecting errors during data encryption. The apparatus includes an encoding circuitry and an error detection circuitry. The encoding circuitry is arranged operably to realize an encryption algorithm including multiple rounds, in which of each round encodes plaintext or an intermediate encryption result with a round key. The error detection circuitry is arranged operably to: calculate redundant data corresponding to the intermediate encryption result; and output an error signal to a processing unit when finding that the intermediate encryption result does not match the redundant data at a check point during an encryption process.

Classes IPC  ?

  • H04L 9/08 - Répartition de clés
  • H04L 9/06 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p.ex. système DES

96.

Memory controller and data processing method

      
Numéro d'application 18072725
Statut En instance
Date de dépôt 2022-12-01
Date de la première publication 2023-06-15
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Wu, Po-Wei

Abrégé

A memory controller includes an error correction code engine, a buffer memory and a microprocessor. In response to a first decoding result of predetermined data, the microprocessor performs a repeated read operation on a memory device to obtain multiple read results of a data chunk having the predetermined data. The data chunk includes multiple bits. The microprocessor further performs a data reconstruction and error correction procedure according to the read results of the data chunk. In an operation of data reconstruction, the microprocessor determines a bit value corresponding to each bit in the data chunk according to the read results of the data chunk to generate a reconstructed data chunk. In an operation of error correction, the microprocessor provides the reconstructed data chunk to the error correction code engine to obtain a second decoding result of the predetermined data.

Classes IPC  ?

  • G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

97.

Data storage device and data storage system

      
Numéro d'application 17884581
Statut En instance
Date de dépôt 2022-08-10
Date de la première publication 2023-06-08
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Chen, Chen-Hao

Abrégé

A data storage device includes multiple storage modules. Each storage module includes a storage which having a memory device and a first memory controller and a second memory controller. The first memory controller is coupled to the memory device for accessing the memory device. The second memory controller is coupled to the storage for accessing the storage. The first memory controller includes a first transmission interface. The second memory controller includes a second transmission interface. The first memory controller and the second memory controller communicate with each other through the first transmission interface and the second transmission interface.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

98.

Bridge device and data storage system

      
Numéro d'application 17884551
Statut En instance
Date de dépôt 2022-08-09
Date de la première publication 2023-06-01
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Chen, Chen-Hao

Abrégé

A bridge device includes a first controller and a second controller. The first controller includes a first transmission interface. The second controller is coupled to the first controller and includes a second transmission interface coupled to the first transmission interface. The first transmission interface and the second transmission interface are both flash memory interface.

Classes IPC  ?

  • G06F 13/40 - Structure du bus
  • G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation

99.

Interface circuit, memory controller and method for calibrating signal processing devices in an interface circuit

      
Numéro d'application 17948254
Statut En instance
Date de dépôt 2022-09-20
Date de la première publication 2023-06-01
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Shih, Fu-Jen

Abrégé

An interface circuit includes a signal processing circuit configured to process a reception signal received from a host device and a transmission signal to be transmitted to the host device. The signal processing circuit includes multiple signal processing devices and a calibration device. The calibration device is coupled to the signal processing devices and configured to sequentially calibrate a characteristic value of each signal processing device in a calibration procedure.

Classes IPC  ?

  • G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
  • H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue

100.

Interface circuit, memory controller and method for calibrating signal processing devices in an interface circuit of a memory controller

      
Numéro d'application 17951090
Numéro de brevet 11901961
Statut Délivré - en vigueur
Date de dépôt 2022-09-22
Date de la première publication 2023-06-01
Date d'octroi 2024-02-13
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Shih, Fu-Jen

Abrégé

A method, for calibrating signal processing devices in an interface circuit coupled to a host device, comprises: negotiating with the host device in a link up process about an operation mode for the interface circuit to operate in a calibration procedure; and calibrating a characteristic value of a first signal processing device and a characteristic value of a second signal processing device in the calibration procedure. The first signal processing device is disposed on a receiving signal processing path and configured to process a received signal and the second signal processing device is disposed on a transmitting signal processing path and configured to process a transmitting signal, and the interface circuit is configured to operate based on the operation mode in the calibration procedure.

Classes IPC  ?

  • H04B 17/11 - Surveillance; Tests d’émetteurs pour l’étalonnage
  • H04J 3/04 - Distributeurs combinés avec des modulateurs ou des démodulateurs
  • H04B 17/21 - Surveillance; Tests de récepteurs pour la correction des mesures
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