Silicon Motion, Inc.

Taïwan, Province de Chine

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Type PI
        Brevet 941
        Marque 22
Juridiction
        États-Unis 959
        Europe 4
Date
Nouveautés (dernières 4 semaines) 12
2023 septembre (MACJ) 5
2023 août 7
2023 juillet 5
2023 juin 10
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Classe IPC
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement 397
G06F 12/02 - Adressage ou affectation; Réadressage 295
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11 151
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires 108
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence 91
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Classe NICE
09 - Appareils et instruments scientifiques et électriques 21
42 - Services scientifiques, technologiques et industriels, recherche et conception 12
Statut
En Instance 85
Enregistré / En vigueur 878
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1.

CONTROL METHOD OF FLASH MEMORY CONTROLLER AND ASSOCIATED FLASH MEMORY CONTROLLER AND ELECTRONIC DEVICE

      
Numéro d'application 17692121
Statut En instance
Date de dépôt 2022-03-10
Date de la première publication 2023-09-14
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Liang, Chia-Chi
  • Lu, Tsu-Han
  • Yen, Hsiao-Chang

Abrégé

The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, the flash memory module includes a plurality of planes, and each plane includes a plurality of blocks; and the control method includes the steps of: after the flash memory controller is powered on, reading a first code bank from a specific block of the plurality of blocks; storing the first code bank into a buffer memory; executing the first code bank to manage the flash memory module; when the flash memory controller starts a code bank swapping operation, trying to read a second code bank from a super block; if the second code bank is read successfully, storing the second code bank into the buffer memory to replace the first code bank; and executing the second code bank to manage the flash memory module.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

2.

METHOD AND APPARATUS FOR CACHING ADDRESS MAPPING INFORMATION IN FLASH MEMORY BASED STORAGE DEVICE

      
Numéro d'application 17693431
Statut En instance
Date de dépôt 2022-03-14
Date de la première publication 2023-09-14
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Pai, Yi-Kai

Abrégé

A method of caching mapping table for use in a flash memory device having a flash memory controller and a flash memory is provided. The method includes: in response to a host read command, determining whether a group of a logical-to-physical (L2P) required by handling the host read command has been loaded to a DRAM of the flash memory controller; if the required group of the L2P mapping table has not been loaded to the DRAM, loading the required group of the L2P mapping table from the flash memory to a SRAM of the flash memory controller; directly accessing the SRAM to obtain an L2P address associated with the host read command from the required group of the L2P mapping table; and performing a read operation on the flash memory in response to the host read command according to the obtained L2P address.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 12/02 - Adressage ou affectation; Réadressage

3.

METHOD AND APPARATUS FOR PERFORMING ACCESS MANAGEMENT OF MEMORY DEVICE WITH AID OF SERIAL NUMBER ASSIGNMENT TIMING CONTROL

      
Numéro d'application 17691137
Statut En instance
Date de dépôt 2022-03-10
Date de la première publication 2023-09-14
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Hong, Wen-Chi
  • Tseng, Hsin-Hsiang

Abrégé

A method for performing access management of a memory device with aid of serial number assignment timing control and associated apparatus are provided. The method includes: managing a plurality of spare blocks with a spare pool; popping a first block from the spare pool to be a host data block, and performing first subsequent operations, wherein the host data block is arranged to receive data from a host device, and serial number assignment of the host data block corresponds to a timing of fully programing the host data block; and popping a second block from the spare pool to be a garbage collection (GC) destination block, and performing second subsequent operations, wherein the GC destination block is arranged to receive data from a GC source block during a GC procedure, and serial number assignment of the GC destination block corresponds to a timing of starting using the GC destination block.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

4.

FLASH MEMORY CONTROLLER AND METHOD CAPABLE OF SENDING READ COMMAND OR DATA TOGGLE COMMAND TO ASK FOR FLASH MEMORY DEVICE RETURN MORE PLANE DATA OF DIFFERENT PLANES

      
Numéro d'application 17679103
Statut En instance
Date de dépôt 2022-02-24
Date de la première publication 2023-09-07
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lu, Tsu-Han
  • Yen, Hsiao-Chang

Abrégé

A method of a flash memory controller includes: providing an input/output (I/O) circuit coupled to a flash memory device through a specific communication interface; and, controlling a processor sending a specific read command or a data toggle command through the I/O circuit and the specific communication interface into the flash memory device, to make the flash memory device perform a data toggle operation to control the flash memory device’s data register selecting and transferring a first data unit and a second data unit to the flash memory device’s I/O control circuit to make the I/O control circuit sequentially transmit the first data unit and the second data unit to the flash memory controller through the specific communication interface in response to the specific read command or the data toggle command.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

5.

FLASH MEMORY DEVICE, CONTROLLER, AND METHOD CAPABLE OF PERFORMING ACCESS OPERATION UPON DATA UNIT(s) OF MULTIPLE PLANES OF FLASH MEMORY DEVICE IN RESPONSE ONE SIMPLIFIED COMMAND SEQUENCE

      
Numéro d'application 17679120
Statut En instance
Date de dépôt 2022-02-24
Date de la première publication 2023-09-07
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lu, Tsu-Han
  • Yen, Hsiao-Chang

Abrégé

A flash memory scheme simplifies the command sequences transmitted between a flash memory device and a flash memory controller into a simplified command sequence so as to reduce the waiting time period of the command transmission and improve the performance of flash memory.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

6.

FLASH MEMORY DEVICE, CONTROLLER, AND METHOD CAPABLE OF PERFORMING ACCESS OPERATION UPON DATA UNIT(s) OF MULTIPLE PLANES OF FLASH MEMORY DEVICE IN RESPONSE ONE SIMPLIFIED COMMAND SEQUENCE

      
Numéro d'application 17679116
Statut En instance
Date de dépôt 2022-02-24
Date de la première publication 2023-08-24
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lu, Tsu-Han
  • Yen, Hsiao-Chang

Abrégé

A flash memory scheme simplifies the command sequences transmitted between a flash memory device and a flash memory controller into a simplified command sequence so as to reduce the waiting time period of the command transmission and improve the performance of flash memory.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 12/02 - Adressage ou affectation; Réadressage

7.

FLASH MEMORY DEVICE, CONTROLLER, AND METHOD CAPABLE OF PERFORMING ACCESS OPERATION UPON DATA UNIT(s) OF MULTIPLE PLANES OF FLASH MEMORY DEVICE IN RESPONSE ONE SIMPLIFIED COMMAND SEQUENCE

      
Numéro d'application 17679125
Statut En instance
Date de dépôt 2022-02-24
Date de la première publication 2023-08-24
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lu, Tsu-Han
  • Yen, Hsiao-Chang

Abrégé

A flash memory scheme simplifies the command sequences transmitted between a flash memory device and a flash memory controller into a simplified command sequence so as to reduce the waiting time period of the command transmission and improve the performance of flash memory.

Classes IPC  ?

  • G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
  • G11C 16/14 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement
  • G11C 16/10 - Circuits de programmation ou d'entrée de données
  • G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
  • G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS

8.

DATA STORAGE DEVICE AND CONTROL METHOD FOR NON-VOLATILE MEMORY

      
Numéro d'application 17835206
Statut En instance
Date de dépôt 2022-06-08
Date de la première publication 2023-08-24
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Chang, Yu-Hao
  • Hsiao, Yu-Han
  • Chou, Po-Sheng

Abrégé

A solution for deteriorated non-volatile memory is shown. When determining that raw data read from the non-volatile memory is undesirable data, the controller updates a deterioration table to record a deteriorated logical address of the raw data that is the undesirable data. When performing garbage collection from a source block associated with the deteriorated logical address to a destination block and determining that the deteriorated logical address is listed in the deterioration table, the controller invalidates target data stored in the source block and mapped to the deteriorated logical address, without moving the target data from the source block to the destination block in the garbage collection.

Classes IPC  ?

  • G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
  • G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
  • G06F 12/02 - Adressage ou affectation; Réadressage

9.

FLASH MEMORY CONTROLLER AND METHOD CAPABLE OF SENDING READ COMMAND OR DATA TOGGLE COMMAND TO ASK FOR FLASH MEMORY DEVICE RETURN MORE PLANE DATA OF DIFFERENT PLANES

      
Numéro d'application 17679111
Statut En instance
Date de dépôt 2022-02-24
Date de la première publication 2023-08-24
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lu, Tsu-Han
  • Yen, Hsiao-Chang

Abrégé

A flash memory device is disclosed. The memory cell array has a first plane and a second plane and stores a first data unit and a second data unit. The data register buffers the first data unit and the second data unit transmitted from the memory cell array when a read command or a data toggle command is received and stored by the command register. The control circuit performs a data toggle operation to control the data register selecting and transferring the first data unit and the second data unit to the I/O control circuit to make the I/O control circuit sequentially transmit the first data unit and the second data unit to the flash memory controller through a specific communication interface in response to the read command or the data toggle command. The transmission of the first data unit is followed by the transmission of the second data unit.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

10.

FLASH MEMORY CONTROLLER AND METHOD CAPABLE OF SENDING DATA TOGGLE SET-FEATURE SIGNAL TO ENABLE, DISABLE, OR CONFIGURE DATA TOGGLE OPERATION OF FLASH MEMORY DEVICE

      
Numéro d'application 17679136
Statut En instance
Date de dépôt 2022-02-24
Date de la première publication 2023-08-24
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lu, Tsu-Han
  • Yen, Hsiao-Chang

Abrégé

A method of a flash memory controller includes: providing an input/output (I/O) circuit coupled to the flash memory device; and sending a data toggle set-feature signal to the flash memory device to enable, disable, or configure a data toggle operation of the flash memory device; the data toggle operation of the flash memory device is arranged to make the flash memory device control the flash memory device's data register selecting and transferring a first data unit and a second data unit to the flash memory device's I/O control circuit to make the I/O control circuit sequentially transmit the first data unit and the second data unit to the flash memory controller through the specific communication interface in response to a specific read command or a data toggle command transmitted by the flash memory controller.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

11.

DATA STORAGE DEVICE AND CONTROL METHOD FOR NON-VOLATILE MEMORY

      
Numéro d'application 17835183
Statut En instance
Date de dépôt 2022-06-08
Date de la première publication 2023-08-24
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Chang, Yu-Hao
  • Hsiao, Yu-Han
  • Chou, Po-Sheng

Abrégé

A solution for deteriorated non-volatile memory is shown. When a controller determines that raw data read from the non-volatile memory is undesirable data, the controller performs safety moving of valid data of an erasure unit that contains the raw data to safely move the valid data of the erasure unit, wherein the erasure unit is a high-risk block, and the raw data in the non-volatile memory is regarded as being in a deteriorated physical address. Prior to being moved in the safety moving, the raw data is changed so that it is different from the undesirable data. In an exemplary embodiment, the undesirable data is all-1's data or all-0's data.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

12.

DATA STORAGE DEVICE AND CONTROL METHOD FOR NON-VOLATILE MEMORY

      
Numéro d'application 17835198
Statut En instance
Date de dépôt 2022-06-08
Date de la première publication 2023-08-24
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Chang, Yu-Hao
  • Hsiao, Yu-Han
  • Chou, Po-Sheng

Abrégé

A solution for deteriorated non-volatile memory is shown. When determining that raw data read from the non-volatile memory is undesirable data, the controller updates a deterioration table to record a deteriorated logical address of the raw data that is the undesirable data. In response to a read request that a host issues to read the non-volatile memory for data of the deteriorated logical address, the controller obtains the deteriorated logical address from the deterioration table and informs the host that deterioration has happened at the deteriorated logical address.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

13.

FLASH MEMORY SCHEME CAPABLE OF DECREASING WAITING TIME OF TRIM COMMAND

      
Numéro d'application 17578380
Statut En instance
Date de dépôt 2022-01-18
Date de la première publication 2023-07-20
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Hong, Wen-Chi
  • Ciou, Huang-Jhih

Abrégé

A method of a flash memory controller used to be externally coupled to a host device and a flash memory, comprising: providing a multi-processor having a plurality of processing units; receiving a trim command and a logical block address (LBA) range sent from the host device; separating multiple operations of the trim command into N threads according to at least one of a number of the processing units, types of the multiple operations, numbers of execution cycles of the multiple operations, and portions of the LBA range; using the processing units to execute the N threads individually; and maximizing a number of execution cycles during which the processing units are busy.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

14.

Method and apparatus for accessing L2P address without searching group-to-flash mapping table

      
Numéro d'application 17693420
Numéro de brevet 11704238
Statut Délivré - en vigueur
Date de dépôt 2022-03-14
Date de la première publication 2023-07-18
Date d'octroi 2023-07-18
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Pai, Yi-Kai

Abrégé

A method of caching mapping table for use in a flash memory device having a flash memory controller and a flash memory is provided. The method includes: in response to a host read/write command, checking a G2F mapping table to determine whether a required group of a L2P mapping table has been loaded to a DRAM of the flash memory controller and accordingly obtain a node index indicating which memory node of the DRAM the group is stored in; recording the node index to a first region of a SRAM of the flash memory controller; accessing the DRAM to obtain an L2P address indicating a physical address that is associated with the host read/write command from the group of the L2P mapping table by referencing the node index stored in the first region of the SRAM; and performing a read/write operation on the flash memory according to the L2P address.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage

15.

METHOD AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM AND APPARATUS FOR DYNAMICALLY UPDATING OPTIMIZATION READ VOLTAGE TABLE

      
Numéro d'application 18080852
Statut En instance
Date de dépôt 2022-12-14
Date de la première publication 2023-07-13
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Chen, Chun-Yi
  • Chang, Hsiao-Te

Abrégé

The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for dynamically updating an optimization read voltage (RV) table. The method includes: obtaining a data-read transaction and replying with the data-read transaction to a host side after listening to a first request for read-performance data, which is issued by the host side, thereby enabling the data-performance transaction to be used in an update of the optimization RV table for a designated memory-cell type; and programming multiple records of an updated optimization RV table for the designated memory-cell type into a designated location of the NAND-flash module after listening to a second request for updating the optimization RV table for the designated memory-cell type, which is issued by the host side. The data-read transaction includes a current environmental parameter of a NAND-flash module, the designated memory-cell type and a bit error rate (BER). Each record includes one set of RV parameters and an environmental parameter associated with the set of RV parameters.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

16.

METHOD AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM AND APPARATUS FOR READING DATA WITH OPTIMIZATION READ VOLTAGE TABLE

      
Numéro d'application 18080842
Statut En instance
Date de dépôt 2022-12-14
Date de la première publication 2023-07-13
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Chen, Chun-Yi
  • Chang, Hsiao-Te

Abrégé

The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for reading data with an optimization read voltage (RV) table. The method includes: determining one set of RVs for a designated memory-cell type according to a current environmental parameter of a NAND-flash module and content of the optimization RV table; and reading data on a page corresponding to the designated memory-cell type from the NAND-flash module with the set of RVs. The optimization RV table includes multiple records and each record includes one set of RV parameters and an environmental parameter associated with the set of RV parameters.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

17.

Method and apparatus for performing access management of memory device with aid of buffer usage reduction control

      
Numéro d'application 17569451
Numéro de brevet 11704054
Statut Délivré - en vigueur
Date de dépôt 2022-01-05
Date de la première publication 2023-07-06
Date d'octroi 2023-07-18
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Li, An-Pang

Abrégé

A method for performing access management of a memory device with aid of buffer usage reduction control and associated apparatus are provided. The method includes: determining whether any host command among a plurality of host commands from a host device is a trim-related read command, wherein the trim-related read command represents a read command indicating that reading from at least one trimmed location is required; in response to the any host command being the trim-related read command, determining an estimated trim-related read operation count regarding a data buffer according to a trimmed range of the at least one trimmed location and a predetermined unit size of accessing the data buffer; writing predetermined trimmed data having the predetermined unit size into the data buffer; and controlling a transmission interface circuit to read the predetermined trimmed data from the data buffer multiple times, for being returned to the host device.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 12/02 - Adressage ou affectation; Réadressage

18.

APPARATUS AND METHOD FOR DRIVING REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) ENGINE

      
Numéro d'application 17984691
Statut En instance
Date de dépôt 2022-11-10
Date de la première publication 2023-06-29
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lee, Lien-Yu
  • Chiu, Shen-Ting

Abrégé

The invention is related to an apparatus and a method for driving redundant array of independent disks (RAID) engine. The method, performed by a RAID controller in a RAID pre-processor, including: completing a driving operation for performing a series of physical-layer signal interactions with a RAID engine according to a driving value in the configuration register. The driving value corresponds to a command issued by a processing unit. The processing unit performs an operation irrelevant from an encoding or a decoding of a parity of a page group in parallel of the driving operation by the RAID controller in coordination with the RAID engine.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

19.

Method for improve read disturbance phenomenon of flash memory module and associated flash memory controller and electronic device

      
Numéro d'application 17574579
Numéro de brevet 11687290
Statut Délivré - en vigueur
Date de dépôt 2022-01-13
Date de la première publication 2023-06-27
Date d'octroi 2023-06-27
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Huang, Cheng-Hao

Abrégé

The present invention provides a control method of a flash memory controller wherein the control method includes the steps of: selecting a first block; reading pages of the first block and determining a bit error rate or a bit error count of each page; for each of the pages, if the bit error rate or the bit error count of the page is not greater than a first threshold value, moving the data of the page into a second block; and for each of the pages, if the bit error rate or the bit error count of the page is greater than the first threshold value, moving the data of the page into a third block; wherein a number of pages corresponding to a word line of the second block is less than a number of pages corresponding to a word line of the third block.

Classes IPC  ?

  • G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

20.

Method and apparatus for performing access control of memory device with aid of additional physical address information

      
Numéro d'application 17568690
Numéro de brevet 11687447
Statut Délivré - en vigueur
Date de dépôt 2022-01-04
Date de la première publication 2023-06-27
Date d'octroi 2023-06-27
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tsung-Chieh

Abrégé

A method and apparatus for performing access control of a memory device with aid of additional physical address information are provided. The method includes: during a garbage collection procedure, reading valid data from a source block and writing the valid data into a destination block; updating at least one logical-to-physical address mapping table; receiving a first read request from a host device, wherein the first read request indicates reading at a first logical address; in response to the first read request, reading the valid data of the destination block according to the second physical address associated with the first logical address; receiving a second read request from the host device, wherein the second read request indicates reading at the first logical address; and in response to the second read request, reading the valid data of the source block according to the first physical address associated with the first logical address.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

21.

APPARATUS AND METHOD FOR DETECTING ERRORS DURING DATA ENCRYPTION

      
Numéro d'application 18076615
Statut En instance
Date de dépôt 2022-12-07
Date de la première publication 2023-06-22
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Wu, Wun-Jhe
  • Chen, Po-Hung
  • Cheng, Chiao-Wen
  • Yu, Jiun-Hung
  • Liu, Chih-Wei

Abrégé

The invention introduces an apparatus for detecting errors during data encryption. The apparatus includes a key generation circuitry and a key-error detection circuitry. The key generation circuitry is arranged operably to realize a key expansion operation for generating multiple round keys based on a root key in an encryption algorithm, where the encryption algorithm encodes plaintext or an intermediate encryption result with one round key in a corresponding round. The error detection circuitry is arranged operably to: calculate redundant data corresponding to each round key; and output an error signal to a processing unit when finding that any round key does not match corresponding redundant data at a check point during the key expansion operation.

Classes IPC  ?

  • H04L 9/08 - Répartition de clés
  • H04L 9/06 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p.ex. système DES

22.

APPARATUS AND METHOD FOR DETECTING ERRORS DURING DATA ENCRYPTION

      
Numéro d'application 18076899
Statut En instance
Date de dépôt 2022-12-07
Date de la première publication 2023-06-22
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Wu, Wun-Jhe
  • Chen, Po-Hung
  • Cheng, Chiao-Wen
  • Yu, Jiun-Hung
  • Liu, Chih-Wei

Abrégé

The invention introduces an apparatus for detecting errors during data encryption. The apparatus includes an encoding circuitry and an error detection circuitry. The encoding circuitry is arranged operably to realize an encryption algorithm including multiple rounds, in which of each round encodes plaintext or an intermediate encryption result with a round key. The error detection circuitry is arranged operably to: calculate redundant data corresponding to the intermediate encryption result; and output an error signal to a processing unit when finding that the intermediate encryption result does not match the redundant data at a check point during an encryption process.

Classes IPC  ?

  • H04L 9/08 - Répartition de clés
  • H04L 9/06 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p.ex. système DES

23.

Memory controller and data processing method

      
Numéro d'application 18072725
Statut En instance
Date de dépôt 2022-12-01
Date de la première publication 2023-06-15
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Wu, Po-Wei

Abrégé

A memory controller includes an error correction code engine, a buffer memory and a microprocessor. In response to a first decoding result of predetermined data, the microprocessor performs a repeated read operation on a memory device to obtain multiple read results of a data chunk having the predetermined data. The data chunk includes multiple bits. The microprocessor further performs a data reconstruction and error correction procedure according to the read results of the data chunk. In an operation of data reconstruction, the microprocessor determines a bit value corresponding to each bit in the data chunk according to the read results of the data chunk to generate a reconstructed data chunk. In an operation of error correction, the microprocessor provides the reconstructed data chunk to the error correction code engine to obtain a second decoding result of the predetermined data.

Classes IPC  ?

  • G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

24.

Data storage device and data storage system

      
Numéro d'application 17884581
Statut En instance
Date de dépôt 2022-08-10
Date de la première publication 2023-06-08
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Chen, Chen-Hao

Abrégé

A data storage device includes multiple storage modules. Each storage module includes a storage which having a memory device and a first memory controller and a second memory controller. The first memory controller is coupled to the memory device for accessing the memory device. The second memory controller is coupled to the storage for accessing the storage. The first memory controller includes a first transmission interface. The second memory controller includes a second transmission interface. The first memory controller and the second memory controller communicate with each other through the first transmission interface and the second transmission interface.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

25.

Bridge device and data storage system

      
Numéro d'application 17884551
Statut En instance
Date de dépôt 2022-08-09
Date de la première publication 2023-06-01
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Chen, Chen-Hao

Abrégé

A bridge device includes a first controller and a second controller. The first controller includes a first transmission interface. The second controller is coupled to the first controller and includes a second transmission interface coupled to the first transmission interface. The first transmission interface and the second transmission interface are both flash memory interface.

Classes IPC  ?

  • G06F 13/40 - Structure du bus
  • G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation

26.

Interface circuit, memory controller and method for calibrating signal processing devices in an interface circuit

      
Numéro d'application 17948254
Statut En instance
Date de dépôt 2022-09-20
Date de la première publication 2023-06-01
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Shih, Fu-Jen

Abrégé

An interface circuit includes a signal processing circuit configured to process a reception signal received from a host device and a transmission signal to be transmitted to the host device. The signal processing circuit includes multiple signal processing devices and a calibration device. The calibration device is coupled to the signal processing devices and configured to sequentially calibrate a characteristic value of each signal processing device in a calibration procedure.

Classes IPC  ?

  • G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
  • H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue

27.

Interface circuit, memory controller and method for calibrating signal processing devices in an interface circuit of a memory controller

      
Numéro d'application 17951090
Statut En instance
Date de dépôt 2022-09-22
Date de la première publication 2023-06-01
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Shih, Fu-Jen

Abrégé

A method, for calibrating signal processing devices in an interface circuit coupled to a host device, comprises: negotiating with the host device in a link up process about an operation mode for the interface circuit to operate in a calibration procedure; and calibrating a characteristic value of a first signal processing device and a characteristic value of a second signal processing device in the calibration procedure. The first signal processing device is disposed on a receiving signal processing path and configured to process a received signal and the second signal processing device is disposed on a transmitting signal processing path and configured to process a transmitting signal, and the interface circuit is configured to operate based on the operation mode in the calibration procedure.

Classes IPC  ?

  • H04B 17/11 - Surveillance; Tests d’émetteurs pour l’étalonnage
  • H04B 17/21 - Surveillance; Tests de récepteurs pour la correction des mesures
  • H04J 3/04 - Distributeurs combinés avec des modulateurs ou des démodulateurs

28.

METHOD AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM AND APPARATUS FOR UPDATING HOST-TO-FLASH ADDRESS MAPPING TABLE

      
Numéro d'application 17971403
Statut En instance
Date de dépôt 2022-10-21
Date de la première publication 2023-05-25
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Chiu, Shen-Ting

Abrégé

The invention relates to a method, a non-transitory computer-readable program product and an apparatus for updating a host-to-flash address mapping (H2F) table. The method includes: allocating space in a random access memory (RAM) for a first H2F sub-table and intermediate information, which is used to update a second H2F sub-table in a flash module; updating the first H2F sub-table and the intermediate information temporarily stored in the RAM during an execution of a host write command or a host discard command; and in a table update procedure, programming the first H2F sub-table temporarily stored in the RAM into a system block in the flash module, updating the second H2F sub-table according to the intermediate information stored in the RAM, and programming updated second H2F sub-table into the system block in the flash module.

Classes IPC  ?

  • G06F 12/1009 - Traduction d'adresses avec tables de pages, p.ex. structures de table de page

29.

METHOD AND APPARATUS FOR PERFORMING ACCESS CONTROL OF MEMORY DEVICE WITH AID OF MULTI-STAGE GARBAGE COLLECTION MANAGEMENT

      
Numéro d'application 17531780
Statut En instance
Date de dépôt 2021-11-21
Date de la première publication 2023-05-25
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tsung-Chieh

Abrégé

A method and apparatus for performing access control of a memory device with aid of multi-stage garbage collection (GC) management are provided. The method includes: during a first GC stage, sending a first simple read command to the NV memory in order to try reading first valid data from a first source block, sending the first valid data into an internal buffer of the NV memory, for being programed into a first destination block, sending a second simple read command to the NV memory in order to try reading second valid data from the first source block, and in response to reading the second valid data from the first source block being unsuccessful, preventing retrying reading the second valid data from the first source block; completing at least one host-triggered operation; and during a second GC stage, retrying reading the second valid data from the first source block.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

30.

STORAGE DEVICES INCLUDING A CONTROLLER AND METHODS OPERATING THE SAME

      
Numéro d'application 17534275
Statut En instance
Date de dépôt 2021-11-23
Date de la première publication 2023-05-25
Propriétaire SILICON MOTION INC. (Taïwan, Province de Chine)
Inventeur(s)
  • Su, Che Jen
  • Guo, Bao Ren

Abrégé

The present invention provides a storage device including a controller and methods for operating the storage device and the controller. A controller of a storage device may comprise: an interface controller; a memory controller; a processor configured to transmit downstream commands and upstream commands to the memory controller. The memory controller may be coupled between the interface controller and the processor and may comprise: a first command queue; a second command queue; and a tag generator. The memory controller may be configured to: store a first command received from the processor in the first command queue; store a second command received from the processor in the second command queue; and in response to a first access region of the first command overlapping a second access region of the second command in the second queue, assign an order tag for the second command based on a first serial number of the first command by the tag generator.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

31.

STORAGE DEVICES INCLUDING A CONTROLLER AND METHODS OPERATING THE SAME

      
Numéro d'application 17534283
Statut En instance
Date de dépôt 2021-11-23
Date de la première publication 2023-05-25
Propriétaire SILICON MOTION INC. (Taïwan, Province de Chine)
Inventeur(s)
  • Su, Che Jen
  • Guo, Bao Ren

Abrégé

The present invention provides a storage device including a controller and methods for operating the storage device and the controller. A controller of a storage device may comprise: an interface controller; a memory controller; a processor configured to transmit downstream commands and upstream commands to the memory controller. The memory controller may be coupled between the interface controller and the processor and may comprise: a first command queue; a second command queue; and a racing handler. The memory controller may be configured to: store a first command received from the processor in the first command queue; transmit, to the interface controller, first information associated with the first command; store a second command received from the processor in the second command queue; transmit, to the interface controller, second information associated with the second command; and in response to a second access region of the second command overlapping a first access region of the first command, assign a second serial number for the second command based on a first serial number for the first command by the racing handler.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

32.

CONTROL METHOD FOR FLASH MEMORY CONTROLLER AND ASSOCIATED FLASH MEMORY CONTROLLER AND STORAGE DEVICE

      
Numéro d'application 18098129
Statut En instance
Date de dépôt 2023-01-18
Date de la première publication 2023-05-18
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Lin, Ching-Hui

Abrégé

The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, and the control method includes the steps of: receiving a settling command from a host device to configure a portion space of the flash memory module as a zoned namespace; receiving a write command from the host device to write data corresponding a first zone into a plurality of blocks of the flash memory module, wherein an access mode chose by the flash memory controller is determined based on a size of each zone and a size of each block.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

33.

FRACTIONAL FREQUENCY DIVIDER AND FLASH MEMORY CONTROLLER

      
Numéro d'application 18092908
Statut En instance
Date de dépôt 2023-01-03
Date de la première publication 2023-05-11
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Yao, Tien-Hsing
  • Lee, Chun-Cheng
  • Hsu, Sheng-I

Abrégé

The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

Classes IPC  ?

  • H03K 21/02 - Circuits d'entrée
  • H03K 21/10 - Circuits de sortie comprenant des circuits logiques
  • G06F 1/3234 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise
  • H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe
  • H03K 21/40 - Surveillance; Détection d'erreurs; Empêchement ou correction d'un fonctionnement incorrect du compteur

34.

DATA STORAGE DEVICE AND SELECTING BAD DATA BLOCK METHOD THEREOF

      
Numéro d'application 17714158
Statut En instance
Date de dépôt 2022-04-06
Date de la première publication 2023-05-04
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Huang, Sheng-Yuan

Abrégé

A data storage device and a selecting bad data block method thereof which includes: writing data to a sample block; reading written data of the sample block as read data; comparing the read data and the written data of each data column in sample block, and calculating a number of error bits in each chunk accordingly; selecting a column with the largest number of error bits in a chunk with the largest number of error bits as a bad data column; and recording the sample block as a bad data block when determining that the number of error bits in the chunk is greater than or equal to the first threshold value and the number of bad columns in the chunk is greater than or equal to the second threshold value.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

35.

DATA STORAGE DEVICE AND ERROR TOLERANCE SELECTING METHOD THEREOF

      
Numéro d'application 17715978
Statut En instance
Date de dépôt 2022-04-08
Date de la première publication 2023-05-04
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Huang, Sheng-Yuan

Abrégé

A data storage device, and an error tolerance selecting method thereof which includes: writing data to data blocks of the data storage device; reading written data of the data blocks as read data; comparing the read data and the written data of each data column in the data blocks, and calculating a number of error bits in each chunk including a plurality of data columns accordingly; calculating a difference value between the number of error bits in the chunk and a first threshold value to store the difference value in an error tolerance list; and selecting a largest difference value in the error tolerance list as an error tolerance.

Classes IPC  ?

  • G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

36.

METHOD AND APPARATUS FOR PERFORMING DATA ACCESS CONTROL OF MEMORY DEVICE WITH AID OF PREDETERMINED COMMAND

      
Numéro d'application 17862428
Statut En instance
Date de dépôt 2022-07-12
Date de la première publication 2023-05-04
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tzu-Yi

Abrégé

A method for performing data access control of a memory device with aid of a predetermined command and associated apparatus are provided. The method may include: utilizing the memory controller to receive a first single command from a host device through a transmission interface circuit of the memory controller; and in response to the first single command conforming to a predetermined format of the predetermined command, utilizing the memory controller to perform a series of operations according to the first single command, wherein the first single command represents a first migrate command, for migrating from a first source logical address to a first destination logical address. The series of operations may include: reading first data at the first source logical address; writing the first data at the first destination logical address; and controlling the memory device to make the first data at the first source logical address become invalid data.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

37.

METHOD AND APPARATUS FOR PERFORMING DATA ACCESS CONTROL OF MEMORY DEVICE WITH AID OF PREDETERMINED COMMAND

      
Numéro d'application 17864449
Statut En instance
Date de dépôt 2022-07-14
Date de la première publication 2023-05-04
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tzu-Yi

Abrégé

A method for performing data access control of a memory device with aid of a predetermined command and associated apparatus are provided. The method may include: utilizing the memory controller to receive a first single command from a host device through a transmission interface circuit of the memory controller; and in response to the first single command conforming to a predetermined format of the predetermined command, utilizing the memory controller to perform a series of operations according to the first single command, wherein the first single command represents a first duplicate command, for duplicating from a first source logical address to a first destination logical address. The series of operations may include: reading first data at the first source logical address; and writing the first data at the first destination logical address.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

38.

DATA STORAGE DEVICE AND SELECTING BAD DATA COLUMN METHOD THEREOF

      
Numéro d'application 17715061
Statut En instance
Date de dépôt 2022-04-07
Date de la première publication 2023-05-04
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Huang, Sheng-Yuan

Abrégé

A selecting bad data column method suitable for a data storage device is provided. The data storage device includes a control unit and a data storage medium. The selecting method performed by the control unit includes: reading written data of each data column as read data; comparing the read data and the written data of each data column to calculate an average number of error bits of each data column; determining whether the average number of error bits of each data column is greater than or equal to a predetermined value; and recording a data column as a bad data column when the average number of error bits of the data column is greater than or equal to the predetermined value. In this way, in order to avoid the problems that the error correction code can't be corrected or the correction capability is excessively consumed.

Classes IPC  ?

  • G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
  • G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

39.

Method and apparatus for performing access control of memory device with aid of aggressor bit information

      
Numéro d'application 17572635
Numéro de brevet 11630590
Statut Délivré - en vigueur
Date de dépôt 2022-01-11
Date de la première publication 2023-04-18
Date d'octroi 2023-04-18
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tsung-Chieh

Abrégé

A method and apparatus for performing access control of a memory device with aid of aggressor bit information are provided. The method includes: receiving a first host read command from a host device; sending a first read command to the NV memory in order to try reading first data from a first page; sending a second read command to the NV memory to obtain soft-decoding information and performing a first soft-decoding operation according to the soft-decoding information in order to try obtaining the first data from the first soft-decoding operation; reading multiple bits from at least one aggressor page to be the aggressor bit information; converting the soft-decoding information into adjusted soft-decoding information according to the aggressor bit information of the at least one aggressor page; and performing a second soft-decoding operation according to the adjusted soft-decoding information to obtain the first data from the second soft-decoding operation.

Classes IPC  ?

  • G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 12/02 - Adressage ou affectation; Réadressage
  • H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité

40.

Method for performing access management in a memory device, associated memory device and controller thereof, and associated electronic device

      
Numéro d'application 18078098
Numéro de brevet 11741016
Statut Délivré - en vigueur
Date de dépôt 2022-12-09
Date de la première publication 2023-04-06
Date d'octroi 2023-08-29
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lee, Jie-Hao
  • Yu, Cheng-Yu

Abrégé

A method for performing access management in a memory device, the associated memory device and the controller thereof, and the associated electronic device are provided. The method may include: receiving a host command and a logical address from a host device; performing at least one checking operation to obtain at least one checking result, for determining whether to load a logical-to-physical (L2P) table from the NV memory to a random access memory (RAM) of the memory device, wherein the L2P table includes address mapping information for accessing the target data, and performing the at least one checking operation to obtain at least one checking result includes checking whether a first L2P-table index pointing toward the L2P table and a second L2P-table index sent from the host device are equivalent to each other; and reading the target data from the NV memory, and sending the target data to the host device.

Classes IPC  ?

  • G06F 12/1009 - Traduction d'adresses avec tables de pages, p.ex. structures de table de page
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G06F 12/14 - Protection contre l'utilisation non autorisée de mémoire

41.

METHOD AND APPARATUS FOR PERFORMING AUTOMATIC SETTING CONTROL OF MEMORY DEVICE IN PREDETERMINED COMMUNICATIONS ARCHITECTURE WITH AID OF AUXILIARY SETTING MANAGEMENT

      
Numéro d'application 17586719
Statut En instance
Date de dépôt 2022-01-27
Date de la première publication 2023-04-06
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Huang, Han-Cheng

Abrégé

A method for performing automatic setting control of a memory device in predetermined communications architecture with aid of auxiliary setting management and associated apparatus are provided. The method may include: during initialization of the memory device, utilizing a processing circuit within a memory controller to load an auxiliary setting management table from a non-volatile memory into at least one storage unit of a hardware control circuit within the memory controller to be a loaded auxiliary setting management table, wherein the hardware control circuit is used for the automatic setting control; and utilizing the hardware control circuit within the memory controller to detect occurrence of a series of events according to state information of a transmission interface circuit within the memory controller, and to dynamically perform parameter setting on the transmission interface circuit according to the series of events, for reconfiguring the transmission interface circuit at runtime of the memory device.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

42.

METHOD AND APPARATUS FOR PERFORMING COMMUNICATIONS SPECIFICATION VERSION CONTROL OF MEMORY DEVICE IN PREDETERMINED COMMUNICATIONS ARCHITECTURE WITH AID OF COMPATIBILITY MANAGEMENT, AND ASSOCIATED COMPUTER-READABLE MEDIUM

      
Numéro d'application 17705413
Statut En instance
Date de dépôt 2022-03-28
Date de la première publication 2023-04-06
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Fang, Hong-Ren
  • Yang, Chun-Che
  • Lee, Cheng-Yu
  • Wang, Te-Kai

Abrégé

A method for performing communications specification version control of a memory device in predetermined communications architecture with aid of compatibility management, associated apparatus and computer-readable medium are provided. The method may include: utilizing a memory controller to receive a first command from a host device through a transmission interface circuit of the memory controller; utilizing the memory controller to execute a device-side compatibility management procedure of a compatibility management function to detect whether the host device conforms to any version of multiple predetermined versions of a predetermined communications specification according to the first command to generate a detection result, and selectively switch from one firmware version to another firmware version according to the detection result; and utilizing the memory controller to send a first response to the host device through the transmission interface circuit, wherein the first response is sent to the host device in response to the first command.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

43.

METHOD AND APPARATUS FOR PROGRAMMING DATA INTO FLASH MEMORY

      
Numéro d'application 17879182
Statut En instance
Date de dépôt 2022-08-02
Date de la première publication 2023-04-06
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Chiu, Shen-Ting

Abrégé

The invention relates to a method and an apparatus for programming data into flash memory. The method includes: obtaining, by the accelerator, an execution table indicating that data related to the first virtual carrier need to go through a mid-end and a back-end processing stages earlier than data related to other virtual carriers; driving, by the routing engine, a host interface (I/F) to obtain data associated with all cargos in the second virtual carrier, updating the second cargo flags with third cargo flags to indicate that data associated with all the cargos in the second virtual carrier are prepared in the front-end processing stage; and determining, by the accelerator, that data associated with any cargo in the first virtual carrier hasn’t been prepared according to information of the first cargo flags, and disallowing the second virtual carrier to proceed to the following processing stages.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

44.

FERRi

      
Numéro d'application 018856433
Statut Enregistrée
Date de dépôt 2023-03-31
Date d'enregistrement 2023-07-21
Propriétaire SILICON MOTION INC. (Taïwan, Province de Chine)
Classes de Nice  ?
  • 09 - Appareils et instruments scientifiques et électriques
  • 42 - Services scientifiques, technologiques et industriels, recherche et conception

Produits et services

Data storage devices; Data processing apparatus; Computers; Computer memory devices; Computer programs [downloadable software]; Computer programs, recorded; Computer software; Flash memory; Computer firmware; Work stations [computers]; Computer terminals; Internet servers; Computer hardware; Interfaces for computers; Card readers; Data carriers; Chips [integrated circuits]; Semi-conductors; Integrated circuits. Design of integrated circuits; Research and development of new products for others; Computer software design; Computer programming; Maintenance of computer software; Computer systems analysis; Advisory services relating to computer software design; Computer programming for data processing; Information technology consultancy; Electronic data storage; Providing information relating to computer technology and programming via a website; Cloud computing; Software as a service [SaaS].

45.

Data storage device and method for rewriting parameters thereof

      
Numéro d'application 18062075
Numéro de brevet 11720249
Statut Délivré - en vigueur
Date de dépôt 2022-12-06
Date de la première publication 2023-03-30
Date d'octroi 2023-08-08
Propriétaire SILICON MOTION, INC. (Taïwan, Province de Chine)
Inventeur(s)
  • Wang, Te-Kai
  • Chen, Yu-Da

Abrégé

A data storage device is provided. The data storage device includes a flash memory and a controller. The flash memory stores a firmware that includes a plurality of mode page settings, and each mode page setting includes a plurality of mode parameters. The controller receives a data out message arranged to rewrite a first mode page setting among the plurality of mode page settings. When determining, based on a reference array, that the data out message will change the mode parameters which cannot be rewritten in the first mode page setting, the controller rejects to change the mode parameters which cannot be rewritten in the first mode page setting. The reference array stores a rewriteable setting for each bit of the first mode page setting.

Classes IPC  ?

  • G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G11C 16/22 - Circuits de sécurité ou de protection pour empêcher l'accès non autorisé ou accidentel aux cellules de mémoire
  • G11C 16/10 - Circuits de programmation ou d'entrée de données
  • G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données

46.

METHOD AND APPARATUS FOR PROGRAMMING DATA INTO FLASH MEMORY

      
Numéro d'application 17879180
Statut En instance
Date de dépôt 2022-08-02
Date de la première publication 2023-03-30
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Chiu, Shen-Ting

Abrégé

The invention relates to a method, and an apparatus for programming data into flash memory. The method includes: driving, by the routing engine, a host interface (I/F) according to the front-end parameter set when determining that a front-end processing stage needs to be activated for the data-programming transaction; driving, by the accelerator, a Redundant Array of Independent Disks (RAID) engine according to the mid-end parameter set when receiving an activation message of the data-programming transaction from the routing engine and determining that a mid-end processing stage needs to be activated; and driving, by the accelerator, a data access engine according to the back-end parameter set when determining that the mid-end processing stage for the data-write transaction does not need to be activated or the mid-end processing stage for the data-write transaction has been completed, and a back-end processing stage for the data-write transaction needs to be activated.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G06F 12/0831 - Protocoles de cohérence de mémoire cache à l’aide d’un schéma de bus, p.ex. avec moyen de contrôle ou de surveillance
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

47.

METHOD AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM AND APPARATUS FOR PROGRAMMING DATA INTO FLASH MEMORY

      
Numéro d'application 17879205
Statut En instance
Date de dépôt 2022-08-02
Date de la première publication 2023-03-30
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Chiu, Shen-Ting

Abrégé

The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for programming data into flash memory. The method includes: generating a front-end parameter set, a mid-end parameter set and a back-end parameter set for each data-programming transaction; transmitting the front-end parameter set of each data-programming transaction to a routing engine, thereby enabling the routing engine to drive a host interface (I/F) to obtain from the host side; transmitting the mid-end parameter set of each data-programming transaction to an accelerator, thereby enabling the accelerator to drive the RAID engine to encrypt raw data or generate parity-page data according to multiple pages of the raw data; and transmitting the back-end parameter set of each data-programming transaction to the accelerator, thereby enabling the accelerator to drive a data access engine to program source data into a designated physical address of a flash module.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

48.

METHOD AND APPARATUS FOR PROGRAMMING DATA INTO FLASH MEMORY

      
Numéro d'application 17879232
Statut En instance
Date de dépôt 2022-08-02
Date de la première publication 2023-03-30
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Chiu, Shen-Ting

Abrégé

The invention relates to a method, and an apparatus for programming data into flash memory. The method includes: reading operating settings of a virtual carrier; setting a redundant array of independent disks (RAID) engine for driving the RAID engine to complete a designated encryption or encoding operation on first data associated with the virtual carrier when the operation settings indicate that the first data associated with the virtual carrier need to go through a mid-end processing stage; and sending a programming index to a data access engine for driving the data access engine to read a programming table from the SRAM, and program the second data associated with the virtual carrier into a designated address in a flash module when the operation settings indicate that the second data associated with the virtual carrier need to go through the back-end processing stage.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

49.

METHOD AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM AND APPARATUS FOR ACCESSING TO ENCODING-HISTORY INFORMATION

      
Numéro d'application 17879426
Statut En instance
Date de dépôt 2022-08-02
Date de la première publication 2023-03-30
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Chiu, Shen-Ting

Abrégé

The invention relates to a method, a non-transitory computer-readable storage medium and an apparatus for accessing to encoding-history information. The method includes: providing a super-block formed by storage space of flash units, where the super-block includes zones, each zone includes super-page strings, and each super-page string includes pages across the flash units; and programming encoding-history information into a metadata section of a designated first page of a designated super-page string, thereby enabling a damaged page that is occurred in the designated super-page string of the designated zone to be recovered according to the encoding-history information. The encoding-history information includes a history profile and history entries. The history profile indicates which zone or zones are covered in the super-block, and a quantity of the history entries. Each history entry includes information indicating that a designated second page of the designated super-page string in a designated zone hasn’t been passed through an engine to generate a parity for the designated super-page string.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11

50.

METHOD, MEMORY CONTROLLER, AND MEMORY SYSTEM FOR READING DATA STORED IN FLASH MEMORY

      
Numéro d'application 17991799
Statut En instance
Date de dépôt 2022-11-21
Date de la première publication 2023-03-16
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tsung-Chieh

Abrégé

An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.

Classes IPC  ?

  • G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
  • G11C 29/52 - Protection du contenu des mémoires; Détection d'erreurs dans le contenu des mémoires
  • G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p.ex. compteurs de rafraîchissement défectueux
  • G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
  • G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
  • H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité

51.

FERRI

      
Numéro de série 97842264
Statut En instance
Date de dépôt 2023-03-16
Propriétaire Silicon Motion Inc. (Taïwan, Province de Chine)
Classes de Nice  ?
  • 09 - Appareils et instruments scientifiques et électriques
  • 42 - Services scientifiques, technologiques et industriels, recherche et conception

Produits et services

(Based on Intent to Use) Computers; Semiconductors; Blank flash memory cards; Blank magnetic data carriers; Computer chips; Computer hardware; Computer memory devices; Computer terminals; Computer workstations comprising central processing units; Data processing apparatus; Downloadable computer programs for data processing tasks; Electronic card readers; Integrated circuits; Interfaces for computers; Internet servers; Recorded computer-aided design (CAD) software for data processing tasks; Recorded computer firmware for data processing tasks; Recorded computer programs for data processing tasks; Solid state drives(Based on 44(d) Priority Application) Computers; Semiconductors; Blank flash memory cards; Blank magnetic data carriers; Computer chips; Computer hardware; Computer memory devices; Computer terminals; Computer workstations comprising central processing units; Data processing apparatus; Downloadable computer programs for data processing tasks; Electronic card readers; Integrated circuits; Interfaces for computers; Internet servers; Recorded computer-aided design (CAD) software for data processing tasks; Recorded computer firmware for data processing tasks; Recorded computer programs for data processing tasks; Solid state drives (Based on Intent to Use) Cloud computing featuring software for use in data processing tasks; Computer programming; Computer software design; Computer systems analysis; Consulting services in the field of design, selection, implementation and use of computer hardware and software systems for others; Development and creation of computer programmes for data processing; Electronic data storage; Maintenance of computer software; Providing information relating to computer technology and programming via a website; Research and development of new products for others; Software as a service (SAAS) services featuring software for software for data processing tasks; Outsource service provider in the field of information technology consulting relating to installation, maintenance and repair of computer software(Based on 44(d) Priority Application) Cloud computing featuring software for use in data processing tasks; Computer programming; Computer software design; Computer systems analysis; Consulting services in the field of design, selection, implementation and use of computer hardware and software systems for others; Development and creation of computer programmes for data processing; Electronic data storage; Maintenance of computer software; Providing information relating to computer technology and programming via a website; Research and development of new products for others; Software as a service (SAAS) services featuring software for software for data processing tasks; Outsource service provider in the field of information technology consulting relating to installation, maintenance and repair of computer software

52.

METHOD FORMING A SEMICONDUCTOR PACKAGE DEVICE

      
Numéro d'application 17568167
Statut En instance
Date de dépôt 2022-01-04
Date de la première publication 2023-03-02
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Chien, Yi-Hung
  • Wang, Chun-Ying
  • Chen, Te-Wei
  • Chen, Hsiu-Yuan
  • Wu, Bing-Ling

Abrégé

A method forming a semiconductor package device includes: providing a substrate; forming a flip chip die on a first side on the substrate; and forming a molding compound on the first side of the substrate. The molding compound covers the flip chip die. The method further includes forming a heat sink on the molding compound; and forming a taping layer on a second side of the substrate, wherein the second side is opposite from the first side in a vertical direction. After forming the taping layer, the method further includes performing a pre-cut process and an etching process on the heat sink; and removing the taping layer.

Classes IPC  ?

  • H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
  • H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements

53.

Method for managing a memory apparatus

      
Numéro d'application 17975565
Numéro de brevet 11748258
Statut Délivré - en vigueur
Date de dépôt 2022-10-27
Date de la première publication 2023-02-16
Date d'octroi 2023-09-05
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lin, Tsai-Cheng
  • Lee, Chun-Kun

Abrégé

A method for managing a memory apparatus including a plurality of non-volatile (NV) memory elements includes: programming a physical block of a specific NV memory element, including: receiving a host command from a host; obtaining a host address and data from the host command; and linking the host address to a page of a physical block of the specific NV memory element and storing the data into the physical block. Before the pages of the physical block are fully programmed, a temporary local page linking address table is stored and is updated each time a linking relationship is changed. When the memory apparatus is to be shut down, the temporary local page linking address table is written to the specific NV memory element; and when the memory apparatus begins a start-up process, a global page address linking table is built by reading the local page address linking table.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G06F 12/1009 - Traduction d'adresses avec tables de pages, p.ex. structures de table de page

54.

FLASH MEMORY APPARATUS AND STORAGE MANAGEMENT METHOD FOR FLASH MEMORY

      
Numéro d'application 17963999
Statut En instance
Date de dépôt 2022-10-11
Date de la première publication 2023-02-02
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Yang, Tsung-Chieh
  • Hsu, Hong-Jung
  • Du, Jian-Dong

Abrégé

A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Classes IPC  ?

  • G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
  • G11C 29/52 - Protection du contenu des mémoires; Détection d'erreurs dans le contenu des mémoires
  • G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
  • G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
  • G11C 16/10 - Circuits de programmation ou d'entrée de données

55.

Garbage collection operation management with early garbage collection starting point

      
Numéro d'application 17955505
Numéro de brevet 11704241
Statut Délivré - en vigueur
Date de dépôt 2022-09-28
Date de la première publication 2023-01-26
Date d'octroi 2023-07-18
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tzu-Yi

Abrégé

A method of managing a garbage collection (GC) operation on a flash memory includes: setting a GC starting threshold, wherein the GC starting threshold indicates a predetermined spare block number that is higher than a target spare block number of spare blocks maintained by a flash translation layer (FTL) of the flash memory; determining whether to start the GC operation according to a current number of spare blocks in the flash memory and the GC starting threshold; and performing the GC operation on a source block in the flash memory when the current number of spare blocks is lower than or equal to the GC starting threshold.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage

56.

Method and apparatus for performing access management of memory device in predetermined communications architecture with aid of flexible delay time control

      
Numéro d'application 17475366
Numéro de brevet 11636055
Statut Délivré - en vigueur
Date de dépôt 2021-09-15
Date de la première publication 2023-01-19
Date d'octroi 2023-04-25
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Chen, Wen-Shu
  • Kuo, Kuo-Cyuan
  • Chen, I-Ta
  • Chen, Chih-Chiang

Abrégé

A method for performing access management of a memory device in predetermined communications architecture with aid of flexible delay time control and associated apparatus are provided. The method may include: utilizing at least one upper layer controller of a transmission interface circuit within the memory controller to dynamically set a delay parameter regarding transmission from the memory device to a host device, for preventing sleeping in delay time(s) corresponding to the delay parameter; utilizing a physical layer (PHY) circuit of the transmission interface circuit to transmit first data from the memory device to the host device, wherein a first delay time starts from a first time point at which transmitting the first data from the memory device to the host device is completed; and utilizing the PHY circuit to start transmitting second data from the memory device to the host device in the first delay time without restarting from sleeping.

Classes IPC  ?

  • G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire

57.

APPARATUS AND SYSTEM FOR DEBUGGING SOLID-STATE DISK (SSD) DEVICE

      
Numéro d'application 17737351
Statut En instance
Date de dépôt 2022-05-05
Date de la première publication 2022-12-29
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Tsai, Han-Chih
  • Chung, Ming-Kun

Abrégé

The invention relates to an apparatus and a system for debugging a solid-state disk (SSD) device. The apparatus includes a Joint Test Action Group (JTAG) add-on board; and a Raspberry Pi. The Raspberry Pi includes a General-Purpose Input/Output (GPIO) interface (I/F), coupled to the JTAG add-on board; and a processing unit, coupled to the GPIO I/F. The processing unit is arranged operably to: simulate to issue a plurality of JTAG command through the GPIO I/F to the SSD device for dumping data generated by the SSD device during operation from the SSD device.

Classes IPC  ?

  • G01R 31/3185 - Reconfiguration pour les essais, p.ex. LSSD, découpage
  • G01R 31/3183 - Génération de signaux d'entrée de test, p.ex. vecteurs, formes ou séquences de test
  • G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
  • G06F 13/38 - Transfert d'informations, p.ex. sur un bus

58.

METHOD AND APPARATUS AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM FOR DEBUGGING SOLID-STATE DISK (SSD) DEVICE

      
Numéro d'application 17729574
Statut En instance
Date de dépôt 2022-04-26
Date de la première publication 2022-12-29
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Jiang, Yu-Lin
  • Ho, Kun-Lin

Abrégé

The invention relates to a method, an apparatus and a non-transitory computer-readable storage medium for debugging a solid-state disk (SSD) device. The method is performed by a processing unit of a single-board personal computer (PC) when loading and executing a function of a runtime library, to include: receiving a request to drive a General-Purpose Input/Output (GPIO) interface (I/F), which includes a parameter required for completing a Joint Test Action Group (JTAG) command; issuing a first hardware instruction to the GPIO I/F to set a register corresponding to a GPIO test data input (TDI) pin according to the parameter carried in the request for emulating to issue the JTAG command to a solid-state disk (SSD) device, wherein the single-board PC is coupled to the SSD device through the GPIO I/F; issuing a second hardware instruction to the GPIO I/F to read a value of the register corresponding to the GPIO TDI pin; and replying with a completion message in response to the request.

Classes IPC  ?

  • G01R 31/3185 - Reconfiguration pour les essais, p.ex. LSSD, découpage
  • G01R 31/3183 - Génération de signaux d'entrée de test, p.ex. vecteurs, formes ou séquences de test
  • G01R 31/317 - Tests de circuits numériques

59.

METHOD AND APPARATUS AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM FOR DEBUGGING SOLID-STATE DISK (SSD) DEVICE

      
Numéro d'application 17729916
Statut En instance
Date de dépôt 2022-04-26
Date de la première publication 2022-12-29
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Yeh, Wei-Chih
  • Ho, Kun-Lin

Abrégé

The invention relates to a method, a non-transitory computer-readable storage medium, and an apparatus for debugging a solid-state disk (SSD) device. The method is performed by a processing unit of a single-board personal computer (PC) to include: simulating to issue a first Joint Test Action Group (JTAG) command through a General-Purpose Input/Output (GPIO) interface (I/F) to the SSD device for stopping a running of a processing unit of a flash controller in the SSD device; simulating to issue a second JTAG command through the GPIO I/F to the SSD device for forcing the SSD device to exit a sleep mode; and simulating to issue a third JTAG command through the GPIO I/F to the SSD device for reading a designated length of data from a static random access memory (SRAM) in the SSD device.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

60.

METHOD FOR ACCESSING FLASH MEMORY AND FLASH MEMORY CONTROLLER AND ELECTRONIC DEVICE THEREOF

      
Numéro d'application 17463542
Statut En instance
Date de dépôt 2021-08-31
Date de la première publication 2022-12-22
Propriétaire SILICON MOTION, INC. (Taïwan, Province de Chine)
Inventeur(s)
  • Ou, Hsu-Ping
  • Lu, Tsu-Han

Abrégé

Disclosed is a method for accessing data from a flash memory. The method comprises a flash memory controller receiving an access command from a host device, according to the access command, the flash memory accessing a plurality of data from the data pages of a plurality of blocks in the flash memory simultaneously and simultaneously temporarily storing the accessed data to the plurality of buffers of the flash memory, and simultaneously temporarily storing the data in the plurality of buffers of the flash memory buffer to the plurality of buffers the flash memory controller.

Classes IPC  ?

  • G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
  • G06F 13/40 - Structure du bus
  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G06F 12/0882 - Mode de page

61.

Memory controller, test device and link identification method

      
Numéro d'application 17700514
Numéro de brevet 11755439
Statut Délivré - en vigueur
Date de dépôt 2022-03-22
Date de la première publication 2022-12-22
Date d'octroi 2023-09-12
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lee, Cheng-Yu
  • Wang, Te-Kai

Abrégé

A memory controller coupled to a memory device and configured to control access operations of the memory device includes a host interface and a microprocessor. The microprocessor is coupled to the host interface and configured to set a value of a predetermined parameter to a specific value after the memory controller powers up and start to perform a link flow to try to establish a transmission link via the host interface. The predetermined parameter is one of a plurality of capability parameters of the host interface and the predetermined parameter is related to reception of the host interface. After the link flow is completed, the microprocessor is further configured to identify an object device with which the host interface establishes the transmission link according to the specific value and at least one of a plurality of attribute parameters associated with the transmission link.

Classes IPC  ?

  • G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p.ex. essais de mise en route
  • G06F 11/273 - Matériel de test, c. à d. circuits de traitement de signaux de sortie
  • G06F 11/263 - Génération de signaux d'entrée de test, p.ex. vecteurs, formes ou séquences de test

62.

Apparatus and method and computer program product for handling flash physical-resource sets

      
Numéro d'application 17879166
Numéro de brevet 11675698
Statut Délivré - en vigueur
Date de dépôt 2022-08-02
Date de la première publication 2022-11-24
Date d'octroi 2023-06-13
Propriétaire SILICON MOTION, INC. (Taïwan, Province de Chine)
Inventeur(s) Hsu, Che-Wei

Abrégé

The invention introduces an apparatus for handling flash physical-resource sets, at least including a random access memory (RAM), a processing unit and an address conversion circuit. The RAM includes multiple segments of temporary space and each segment thereof stores variables associated with a specific flash physical-resource set. The processing unit accesses user data of a flash physical-resource set when executing program code of a Flash Translation Layer (FTL). The address conversion circuit receives a memory address issued from the FTL, converts the memory address into a relative address of one segment of temporary space associated with the flash physical-resource set and outputs the relative address to the RAM for accessing a variable of the associated segment of temporary space.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G06F 12/0882 - Mode de page
  • G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
  • G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
  • G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul

63.

METHOD AND APPARATUS FOR PERFORMING ON-SYSTEM PHASE-LOCKED LOOP MANAGEMENT IN MEMORY DEVICE

      
Numéro d'application 17878042
Statut En instance
Date de dépôt 2022-07-31
Date de la première publication 2022-11-24
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Shih, Fu-Jen

Abrégé

A method and apparatus for performing on-system phase-locked loop (PLL) management in a memory device are provided. The method may include: utilizing a processing circuit within the memory controller to set multiple control parameters among multiple parameters stored in a register circuit of a transmission interface circuit within the memory controller, for controlling parameter adjustment of a PLL of the transmission interface circuit; utilizing a trimming control circuit to perform the parameter adjustment of the PLL according to the multiple control parameters, to adjust a set of voltage parameters among the multiple parameters, for optimizing a control voltage of a voltage controlled oscillator (VCO); and during the parameter adjustment of the PLL, utilizing the trimming control circuit to generate and store multiple processing results in the register circuit, for being sent back to the processing circuit, to complete the parameter adjustment of the PLL, thereby achieving the on-system PLL management.

Classes IPC  ?

  • H03L 7/23 - Synthèse de fréquence indirecte, c. à d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant plus d'une boucle avec des compteurs d'impulsions ou des diviseurs de fréquence
  • G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p.ex. compteurs de rafraîchissement défectueux
  • H03L 7/085 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie
  • H03L 7/187 - Synthèse de fréquence indirecte, c. à d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle une différence de temps étant utilisée pour verrouiller la boucle, le compteur entre des nombres fixes ou le diviseur de fréquence divisant par un nombre fixe utilisant des moyens pour accorder grossièrement l'oscillateur commandé en tension de la boucle

64.

METHOD AND APPARATUS FOR PERFORMING ACCESS MANAGEMENT OF MEMORY DEVICE IN HOST PERFORMANCE BOOSTER ARCHITECTURE WITH AID OF DEVICE SIDE TABLE INFORMATION

      
Numéro d'application 17874329
Statut En instance
Date de dépôt 2022-07-27
Date de la première publication 2022-11-17
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Chen, Yu-Ta

Abrégé

A method and apparatus for performing access management of a memory device in a Host Performance Booster (HPB) architecture with aid of device side table information are provided. The method may include: sending internal information of the memory device to a host device, to allow the host device to store the internal information of the memory device in a memory within the host device as host side table information at the host device; generating and storing multiple entries of at least one address mapping control table into a random access memory (RAM) as at least one portion of device side table information at the memory device; determining at least two physical addresses associated with at least two logical addresses according to the at least one address mapping control table; and reading data from the NV memory according to the at least two physical addresses.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

65.

MEMORY ADDRESSING METHODS AND ASSOCIATED CONTROLLER, MEMORY DEVICE AND HOST

      
Numéro d'application 17865130
Statut En instance
Date de dépôt 2022-07-14
Date de la première publication 2022-11-03
Propriétaire SILICON MOTION INC. (Taïwan, Province de Chine)
Inventeur(s) Hsieh, Chao-Kuei

Abrégé

The present invention provides a method for accessing a secure digital (SD) card, which includes a voltage supply pin for receiving voltage supply from a host, at least one ground pin, a clock pin for receiving a clock signal from a host, a command pin for receiving a command from a host, and four data pins for writing data into the SD card or reading data from the SD card. The method includes receiving, via the command pin, an address extension command including a first address from a host, receiving, via the command pin, an access command including a second address from a host, and accessing, via the data pins, at least a memory location of the SD card indicated by a third address, which is a combination of the first address and the second address. The access command indicates an access operation to be performed on the SD card selected from: a single read operation, a single write operation, a multiple read operation, a multiple write operation and an erase operation.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire

66.

APPARATUS AND METHOD FOR SEGMENTING A DATA STREAM OF A PHYSICAL LAYER

      
Numéro d'application 17858398
Statut En instance
Date de dépôt 2022-07-06
Date de la première publication 2022-11-03
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Huang, Han-Cheng

Abrégé

The invention introduces an apparatus for segmenting a data stream, installed in a physical layer, to include a host interface, a data register and a boundary detector. The data register is arranged to operably store data received from the host side through the host interface. The boundary detector is arranged to operably detect the content of a data register. When the data register includes a special symbol, the boundary detector outputs a starting address that the special symbol is stored in the data register to an offset register to update a value stored in the offset register, thereby enabling a stream splitter to divide data bits of the data register according to the updated value of the offset register.

Classes IPC  ?

  • G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
  • G06F 9/38 - Exécution simultanée d'instructions
  • G06F 13/14 - Gestion de demandes d'interconnexion ou de transfert
  • G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S

67.

Method and apparatus for data reads in host performance acceleration mode

      
Numéro d'application 17865706
Numéro de brevet 11650942
Statut Délivré - en vigueur
Date de dépôt 2022-07-15
Date de la première publication 2022-11-03
Date d'octroi 2023-05-16
Propriétaire SILICON MOTION, INC. (Taïwan, Province de Chine)
Inventeur(s) Shih, Po-Yi

Abrégé

The invention relates to a method, a non-transitory computer-readable storage medium, and an apparatus for executing an embedded multi-media card (eMMC) command. The method is performed by a processing unit of a flash controller to include: receiving an eMMC command from a host side; and performing a first function associated with a host performance acceleration (HPA) mode according to content of reserved bits of the eMMC command. The HPA mode allows the host side to allocate space in a system memory as an HPA buffer. The HPA buffer stores logical-block-address to physical-block-address (L2P) mapping entries obtained from the flash controller, and each L2P mapping entry stores information indicating which physical address that user data of a corresponding logical address is physically stored in a flash device, thereby enabling the host side to issue an HPA read command carrying the physical address to the flash controller.

Classes IPC  ?

  • G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
  • G06F 12/0875 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec mémoire cache dédiée, p.ex. instruction ou pile
  • G06F 12/1009 - Traduction d'adresses avec tables de pages, p.ex. structures de table de page

68.

Method and apparatus for page validity management and related storage system

      
Numéro d'application 17239669
Numéro de brevet 11580018
Statut Délivré - en vigueur
Date de dépôt 2021-04-25
Date de la première publication 2022-10-27
Date d'octroi 2023-02-14
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tzu-Yi

Abrégé

A method of performing a garbage collection operation on a source block includes: performing a plurality of partial page clean operations during a series of host write operations. Each partial clean operation includes: performing a validity check process within a partitioned searching range of the source block to obtain valid page information; and performing a page clean process according to the valid page information and a target clean page number to read valid pages indicated by the valid page information.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G06F 12/0882 - Mode de page
  • G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
  • G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation

69.

Method for managing flash memory module and associated flash memory controller and electronic device

      
Numéro d'application 17853888
Numéro de brevet 11630768
Statut Délivré - en vigueur
Date de dépôt 2022-06-29
Date de la première publication 2022-10-20
Date d'octroi 2023-04-18
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Du, Jian-Dong
  • Hsiao, Chia-Jung
  • Tsai, Pi-Ju

Abrégé

A flash memory controller includes a read only memory (ROM) and a microprocessor. The ROM is arranged to store a program code. The microprocessor is arranged to execute the program code to control access of a flash memory module. When executing the program code, the microprocessor is arranged to perform operations of: monitoring data retention state of one or more blocks in the flash memory module by reading a last page of the one or more blocks to obtain time information regarding the one or more blocks, which is generated by the flash memory controller; and arranging a specific block to a garbage collection process if time information obtained from the last page of the specific block exceeds a threshold.

Classes IPC  ?

  • G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G06F 12/0882 - Mode de page
  • G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
  • G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
  • G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p.ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
  • G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts

70.

Control method of flash memory controller and associated flash memory controller and storage device

      
Numéro d'application 17671602
Numéro de brevet 11748011
Statut Délivré - en vigueur
Date de dépôt 2022-02-15
Date de la première publication 2022-10-06
Date d'octroi 2023-09-05
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Lin, Ching-Hui

Abrégé

The present invention provides a control method of the flash memory controller. In the control method, after receiving a deallocate command from a host device, the flash memory controller will update a valid page count table, a detailed valid page count table and/or a zone valid page count table according to deallocate command, for the flash memory controller to efficiently and quickly determine if any one of the zones does not have any valid data, so that the flash memory controller can recommend the host device to send a reset command to reset the zone.

Classes IPC  ?

  • G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G06F 12/1009 - Traduction d'adresses avec tables de pages, p.ex. structures de table de page

71.

Initialization methods and associated controller, memory device and host

      
Numéro d'application 17843691
Numéro de brevet 11726686
Statut Délivré - en vigueur
Date de dépôt 2022-06-17
Date de la première publication 2022-10-06
Date d'octroi 2023-08-15
Propriétaire SILICON MOTION INC. (Taïwan, Province de Chine)
Inventeur(s) Hsieh, Chao-Kuei

Abrégé

The present invention provides a method performed by a secure digital (SD) card supporting both an SD mode and a peripheral component interconnect express (PCIe) mode for initializing the SD card. The method includes: (a) after receiving a first supply voltage through a first voltage supply pin from a host coupled to the SD card, entering the SD mode if the SD card is not in the PCIe mode and a CMD0 command for entering the SD mode is received through a command pin from the host coupled to the SD card; and (b) after receiving the first supply voltage through the first voltage supply pin from the host coupled to the SD card, performing a PCIe linkup process if the SD card is not in the SD mode and a second supply voltage is received through a second voltage supply pin from the host coupled to the SD card. The SD card enters the PCIe mode if the PCIe linkup process succeeds.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation

72.

CONTROL METHOD OF FLASH MEMORY CONTROLLER AND ASSOCIATED FLASH MEMORY CONTROLLER AND STORAGE DEVICE

      
Numéro d'application 17581998
Statut En instance
Date de dépôt 2022-01-24
Date de la première publication 2022-10-06
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Hsu, Ken-Fu
  • Lin, Ching-Hui

Abrégé

The present invention provides a control method of the flash memory controller. In the control method, by establishing a valid page count table, a detailed valid page count table and/or a zone valid page count table according to deallocate command from the host device, the flash memory controller can efficiently and quickly determine if any one of the zones does not have any valid data, so that the flash memory controller can recommend the host device to send a reset command to reset the zone. In addition, after receiving the reset command from the host device, the flash memory controller can use a garbage collection operation or directly put the blocks corresponding to the erased zone into a spare block pool, for the further use.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G06F 12/0882 - Mode de page
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

73.

CONTROL METHOD OF FLASH MEMORY CONTROLLER AND ASSOCIATED FLASH MEMORY CONTROLLER AND STORAGE DEVICE

      
Numéro d'application 17582010
Statut En instance
Date de dépôt 2022-01-24
Date de la première publication 2022-10-06
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Hsu, Ken-Fu
  • Lin, Ching-Hui

Abrégé

The present invention provides a control method of the flash memory controller. In the control method, by establishing a valid page count table, a detailed valid page count table and/or a zone valid page count table according to deallocate command from the host device, the flash memory controller can efficiently and quickly determine if any one of the zones does not have any valid data, so that the flash memory controller can recommend the host device to send a reset command to reset the zone. In addition, after receiving the reset command from the host device, the flash memory controller can use a garbage collection operation or directly put the blocks corresponding to the erased zone into a spare block pool, for the further use.

Classes IPC  ?

  • G06F 12/1009 - Traduction d'adresses avec tables de pages, p.ex. structures de table de page
  • G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire

74.

Control method of flash memory controller and associated flash memory controller and storage device

      
Numéro d'application 17671603
Numéro de brevet 11733895
Statut Délivré - en vigueur
Date de dépôt 2022-02-15
Date de la première publication 2022-10-06
Date d'octroi 2023-08-22
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Lin, Ching-Hui

Abrégé

The present invention provides a control method of the flash memory controller. In the control method, after receiving a deallocate command from a host device, the flash memory controller will update a valid page count table, a detailed valid page count table and/or a zone valid page count table according to deallocate command, for the flash memory controller to efficiently and quickly determine if any one of the zones does not have any valid data, so that the flash memory controller can recommend the host device to send a reset command to reset the zone.

Classes IPC  ?

  • G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

75.

METHOD OF PERFORMING WEAR-LEVELING OPERATION IN FLASH MEMORY AND RELATED CONTROLLER AND STORAGE SYSTEM

      
Numéro d'application 17206147
Statut En instance
Date de dépôt 2021-03-19
Date de la première publication 2022-09-22
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tzu-Yi

Abrégé

A method of performing a wear-leveling operation in a flash memory includes: determining a block age for each of a plurality of blocks in the flash memory according to a number of erase operations that have been performed on the flash memory after the block is erased; selecting one or more candidate source blocks from the plurality of blocks by comparing block ages of the plurality of blocks with an age limit; determining a source block from the one or more candidate source blocks according to erase counts or block ages of the one or more candidate source blocks; and performing the wear-leveling operation on the source block.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G11C 16/16 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p.ex. des réseaux, des mots, des groupes
  • G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention

76.

MEMORY ACCESS MODULE FOR PERFORMING A PLURALITY OF SENSING OPERATIONS TO GENERATE DIGITAL VALUES OF A STORAGE CELL IN ORDER TO PERFORM DECODING OF THE STORAGE CELL

      
Numéro d'application 17832680
Statut En instance
Date de dépôt 2022-06-05
Date de la première publication 2022-09-22
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Yang, Tsung-Chieh
  • Chang, Hsiao-Te
  • Wang, Wen-Long

Abrégé

A method for performing memory access of a Flash cell of a Flash memory includes: performing a plurality of sensing operations respectively corresponding to a plurality of sensing voltages to generate a first digital value and a second digital value of the Flash cell, the second digital value representing at least one candidate threshold voltage of the Flash cell; determining a threshold voltage of the Flash cell according to whether the at least one candidate threshold voltage is high or low; determining soft information of a bit stored in the Flash cell according to the threshold voltage of the Flash cell; and using the soft information to perform soft decoding.

Classes IPC  ?

  • G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
  • G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots

77.

Method and apparatus for executing host commands

      
Numéro d'application 17380402
Numéro de brevet 11537328
Statut Délivré - en vigueur
Date de dépôt 2021-07-20
Date de la première publication 2022-09-22
Date d'octroi 2022-12-27
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Wu, Po-Wei

Abrégé

An apparatus and a method for executing host commands, which is performed by a host interface in a flash controller, to include: determining whether a preset number of successive unaligned host long-write commands have been detected, where a first starting logical block address (LBA) number of data to be written, which is requested by each unaligned host long-write command, does not align with a first physical page of one super page; if so, calculating an offset, so that a second starting LBA number of data to be written, which is requested by a host write command, plus the offset aligns with a first physical page of one super page; generating a third starting LBA number by adding the offset to the second starting LBA number; and storing an entry in an LBA shifting table, which includes information about the second starting LBA number and the offset.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

78.

PERFORMASHAPE

      
Numéro de série 97583359
Statut En instance
Date de dépôt 2022-09-08
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Classes de Nice  ?
  • 09 - Appareils et instruments scientifiques et électriques
  • 42 - Services scientifiques, technologiques et industriels, recherche et conception

Produits et services

Blank flash memory cards; Blank magnetic data carriers; Blank optical data carriers; Computer chips; Computer hardware; Computer memory devices; Computer terminals; Computer workstations comprising central processing units; Computers; Data processing apparatus; Downloadable computer programs for data processing tasks; Electronic card readers; Integrated circuits; Interfaces for computers; Internet servers; Recorded computer-aided design (CAD) software for data processing tasks; Recorded computer firmware for data processing tasks; Recorded computer programs for data processing tasks; Semiconductors; Solid state drives Cloud computing featuring software for use in data processing tasks; Computer programming and software design; Computer systems analysis; Consulting services in the field of design of computer software systems for others; Design of integrated circuits; Development and creation of computer programmes for data processing; Electronic data storage; Information technology consulting services; Maintenance of computer software; Providing information relating to computer technology and programming via a website; Research and development of new products for others; Software as a service (SAAS) services featuring software for data processing tasks

79.

NANDCOMMAND

      
Numéro de série 97583499
Statut En instance
Date de dépôt 2022-09-08
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Classes de Nice  ?
  • 09 - Appareils et instruments scientifiques et électriques
  • 42 - Services scientifiques, technologiques et industriels, recherche et conception

Produits et services

Blank flash memory cards; Blank magnetic data carriers; Blank optical data carriers; Computer chips; Computer hardware; Computer memory devices; Computer terminals; Computer workstations comprising central processing units; Computers; Data processing apparatus; Downloadable computer programs for data processing tasks; Electronic card readers; Integrated circuits; Interfaces for computers; Internet servers; Recorded computer-aided design (CAD) software for data processing tasks; Recorded computer firmware for data processing tasks; Recorded computer programs for data processing tasks; Semiconductors; Solid state drives Cloud computing featuring software for use in data processing tasks; Computer programming and software design; Computer systems analysis; Consulting services in the field of design, selection, implementation and use of computer hardware and software systems for others; Design of integrated circuits; Development and creation of computer programmes for data processing; Electronic data storage; Information technology consulting services; Maintenance of computer software; Providing information relating to computer technology and programming via a website; Research and development of new products for others; Software as a service (SAAS) services featuring software for data processing tasks

80.

Memory and apparatus for performing access control with aid of multi-phase memory-mapped queue

      
Numéro d'application 17515570
Numéro de brevet 11630601
Statut Délivré - en vigueur
Date de dépôt 2021-11-01
Date de la première publication 2022-09-08
Date d'octroi 2023-04-18
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Yi, Cheng
  • Wang, Kaihong
  • Hsu, Sheng-I
  • Tseng, I-Ling

Abrégé

A method and apparatus for performing access control of a memory device with aid of a multi-phase memory-mapped queue are provided. The method includes: receiving a first host command from a host device; and in response to the first host command, utilizing a processing circuit within the controller to send a first operation command to the NV memory through a control logic circuit of the controller, and trigger a first set of secondary processing circuits within the controller to operate and interact via the multi-phase memory-mapped queue, for accessing the first data for the host device, wherein the processing circuit and the first set of secondary processing circuits share the multi-phase memory-mapped queue, and use the multi-phase memory-mapped queue as multiple chained message queues associated with multiple phases, respectively, for performing message queuing for a chained processing architecture including the processing circuit and the first set of secondary processing circuits.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

81.

METHOD AND COMPUTER PROGRAM PRODUCT FOR PERFORMING DATA WRITES INTO A FLASH MEMORY

      
Numéro d'application 17667801
Statut En instance
Date de dépôt 2022-02-09
Date de la première publication 2022-08-25
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Huang, Kuo-Ting

Abrégé

The invention introduces a method for performing data writes into a flash memory, at least including the steps: determining whether at least one host write command that requires to process immediately is presented in a submission queue (SQ) before performing a portion of a Host-Flash mapping (H2F) table update or a GC process; and executing the host write command that requires to process immediately in a batch and then performing the portion of the H2F table update or the GC process when the determination is positive.

Classes IPC  ?

82.

Data storage device and control method of address management using mapping tables

      
Numéro d'application 17584753
Numéro de brevet 11657001
Statut Délivré - en vigueur
Date de dépôt 2022-01-26
Date de la première publication 2022-08-25
Date d'octroi 2023-05-23
Propriétaire SILICON MOTION, INC. (Taïwan, Province de Chine)
Inventeur(s) Lin, Sheng-Hsun

Abrégé

A management technology for mapping data of a non-volatile memory is shown. A controller establishes a first mapping table and a second mapping table. By looking up the first mapping table, the controller maps a first logical address issued by the host for data reading to a first block substitute. By looking up the second mapping table, the controller maps the first block substitute to a first physical block of the non-volatile memory. The first mapping table further records a first offset for the first logical address. According to the first offset recorded in the first mapping table, the first logical address is mapped to a first data management unit having the first offset in the first physical block represented by the first block substitute.

Classes IPC  ?

  • G06F 12/1009 - Traduction d'adresses avec tables de pages, p.ex. structures de table de page

83.

Data Storage Device and Non-Volatile Memory Control Method

      
Numéro d'application 17648679
Statut En instance
Date de dépôt 2022-01-24
Date de la première publication 2022-08-25
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Chou, Po-Sheng
  • Huang, Hsiang-Yu

Abrégé

A control method for a multi-channel non-volatile memory is shown. When reading a read target on the non-volatile memory, the controller increases the read count of the monitored unit to which the read target belongs and, based on the read count, determines whether to move data of the monitored unit covering the read target to a safe space to deal with reading interference. The monitored unit is smaller than a cross-channel management unit in read-count group. The controller accesses a parallel accessing space of the non-volatile memory in parallel through all of the channels, and allocates the parallel accessing space based on the cross-channel management unit.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

84.

CONTROL METHOD FOR FLASH MEMORY CONTROLLER AND ASSOCIATED FLASH MEMORY CONTROLLER AND STORAGE DEVICE

      
Numéro d'application 17394427
Statut En instance
Date de dépôt 2021-08-05
Date de la première publication 2022-08-25
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Lin, Ching-Hui

Abrégé

The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, and the control method includes the steps of: receiving a settling command from a host device to configure a portion of the flash memory module as a zoned namespace; and determining a number of blocks within each block according to a size of each zone and a size of each block within the flash memory module.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

85.

Garbage collection operation management with early garbage collection starting point

      
Numéro d'application 17179342
Numéro de brevet 11494299
Statut Délivré - en vigueur
Date de dépôt 2021-02-18
Date de la première publication 2022-08-18
Date d'octroi 2022-11-08
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tzu-Yi

Abrégé

A method of managing a garbage collection (GC) operation on a flash memory includes: setting a GC starting threshold, wherein the GC starting threshold indicates a predetermined spare block number that is higher than a target spare block number of spare blocks maintained by a flash translation layer (FTL) of the flash memory; determining whether to start the GC operation according to a current number of spare blocks in the flash memory and the GC starting threshold; and performing the GC operation on a source block in the flash memory when the current number of spare blocks is lower than or equal to the GC starting threshold.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage

86.

GARBAGE COLLECTION OPERATION MANAGEMENT

      
Numéro d'application 17206137
Statut En instance
Date de dépôt 2021-03-19
Date de la première publication 2022-08-18
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tzu-Yi

Abrégé

A method of managing a garbage collection (GC) operation on a flash memory includes: calculating an overall spare area in a flash memory, which includes a spare area in a plurality of spare blocks in the flash memory and at least two of a spare area in one or more target blocks corresponding to writing of user data based on host write commands, a spare area in one or more destination blocks corresponding to writing of valid data based on the GC operation and a spare area in a source block corresponding to reading of valid data based on the GC operation; determining an adjustment factor according to the overall spare area; and performing the GC operation on the source block according to a GC-to-host base ratio and the adjustment factor.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage

87.

Garbage collection operation management based on overall valid page percentage of source block and candidate source block

      
Numéro d'application 17206149
Numéro de brevet 11681615
Statut Délivré - en vigueur
Date de dépôt 2021-03-19
Date de la première publication 2022-08-18
Date d'octroi 2023-06-20
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tzu-Yi

Abrégé

A method of managing a garbage collection (GC) operation includes: comprising: selecting a source block and at least one candidate source block from the flash memory; calculating an overall valid page percentage according to a number of valid pages in the source block and the at least one candidate source block; determining a GC-to-host base ratio according to the overall valid page percentage; and performing the GC operation on the source block according to at least the GC-to-host base ratio.

Classes IPC  ?

  • G06F 12/02 - Adressage ou affectation; Réadressage

88.

Method and computer-readable storage medium and apparatus for adjusting operating frequencies

      
Numéro d'application 17729319
Numéro de brevet 11714475
Statut Délivré - en vigueur
Date de dépôt 2022-04-26
Date de la première publication 2022-08-11
Date d'octroi 2023-08-01
Propriétaire SILICON MOTION, INC. (Taïwan, Province de Chine)
Inventeur(s)
  • Shen, Chang-Wei
  • Wang, Te-Kai
  • Chen, Pin-Hua

Abrégé

The invention introduces a non-transitory computer-readable storage medium for adjusting operating frequencies when executed by a processing unit of a device, containing program code to: collect an interface-activity parameter comprising information about data transmissions on a host access interface and/or a flash access interface; select one from multiple frequencies according to the interface-activity parameter; and drive a clock generator to output a clock signal at the selected frequency, thereby enabling the host access interface and/or the flash access interface to operate at an operating frequency.

Classes IPC  ?

  • G06F 1/324 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par réduction de la fréquence d’horloge
  • G06F 1/3234 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise
  • G06F 1/3225 - Surveillance de dispositifs périphériques de mémoires
  • G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
  • G06F 1/3206 - Surveillance d’événements, de dispositifs ou de paramètres initiant un changement de mode d’alimentation
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

89.

Memory controller having a plurality of control modules and associated server

      
Numéro d'application 17167099
Numéro de brevet 11507319
Statut Délivré - en vigueur
Date de dépôt 2021-02-04
Date de la première publication 2022-08-04
Date d'octroi 2022-11-22
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tsung-Chieh

Abrégé

The present invention provides a memory controller configured to access a plurality of channels, wherein each of the channels includes a plurality flash memory chips, and the memory controller includes a flash translation layer and a plurality of control modules. The flash translation layer is configured to generate commands with corresponding physical addresses of at least one of the channels. The plurality of control modules are connected to the plurality of channels, respectively, and each of the control modules operates independently to receive the corresponding command with the corresponding physical address from the flash translation layer, to access the flash memory chips within the corresponding channels.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 12/02 - Adressage ou affectation; Réadressage

90.

Memory controller having a plurality of control modules and associated server

      
Numéro d'application 17168153
Numéro de brevet 11567699
Statut Délivré - en vigueur
Date de dépôt 2021-02-04
Date de la première publication 2022-08-04
Date d'octroi 2023-01-31
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tsung-Chieh

Abrégé

The present invention provides a memory controller configured to access a plurality of channels, wherein each of the channels includes a plurality flash memory chips, and the memory controller includes a flash translation layer and a plurality of control modules. The flash translation layer is configured to generate commands with corresponding physical addresses of at least one of the channels. The plurality of control modules are connected to the plurality of channels, respectively, and each of the control modules operates independently to receive the corresponding command with the corresponding physical address from the flash translation layer, to access the flash memory chips within the corresponding channels.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 12/1081 - Traduction d'adresses pour accès périphérique à la mémoire principale, p.ex. accès direct en mémoire [DMA]
  • G06F 12/02 - Adressage ou affectation; Réadressage

91.

Method and apparatus for accessing to data in response to power-supply event

      
Numéro d'application 17723989
Numéro de brevet 11664056
Statut Délivré - en vigueur
Date de dépôt 2022-04-19
Date de la première publication 2022-08-04
Date d'octroi 2023-05-30
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Lin, Wen-Sheng

Abrégé

th page to a page before a last valid page in the current block when the power-supply event has occurred; and programming the reconstructed first F2H table into a location of the flash module.

Classes IPC  ?

  • G11C 5/14 - Dispositions pour l'alimentation

92.

Method and apparatus for performing access management of memory device with aid of universal asynchronous receiver-transmitter connection

      
Numéro d'application 17399005
Numéro de brevet 11513980
Statut Délivré - en vigueur
Date de dépôt 2021-08-10
Date de la première publication 2022-07-21
Date d'octroi 2022-11-29
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Chen, Chih-Yung

Abrégé

A method for performing access management of a memory device with aid of a Universal Asynchronous Receiver-Transmitter (UART) connection and associated apparatus are provided. The method may include: utilizing a UART of a memory controller within the memory device to receive a set of intermediate commands corresponding to a set of operating commands through the UART connection between the memory device and a host device, wherein before sending the set of intermediate commands to the controller through the UART connection, the host device converts the set of operating commands into the set of intermediate commands; converting the set of intermediate commands into the set of operating commands according to a command mapping table; and accessing a non-volatile (NV) memory within the memory device with the set of operating commands for the host device, and sending a response to the host device through the UART connection.

Classes IPC  ?

  • G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
  • G06F 12/14 - Protection contre l'utilisation non autorisée de mémoire
  • G06F 12/02 - Adressage ou affectation; Réadressage

93.

Data accessing method using dynamic speed adjustment with aid of thermal control unit, and associated apparatus

      
Numéro d'application 17149663
Numéro de brevet 11687432
Statut Délivré - en vigueur
Date de dépôt 2021-01-14
Date de la première publication 2022-07-14
Date d'octroi 2023-06-27
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Lee, Chun-Cheng
  • Lin, Che-Min
  • Yu, Kuan-Chun
  • Hsu, Sheng-I

Abrégé

A data accessing method using dynamic speed adjustment with aid of a thermal control unit, and associated apparatus such as memory device, memory controller, etc. are provided. The data accessing method includes: utilizing a thermal control unit to start monitoring temperature at a predetermined intra-controller location of the memory controller; in response to at least one accessing request from a host device, controlling a transmission interface circuit to perform data transmission between the host device and the memory controller at an original communications speed, for accessing data in the NV memory; in response to the temperature being greater than a first temperature threshold, detecting an increment of the temperature between a first start time point and a first end time point; based on at least one first predetermined rule, determining a first communications speed according to the increment; and switching from the original communications speed to the first communications speed.

Classes IPC  ?

  • G06F 11/30 - Surveillance du fonctionnement
  • G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
  • G06F 11/00 - Détection d'erreurs; Correction d'erreurs; Contrôle de fonctionnement
  • G06F 12/02 - Adressage ou affectation; Réadressage
  • G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts

94.

Fractional frequency divider and flash memory controller

      
Numéro d'application 17707992
Numéro de brevet 11705907
Statut Délivré - en vigueur
Date de dépôt 2022-03-30
Date de la première publication 2022-07-14
Date d'octroi 2023-07-18
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s)
  • Yao, Tien-Hsing
  • Lee, Chun-Cheng
  • Hsu, Sheng-I

Abrégé

The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

Classes IPC  ?

  • H03K 21/02 - Circuits d'entrée
  • H03K 21/08 - Circuits de sortie
  • H03K 21/10 - Circuits de sortie comprenant des circuits logiques
  • G06F 1/3234 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise
  • H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe
  • H03K 21/40 - Surveillance; Détection d'erreurs; Empêchement ou correction d'un fonctionnement incorrect du compteur

95.

Control method for flash memory controller and associated flash memory controller and storage device

      
Numéro d'application 17394401
Numéro de brevet 11593008
Statut Délivré - en vigueur
Date de dépôt 2021-08-05
Date de la première publication 2022-07-07
Date d'octroi 2023-02-28
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Lin, Ching-Hui

Abrégé

The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, and the control method includes the steps of: receiving a settling command from a host device to configure a portion space of the flash memory module as a zoned namespace; receiving a write command from the host device to write data corresponding a first zone into a plurality of blocks of the flash memory module, wherein an access mode chose by the flash memory controller is determined based on a size of each zone and a size of each block.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

96.

Memory controller having a plurality of control modules and associated server for coding and decoding raw data from flash memory chips

      
Numéro d'application 17168119
Numéro de brevet 11372592
Statut Délivré - en vigueur
Date de dépôt 2021-02-04
Date de la première publication 2022-06-28
Date d'octroi 2022-06-28
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Yang, Tsung-Chieh

Abrégé

The present invention provides a memory controller configured to access a plurality of channels, wherein each of the channels includes a plurality flash memory chips, and the memory controller includes a flash translation layer and a plurality of control modules. The flash translation layer is configured to generate commands with corresponding physical addresses of at least one of the channels. The plurality of control modules are connected to the plurality of channels, respectively, and each of the control modules operates independently to receive the corresponding command with the corresponding physical address from the flash translation layer, to access the flash memory chips within the corresponding channels.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle

97.

Data storage device with an exclusive channel for flag checking of read data, and non-volatile memory control method

      
Numéro d'application 17690555
Numéro de brevet 11550740
Statut Délivré - en vigueur
Date de dépôt 2022-03-09
Date de la première publication 2022-06-23
Date d'octroi 2023-01-10
Propriétaire SILICON MOTION, INC. (Taïwan, Province de Chine)
Inventeur(s) Li, An-Pang

Abrégé

A non-volatile memory control technology. In response to a read command, a non-volatile memory interface controller temporarily stores data read from a non-volatile memory to a system memory and, accordingly, asserts a flag in the system memory. Through a write channel provided by the interconnect bus, the host bridge controller confirms that the flag is asserted to correctly read the data from the system memory. A master computing unit reads the system memory through a read channel provided by the interconnect bus, without being delayed by the status checking of the flag. The host bridge controller executes a data detection command or a preset vendor command to issue a write request for programming data in a virtual address, to trigger a handshake between the host bridge controller and the system memory through the write channel. During the handshake, flag checking is achieved.

Classes IPC  ?

  • G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 13/40 - Structure du bus

98.

Data storage device with an exclusive channel for flag checking of read data, and non-volatile memory control method

      
Numéro d'application 17690535
Numéro de brevet 11526454
Statut Délivré - en vigueur
Date de dépôt 2022-03-09
Date de la première publication 2022-06-23
Date d'octroi 2022-12-13
Propriétaire SILICON MOTION, INC. (Taïwan, Province de Chine)
Inventeur(s) Li, An-Pang

Abrégé

A non-volatile memory control technology. In response to a read command, a non-volatile memory interface controller temporarily stores data read from a non-volatile memory to the system memory and, accordingly, asserts a flag in the system memory. Through a flag reading channel provided by a interconnect bus, the host bridge controller confirms that the flag is asserted to correctly read the data from the system memory. A master computing unit reads the system memory through a data reading channel provided by the interconnect bus, without being delayed by the status checking of the flag. The interconnect bus further provides a flag writing channel and a data writing channel.

Classes IPC  ?

  • G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
  • G06F 13/40 - Structure du bus

99.

METHOD AND APPARATUS FOR PERFORMING OPERATIONS TO NAMESPACES OF A FLASH MEMORY DEVICE

      
Numéro d'application 17690800
Statut En instance
Date de dépôt 2022-03-09
Date de la première publication 2022-06-23
Propriétaire Silicon Motion, Inc. (Taïwan, Province de Chine)
Inventeur(s) Lin, Sheng-Liu

Abrégé

The invention introduces a method for performing operations to namespaces of a flash memory device, by a processing unit of a storage device, at least including the steps: receiving a cross-namespace data-movement command from a host, requesting to move user data of a first logical address of a first namespace to a second logical address of a second namespace; cutting first physical address information corresponding to the first logical address of a first logical-physical mapping table corresponding to the first namespace; and storing the first physical address information in an entry corresponding to a second logical address of a second logical-physical mapping table corresponding to the second namespace.

Classes IPC  ?

  • G06F 12/1009 - Traduction d'adresses avec tables de pages, p.ex. structures de table de page
  • G06F 12/109 - Traduction d'adresses pour espaces adresse virtuels multiples, p.ex. segmentation

100.

Multi-screen display control device

      
Numéro d'application 17249945
Numéro de brevet 11630629
Statut Délivré - en vigueur
Date de dépôt 2021-03-19
Date de la première publication 2022-06-16
Date d'octroi 2023-04-18
Propriétaire SILICON MOTION, INC. (Taïwan, Province de Chine)
Inventeur(s)
  • Qi, Chengliang
  • Lyu, Guangjun
  • Li, Cong

Abrégé

A multi-screen display control device is shown, which is linked to a host through a universal serial bus (USB) port to receive image data from the host, and uses a plurality of high-definition multimedia interface (HDMI) ports to output a plurality of HDMI sub-images to a plurality of screens. The multi-screen display control device has a USB hub that couples the USB port to a plurality of graphics processing units (GPUs), so that the GPUs generate the HDMI sub-images based on the image data transferred from the host via USB communication technology.

Classes IPC  ?

  • G06F 3/14 - Sortie numérique vers un dispositif de visualisation
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