Sony Semiconductor Solutions Corporation

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Date
Nouveautés (dernières 4 semaines) 52
2024 avril (MACJ) 29
2024 mars 55
2024 février 86
2024 janvier 97
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Classe IPC
H01L 27/146 - Structures de capteurs d'images 1 448
H04N 5/3745 - Capteurs adressés, p.ex. capteurs MOS ou CMOS ayant des composants supplémentaires incorporés au sein d'un pixel ou connectés à un groupe de pixels au sein d'une matrice de capteurs, p.ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs 366
H04N 5/378 - Circuits de lecture, p.ex. circuits d’échantillonnage double corrélé [CDS], amplificateurs de sortie ou convertisseurs A/N 354
H04N 5/369 - Transformation d'informations lumineuses ou analogues en informations électriques utilisant des capteurs d'images à l'état solide [capteurs SSIS]  circuits associés à cette dernière 342
H04N 5/374 - Capteurs adressés, p.ex. capteurs MOS ou CMOS 243
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Statut
En Instance 1 625
Enregistré / En vigueur 2 450
Résultats pour  brevets
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1.

SEMICONDUCTOR DEVICE

      
Numéro d'application 18263931
Statut En instance
Date de dépôt 2022-01-05
Date de la première publication 2024-04-18
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Murashima, Akihiko

Abrégé

The present disclosure relates to a semiconductor device capable of reducing design load. The present disclosure relates to a semiconductor device capable of reducing design load. Provided is a semiconductor device including: a first substrate; and a second substrate bonded to the first substrate with a bonding portion where a bump is bonded, in which the bump pairs up with a predetermined function to constitute a unit. The present disclosure is applicable to, for example, a photodetection device such as a solid-state imaging device.

Classes IPC  ?

  • H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
  • H01L 23/528 - Configuration de la structure d'interconnexion
  • H01L 27/146 - Structures de capteurs d'images

2.

IMAGING DEVICE

      
Numéro d'application 17768405
Statut En instance
Date de dépôt 2020-07-15
Date de la première publication 2024-04-18
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Oshiyama, Itaru
  • Ogata, Ryo

Abrégé

There is provided an imaging device including: a semiconductor substrate including a photoelectric conversion section provided for each of pixels that are two-dimensionally arranged, in which the photoelectric conversion section performs photoelectric conversion on incident light; and an uneven structure provided on a light-receiving-side principal surface of the semiconductor substrate, in which the uneven structure includes a plurality of pillars arranged at a period shorter than a wavelength of light belonging to a visible light band.

Classes IPC  ?

3.

LIGHT RECEIVING DEVICE, DISTANCE MEASURING DEVICE, AND SIGNAL PROCESSING METHOD IN LIGHT RECEIVING DEVICE

      
Numéro d'application 18264465
Statut En instance
Date de dépôt 2022-01-26
Date de la première publication 2024-04-18
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Sakaguchi, Hiroaki
  • Hasegawa, Koichi

Abrégé

A light receiving device (20) according to one aspect of the present disclosure includes: a light receiving section (22) including a plurality of photon-counting light receiving elements that receives reflected light from a distance measurement target (40) based on irradiation pulsed light from a light source section (10); a selecting section (23) that selects individual detection values of the plurality of light receiving elements at a predetermined time; an addition section (24) that generates 2N−1 binary values (N is a positive integer) from the individual detection values of the plurality of light receiving elements at the predetermined time selected by the selecting section (23) and that calculates an N-bit pixel value by adding up all the 2N−1 binary values; and a computing section (26) that performs computation related to distance measurement using the N-bit pixel value calculated by the addition section (24).

Classes IPC  ?

  • G01S 17/10 - Systèmes déterminant les données relatives à la position d'une cible pour mesurer la distance uniquement utilisant la transmission d'ondes à modulation d'impulsion interrompues
  • G01S 7/4863 - Réseaux des détecteurs, p.ex. portes de transfert de charge
  • G01S 7/4865 - Mesure du temps de retard, p.ex. mesure du temps de vol ou de l'heure d'arrivée ou détermination de la position exacte d'un pic

4.

SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND METHOD OF CONTROLLING SEMICONDUCTOR DEVICE

      
Numéro d'application 18279148
Statut En instance
Date de dépôt 2022-02-16
Date de la première publication 2024-04-18
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Okamoto, Koichi
  • Mogi, Hideaki
  • Masuda, Takashi
  • Saeki, Shinichirou
  • Tabata, Mitsushi

Abrégé

A semiconductor device (10) according to one aspect of the present disclosure includes: a driving section (40) that drives an object to be driven; an abnormality detecting circuit (30), which is one example of an instruction circuit that outputs an instruction signal to the driving section (40); and a light amount detecting section (20) that detects an amount of incident light and invalidates the instruction signal output from the abnormality detecting circuit (30) in accordance with the amount of incident light.

Classes IPC  ?

  • H01L 27/146 - Structures de capteurs d'images
  • H01S 5/068 - Stabilisation des paramètres de sortie du laser

5.

Solid-State Imaging Device and Solid-State Imaging Apparatus

      
Numéro d'application 18394741
Statut En instance
Date de dépôt 2023-12-22
Date de la première publication 2024-04-18
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Fukui, Hironobu

Abrégé

A solid-state imaging device including: a semiconductor substrate having a first surface and a second surface opposed to each other, and including a photoelectric converter provided for each of pixel regions; an impurity diffusion region provided, for each of the pixel regions, in proximity to the first surface of the semiconductor substrate; and a contact electrode embedded in the semiconductor substrate from the first surface, and provided over and in contact with the impurity diffusion regions each provided for each of the pixel regions adjacent to each other.

Classes IPC  ?

6.

WIRING MODULE AND IMAGING APPARATUS

      
Numéro d'application 18540173
Statut En instance
Date de dépôt 2023-12-14
Date de la première publication 2024-04-18
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Yamashita, Yutaro

Abrégé

A wiring module according to an embodiment of the present technology includes: a wiring board and a heat dissipation member. The wiring board includes a body portion and one or more heat dissipation vias, the body portion including a front surface layer to which a device package is connected and a rear surface layer opposite to the front surface layer, the one or more heat dissipation vias penetrating the body portion from the front surface layer to the rear surface layer. The heat dissipation member is connected to the rear surface layer so as to thermally bond with the one or more heat dissipation vias.

Classes IPC  ?

7.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING METHOD, AND RECORDING MEDIUM

      
Numéro d'application 18547161
Statut En instance
Date de dépôt 2022-02-16
Date de la première publication 2024-04-18
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Ishikawa, Hirotaka
  • Yonezawa, Kota

Abrégé

An edge device (20) that is an example of an information processing device of an embodiment according to the present disclosure includes a transmitting section that transmits, to a server device (10) that generates a neural network, information related to a processing capability for processing the neural network supplied from the server device (10), wherein the information related to the processing capability includes at least one of capacity information of the neural network, filter size information of a favorite convolutional neural network, hardware architecture type information, chip information, and device model number information.

Classes IPC  ?

8.

SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS

      
Numéro d'application 17769556
Statut En instance
Date de dépôt 2020-07-21
Date de la première publication 2024-04-18
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Kudou, Tomoaki
  • Otake, Yusuke

Abrégé

Provided is a semiconductor device capable of improving quantum efficiency and time resolution. In the semiconductor device, each of a plurality of pixels includes an APD element formed in a semiconductor layer, and a first metal wiring provided on a first surface of the semiconductor layer. The APD element includes: a multiplication portion which includes a first electrode region of a first conductivity type provided on the first surface side of the semiconductor layer and a second electrode region of a second conductivity type provided at a position shallower than the first electrode region to form a pn junction with the first electrode region, and in which an avalanche multiplication region is formed at an interface of the pn junction; and a first contact region of the second conductivity type which is provided in contact with the second electrode region between the first surface of the semiconductor layer and the second electrode region, and of which the contour is located inside a contour of the second electrode region in a plan view. The first metal wiring is electrically connected to the first contact region, and a contour thereof is located between the contour of the second electrode region and the contour of the first contact region in a plan view.

Classes IPC  ?

  • H01L 27/146 - Structures de capteurs d'images
  • H04N 25/773 - Circuits de pixels, p.ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des convertisseurs A/N, V/T, V/F, I/T ou I/F comprenant des circuits de comptage de photons, p. ex. des diodes de détection de photons uniques [SPD] ou des diodes à avalanche de photons uniques [SPAD]

9.

DISPLAY DEVICE

      
Numéro d'application 18251546
Statut En instance
Date de dépôt 2021-10-29
Date de la première publication 2024-04-11
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Yagi, Keiichi
  • Miura, Kiwamu
  • Hamachi, Chugen

Abrégé

A display device includes a first substrate (41), a second substrate (42), a plurality of light emitting elements (10) provided in a display region, and a sealing part (50) that is provided in a peripheral region surrounding the display region and seals between the first substrate (41) and the second substrate (42), wherein the sealing part (50) includes main sealing parts (51) and a sub sealing part (52) positioned between the main sealing parts, an alignment mark (55) is provided between the sub sealing part (52) and the first substrate (41), each of the main sealing part (51) has a stacked structure of a light shielding member layer (56, 57) and a sealing member layer (53) from the first substrate side, and the sub sealing part (52) has a stacked structure (53) of a base material layer (54) formed of a non-light shielding member and the sealing member layer from the first substrate side.

Classes IPC  ?

  • H10K 59/38 - Dispositifs spécialement adaptés à l'émission de lumière multicolore comprenant des filtres de couleur ou des supports changeant de couleur [CCM]
  • H10K 59/126 - Blindage, p. ex. moyens de blocage de la lumière sur les TFT
  • H10K 59/127 - Affichages à OLED à matrice active [AMOLED] comprenant deux substrats, p. ex. un affichage comprenant une matrice OLED et un circuit de commande de TFT sur des substrats différents
  • H10K 59/80 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comprenant au moins un élément organique émetteur de lumière couvert par le groupe - Détails de structure

10.

DISPLAY DEVICE AND ELECTRONIC DEVICE

      
Numéro d'application 18260370
Statut En instance
Date de dépôt 2022-02-10
Date de la première publication 2024-04-11
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Sudo, Shoji
  • Sawabe, Tomoaki

Abrégé

Display devices that suppress complications due to uneven shape of a surface on which a semi-transmissive reflective layer is formed are disclosed. In one example, a display device includes first sub-pixels, second sub-pixels, and third sub-pixels. The first sub-pixel includes a first light emitting element that emits first light and third light, the second sub-pixel includes a second light emitting element that emits second light, and the third sub-pixel includes a third light emitting element that emits first light and third light. The light emitting elements respectively include a first electrode, an organic layer including a light emitting layer, a second electrode, and a semi-transmissive reflective layer, and a resonator structure is configured by the first electrode and the semi-transmissive reflective layer. The heights of the semi-transmissive reflective layers in the first light emitting element and the third light emitting element are the same.

Classes IPC  ?

  • H10K 59/80 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comprenant au moins un élément organique émetteur de lumière couvert par le groupe - Détails de structure
  • H10K 59/38 - Dispositifs spécialement adaptés à l'émission de lumière multicolore comprenant des filtres de couleur ou des supports changeant de couleur [CCM]

11.

SOLID-STATE IMAGING DEVICE AND IMAGING APPARATUS

      
Numéro d'application 18263729
Statut En instance
Date de dépôt 2022-01-28
Date de la première publication 2024-04-11
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Hanzawa, Katsuhiko
  • Miyake, Shinichi
  • Tomida, Kazuyuki

Abrégé

A solid-state imaging device (200) includes a photoelectric conversion device (211), a current-voltage conversion circuit (310), and an output circuit. The photoelectric conversion device (211) performs photoelectric conversion of incident light. The current-voltage conversion circuit (310) includes a first transistor (311) that converts an amount of electric charge generated by photoelectric conversion into a voltage signal. The output circuit includes a second transistor having an S value smaller than an S value of the first transistor (311) and generates an output signal based on the voltage signal.

Classes IPC  ?

  • H01L 27/146 - Structures de capteurs d'images
  • H04N 25/779 - Circuits de balayage ou d'adressage de la matrice de pixels

12.

IMAGING APPARATUS AND IMAGING METHOD

      
Numéro d'application 18263774
Statut En instance
Date de dépôt 2022-01-25
Date de la première publication 2024-04-11
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s) Mahara, Kumiko

Abrégé

An imaging apparatus according to an embodiment includes a pixel array unit (101) including a plurality of pixels arranged in a matrix array, each of the pixels generating a pixel signal corresponding to light received by exposure, the pixel array unit acquiring image data based on each of the pixel signals respectively generated by the plurality of pixels, a compression unit (1020) configured to compress a data amount of the image data to generate compressed image data, a signature generation unit (1021) configured to generate signature data based on the compressed image data; and an output unit (104,131,132) configured to output the image data and authenticity proof data obtained by adding the signature data to the compressed image data.

Classes IPC  ?

  • H04N 19/467 - Inclusion d’information supplémentaire dans le signal vidéo pendant le processus de compression caractérisée par le caractère invisible de l’information incluse, p.ex. un filigrane
  • G06F 21/64 - Protection de l’intégrité des données, p.ex. par sommes de contrôle, certificats ou signatures
  • H04N 25/11 - Agencement de matrices de filtres colorés [CFA]; Mosaïques de filtres
  • H04N 25/79 - Agencements de circuits répartis entre des substrats, des puces ou des cartes de circuits différents ou multiples, p. ex. des capteurs d'images empilés

13.

SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS

      
Numéro d'application 18544833
Statut En instance
Date de dépôt 2023-12-19
Date de la première publication 2024-04-11
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Yamashita, Hirofumi
  • Shimada, Shohei
  • Otake, Yusuke
  • Tanaka, Yusuke
  • Wakano, Toshifumi

Abrégé

To provide a solid-state imaging device and an electronic apparatus capable of achieving both of a high dynamic range operation and an auto focus operation in a pixel configuration in which a plurality of unit pixels includes two or more subpixels. There is provided a solid-state imaging device including: a first pixel separation region that separates a plurality of unit pixels including two or more subpixels; a second pixel separation region that separates each of the plurality of unit pixels separated by the first pixel separation region; and an overflow region that causes signal charges accumulated in the subpixels to overflow to at least one of adjacent subpixels, in which the overflow region is formed between a first subpixel and a second subpixel.

Classes IPC  ?

  • H04N 25/704 - Pixels spécialement adaptés à la mise au point, p. ex. des ensembles de pixels à différence de phase
  • H01L 27/146 - Structures de capteurs d'images
  • H04N 25/711 - Registres à report et intégration [TDI]; Registres à décalage TDI
  • H04N 25/772 - Circuits de pixels, p.ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des convertisseurs A/N, V/T, V/F, I/T ou I/F

14.

PHOTODETECTION DEVICE AND ELECTRONIC APPARATUS

      
Numéro d'application 18546252
Statut En instance
Date de dépôt 2022-02-21
Date de la première publication 2024-04-11
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Moriya, Yusuke
  • Yamamoto, Atsushi
  • Yukawa, Tomiyuki
  • Nishimura, Kotaro
  • Ikehara, Shigehiro
  • Otani, Shogo
  • Kato, Hiroshi

Abrégé

The present disclosure relates to a photodetection device and an electronic apparatus that allow for reducing surface reflection from an on-chip microlens and suppressing deterioration of image quality. Provided is a photodetection device including: a plurality of pixels that have photoelectric conversion units; on-chip microlenses that are formed in such a way as to correspond to the individual pixels; and an antireflection film that is formed on a surface of the on-chip microlens, in which the antireflection film is constituted by a stacking of: a first inorganic film that is formed by a metal oxide film; and a second inorganic film that is formed on a surface of the first inorganic film and has a lower refractive index than the first inorganic film. The present disclosure can be applied to, for example, a CMOS solid-state imaging device.

Classes IPC  ?

15.

LIQUID CRYSTAL DISPLAY ELEMENT, DISPLAY DEVICE, ELECTRONIC DEVICE, DRIVE SUBSTRATE, AND METHOD FOR MANUFACTURING DRIVE SUBSTRATE

      
Numéro d'application 18251581
Statut En instance
Date de dépôt 2021-11-02
Date de la première publication 2024-04-11
Propriétaire
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
  • SONY GROUP CORPORATION (Japon)
Inventeur(s)
  • Sakairi, Takashi
  • Honda, Tomoaki

Abrégé

Provided is a liquid crystal display element capable of reducing the decrease in light utilization efficiency caused by the increase in definition. Provided is a liquid crystal display element capable of reducing the decrease in light utilization efficiency caused by the increase in definition. A liquid crystal display element includes: a drive substrate having pixel electrodes having light-reflective properties and arranged in a matrix; a counter substrate arranged opposite to the drive substrate; and a liquid crystal material layer sandwiched between the drive substrate and the counter substrate, in which the pixel electrodes are arranged on a display surface side of the drive substrate in a state of being separated from each other with a slit portion interposed therebetween, an entire surface including surfaces on the pixel electrodes is covered with a first dielectric film formed on the pixel electrodes and a second dielectric film formed in the slit portion, and the second dielectric film has a hollow portion extending along the slit portion.

Classes IPC  ?

  • G02F 1/1335 - Association structurelle de cellules avec des dispositifs optiques, p.ex. des polariseurs ou des réflecteurs

16.

LIGHT EMITTING DEVICE AND DISPLAY DEVICE

      
Numéro d'application 18264374
Statut En instance
Date de dépôt 2022-02-16
Date de la première publication 2024-04-11
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Nishinaka, Ippei
  • Naito, Hiroki
  • Tomoda, Katsuhiro

Abrégé

For example, deterioration in image quality due to end-surface vignetting is suppressed. A light emitting device includes at least two light emitting elements provided on a substrate, and a transparent resin part provided so as to cover the light emitting elements, in which in a sectional view, when the size of the width of the light emitting element positioned at an end part is a (μm), a surface distance between the light emitting element and a surface of the transparent resin part is x (μm), an end surface distance between the light emitting element and an end surface of the transparent resin part closest to the light emitting element is y (μm), and the refractive index of the transparent resin part is λm, an expression (1) below or expressions (2) and (3) below are satisfied. For example, deterioration in image quality due to end-surface vignetting is suppressed. A light emitting device includes at least two light emitting elements provided on a substrate, and a transparent resin part provided so as to cover the light emitting elements, in which in a sectional view, when the size of the width of the light emitting element positioned at an end part is a (μm), a surface distance between the light emitting element and a surface of the transparent resin part is x (μm), an end surface distance between the light emitting element and an end surface of the transparent resin part closest to the light emitting element is y (μm), and the refractive index of the transparent resin part is λm, an expression (1) below or expressions (2) and (3) below are satisfied. y<(1.44λm−0.76)×x+(0.08λm−0.04)×a−0.02λm−0.47  (Expression 1) For example, deterioration in image quality due to end-surface vignetting is suppressed. A light emitting device includes at least two light emitting elements provided on a substrate, and a transparent resin part provided so as to cover the light emitting elements, in which in a sectional view, when the size of the width of the light emitting element positioned at an end part is a (μm), a surface distance between the light emitting element and a surface of the transparent resin part is x (μm), an end surface distance between the light emitting element and an end surface of the transparent resin part closest to the light emitting element is y (μm), and the refractive index of the transparent resin part is λm, an expression (1) below or expressions (2) and (3) below are satisfied. y<(1.44λm−0.76)×x+(0.08λm−0.04)×a−0.02λm−0.47  (Expression 1) y<(1.44λm−0.76)×x+(0.08λm−0.04)×a−0.02λm−0.47  (Expression 2) For example, deterioration in image quality due to end-surface vignetting is suppressed. A light emitting device includes at least two light emitting elements provided on a substrate, and a transparent resin part provided so as to cover the light emitting elements, in which in a sectional view, when the size of the width of the light emitting element positioned at an end part is a (μm), a surface distance between the light emitting element and a surface of the transparent resin part is x (μm), an end surface distance between the light emitting element and an end surface of the transparent resin part closest to the light emitting element is y (μm), and the refractive index of the transparent resin part is λm, an expression (1) below or expressions (2) and (3) below are satisfied. y<(1.44λm−0.76)×x+(0.08λm−0.04)×a−0.02λm−0.47  (Expression 1) y<(1.44λm−0.76)×x+(0.08λm−0.04)×a−0.02λm−0.47  (Expression 2) y<(1.44λm−0.76)×x+(0.15λm−0.08)×a−0.06λm−0.61  (Expression 3)

Classes IPC  ?

  • H01L 33/56 - Matériaux, p.ex. résine époxy ou silicone
  • H01L 27/15 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants semi-conducteurs avec au moins une barrière de potentiel ou une barrière de surface, spécialement adaptés pour l'émission de lumière
  • H01L 33/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails

17.

IMAGING APPARATUS, ELECTRONIC DEVICE, AND SIGNAL PROCESSING METHOD

      
Numéro d'application 18554043
Statut En instance
Date de dépôt 2022-02-22
Date de la première publication 2024-04-11
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Saito, Daisuke

Abrégé

To provide an imaging apparatus which enables sophisticated calculations to be realized at lower power. An imaging apparatus according to an embodiment of the present disclosure includes: a first substrate group in which is arranged a light source cell array portion configured to generate a light signal; and a second substrate group in which is arranged a pixel array portion configured to photoelectrically convert the light signal and output a pixel signal representing a result of a sum-of-product computation. The first substrate group and the second substrate group are stacked so that at least a part of the light source cell array portion overlaps with the pixel array portion.

Classes IPC  ?

  • H04N 25/77 - Circuits de pixels, p.ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs
  • H04N 25/10 - Circuits de capteurs d'images à l'état solide [capteurs SSIS]; Leur commande pour transformer les différentes longueurs d'onde en signaux d'image

18.

IMAGE CAPTURING APPARATUS AND ELECTRONIC DEVICE

      
Numéro d'application 18554342
Statut En instance
Date de dépôt 2022-03-29
Date de la première publication 2024-04-11
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Naganokawa, Haruhisa
  • Umeda, Kengo

Abrégé

Image capturing that suppresses a drop in numerical aperture and achieves a smaller size is disclosed. In one example, an image capturing apparatus includes pixels each having a photoelectric conversion unit, a floating diffusion that outputs a voltage according to a charge obtained from photoelectric conversion by the photoelectric conversion unit, and a current amplification unit that amplifies a current according to the voltage of the floating diffusion. The region in which the photoelectric conversion units are disposed and the region in which the current amplification units are disposed transmit and receive the voltages of the floating diffusions through a corresponding signal transmission unit.

Classes IPC  ?

  • H04N 25/75 - Circuits pour fournir, modifier ou traiter des signaux d'image provenant de la matrice de pixels
  • H04N 25/772 - Circuits de pixels, p.ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des convertisseurs A/N, V/T, V/F, I/T ou I/F
  • H04N 25/778 - Circuits de pixels, p.ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des amplificateurs partagés entre une pluralité de pixels, c. à d. qu'au moins une partie de l'amplificateur doit se trouver sur la matrice de capteurs elle-même

19.

IMAGING DEVICE AND ELECTRONIC APPARATUS

      
Numéro d'application 18554893
Statut En instance
Date de dépôt 2022-03-29
Date de la première publication 2024-04-11
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s) Kurihara, Shinichiro

Abrégé

[Problem] To provide an imaging device capable of suppressing color mixing and an electronic apparatus using the imaging device. [Problem] To provide an imaging device capable of suppressing color mixing and an electronic apparatus using the imaging device. [Solution] An imaging device of the present disclosure includes a photoelectric conversion layer disposed on a semiconductor substrate, a transparent electrode layer disposed on the photoelectric conversion layer, a first light-shielding portion that separates the photoelectric conversion layer into a plurality of pixels arranged in a first direction and a second direction that intersects the first direction, and is disposed along a boundary between the separated pixels, and a second light-shielding portion disposed along the boundary between the separated pixels inside the transparent electrode layer and disposed so that a portion of the boundary between adjacent pixels is interrupted.

Classes IPC  ?

20.

LIGHT RECEIVING DEVICE, ELECTRONIC APPARATUS, AND LIGHT RECEIVING METHOD

      
Numéro d'application 17767694
Statut En instance
Date de dépôt 2020-10-05
Date de la première publication 2024-04-11
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Suzuki, Nobuharu

Abrégé

An increase in a load current in a processing circuit is reduced. A light receiving device includes an imaging unit that photoelectrically converts light received in a plurality of pixels to acquire an analog image signal, a conversion unit that converts the analog image signal acquired by the imaging unit into digital image data, and a data processing unit that executes data processing on the digital image data and reduces a load of the data processing in a period in which the conversion unit executes conversion as compared to a period in which the conversion unit does not execute conversion.

Classes IPC  ?

  • H04N 25/78 - Circuits de lecture pour capteurs adressés, p. ex. amplificateurs de sortie ou convertisseurs A/N

21.

NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

      
Numéro d'application 18261655
Statut En instance
Date de dépôt 2021-12-07
Date de la première publication 2024-04-04
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Sumino, Jun
  • Aratani, Katsuhisa
  • Sone, Takeyuki
  • Mizuguchi, Tetsuya

Abrégé

Provided is a nonvolatile memory device that makes it possible to achieve high performance. The nonvolatile memory device includes a first electrode, a memory material layer, a second electrode, and a first buffer layer. The memory material layer includes a first element and is provided on the first electrode. The second electrode is provided on the memory material layer. The first buffer layer is provided between the memory material layer and the second electrode. In the first buffer layer, a segregation of the first element is smaller than a segregation of the first element in the second electrode.

Classes IPC  ?

  • H10B 63/00 - Dispositifs de mémoire par changement de résistance, p.ex. dispositifs RAM résistifs [ReRAM]
  • H10N 70/00 - Dispositifs à l’état solide sans barrière de potentiel ni de surface, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation

22.

WIRELESS SYSTEM

      
Numéro d'application 18264638
Statut En instance
Date de dépôt 2022-01-13
Date de la première publication 2024-04-04
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Uno, Masahiro

Abrégé

A wireless system according to an embodiment of the present disclosure includes: one or a plurality of distributed units each including an antenna, a wireless circuit, and a camera, the wireless circuit transmitting and receiving a wireless signal via the antenna, the camera outputting an image signal; and a central unit that is line-coupled to each of the distributed units. The each of the distributed units transmits the wireless signal from the wireless circuit and image information based on the image signal outputted from the camera to the central unit using one line. The central unit includes a radio resource control circuit, a baseband circuit that performs signal processing on the wireless signal from the each of the distributed units on a basis of control performed by the radio resource control circuit, and a processing circuit that performs a process based on the image information from the each of the distributed units.

Classes IPC  ?

  • H04B 10/2575 - Radio sur fibre, p.ex. signal radio modulé en fréquence sur une porteuse optique
  • G06V 20/50 - Contexte ou environnement de l’image
  • G06V 40/20 - Mouvements ou comportement, p.ex. reconnaissance des gestes
  • H04W 16/28 - Structures des cellules utilisant l'orientation du faisceau
  • H04W 28/06 - Optimisation, p.ex. compression de l'en-tête, calibrage des informations

23.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

      
Numéro d'application 18264725
Statut En instance
Date de dépôt 2022-01-13
Date de la première publication 2024-04-04
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Makino, Hirofumi

Abrégé

A semiconductor device according to the present technology includes a semiconductor chip, and a wiring board portion having the semiconductor chip mounted thereon and having an external connection terminal for establishing electrical connection to the outside, the external connection terminal being formed on its back surface which is a surface opposite to its front surface which is a surface on which the semiconductor chip is mounted, in which the semiconductor chip is connected to a terminal formed on the front surface of the wiring board portion through a bonding wire to be wire-bonded to the wiring board portion, and a heat dissipation member is disposed between the bonding wire and the wiring board portion.

Classes IPC  ?

  • H01L 23/427 - Refroidissement par changement d'état, p.ex. caloducs
  • H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
  • H01L 23/053 - Conteneurs; Scellements caractérisés par la forme le conteneur étant une structure creuse ayant une base isolante qui sert de support pour le corps semi-conducteur
  • H01L 23/29 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par le matériau
  • H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
  • H01L 27/146 - Structures de capteurs d'images

24.

PHOTODETECTION DEVICE AND PHOTODETECTION SYSTEM

      
Numéro d'application 18249387
Statut En instance
Date de dépôt 2021-09-02
Date de la première publication 2024-04-04
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Ikeda, Yasuji

Abrégé

A photodetection device according to the present disclosure includes a plurality of light-receiving sections that each generates a pulse signal including a pulse corresponding to a result of light reception, a plurality of edge detectors that each generates a detection signal by detecting an edge of the pulse in the pulse signal generated by a corresponding light-receiving section, and an adder that generates a detection value indicating number of the pulses on the basis of a plurality of the detection signals. The edge detectors each include a first latch circuit that generates a first signal by latching the pulse signal on the basis of a first clock signal, a second latch circuit that generates a second signal by latching the first signal on the basis of a second clock signal that is an inverted signal of the first clock signal, a combination circuit that generates a third signal on the basis of the pulse signal, the first signal, and the second signal, and a third latch circuit that generates the detection signal by latching the third signal on the basis of the first clock signal.

Classes IPC  ?

  • G01S 7/4863 - Réseaux des détecteurs, p.ex. portes de transfert de charge
  • G01S 7/481 - Caractéristiques de structure, p.ex. agencements d'éléments optiques
  • G01S 7/487 - Extraction des signaux d'écho désirés

25.

PIXEL CIRCUIT, DISPLAY DEVICE, AND DRIVING METHOD

      
Numéro d'application 18255585
Statut En instance
Date de dépôt 2021-11-26
Date de la première publication 2024-04-04
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Toyomura, Naobumi

Abrégé

Provided are a pixel circuit, a display device, and a driving method that suppress a decrease in luminance. A pixel circuit according to the present disclosure includes a first transistor configured to control a current supplied to a light emitting element according to a voltage supplied to a first terminal, a first capacitor configured to hold the voltage supplied to the first terminal, a second transistor configured to sample a signal voltage of a video signal line, a second capacitor configured to hold the signal voltage sampled by the second transistor, and a third transistor configured to connect the second capacitor and the first capacitor and set a voltage corresponding to the signal voltage to the first capacitor by transferring electric charges accumulated in the second capacitor to the first capacitor.

Classes IPC  ?

  • G09G 3/3233 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p.ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p.ex. utilisant des diodes électroluminescentes [LED] organiques, p.ex. utilisant des diodes électroluminescentes organiques [OLED] utilisant une matrice active avec un circuit de pixel pour commander le courant à travers l'élément électroluminescent

26.

SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE

      
Numéro d'application 18264707
Statut En instance
Date de dépôt 2022-02-03
Date de la première publication 2024-04-04
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Tojinbara, Hiroki

Abrégé

A solid-state imaging device as disclosed includes a semiconductor layer having a light incidence surface and an element formation surface. The semiconductor layer includes a plurality of photoelectric conversion units including a first photoelectric conversion portion, a second photoelectric conversion portion, an isolation portion, a charge accumulation region, a first transfer transistor capable of transferring a signal charge from the first photoelectric conversion portion to the charge accumulation region, and a second transfer transistor capable of transferring a signal charge from the second photoelectric conversion portion to the charge accumulation region. The isolation portion includes a first region formed by an insulating material extending in a thickness direction of the semiconductor layer from the element formation surface side, and a second region provided on the light incidence surface side of the first region and formed by a semiconductor region into which impurities exhibiting a first conductivity type are implanted.

Classes IPC  ?

27.

ELECTRONIC DEVICE

      
Numéro d'application 18264719
Statut En instance
Date de dépôt 2022-01-28
Date de la première publication 2024-04-04
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Imahigashi, Takashi

Abrégé

An electronic device according to the present disclosure includes a semiconductor substrate, a chip, a bump, and a sidewall portion. The bump connects a plurality of connection pads provided on the opposing main surfaces of the semiconductor substrate and the chip. The sidewall portion includes a porous metal layer and that annularly surrounds a region where a plurality of bumps is provided, and connects the semiconductor substrate and the chip. The chip has a thermal expansion coefficient different from that of the semiconductor substrate by 0.1 ppm/° C. or more. The chip is a semiconductor laser, and the semiconductor substrate includes a drive circuit that drives the semiconductor laser.

Classes IPC  ?

  • H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
  • H01S 5/0234 - Montage à orientation inversée, p.ex. puce retournée [flip-chip], montage à côté épitaxial au-dessous ou montage à jonction au-dessous
  • H01S 5/026 - Composants intégrés monolithiques, p.ex. guides d'ondes, photodétecteurs de surveillance ou dispositifs d'attaque

28.

IMAGING ELEMENT AND IMAGING DEVICE

      
Numéro d'application 18264724
Statut En instance
Date de dépôt 2022-01-27
Date de la première publication 2024-04-04
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s) Okazaki, Tetsushi

Abrégé

Imaging elements and devices that maintain the linearity of image signals with respect to the amount of incident light are disclosed. In one example, an imaging element includes a pixel, a photoelectric conversion unit connecting unit, a charge holding unit, charge transfer units, an image signal generating unit. The pixel includes photoelectric conversion units formed on a semiconductor substrate, the semiconductor substrate including a wiring region disposed on a front surface side, the photoelectric conversion units performing photoelectric conversion of incident light from an object to generate charges. The photoelectric conversion unit connecting unit connects the photoelectric conversion units to each other. The charge transfer units transfer the charges generated by the photoelectric conversion units to the charge holding unit. The image signal generating unit generates an image signal based on the held charges.

Classes IPC  ?

29.

OPTICAL MODULE AND DISTANCE MEASURING DEVICE

      
Numéro d'application 18276347
Statut En instance
Date de dépôt 2021-12-23
Date de la première publication 2024-04-04
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Kobayashi, Takashi
  • Oiwa, Tatsuya
  • Xu, Jialun
  • Kimura, Motoi

Abrégé

To improve resolution while suppressing the number of light emitting elements arranged in an optical module. To improve resolution while suppressing the number of light emitting elements arranged in an optical module. The optical module is provided with an optical element that converts a light beam emitted from the light emitting element into a substantially parallel light beam or a light beam having a predetermined angular width, and a diffraction element that diffracts the light beam to separate into a plurality of light beams. The diffraction element generates diffracted lights in n direction, and an angle θx formed between one diffraction direction and a side in a direction in which the light emitting element is arranged satisfies tan−1 (b/3a). A diffraction angle φx of the diffracted light satisfies m·sgrt((3φa){circumflex over ( )}2+φb{circumflex over ( )}2)/(2(2n+1)). Note that, φa and φb are angular differences of two light beams caused by inter-light emission distances a and b. Furthermore, n is a natural number, and m is a natural number excluding an integral multiple of 2n+1.

Classes IPC  ?

  • G01S 7/481 - Caractéristiques de structure, p.ex. agencements d'éléments optiques

30.

SOLID-STATE IMAGING ELEMENT AND ELECTRONIC APPARATUS

      
Numéro d'application 18256289
Statut En instance
Date de dépôt 2021-12-07
Date de la première publication 2024-03-28
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Kugimiya, Katsuhisa

Abrégé

A solid-state imaging element (1) according to the present disclosure includes a pixel array unit (10) in which a plurality of light receiving pixels (11) is two-dimensionally arranged. Each of the light receiving pixels (11) includes an organic photoelectric conversion unit (61) and another photoelectric conversion unit. The organic photoelectric conversion unit (61) includes a photoelectric conversion layer (63) made of an organic semiconductor material, a first electrode (62) located on a light incident side of the photoelectric conversion layer (63), and a second electrode (65) located on a side opposite to the light incident side of the photoelectric conversion layer (63). The other photoelectric conversion unit is located on a side opposite to the light incident side of the organic photoelectric conversion unit (61), and performs photoelectric conversion in a wavelength region different from a wavelength region of the organic photoelectric conversion unit (61). The second electrode (65) is connected to a connection wiring (51) including a metal wiring (54) made of metal and a transparent wiring (53) made of a transparent conductive film. The metal wiring (54) extends in a horizontal direction from a peripheral portion of the light receiving pixel (11) to a peripheral portion of the pixel array unit (10).

Classes IPC  ?

  • H10K 39/32 - Capteurs d'images organiques
  • H10K 39/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comprenant au moins un composant organique sensible aux rayonnements couvert par le groupe
  • H10K 39/38 - Interconnexions, p. ex. bornes

31.

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND SENSING SYSTEM

      
Numéro d'application 18264862
Statut En instance
Date de dépôt 2021-12-23
Date de la première publication 2024-03-28
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Takahashi, Kousuke
  • Kitano, Kazutoshi
  • Kawamura, Yuusuke
  • Kubota, Takeshi

Abrégé

An information processing apparatus according to an embodiment includes: a recognition unit (122) configured to perform recognition processing on the basis of a point cloud output from a photodetection ranging unit (11) using a frequency modulated continuous wave to determine a designated area in a real object, the photodetection ranging unit being configured to output the point cloud including velocity information and three-dimensional coordinates of the point cloud on the basis of a reception signal reflected by an object and received, and configured to output three-dimensional recognition information including information indicating the determined designated area, and a correction unit (125) configured to correct three-dimensional coordinates of the designated area in the point cloud on the basis of the three-dimensional recognition information output by the recognition unit.

Classes IPC  ?

  • G01S 7/48 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe
  • G01S 17/42 - Mesure simultanée de la distance et d'autres coordonnées
  • G01S 17/58 - Systèmes de détermination de la vitesse ou de la trajectoire; Systèmes de détermination du sens d'un mouvement
  • G06F 3/01 - Dispositions d'entrée ou dispositions d'entrée et de sortie combinées pour l'interaction entre l'utilisateur et le calculateur

32.

THREE-DIMENSIONAL IMAGE CAPTURING ACCORDING TO TIME-OF-FLIGHT MEASUREMENT AND LIGHT SPOT PATTERN MEASUREMENT

      
Numéro d'application 18273546
Statut En instance
Date de dépôt 2022-01-26
Date de la première publication 2024-03-28
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Cacho, Pepe Gil
  • Louveaux, Sebastien

Abrégé

An electronic device comprising circuitry configured to disambiguate a first phase delay obtained according to an indirect Time-of-Flight principle to obtain a second phase delay, wherein the circuitry is configured to disambiguate the first phase delay based on a captured spot position.

Classes IPC  ?

  • G01S 17/36 - Systèmes déterminant les données relatives à la position d'une cible pour mesurer la distance uniquement utilisant la transmission d'ondes continues, soit modulées en amplitude, en fréquence ou en phase, soit non modulées avec comparaison en phase entre le signal reçu et le signal transmis au même moment
  • G01S 17/46 - Détermination indirecte des données relatives à la position
  • G01S 17/894 - Imagerie 3D avec mesure simultanée du temps de vol sur une matrice 2D de pixels récepteurs, p.ex. caméras à temps de vol ou lidar flash

33.

PIXEL CIRCUIT AND SOLID-STATE IMAGING DEVICE

      
Numéro d'application 18275221
Statut En instance
Date de dépôt 2022-02-17
Date de la première publication 2024-03-28
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Zeituni, Golan
  • Eshel, Noam Zeev

Abrégé

A pixel circuit (100) includes a photoelectric conversion circuit (110), an integration capacitor (Cint) and a supplementary circuit (120). The photoelectric conversion circuit (110) generates and outputs a photocurrent (Iphoto). The integration capacitor (Cint) includes a storage electrode (CintS) and a reference electrode (CintR), wherein the reference electrode (CintR) is connected to a first supply potential (VSUP1), and wherein the integration capacitor (Cint) is configured to integrate the photocurrent on the storage electrode (CintS) in an integration period (Tint). The supplementary circuit (120) pre-charges a working node (WN) between the photoelectric conversion circuit (110) and the storage electrode (CintS) to a pre-charge potential (Vpre) that differs from the first supply potential (VSUP1).

Classes IPC  ?

  • H04N 25/78 - Circuits de lecture pour capteurs adressés, p. ex. amplificateurs de sortie ou convertisseurs A/N
  • H01L 27/146 - Structures de capteurs d'images
  • H04N 25/709 - Circuits de commande de l'alimentation électrique
  • H04N 25/771 - Circuits de pixels, p.ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des moyens de stockage autres que la diffusion flottante

34.

COLUMN SIGNAL PROCESSING UNIT AND SOLID-STATE IMAGING DEVICE

      
Numéro d'application 18276647
Statut En instance
Date de dépôt 2022-02-17
Date de la première publication 2024-03-28
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Zeituni, Golan
  • Eshel, Noam Zeev

Abrégé

A column signal processing unit includes a current control circuit (110) and a feedback circuit (120). The current control circuit (110) is electrically connected between a data signal line (VSL) and a supply reference potential (GND). The feedback circuit (120) is configured to reduce a capacitive load of the data signal line (VSL). A feedback path (121) of the feedback circuit (120) includes a series connection of a feedback capacitor (122) and a delay element (123), wherein the delay element (123) is configured to increase a time delay in the feedback path (121).

Classes IPC  ?

  • H04N 25/78 - Circuits de lecture pour capteurs adressés, p. ex. amplificateurs de sortie ou convertisseurs A/N

35.

IMAGING ELEMENT AND ELECTRONIC APPARATUS

      
Numéro d'application 18529579
Statut En instance
Date de dépôt 2023-12-05
Date de la première publication 2024-03-28
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Nomura, Hirotoshi

Abrégé

The present disclosure relates to an imaging element and an electronic apparatus configured to achieve higher-resolution image taking. The imaging element includes: a photoelectric conversion portion provided in a semiconductor substrate for each pixel that performs photoelectric conversion on light that enters through a filter layer; an element isolation portion configured to separate the photoelectric conversion portions of adjacent pixels; and an inter-pixel light shielding portion disposed between the pixels in a layer and provided between the semiconductor substrate and the filter layer and separated from a light receiving surface of the semiconductor substrate by a predetermined interval. Moreover, an interval between the light receiving surface of the semiconductor substrate and a tip end surface of the inter-pixel light shielding portion is smaller than a width of the tip end surface of the inter-pixel light shielding portion. The present technology is applicable to back-illuminated CMOS image sensors, for example.

Classes IPC  ?

36.

SOLID-STATE IMAGING DEVICE, METHOD FOR DRIVING THE SAME, AND ELECTRONIC DEVICE

      
Numéro d'application 18531208
Statut En instance
Date de dépôt 2023-12-06
Date de la première publication 2024-03-28
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Hatano, Keisuke
  • Koga, Fumihiko
  • Yamaguchi, Tetsuji
  • Izawa, Shinichiro

Abrégé

The present disclosure relates to a solid-state imaging device, a method for driving the solid-state imaging device, and an electronic device capable of improving auto-focusing accuracy by using a phase difference signal obtained by using a photoelectric conversion film. The solid-state imaging device includes a pixel including a photoelectric conversion portion having a structure where a photoelectric conversion film is interposed by an upper electrode on the photoelectric conversion film and a lower electrode under the photoelectric conversion film. The upper electrode is divided into a first upper electrode and a second upper electrode. The present disclosure can be applied to, for example, a solid-state imaging device or the like.

Classes IPC  ?

  • H04N 23/663 - Commande à distance de caméras ou de parties de caméra, p. ex. par des dispositifs de commande à distance pour commander des éléments de caméra interchangeables sur la base de signaux de capteurs d'images électroniques
  • G02B 7/34 - Systèmes pour la génération automatique de signaux de mise au point utilisant des zones différentes dans un plan pupillaire
  • H01L 27/146 - Structures de capteurs d'images
  • H04N 23/67 - Commande de la mise au point basée sur les signaux électroniques du capteur d'image
  • H04N 25/13 - Agencement de matrices de filtres colorés [CFA]; Mosaïques de filtres caractérisées par les caractéristiques spectrales des éléments filtrants
  • H04N 25/704 - Pixels spécialement adaptés à la mise au point, p. ex. des ensembles de pixels à différence de phase
  • H04N 25/778 - Circuits de pixels, p.ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des amplificateurs partagés entre une pluralité de pixels, c. à d. qu'au moins une partie de l'amplificateur doit se trouver sur la matrice de capteurs elle-même
  • H10K 39/32 - Capteurs d'images organiques

37.

LIGHT-RECEIVING DEVICE, IMAGING DEVICE, AND DISTANCE MEASUREMENT DEVICE

      
Numéro d'application 18531446
Statut En instance
Date de dépôt 2023-12-06
Date de la première publication 2024-03-28
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Ito, Kyosuke
  • Otake, Yusuke

Abrégé

A light-receiving device according to an embodiment of the present disclosure includes a pixel array including light-receiving elements provided in respective pixels. The light-receiving elements each include a high electric field region and a photoelectric conversion region. A plurality of the light-receiving elements provided in the respective pixels includes a plurality of types of elements that have temperature regions having high photon detection efficiency (PDE). The temperature regions are different from each other and partially overlap each other.

Classes IPC  ?

  • H04N 23/52 - Caméras ou modules de caméras comprenant des capteurs d'images électroniques; Leur commande - Détails de structure Éléments optimisant le fonctionnement du capteur d'images, p. ex. pour la protection contre les interférences électromagnétiques [EMI] ou la commande de la température par des éléments de transfert de chaleur ou de refroidissement
  • G01S 7/481 - Caractéristiques de structure, p.ex. agencements d'éléments optiques
  • H04N 23/65 - Commande du fonctionnement de la caméra en fonction de l'alimentation électrique

38.

IMAGE SENSOR DEVICE, METHOD AND COMPUTER PROGRAM

      
Numéro d'application 18242424
Statut En instance
Date de dépôt 2023-09-05
Date de la première publication 2024-03-28
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Finatti, Salvatore
  • Avitabile, Antonio

Abrégé

An image sensor device includes circuitry configured to: receive an image; run a first neural network configured to detect one or more regions of interest in the image; and run a second neural network configured to determine, based on the image, whether a predetermined event has occurred; wherein when it is determined that the predetermined event has occurred, the image is output; and the circuitry is further configured such that the first neural network initiates obscuring processing to produce an obscured image in which the one or more regions of interest are obscured and the circuitry is configured to output the obscured image when it is determined that the predetermined event has not occurred.

Classes IPC  ?

  • G06V 10/25 - Détermination d’une région d’intérêt [ROI] ou d’un volume d’intérêt [VOI]
  • G06T 5/00 - Amélioration ou restauration d'image
  • G06V 10/74 - Appariement de motifs d’image ou de vidéo; Mesures de proximité dans les espaces de caractéristiques
  • G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
  • G06V 20/40 - RECONNAISSANCE OU COMPRÉHENSION D’IMAGES OU DE VIDÉOS Éléments spécifiques à la scène dans le contenu vidéo
  • G06V 20/62 - Texte, p.ex. plaques d’immatriculation, textes superposés ou légendes des images de télévision
  • G06V 40/16 - Visages humains, p.ex. parties du visage, croquis ou expressions
  • G06V 40/20 - Mouvements ou comportement, p.ex. reconnaissance des gestes

39.

DISTANCE MEASURING DEVICE

      
Numéro d'application 18255603
Statut En instance
Date de dépôt 2021-11-22
Date de la première publication 2024-03-28
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Yoshida, Atsushi

Abrégé

A distance measuring device according to the present disclosure includes a luminescence element, a light receiving element, and a substrate. The luminescence element irradiates an object (X) with light. The light receiving element receives light from the luminescence element reflected from the object (X). The luminescence element and the light receiving element are mounted on a substrate. In addition, a bonding wire (W) electrically connecting the light receiving element and the substrate is not disposed on an edge of the light receiving element on a side of the luminescence element.

Classes IPC  ?

  • G01S 7/481 - Caractéristiques de structure, p.ex. agencements d'éléments optiques
  • G01S 7/4863 - Réseaux des détecteurs, p.ex. portes de transfert de charge

40.

INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD

      
Numéro d'application 18255701
Statut En instance
Date de dépôt 2021-10-22
Date de la première publication 2024-03-28
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Machino, Yuki
  • Aoyagi, Seiichi

Abrégé

Provided is an information processing apparatus capable of improving detection accuracy of a position pointed by a target object. An acquisition unit acquires a distance image indicating a distance to each object present within a predetermined range. Subsequently, a vector calculation unit calculates a vector extending from the target object present within the predetermined range in a direction pointed by the target object on the basis of the acquired distance image. Subsequently, an intersection calculation unit calculates a position of an intersection of a predetermined surface present within the predetermined range and the calculated vector on the basis of the acquired distance image. Subsequently, a processing execution unit executes processing corresponding to the calculated position of the intersection.

Classes IPC  ?

  • G06V 10/94 - Architectures logicielles ou matérielles spécialement adaptées à la compréhension d’images ou de vidéos
  • G06F 3/042 - Numériseurs, p.ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction par des moyens opto-électroniques
  • G06F 3/0488 - Techniques d’interaction fondées sur les interfaces utilisateur graphiques [GUI] utilisant des caractéristiques spécifiques fournies par le périphérique d’entrée, p.ex. des fonctions commandées par la rotation d’une souris à deux capteurs, ou par la nature du périphérique d’entrée, p.ex. des gestes en fonction de la pression exer utilisant un écran tactile ou une tablette numérique, p.ex. entrée de commandes par des tracés gestuels
  • G06T 7/73 - Détermination de la position ou de l'orientation des objets ou des caméras utilisant des procédés basés sur les caractéristiques
  • G06V 30/14 - Acquisition d’images
  • G06V 30/19 - Reconnaissance utilisant des moyens électroniques
  • G06V 30/20 - Combinaison des fonctions d’acquisition, de prétraitement ou de reconnaissance
  • G06V 40/20 - Mouvements ou comportement, p.ex. reconnaissance des gestes

41.

DISPLAY MODULE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE

      
Numéro d'application 18264096
Statut En instance
Date de dépôt 2022-02-10
Date de la première publication 2024-03-28
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Nishikawa, Hiroshi

Abrégé

Provided is a display module capable of reducing connection resistance between a mounting board and a display. Provided is a display module capable of reducing connection resistance between a mounting board and a display. A display module includes a mounting board provided with a bump, and a display mounted on the mounting board and provided with a connection terminal bonded to the bump by solid-phase diffusion bonding.

Classes IPC  ?

  • H10K 59/131 - Interconnexions, p. ex. lignes de câblage ou bornes
  • G02F 1/1362 - Cellules à adressage par une matrice active
  • H01L 33/48 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les éléments du boîtier des corps semi-conducteurs
  • H01L 33/62 - Dispositions pour conduire le courant électrique vers le corps semi-conducteur ou depuis celui-ci, p.ex. grille de connexion, fil de connexion ou billes de soudure
  • H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
  • H10K 59/12 - Affichages à OLED à matrice active [AMOLED]

42.

IMAGING DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS

      
Numéro d'application 18529624
Statut En instance
Date de dépôt 2023-12-05
Date de la première publication 2024-03-28
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Miyanami, Yuki
  • Okuyama, Atsushi

Abrégé

An imaging device having a superior light-shielding property for a charge-holding section is provided. The imaging device includes: an Si {111} substrate extending along a horizontal plane; a photoelectric conversion section provided in the Si {111} substrate and generating charges corresponding to a light reception amount by photoelectric conversion; a charge-holding section provided in the Si {111} substrate and holding charges transferred from the photoelectric conversion section; and a light-shielding section including a horizontal light-shielding part positioned between the photoelectric conversion section and the charge-holding section in a thickness direction and extending along the horizontal plane and a vertical light-shielding part orthogonal thereto. The horizontal light-shielding section includes a first plane along a first crystal plane of the Si {111} substrate of a plane index {111} orthogonal to the thickness direction, and a second plane along a second crystal plane of the Si {111} substrate inclined to the thickness direction.

Classes IPC  ?

43.

NON-VOLATILE STORAGE CIRCUIT

      
Numéro d'application 17766568
Statut En instance
Date de dépôt 2020-10-16
Date de la première publication 2024-03-28
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s) Hiraga, Keizo

Abrégé

A non-volatile storage circuit (10) of an embodiment includes a volatile storage unit (11) that stores information, a non-volatile storage unit (20) into which the information in the volatile storage unit is written by a store operation, and from which the information is read out to the volatile storage unit (11) by a restore operation via a restore path different from a store path in the store operation, a driver unit (12, 15) that receives a power supply and performs the store operation, and a switch unit (13, 14, 16, 17) that shuts off the power supply to the driver unit (12, 15) during the restore operation.

Classes IPC  ?

  • G11C 14/00 - Mémoires numériques caractérisées par des dispositions de cellules ayant des propriétés de mémoire volatile et non volatile pour sauvegarder l'information en cas de défaillance de l'alimentation
  • G11C 5/14 - Dispositions pour l'alimentation

44.

ELECTRONIC CIRCUIT BOARD, BASE MEMBER, ELECTRONIC EQUIPMENT, ELECTRONIC EQUIPMENT MANUFACTURING METHOD, AND ELECTRONIC CIRCUIT BOARD MANUFACTURING METHOD

      
Numéro d'application 17754819
Statut En instance
Date de dépôt 2020-10-22
Date de la première publication 2024-03-28
Propriétaire
  • SONY GROUP CORPORATION (Japon)
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Ohtorii, Hiizu
  • Morita, Hiroshi
  • Oyama, Yusuke
  • Otani, Eiji
  • Kikuchi, Ken

Abrégé

The present technology relates to an electronic circuit board, a base member, electronic equipment, an electronic equipment manufacturing method and an electronic circuit board manufacturing method that make it possible to mount an electronic circuit board easily on a curved surface, for example. An electronic circuit board has a deformable wiring board having a plurality of areas that is long in one direction and is formed to be partially continuous with each other, and the plurality of areas of the wiring board is provided with deformable plate-like plate members that are more rigid than the wiring board. For example, the present technology can be applied to an electronic circuit board on which various devices are mounted.

Classes IPC  ?

  • H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
  • H05K 1/02 - Circuits imprimés - Détails

45.

LIGHT SOURCE APPARATUS

      
Numéro d'application 17754825
Statut En instance
Date de dépôt 2020-10-22
Date de la première publication 2024-03-28
Propriétaire
  • SONY GROUP CORPORATION (Japon)
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Ohtorii, Hiizu
  • Morita, Hiroshi
  • Oyama, Yusuke
  • Otani, Eiji
  • Kikuchi, Ken

Abrégé

The present technology relates to a light source apparatus that makes it possible to provide a widely applicable light source apparatus. A light source apparatus includes a transmissive board that transmits light emitted by a light-emitting element, a circuit board that drives the light-emitting element and is joined to the transmissive board, and a light-emitting board that has the light-emitting element and is connected to the circuit board via a first bump. Further, in the light source apparatus, the circuit board and an organic board are configured to be connected by sandwiching the light-emitting board via second bumps. The present technology can be applied to a light source apparatus that emits light.

Classes IPC  ?

  • H01L 27/15 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants semi-conducteurs avec au moins une barrière de potentiel ou une barrière de surface, spécialement adaptés pour l'émission de lumière
  • H01L 33/58 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les éléments du boîtier des corps semi-conducteurs Éléments de mise en forme du champ optique
  • H01L 33/64 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les éléments du boîtier des corps semi-conducteurs Éléments d'extraction de la chaleur ou de refroidissement
  • H05K 1/02 - Circuits imprimés - Détails

46.

SOLID-STATE IMAGING ELEMENT AND METHOD OF MANUFACTURING SAME

      
Numéro d'application 18257874
Statut En instance
Date de dépôt 2021-11-09
Date de la première publication 2024-03-21
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Kato, Akihiko
  • Kurobe, Toshihiro
  • Honjo, Akiko
  • Baba, Koichi
  • Kimizuka, Naohiko
  • Hirose, Yohei
  • Kataoka, Toyotaka
  • Toyofuku, Takuya

Abrégé

There is provided a solid-state imaging element capable of increasing a channel area of a pixel transistor and reducing a parasitic capacitance of a gate. A solid-state imaging element is a solid-state imaging element including pixels that photoelectrically convert incident light, and includes a substrate on which the pixels are provided, a first transistor provided in the pixels and including a first gate electrode portion embedded in a first direction from a first surface of the substrate toward a second surface of the substrate opposite to the first surface, a first gate insulating film provided between an active region of the substrate in which a channel of the first transistor is formed and a first side surface of the first gate electrode portion facing the active region, and a first insulating film provided on a second side surface of the first gate electrode portion other than the first side surface and thicker than the first gate insulating film, in which a depth of the first insulating film from the first surface to the second surface of the substrate is substantially the same as or deeper than a depth of the first gate electrode portion, and a width of an upper surface of the first gate electrode portion is wider than a width of a bottom surface of the first gate electrode portion in a cross section in the first direction.

Classes IPC  ?

47.

OPTICAL DETECTION DEVICE AND ELECTRONIC APPARATUS

      
Numéro d'application 18264123
Statut En instance
Date de dépôt 2021-12-24
Date de la première publication 2024-03-21
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Motokubota, Masaya

Abrégé

Provided is an optical detection device capable of obtaining an image with higher image quality. The optical detection device includes a plurality of color filters arranged in a two-dimensional array and a substrate including a plurality of photoelectric conversion units on which light passing through the color filters is incident. Then, the optical detection device has a configuration where an angle formed by a light receiving surface of the substrate and color filters (outer color filters) located outside a central portion of the two-dimensional array (color filter array) is different from an angle formed by the light receiving surface of the substrate and a color filter (central portion color filter) located at the central portion such that the outer color filters are inclined toward the central portion relative to the central portion color filter.

Classes IPC  ?

  • G02B 5/20 - Filtres
  • H04N 25/13 - Agencement de matrices de filtres colorés [CFA]; Mosaïques de filtres caractérisées par les caractéristiques spectrales des éléments filtrants

48.

SOLID-STATE IMAGE PICKUP APPARATUS AND ELECTRONIC EQUIPMENT

      
Numéro d'application 18476776
Statut En instance
Date de dépôt 2023-09-28
Date de la première publication 2024-03-21
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Ammo, Hiroaki
  • Ejiri, Hirokazu
  • Honjo, Akiko

Abrégé

A solid-state image pickup apparatus according to a first aspect of the present technology includes a photoelectric conversion section that generates and holds a charge in response to incident light, a transfer section that includes a V-NW transistor (Vertical Nano Wire transistor) and transfers the charge held in the photoelectric conversion section, and an accumulation section that includes a wiring layer connected to a drain of the transfer section including the V-NW transistor and accumulates the charge transferred by the transfer section. The present technology is applicable to a CMOS image sensor, for example.

Classes IPC  ?

  • H01L 27/146 - Structures de capteurs d'images
  • H01L 27/118 - Circuits intégrés à tranche maîtresse
  • H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
  • H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
  • H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
  • H10K 39/32 - Capteurs d'images organiques

49.

NFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING APPARATUS

      
Numéro d'application 18262282
Statut En instance
Date de dépôt 2022-01-04
Date de la première publication 2024-03-21
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Ishii, Michito
  • Onuki, Ryotaro

Abrégé

The present disclosure relates to an information processing system, an information processing method, and an information processing apparatus that obtain a more accurate distance. A first angle detection section detects a first reception angle of a signal in a first apparatus that is received from a transmitter. A second angle detection section detects a second reception angle of the signal in a second apparatus. A distance calculation section calculates distance information regarding a distance to the transmitter according to the first reception angle, the second reception angle, and the inter-apparatus distance between the first apparatus and the second apparatus. The technology according to the present disclosure is applicable, for example, to TWS based on the use of BLE.

Classes IPC  ?

  • G01S 5/04 - Position de source déterminée par plusieurs radiogoniomètres espacés
  • G06F 3/16 - Entrée acoustique; Sortie acoustique
  • H04R 1/10 - Ecouteurs; Leurs fixations

50.

IMAGE SENSOR AND ELECTRONIC DEVICE

      
Numéro d'application 18264159
Statut En instance
Date de dépôt 2022-01-06
Date de la première publication 2024-03-21
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Hiyoshi, Ren

Abrégé

The present disclosure relates to an image sensor and an electronic device capable of further improving performance. An image sensor includes: a photoelectric conversion unit provided for each of a plurality of pixels arranged in a matrix on a sensor surface; a TG transistor that transfers a charge generated by photoelectric conversion in the photoelectric conversion unit to an FD node; and a TGD transistor that transfers a charge generated by photoelectric conversion in the photoelectric conversion unit to an SN node. In addition, at least a part of a predetermined number of the pixels included in an intensity sharing unit that shares and uses the FD node and a predetermined number of the pixels included in an event sharing unit that shares and uses the SN node have different sharing destinations. The present technology can be applied to, for example, an image sensor that detects occurrence of an event and acquires an image.

Classes IPC  ?

  • H04N 25/77 - Circuits de pixels, p.ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs
  • H01L 27/146 - Structures de capteurs d'images
  • H04N 25/47 - Capteurs d'images avec sortie d'adresse de pixel; Capteurs d'images commandés par événement; Sélection des pixels à lire en fonction des données d'image

51.

SEMICONDUCTOR DEVICE, IMAGING DEVICE, AND MANUFACTURING METHOD

      
Numéro d'application 18264790
Statut En instance
Date de dépôt 2022-01-06
Date de la première publication 2024-03-21
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Shigetoshi, Takushi

Abrégé

The present technology relates to a semiconductor device, an imaging device, and a manufacturing method capable of forming a via connected to wirings at different depths so as not to cause a defect. The present technology relates to a semiconductor device, an imaging device, and a manufacturing method capable of forming a via connected to wirings at different depths so as not to cause a defect. A plurality of vias is provided, and an aspect ratio defined by a depth and a width of the via is substantially the same in the plurality of vias. The via is connected to the wiring in the wiring layer constituting the chip. The plurality of vias includes a first via that penetrates a chip stacked in the wiring layer and a second via that does not penetrate the chip. The present technology can be applied to, for example, a chip on which a solid-state imaging element is formed and an imaging element in which other chips are stacked.

Classes IPC  ?

52.

CONFIGURATION CONTROL CIRCUITRY AND CONFIGURATION CONTROL METHOD

      
Numéro d'application 18275808
Statut En instance
Date de dépôt 2022-02-08
Date de la première publication 2024-03-21
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Demaeyer, Jonathan
  • Amaya-Benitez, Manuel
  • Dehan, Morin
  • Cambareri, Valerio

Abrégé

A configuration control circuitry for a time-of-flight system, the time-of-flight system including an illumination source configured to emit light to a scene and an image sensor configured to generate image data representing a time-of-flight measurement of light reflected from the scene.

Classes IPC  ?

  • G01S 17/894 - Imagerie 3D avec mesure simultanée du temps de vol sur une matrice 2D de pixels récepteurs, p.ex. caméras à temps de vol ou lidar flash
  • G01S 7/487 - Extraction des signaux d'écho désirés

53.

SEMICONDUCTOR DEVICE AND IMAGING DEVICE

      
Numéro d'application 18262932
Statut En instance
Date de dépôt 2022-01-05
Date de la première publication 2024-03-14
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Hamaguchi, Shingo
  • Andou, Takeshi

Abrégé

The present technology relates to a semiconductor device and an imaging device capable of achieving a configuration that does not hinder downsizing even when a plurality of terminals including terminals with a potential difference is arranged. The present technology relates to a semiconductor device and an imaging device capable of achieving a configuration that does not hinder downsizing even when a plurality of terminals including terminals with a potential difference is arranged. A chip, a wiring substrate, and a wire connecting the chip and the wiring substrate are included, and a first opening and a second opening to which the wire is connected are formed on at least one side of the wiring substrate, the one side being on a surface of the wiring substrate on which an insulating film is formed. A first terminal formed in the first opening and a second terminal formed in the second opening are arranged at positions separated by a predetermined distance in the opening. The present technology can be applied to, for example, an imaging device in which a wiring substrate and a chip are connected by a bonding wire.

Classes IPC  ?

  • H01L 23/498 - Connexions électriques sur des substrats isolants
  • H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
  • H01L 27/146 - Structures de capteurs d'images

54.

IMAGING DEVICE, ELECTRONIC DEVICE, AND SIGNAL PROCESSING METHOD

      
Numéro d'application 18263042
Statut En instance
Date de dépôt 2022-01-18
Date de la première publication 2024-03-14
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Saito, Daisuke
  • Hanzawa, Katsuhiko

Abrégé

An imaging device according to an embodiment of the present disclosure includes a first substrate on which a pixel array unit that outputs a pixel signal obtained by photoelectrically converting incident light in a first direction is arranged, and a second substrate on which a memory array unit that outputs a convolution signal indicating a result of a product-sum operation of an input signal based on the pixel signal in a second direction is arranged. The first substrate and the second substrate at least partially overlap each other.

Classes IPC  ?

  • H01L 27/146 - Structures de capteurs d'images
  • H04N 25/77 - Circuits de pixels, p.ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs
  • H04N 25/79 - Agencements de circuits répartis entre des substrats, des puces ou des cartes de circuits différents ou multiples, p. ex. des capteurs d'images empilés

55.

IMAGING DEVICE AND ELECTRONIC EQUIPMENT

      
Numéro d'application 18263662
Statut En instance
Date de dépôt 2022-02-18
Date de la première publication 2024-03-14
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Otsuki, Seichi
  • Nakamura, Shigeki
  • Nomura, Yoshikuni

Abrégé

There is provided an imaging device including a pixel array unit (300) configured by arraying, in a row direction and a column direction, a plurality of pixels (304) of five or more types in which wavelength bands of detectable light are different in stages. The plurality of pixels are arrayed such that, at points having any spatial phases on the pixel array unit, mixed spectral characteristics obtained by mixing spectral characteristics of a predetermined number of pixels around the points are substantially same.

Classes IPC  ?

  • H04N 23/10 - Caméras ou modules de caméras comprenant des capteurs d'images électroniques; Leur commande pour générer des signaux d'image à partir de différentes longueurs d'onde

56.

PHOTOELECTRIC CONVERSION DEVICE AND ELECTRONIC APPARATUS

      
Numéro d'application 18263928
Statut En instance
Date de dépôt 2022-01-19
Date de la première publication 2024-03-14
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Nomoto, Kazuki
  • Ammo, Hiroaki

Abrégé

A photoelectric conversion device according to an embodiment of the present disclosure includes: a first semiconductor layer in which a transfer transistor is provided; a second semiconductor layer in which a pixel transistor is provided; and a wiring layer in which a gate wiring line coupled to a gate of the transfer transistor is provided. A portion or all of the pixel transistor is disposed, in plan view, in a region between a first gate wiring line and a second gate wiring line. The first gate wiring line is coupled to the gate of the transfer transistor in one of two pixels adjacent to each other. The second gate wiring line is coupled to the gate of the transfer transistor in another of the two pixels adjacent to each other.

Classes IPC  ?

57.

COMMUNICATION APPARATUS AND COMMUNICATION SYSTEM

      
Numéro d'application 18264112
Statut En instance
Date de dépôt 2022-02-03
Date de la première publication 2024-03-14
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Hyakudai, Toshihisa
  • Yamada, Junya
  • Ota, Satoshi

Abrégé

Communication apparatus with correct audio signal regeneration are disclosed. In one example, a communication apparatus includes a counter that counts the number of a predetermined reference clock included in one cycle of a divided signal of an audio master clock with a frequency that is equal to a product of a frequency of a sampling clock for sampling of an audio signal and a multiplier on the basis of the audio master clock, a ratio of division of the divided signal and the predetermined reference clock. A packet generator generates a packet including the counted number counted, a bit width of SD (Serial Data) conforming to an I2S standard, the frequency of the sampling clock, the ratio of division of the divided signal to the audio master clock, a frequency ratio of the frequency of the audio master clock to the frequency of the sampling clock, and the SD.

Classes IPC  ?

  • H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
  • G10L 19/02 - Techniques d'analyse ou de synthèse de la parole ou des signaux audio pour la réduction de la redondance, p.ex. dans les vocodeurs; Codage ou décodage de la parole ou des signaux audio utilisant les modèles source-filtre ou l’analyse psychoacoustique utilisant l'analyse spectrale, p.ex. vocodeurs à transformée ou vocodeurs à sous-bandes

58.

SOLID-STATE IMAGING APPARATUS AND ELECTRONIC APPARATUS

      
Numéro d'application 18511444
Statut En instance
Date de dépôt 2023-11-16
Date de la première publication 2024-03-14
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Uchida, Tetsuya
  • Suzuki, Ryoji
  • Ansai, Hisahiro
  • Ueda, Yoichi
  • Yoshida, Shinichi
  • Takeya, Yukari
  • Hirano, Tomoyuki
  • Mori, Hiroyuki
  • Nomura, Hirotoshi
  • Kudoh, Yoshiharu
  • Ohura, Masashi
  • Iwabuchi, Shin

Abrégé

There is provided a imaging device including: an N-type region formed for each pixel and configured to perform photoelectric conversion; an inter-pixel light-shielding wall penetrating a semiconductor substrate in a depth direction and formed between N-type regions configured to perform the photoelectric conversion, the N-type regions each being formed for each of pixels adjacent to each other; a P-type layer formed between the N-type region configured to perform the photoelectric conversion and the inter-pixel light-shielding wall; and a P-type region adjacent to the P-type layer and formed between the N-type region and an interface on a side of a light incident surface of the semiconductor substrate.

Classes IPC  ?

59.

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING PROGRAM

      
Numéro d'application 18512920
Statut En instance
Date de dépôt 2023-11-17
Date de la première publication 2024-03-14
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s) Handa, Yuji

Abrégé

An information processing apparatus comprising, at least one first processor configured to carry out a first process on data input from at least one sensor to produce first processed data, a selector configured to select, according to a first predetermined condition, at least one of a plurality of second processes, and at least one second processor configured to receive the first processed data from the at least one first processor and to carry out the selected at least one of the plurality of second processes on the first processed data to produce second processed data, each of the plurality of second processes having a lower processing load than the first process.

Classes IPC  ?

  • G06F 9/50 - Allocation de ressources, p.ex. de l'unité centrale de traitement [UCT]
  • B60W 60/00 - Systèmes d’aide à la conduite spécialement adaptés aux véhicules routiers autonomes
  • G01S 13/86 - Combinaisons de systèmes radar avec des systèmes autres que radar, p.ex. sonar, chercheur de direction
  • G01S 13/931 - Radar ou systèmes analogues, spécialement adaptés pour des applications spécifiques pour prévenir les collisions de véhicules terrestres
  • G06F 9/48 - Lancement de programmes; Commutation de programmes, p.ex. par interruption
  • G06V 10/70 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique
  • G06V 10/764 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant la classification, p.ex. des objets vidéo
  • G06V 10/80 - Fusion, c. à d. combinaison des données de diverses sources au niveau du capteur, du prétraitement, de l’extraction des caractéristiques ou de la classification
  • G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
  • G06V 10/94 - Architectures logicielles ou matérielles spécialement adaptées à la compréhension d’images ou de vidéos
  • G06V 10/96 - Gestion de tâches de reconnaissance d’images ou de vidéos
  • G06V 20/58 - Reconnaissance d’objets en mouvement ou d’obstacles, p.ex. véhicules ou piétons; Reconnaissance des objets de la circulation, p.ex. signalisation routière, feux de signalisation ou routes

60.

IMAGING DEVICE

      
Numéro d'application 17766833
Statut En instance
Date de dépôt 2020-04-23
Date de la première publication 2024-03-14
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Hoshi, Hironori
  • Masagaki, Atsushi

Abrégé

To provide an imaging device capable of further suppressing noise in a pixel signal. An imaging device includes: a semiconductor substrate (30) that includes a photoelectric conversion portion (31) configured to photoelectrically convert incident light, or a charge holding portion (32) configured to hold charge photoelectrically converted by the photoelectric conversion portion; a field effect transistor provided on the photoelectric conversion portion, or on the semiconductor substrate near the charge holding portion; a contact plug (26) that extends in a direction normal to one main surface of the semiconductor substrate from a gate electrode (25) of the field effect transistor; and a projecting portion (27) that extends in an in-plane direction of the one main surface of the semiconductor substrate from the contact plug.

Classes IPC  ?

61.

LIGHT DETECTION DEVICE AND ELECTRONIC APPARATUS

      
Numéro d'application 18259783
Statut En instance
Date de dépôt 2021-12-24
Date de la première publication 2024-03-14
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Yamashita, Kazuyoshi
  • Goi, Kazuhiro
  • Noudo, Shinichiro
  • Yamazaki, Tomohiro
  • Toda, Atsushi
  • Ogasahara, Takayuki
  • Miyata, Koji

Abrégé

The present technology relates to a light detection device and an electronic apparatus capable of increasing sensitivity of a specific pixel. The light detection device includes a pixel array unit in which a plurality of pixels is regularly arranged, the plurality of pixels including a first pixel and a second pixel, the first pixel including at least a photodiode and one or more pixel transistors, the second pixel including at least a photodiode larger in size than the photodiode of the first pixel, in which the pixel transistor in the first pixel is shared by the first pixel and the second pixel. The present technology may be applied to image sensors and the like, for example.

Classes IPC  ?

  • H04N 25/13 - Agencement de matrices de filtres colorés [CFA]; Mosaïques de filtres caractérisées par les caractéristiques spectrales des éléments filtrants

62.

PHOTODETECTION DEVICE AND PHOTODETECTION SYSTEM

      
Numéro d'application 18260198
Statut En instance
Date de dépôt 2022-01-11
Date de la première publication 2024-03-14
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Homma, Ryutaro
  • Shinozuka, Yasuhiro

Abrégé

A photodetection device according to the present disclosure includes: a light-receiving section including a light-receiving element, a first switch, a second switch, and a signal generator, the first switch that couples the light-receiving element to a first node by being turned on, the second switch that applies a predetermined voltage to the first node by being turned on, and the signal generator that generates a pulse signal on the basis of a voltage at the first node; a controller that controls operations of the first switch and the second switch; a detector that detects a timing at which the pulse signal is changed, on the basis of the pulse signal; and an output section that outputs a detection signal corresponding to a detection result by the detector when the second switch is turned on.

Classes IPC  ?

  • G01C 3/08 - Utilisation de détecteurs électriques de radiations
  • G01J 1/02 - Photométrie, p.ex. posemètres photographiques - Parties constitutives

63.

COMMUNICATION APPARATUS, COMMUNICATION SYSTEM, AND COMMUNICATION METHOD

      
Numéro d'application 18261034
Statut En instance
Date de dépôt 2021-12-16
Date de la première publication 2024-03-14
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Nakano, Hiroaki
  • Miyauchi, Toshiyuki
  • Fujimaki, Kenichi

Abrégé

[Object] [Object] Distance information can be acquired with a high degree of accuracy by a simple configuration, and positioning of high reliability is performed. [Object] Distance information can be acquired with a high degree of accuracy by a simple configuration, and positioning of high reliability is performed. [Solving Means] [Object] Distance information can be acquired with a high degree of accuracy by a simple configuration, and positioning of high reliability is performed. [Solving Means] A communication apparatus includes a phase acquisition unit that acquires a phase characteristic of a frequency in a propagation channel with a different communication apparatus, a distance generation unit that generates distance information in reference to the phase characteristic, and a speed sensor unit that measures a movement speed of a transmission side of the propagation channel, the movement speed being usable for correction of the phase characteristic.

Classes IPC  ?

  • G01S 13/58 - Systèmes de détermination de la vitesse ou de la trajectoire; Systèmes de détermination du sens d'un mouvement
  • G01S 7/40 - Moyens de contrôle ou d'étalonnage
  • G01S 13/84 - Systèmes utilisant la reradiation d'ondes radio, p.ex. du type radar secondaire; Systèmes analogues dans lesquels des signaux de type continu sont transmis pour la détermination de distance par mesure de phase

64.

RANGING SENSOR AND RANGING MODULE

      
Numéro d'application 18261201
Statut En instance
Date de dépôt 2021-12-16
Date de la première publication 2024-03-14
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Yokogawa, Sozo

Abrégé

A ranging sensor includes a pixel including a photoelectric conversion element, a first storage node and a second storage node that store charge transferred from the photoelectric conversion element, a first transfer gate and a second transfer gate connected to the photoelectric conversion element so as to branch and transfer the charge generated in the photoelectric conversion element to different paths, a third transfer gate connected between the first storage node and the first transfer gate, a fourth transfer gate connected between the second storage node and the second transfer gate, a fifth transfer gate connected between the first storage node and the second transfer gate, and a sixth transfer gate connected between the second storage node and the first transfer gate, the ranging sensor including a transfer gate drive unit that drives each of the first to sixth transfer gates.

Classes IPC  ?

  • G01S 7/4863 - Réseaux des détecteurs, p.ex. portes de transfert de charge
  • G01S 7/484 - Emetteurs
  • G01S 17/894 - Imagerie 3D avec mesure simultanée du temps de vol sur une matrice 2D de pixels récepteurs, p.ex. caméras à temps de vol ou lidar flash

65.

IMAGING APPARATUS

      
Numéro d'application 18261575
Statut En instance
Date de dépôt 2021-12-23
Date de la première publication 2024-03-14
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Yokoyama, Masanao

Abrégé

An imaging apparatus of the present disclosure includes: a pixel array including a plurality of light-receiving pixels including a first light-receiving pixel, a second light-receiving pixel, and a third light-receiving pixel, each generating a pixel signal in response to a received light amount, in which the first light-receiving pixel, the second light-receiving pixel, and the third light-receiving pixel are arranged in this order in a first direction; and a readout section including a first AD converter that performs AD conversion on the basis of each of the pixel signal generated by the first light-receiving pixel and the pixel signal generated by the third light-receiving pixel, and a second AD converter that performs AD conversion on the basis of the pixel signal generated by the second light-receiving pixel.

Classes IPC  ?

  • H04N 25/78 - Circuits de lecture pour capteurs adressés, p. ex. amplificateurs de sortie ou convertisseurs A/N
  • H04N 23/667 - Changement de mode de fonctionnement de la caméra, p. ex. entre les modes photo et vidéo, sport et normal ou haute et basse résolutions
  • H04N 25/79 - Agencements de circuits répartis entre des substrats, des puces ou des cartes de circuits différents ou multiples, p. ex. des capteurs d'images empilés

66.

SEMICONDUCTOR INTEGRATED CIRCUIT

      
Numéro d'application 18262129
Statut En instance
Date de dépôt 2022-01-26
Date de la première publication 2024-03-14
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Pham, Van Tuan
  • Nakahara, Hironori
  • Tamura, Masahisa

Abrégé

Provided are a semiconductor integrated circuit and an imaging device capable of reducing power consumption without complicating a configuration of oscillation control. Provided are a semiconductor integrated circuit and an imaging device capable of reducing power consumption without complicating a configuration of oscillation control. A semiconductor integrated circuit includes an oscillator that generates an oscillation signal whose oscillation frequency is discretely adjustable on the basis of a digital control input signal, an oscillation controller that generates the digital control input signal, and an intermittent controller that generates an intermittent control signal and supplies the intermittent control signal to the oscillation controller so that the oscillation controller intermittently updates the digital control input signal.

Classes IPC  ?

  • H03L 7/099 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
  • H04N 25/709 - Circuits de commande de l'alimentation électrique
  • H04N 25/76 - Capteurs adressés, p.ex. capteurs MOS ou CMOS

67.

SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE

      
Numéro d'application 18263311
Statut En instance
Date de dépôt 2021-12-17
Date de la première publication 2024-03-14
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Toyoshima, Takahiro

Abrégé

Provided is a solid-state imaging device capable of obtaining an image with a higher image quality. The solid-state imaging device includes a substrate, a pixel region formed on the substrate and configured such that a plurality of pixels is arrayed therein, a dug structure formed in the pixel region, and a p-type semiconductor region formed in a region adjacent to the dug structure in the substrate. Further, the pixel region is divided into an effective pixel region where effective pixels including photoelectric conversion units not shielded from light are arrayed and an OPB pixel region formed adjacent to the effective pixel region and configured such that light shielding pixels including photoelectric conversion units shielded from light are arrayed therein. In addition, in plan view, the percentage of an area occupied by the dug structure in the OPB pixel region is smaller than the percentage of an area occupied by the dug structure in the effective pixel region.

Classes IPC  ?

68.

SURFACE EMITTING LASER

      
Numéro d'application 18272878
Statut En instance
Date de dépôt 2022-01-07
Date de la première publication 2024-03-14
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Arakida, Takahiro

Abrégé

The present technology provides a surface emitting laser capable of reducing a voltage drop at a tunnel junction. The present technology provides a surface emitting laser capable of reducing a voltage drop at a tunnel junction. The present technology provides a surface emitting laser including: first and second multilayer film reflectors (102, 112) laminated together; a plurality of active layers laminated together between the first and second multilayer film reflectors (102, 112); and a tunnel junction (107) disposed between first and second active layers (104, 110) adjacent to each other in a lamination direction among the plurality of active layers, in which the tunnel junction (107) includes an n-type semiconductor layer (107b) and a p-type semiconductor layer (107a) laminated together, and the p-type semiconductor layer (107a) includes first and second p-type semiconductor regions (107a1, 107a2) laminated together.

Classes IPC  ?

  • H01S 5/30 - Structure ou forme de la région active; Matériaux pour la région active
  • H01S 5/183 - Lasers à émission de surface [lasers SE], p.ex. comportant à la fois des cavités horizontales et verticales comportant uniquement des cavités verticales, p.ex. lasers à émission de surface à cavité verticale [VCSEL]
  • H01S 5/32 - Structure ou forme de la région active; Matériaux pour la région active comprenant des jonctions PN, p.ex. hétérostructures ou doubles hétérostructures

69.

IMAGING DEVICE AND ELECTRONIC DEVICE

      
Numéro d'application 18370593
Statut En instance
Date de dépôt 2023-09-20
Date de la première publication 2024-03-14
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Yamagishi, Hajime
  • Hida, Shota
  • Kobayashi, Yuusaku

Abrégé

An imaging device comprises a first chip that includes a first semiconductor substrate including a photoelectric conversion region. The first chip includes a first insulating layer including a first multilayer wiring electrically connected to the photoelectric conversion region. The first multilayer wiring includes a first vertical signal line (VSL1) to output a first pixel signal, and a first wiring. The imaging device includes a second chip including a second semiconductor substrate including a logic circuit. The second chip includes a second insulating layer including a second multilayer wiring electrically connected to the logic circuit. The second multilayer wiring includes a second wiring. The first chip and the second chip are bonded to one another, and, in a plan view, the first wiring and the second wiring overlap with at least a portion of the first vertical signal line (VSL1).

Classes IPC  ?

70.

MEASUREMENT CIRCUIT AND ELECTRONIC EQUIPMENT

      
Numéro d'application 17754688
Statut En instance
Date de dépôt 2020-07-13
Date de la première publication 2024-03-14
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Kosaka, Takuro
  • Takenaka, Kyoichi

Abrégé

To improve the temperature measurement accuracy in a circuit that measures temperature by using an operational amplifier. To improve the temperature measurement accuracy in a circuit that measures temperature by using an operational amplifier. An operational amplifier outputs an output voltage corresponding to a difference between terminal voltages of a pair of input terminals. A resistor has one end connected to one of the pair of input terminals. A resistor-side rectification element is connected to another end of the resistor. A terminal-side rectification element is connected to the other one of the pair of input terminals. A switch connects an additional rectification element in parallel with either the resistor-side rectification element or the terminal-side rectification element. A current output section outputs a current corresponding to the output voltage. A difference acquisition section acquires, as temperature data, a difference between a signal corresponding to the current provided when the additional rectification element is not connected to the resistor-side rectification element or the terminal-side rectification element and a signal corresponding to the current provided when the additional rectification element is connected to the resistor-side rectification element or the terminal-side rectification element.

Classes IPC  ?

  • G01K 7/00 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur
  • G01R 19/00 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe
  • G01R 19/10 - Mesure d'une somme, d'une différence, ou d'un rapport

71.

ILLUMINATION DEVICE, LIGHT DETECTION DEVICE AND METHOD

      
Numéro d'application 17767916
Statut En instance
Date de dépôt 2020-10-20
Date de la première publication 2024-03-14
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Antoun, Anthony
  • Florea, Ruxandra-Marina
  • Belokonskiy, Victor

Abrégé

An illumination device for a light detection device, the light detection device including a light detection sensor and an optical lens portion, wherein the illumination device includes a light source configured to emit light to a scene and a light intensity adapting device configured to adapt a light intensity profile of the light emitted by the light source for at least partially providing a uniform light intensity on the light detection sensor of light reflected from the scene and detected by the light detection sensor through the optical lens portion.

Classes IPC  ?

  • G01S 7/484 - Emetteurs
  • G01S 7/4911 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe - Détails des systèmes non pulsés Émetteurs

72.

IMAGING DEVICE

      
Numéro d'application 18261685
Statut En instance
Date de dépôt 2021-12-28
Date de la première publication 2024-03-07
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Higano, Shun

Abrégé

To provide an imaging device that can suppress color mixing between adjacent pixels. An imaging device includes: a plurality of pixels arranged side by side in a direction parallel to one surface of a semiconductor substrate; an inter-pixel separation part provided on the semiconductor substrate and separating adjacent pixels among the plurality of pixels; a color filter provided on the one surface side of the semiconductor substrate; a plurality of convex lenses provided on the one surface side of the semiconductor substrate with the color filter interposed therebetween and arranged side by side in the direction parallel to the one surface; and a concave lens provided on the one surface side of the semiconductor substrate with the color filter and the plurality of convex lenses interposed therebetween. The inter-pixel separation part includes a same-color pixel separation part arranged between adjacent pixels of the same color among a first color pixel, a second color pixel, and a third color pixel, and a different-color pixel separation part arranged between adjacent pixels of different colors among the first color pixel, the second color pixel, and the third color pixel. The different-color pixel separation part has a trench isolation structure.

Classes IPC  ?

73.

INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD

      
Numéro d'application 18263386
Statut En instance
Date de dépôt 2022-01-05
Date de la première publication 2024-03-07
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Kim, Jongdae

Abrégé

The present disclosure relates to an information processing apparatus and an information processing method that enable suppression of an increase in time period in which image quality of a decoded image is degraded due to an error occurring on a reception side when encoded data of a video is transmitted. The present disclosure relates to an information processing apparatus and an information processing method that enable suppression of an increase in time period in which image quality of a decoded image is degraded due to an error occurring on a reception side when encoded data of a video is transmitted. Error information that is transmitted, via a second wireless channel, from a reception apparatus that receives encoded data of a video transmitted via a first wireless channel is acquired, the second wireless channel enabling transmission involving lower latency than the first wireless channel, and encoding of the video is controlled on the basis of the error information acquired. The present disclosure can be applied to, for example, an information processing apparatus, an encoding apparatus, a decoding apparatus, electronic equipment, an information processing method, a program, or the like.

Classes IPC  ?

  • H04N 19/166 - Retour d’information en provenance du récepteur ou du canal de transmission concernant la quantité d’erreurs de transmission, p.ex. le taux d’erreur binaire
  • H04N 19/107 - Sélection du mode de codage ou du mode de prédiction entre codage prédictif spatial et temporel, p.ex. rafraîchissement d’image
  • H04N 19/172 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c. à d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p.ex. un objet la zone étant une image, une trame ou un champ

74.

ELECTROMAGNETIC WAVE DETECTION DEVICE, ELECTROMAGNETIC WAVE DETECTION SYSTEM, AND ELECTROMAGNETIC WAVE DETECTION METHOD

      
Numéro d'application 17767617
Statut En instance
Date de dépôt 2020-09-18
Date de la première publication 2024-03-07
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Yamaguchi, Tetsuji

Abrégé

An electromagnetic wave detection device including: an electromagnetic wave absorption layer including a low-dimensional electronic material that absorbs an electromagnetic wave; a first electrode provided on a first principal surface of the electromagnetic wave absorption layer; a second electrode provided on a second principal surface of the electromagnetic wave absorption layer, the second principal surface being opposed to the first principal surface; and a read circuit that reads, from the second electrode, a signal generated by thermoelectric conversion of heat generated by the electromagnetic wave absorption layer that has absorbed the electromagnetic wave.

Classes IPC  ?

  • H10N 10/13 - Dispositifs thermoélectriques comportant une jonction de matériaux différents, c. à d. dispositifs présentant l'effet Seebeck ou l'effet Peltier fonctionnant exclusivement par les effets Peltier ou Seebeck caractérisés par les moyens d'échange de chaleur à la jonction
  • G01J 1/44 - Circuits électriques
  • H10N 10/855 - Matériaux actifs thermoélectriques comprenant des compositions inorganiques comprenant des composés contenant du bore, du carbone, de l'oxygène ou de l'azote

75.

IMAGING APPARATUS AND MANUFACTURING METHOD OF IMAGING APPARATUS

      
Numéro d'application 18256179
Statut En instance
Date de dépôt 2021-11-11
Date de la première publication 2024-03-07
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Fukuhara, Kei

Abrégé

Provided is an imaging apparatus capable of enhancing heat resistance of a color filter and a manufacturing method of the imaging apparatus. An imaging apparatus includes a semiconductor substrate, a color filter provided on one surface side of the semiconductor substrate, and a first sealing material provided on the one surface side, the first sealing material that covers the color filter. The first sealing material includes a material capable of transmitting light of a wavelength band set in advance and having a thermal conductivity of 0.5 W/m·K or less.

Classes IPC  ?

76.

SOLID-STATE IMAGING DEVICE AND ELECTRONIC INSTRUMENT

      
Numéro d'application 18260091
Statut En instance
Date de dépôt 2021-12-28
Date de la première publication 2024-03-07
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Kato, Eriko
  • Kato, Akihiko

Abrégé

To reduce the number of wirings through which transmission and reception are made between chips. To reduce the number of wirings through which transmission and reception are made between chips. The solid-state imaging device includes a first substrate including a pixel array unit in which a plurality of pixels is arranged, each of the plurality of pixels including a photoelectric conversion unit, and the first substrate includes a first wiring through which an imaging pixel signal is transmitted, the imaging pixel signal being read from two or more of the pixels arranged in a first direction in the pixel array unit, a second wiring through which a reset voltage for initializing the first wiring is supplied, and a first switching circuit configured to switch whether or not to short-circuit the first wiring and the second wiring.

Classes IPC  ?

  • H04N 25/77 - Circuits de pixels, p.ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs
  • H01L 27/146 - Structures de capteurs d'images
  • H04N 25/76 - Capteurs adressés, p.ex. capteurs MOS ou CMOS

77.

COMMUNICATION APPARATUS, COMMUNICATION SYSTEM, AND COMMUNICATION METHOD

      
Numéro d'application 18261360
Statut En instance
Date de dépôt 2022-02-03
Date de la première publication 2024-03-07
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Hyakudai, Toshihisa
  • Yamada, Junya
  • Ota, Satoshi

Abrégé

[Object] [Object] To perform serial communication at high speed by combining different communication methods with each other. [Object] To perform serial communication at high speed by combining different communication methods with each other. [Solving Means] [Object] To perform serial communication at high speed by combining different communication methods with each other. [Solving Means] A communication apparatus includes a communicating unit configured to add identification information identifying a data block to one set of the data block including a serial signal group, the serial signal group being transmitted from a master in synchronism with a clock and complying with SPI (Serial Peripheral Interface), and transmit the one set of the data block to a communication partner apparatus within one frame period of a predetermined communication protocol, or add identification information identifying each of multiple data blocks to the multiple data blocks each including a part of the serial signal group and transmit the multiple data blocks to the communication partner apparatus in multiple frame periods.

Classes IPC  ?

  • G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation
  • G06F 13/40 - Structure du bus
  • H04L 5/14 - Fonctionnement à double voie utilisant le même type de signal, c. à d. duplex

78.

PHOTODETECTOR AND ELECTRONIC APPARATUS

      
Numéro d'application 18261736
Statut En instance
Date de dépôt 2022-01-12
Date de la première publication 2024-03-07
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s) Suzuki, Yuichiro

Abrégé

The present disclosure suppresses deterioration of white spot and dark current characteristics. A photodetector includes a semiconductor layer having a first surface and a second surface located opposite to each other and provided with an element isolation region on a side of the first surface, a photoelectric converter provided in the semiconductor layer, and a transistor provided adjacent to the photoelectric converter on the side of the first surface of the semiconductor layer across the element isolation region. Then, the element isolation region includes a conductive film provided in a groove on the side of the first surface of the semiconductor layer with the first insulating film interposed therebetween, and a second insulating film provided on the side of the first surface of the semiconductor layer so as to overlap the conductive film.

Classes IPC  ?

79.

INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING DEVICE, AND INFORMATION PROCESSING METHOD

      
Numéro d'application 18261744
Statut En instance
Date de dépôt 2021-12-24
Date de la première publication 2024-03-07
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Shinozaki, Katsuya

Abrégé

The present technology relates to an information processing system, an information processing device, and an information processing method that make it possible to reduce labor and time for updating of white lists of a plurality of information processing devices with the same contents. The present technology relates to an information processing system, an information processing device, and an information processing method that make it possible to reduce labor and time for updating of white lists of a plurality of information processing devices with the same contents. The information processing system includes a plurality of information processing devices each having connection permission device information including identification information of a connection permission device to which connection by wireless communication is to be permitted. In a case in which predetermined updating is performed for the connection permission device information of a predetermined information processing device from among the plurality of information processing devices, another information processing device from among the plurality of information processing devices acquires contents of the predetermined updating and performs updating for the connection permission device information with the same contents as those of the predetermined updating.

Classes IPC  ?

  • H04W 40/24 - Gestion d'informations sur la connectabilité, p.ex. exploration de connectabilité ou mise à jour de connectabilité
  • H04W 48/02 - Restriction d'accès effectuée dans des conditions spécifiques

80.

TRANSMISSION DEVICE AND COMMUNICATION SYSTEM

      
Numéro d'application 18262388
Statut En instance
Date de dépôt 2021-12-23
Date de la première publication 2024-03-07
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Ochiai, Yasuhiro

Abrégé

A transmission device according to the present disclosure includes: a driver that transmits a transmission signal including two or more signals; an alternating current signal generator including a phase-locked loop circuit that generates an alternating current signal, the alternating current signal generator being configured to set a phase and frequency of the alternating current signal; an amplifier configured to amplify the alternating current signal generated by the alternating current signal generator and set amplitude of the alternating current signal; and a superimposer that superimposes the alternating current signal amplified by the amplifier on the two or more signals.

Classes IPC  ?

  • H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p.ex. en utilisant une boucle verrouillée en phase
  • H03K 5/01 - Mise en forme d'impulsions

81.

INFORMATION PROCESSING METHOD, INFORMATION PROCESSING DEVICE, AND NON-VOLATILE STORAGE MEDIUM

      
Numéro d'application 18262434
Statut En instance
Date de dépôt 2022-01-27
Date de la première publication 2024-03-07
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Doi, Hiromasa
  • Nakagawa, Takaaki
  • Wang, Guangyu

Abrégé

The information processing method includes segment extraction processing and adjustment processing. In the segment extraction processing, a segment corresponding to a label associated with an effect is extracted from a video of a camera (20). In the adjustment processing, an application position of the effect is adjusted according to a change in a posture of the camera (20), which posture is detected by utilization of information including acceleration data, in such a manner that the application position of the effect is not deviated from the extracted segment.

Classes IPC  ?

  • G06T 11/00 - Génération d'images bidimensionnelles [2D]
  • G06F 3/01 - Dispositions d'entrée ou dispositions d'entrée et de sortie combinées pour l'interaction entre l'utilisateur et le calculateur
  • G06T 7/10 - Découpage; Détection de bords
  • G06T 7/50 - Récupération de la profondeur ou de la forme
  • G06T 7/70 - Détermination de la position ou de l'orientation des objets ou des caméras

82.

INFORMATION PROCESSING APPARATUS, IMAGING SYSTEM, INFORMATION PROCESSING METHOD, AND PROGRAM

      
Numéro d'application 18262435
Statut En instance
Date de dépôt 2022-01-07
Date de la première publication 2024-03-07
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Yamashita, Hiroki
  • Siddiqui, Muhammad
  • Incesu, Yalcin
  • Ueda, Tomoki
  • Suzuki, Masaru
  • Ito, Masahiro

Abrégé

An information processing apparatus (10) includes a first acquisition unit (111), a second acquisition unit (111), and an estimation unit (112). The first acquisition unit (111) acquires first sensing information obtained by capturing an image of a subject using a first sensor (20A) including a single-plate image sensor. The second acquisition unit (111) acquires second sensing information obtained by sensing a direction different from a direction of the first sensor (20A) using second sensor (20B). The estimation unit (112) estimates the spectral reflectance of the subject based on the first sensing information and the second sensing information.

Classes IPC  ?

  • H04N 23/13 - Caméras ou modules de caméras comprenant des capteurs d'images électroniques; Leur commande pour générer des signaux d'image à partir de différentes longueurs d'onde avec plusieurs capteurs
  • G06T 7/90 - Détermination de caractéristiques de couleur

83.

SOLID-STATE IMAGE SENSOR

      
Numéro d'application 18327978
Statut En instance
Date de dépôt 2023-06-02
Date de la première publication 2024-03-07
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Sato, Yusuke

Abrégé

A solid-state image sensor includes a plurality of imaging element blocks 10 each configured from a plurality of imaging elements. Each of the imaging elements includes a first electrode, a charge accumulating electrode arranged in a spaced relation from the first electrode, a photoelectric conversion portion contacting with the first electrode and formed above the charge accumulating electrode with an insulating layer interposed therebetween, and a second electrode formed on the photoelectric conversion portion. The first electrode and the charge accumulating electrode are provided on an interlayer insulating layer, and the first electrode is connected to a connection portion provided in the interlayer insulating layer.

Classes IPC  ?

  • H10K 39/32 - Capteurs d'images organiques
  • H04N 25/79 - Agencements de circuits répartis entre des substrats, des puces ou des cartes de circuits différents ou multiples, p. ex. des capteurs d'images empilés
  • H10K 19/20 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comprenant au moins un élément organique spécialement adapté au redressement, à l'amplification, à l'oscillation ou à la commutation couvert par le groupe . comprenant des composants ayant une région active qui comprend un semi-conducteur inorganique
  • H10K 30/30 - Dispositifs organiques sensibles au rayonnement infrarouge, à la lumière, au rayonnement électromagnétique de plus courte longueur d'onde ou au rayonnement corpusculaire comprenant des hétérojonctions de masse, p. ex. des réseaux interpénétrés de domaines de matériaux donneurs et accepteurs
  • H10K 30/82 - Dispositifs organiques sensibles au rayonnement infrarouge, à la lumière, au rayonnement électromagnétique de plus courte longueur d'onde ou au rayonnement corpusculaire - Détails de structure Électrodes Électrodes transparentes, p. ex. électrodes en oxyde d'étain indium [ITO]

84.

IMAGING APPARATUS AND ELECTRONIC EQUIPMENT

      
Numéro d'application 17754711
Statut En instance
Date de dépôt 2020-10-08
Date de la première publication 2024-03-07
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Yamada, Satoshi
  • Ozawa, Hiroyuki
  • Kai, Hitoshi

Abrégé

Signal processing is performed using a built-in memory. An imaging apparatus includes: a pixel array unit that includes a plurality of pixels performing photoelectric conversion; a converter that converts an analog pixel signal output from the pixel array unit into digital image data; an image processing unit that performs image processing on the digital image data; and a storage unit that includes a plurality of regions for which a power distribution state is able to be selectively designated, and stores at least the digital image data output by the image processing unit.

Classes IPC  ?

  • H04N 23/65 - Commande du fonctionnement de la caméra en fonction de l'alimentation électrique
  • G06V 10/774 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant l’intégration et la réduction de données, p.ex. analyse en composantes principales [PCA] ou analyse en composantes indépendantes [ ICA] ou cartes auto-organisatrices [SOM]; Séparation aveugle de source méthodes de Bootstrap, p.ex. "bagging” ou “boosting”
  • G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
  • H04N 5/262 - Circuits de studio, p.ex. pour mélanger, commuter, changer le caractère de l'image, pour d'autres effets spéciaux
  • H04N 23/611 - Commande des caméras ou des modules de caméras en fonction des objets reconnus les objets reconnus comprenant des parties du corps humain
  • H04N 23/81 - Chaînes de traitement de la caméra; Leurs composants pour supprimer ou minimiser les perturbations lors de la génération de signaux d'image
  • H04N 25/78 - Circuits de lecture pour capteurs adressés, p. ex. amplificateurs de sortie ou convertisseurs A/N

85.

LIGHT DETECTION DEVICE AND DISTANCE MEASUREMENT APPARATUS

      
Numéro d'application 18258063
Statut En instance
Date de dépôt 2022-01-13
Date de la première publication 2024-02-29
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Otake, Yusuke
  • Wakano, Toshifumi

Abrégé

A light detection device according to an embodiment of the present disclosure includes: a semiconductor substrate that includes a first surface and a second surface opposed to each other, and includes a pixel array in which a plurality of pixels is disposed in an array; a semiconductor layer that is provided on a side of the first surface of the semiconductor substrate; a light receiver that is provided inside the semiconductor substrate for each of the pixels, and generates carriers corresponding to a received light amount by photoelectric conversion; a multiplier that includes a first conduction-type region and a second conduction-type region sequentially stacked on the side of the first surface, at least the second conduction-type region being provided in the semiconductor layer, and that performs avalanche multiplication on the carriers generated by the light receiver; a first electrode that is provided on the side of the first surface, and is electrically coupled to the light receiver; and a second electrode that is provided on the side of the first surface, and is electrically coupled to the multiplier.

Classes IPC  ?

  • H01L 27/146 - Structures de capteurs d'images
  • G01S 7/481 - Caractéristiques de structure, p.ex. agencements d'éléments optiques
  • G01S 17/08 - Systèmes déterminant les données relatives à la position d'une cible pour mesurer la distance uniquement

86.

MULTIPLY-ACCUMULATE OPERATION DEVICE AND NEURAL NETWORK

      
Numéro d'application 18258278
Statut En instance
Date de dépôt 2021-12-16
Date de la première publication 2024-02-29
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Tsukamoto, Masanori

Abrégé

A multiply-accumulate operation device according to an aspect of the present disclosure includes multiple cells each including a transistor and a ferroelectric capacitor that is coupled to a first source and drain terminal of the transistor. The multiple cells are arranged in rows and columns. This multiply-accumulate operation device further includes multiple input wiring lines and multiple output wiring lines. Each unit of one or more of the multiple input wiring lines is assigned to corresponding one of the rows of the multiple cells. The multiple input wiring lines are coupled to the ferroelectric capacitors. Each of the multiple output wiring lines is assigned to corresponding one of the columns of the multiple cells. The multiple output wiring lines are coupled to second source and drain terminals of the transistors. The multiple output wiring lines are each configured to store an amount of electric charge corresponding to a product of capacitance of the ferroelectric capacitor of each of the cells and an input voltage supplied to the input wiring line.

Classes IPC  ?

  • G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
  • G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
  • G11C 11/22 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des éléments ferro-électriques
  • G11C 11/54 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments simulateurs de cellules biologiques, p.ex. neurone

87.

IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND IMAGE PROCESSING PROGRAM

      
Numéro d'application 18261354
Statut En instance
Date de dépôt 2022-01-18
Date de la première publication 2024-02-29
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Ueda, Tomoki
  • Ito, Masahiro
  • Suzuki, Masaru
  • Yamashita, Hiroki

Abrégé

Detection of a spectral distribution of a light source is simplified. An image processing device according to the present disclosure includes a specific region detection unit, a chromaticity information detection unit, and a light source spectral information generation unit. The specific region detection unit detects a specific region that is a region of an image of a specific object from an image of a subject to which light from a light source is emitted. The chromaticity information detection unit detects light source color information on the basis of a plurality of image signals of the detected specific region. The light source spectral information generation unit generates light source spectral information, which is information of a spectrum of the light source, on the basis of the detected light source color information.

Classes IPC  ?

  • G06T 7/90 - Détermination de caractéristiques de couleur
  • G06V 10/25 - Détermination d’une région d’intérêt [ROI] ou d’un volume d’intérêt [VOI]
  • G06V 10/56 - Extraction de caractéristiques d’images ou de vidéos relative à la couleur
  • G06V 10/60 - Extraction de caractéristiques d’images ou de vidéos relative aux propriétés luminescentes, p.ex. utilisant un modèle de réflectance ou d’éclairage

88.

SENSOR MODULE

      
Numéro d'application 18269741
Statut En instance
Date de dépôt 2021-12-14
Date de la première publication 2024-02-29
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s) Tanaka, Haruki

Abrégé

[Object] To provide a sensor module that makes it possible to suppress generation of resin burrs and improve workability. [Object] To provide a sensor module that makes it possible to suppress generation of resin burrs and improve workability. [Solving Means] A sensor module (100) according to an embodiment of the present technology includes a sensor element, a first case (11), a second case (12), and a groove (70). The first case (11) includes an opening end including a first welded region and accommodates therein the sensor element. The second case (12) includes a joining surface (123) including a second welded region (50), the second welded region (50) being welded to the first welded region to form a welded portion. The groove (70) is formed in at least one of the first welded region or the second welded region (50).

Classes IPC  ?

89.

CONTROL DEVICE, STORAGE DEVICE, SEMICONDUCTOR DEVICE, AND CONTROL METHOD

      
Numéro d'application 18270980
Statut En instance
Date de dépôt 2021-12-17
Date de la première publication 2024-02-29
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Nakazawa, Masaaki
  • Kuroda, Masami

Abrégé

A control device (10) according to an embodiment includes an initial write instruction unit (30) and a data write instruction unit (40). The initial write instruction unit (30), before accepting an information write request to a storage device (20) including a plurality of resistance change storage elements each of which stores information by using a difference of the resistance state, outputs to the storage device (20) a write instruction to bring the storage element into a first resistance state. The data write instruction unit (40), upon accepting a write request, outputs to the storage device (20) a write instruction to bring the storage element into the first resistance state or a second resistance state according to the write request.

Classes IPC  ?

  • G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou

90.

SOLID-STATE IMAGE SENSOR AND ELECTRONIC DEVICE

      
Numéro d'application 18485703
Statut En instance
Date de dépôt 2023-10-12
Date de la première publication 2024-02-29
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Nishino, Tatsuki
  • Hiyama, Hiroki
  • Matsumoto, Shizunori
  • Miura, Takahiro
  • Miyanohara, Akihiko
  • Matsumoto, Tomohiro

Abrégé

To control an excess bias to an appropriate value in a light detection device. To control an excess bias to an appropriate value in a light detection device. A solid-state image sensor includes a photodiode, a resistor, and a control circuit. In this solid-state image sensor, the photodiode photoelectrically converts incident light and outputs a photocurrent. Furthermore, in the solid-state image sensor, the resistor is connected to a cathode of the photodiode. Furthermore, in the solid-state image sensor, the control circuit supplies a lower potential to an anode of the photodiode as a potential of the cathode of when the photocurrent flows through the resistor is higher.

Classes IPC  ?

  • H04N 25/704 - Pixels spécialement adaptés à la mise au point, p. ex. des ensembles de pixels à différence de phase
  • G01J 1/44 - Circuits électriques
  • H01L 27/146 - Structures de capteurs d'images
  • H04N 25/50 - Commande des paramètres d'exposition de capteurs SSIS

91.

DELAY ADJUSTMENT CIRCUIT AND DISTANCE MEASURING DEVICE

      
Numéro d'application 18549067
Statut En instance
Date de dépôt 2022-03-02
Date de la première publication 2024-02-29
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Tabata, Mitsushi
  • Masuda, Takashi
  • Suzuki, Daisuke

Abrégé

A delay adjustment circuit according to an embodiment includes: a plurality of delay adjustment units connected in series, each of the plurality of delay adjustment units including one or more first delay elements (102) connected in series that delay an input signal on the basis of a clock, and a first selector (120) that outputs one of the input signal and an output of the first delay element at a last stage among the one or more first delay elements; and an output unit (103, 104, 130a, 130b, 140) that outputs a clock according to an output of the first selector included in a delay adjustment unit at a last stage among the plurality of delay adjustment units, in which each of the plurality of delay adjustment units includes a different number of the first delay elements.

Classes IPC  ?

  • H03K 5/133 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés utilisant une chaîne de dispositifs actifs de retard
  • G01S 7/4915 - Mesure du temps de retard, p.ex. détails opérationnels pour les composants de pixels; Mesure de la phase
  • H03K 5/156 - Dispositions dans lesquelles un train d'impulsions est transformé en un train ayant une caractéristique désirée

92.

OPTICAL DETECTION DEVICE

      
Numéro d'application 18258049
Statut En instance
Date de dépôt 2022-01-05
Date de la première publication 2024-02-29
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Jibiki, Yuma
  • Shimada, Shohei
  • Otake, Yusuke

Abrégé

Provided is an optical detection device capable of suppressing a fluctuation of a drive starting voltage in a pixel. Provided is an optical detection device capable of suppressing a fluctuation of a drive starting voltage in a pixel. The optical detection device according to the present disclosure includes: a semiconductor substrate that has a first surface as a light incident surface and a second surface on an opposite side to the light incident surface; a first pixel that is in the semiconductor substrate and has an avalanche amplification region including a first conductive region and a second conductive region; a pixel isolation portion that isolates the first pixel from an adjacent pixel; a first insulation film that is provided on the second surface side and in contact with the pixel isolation portion; and a second insulation film that is provided between the first insulation film and the avalanche amplification region, in which a film thickness of the second insulation film is larger than the film thickness of the first insulation film.

Classes IPC  ?

  • H01L 31/107 - Dispositifs sensibles au rayonnement infrarouge, visible ou ultraviolet caractérisés par une seule barrière de potentiel ou de surface la barrière de potentiel fonctionnant en régime d'avalanche, p.ex. photodiode à avalanche
  • H01L 27/146 - Structures de capteurs d'images

93.

SOLID-STATE IMAGING ELEMENT AND IMAGING DEVICE

      
Numéro d'application 18259590
Statut En instance
Date de dépôt 2021-12-20
Date de la première publication 2024-02-29
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Miyake, Shinichi
  • Tomida, Kazuyuki
  • Niwa, Atsumi

Abrégé

A solid-state imaging element (200) according to the present disclosure includes a light receiving substrate (201) and a circuit board (202). The light receiving substrate (201) includes a plurality of light receiving circuits (211) in which photoelectric conversion elements are provided. The circuit board (202) is bonded to the light receiving substrate (201) and includes a plurality of address event detection circuits (231) that respectively detects voltage changes output from the photoelectric conversion elements of the plurality of light receiving circuits (211). The circuit board (202) includes a first element region (501) and a second element region (502). In the first element region (501), a first transistor (T1) driven by a first voltage (VDD1) is arranged. In the second element region (502), a second transistor (T2) driven by a second voltage (VDD2) lower than the first voltage (VDD1) is arranged. A full trench isolation (FTI) structure (521) is arranged between the first element region (501) and the second element region (502) adjacent to each other.

Classes IPC  ?

  • H01L 27/146 - Structures de capteurs d'images
  • H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
  • H04N 25/77 - Circuits de pixels, p.ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs

94.

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, METHOD, AND PROGRAM

      
Numéro d'application 18259899
Statut En instance
Date de dépôt 2021-12-24
Date de la première publication 2024-02-29
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Shigematsu, Kazuma

Abrégé

Images of a chart installed on a road are captured from positions at a constant distance, the captured images are analyzed to calculate a camera resolution, and a warning output/automated-driving-level lowering process is executed depending on a result of the calculation. An image analyzing section selects, from camera-captured images and as an image for resolution analysis, an image captured at a timing of detection of a reference line. A resolution calculating section calculates the resolution of captured images by using a chart image for resolution analysis included in the image for resolution analysis selected by the image analyzing section. The reference line is recorded on a road where a moving apparatus is running, at positions at a constant distance from a chart for resolution analysis installed on the road, and a highly precise resolution of captured images based on images of the chart captured from the positions at the constant distance can be calculated.

Classes IPC  ?

  • H04N 17/00 - Diagnostic, test ou mesure, ou leurs détails, pour les systèmes de télévision
  • B60W 50/14 - Moyens d'information du conducteur, pour l'avertir ou provoquer son intervention
  • B60W 60/00 - Systèmes d’aide à la conduite spécialement adaptés aux véhicules routiers autonomes
  • H04N 23/62 - Commande des paramètres via des interfaces utilisateur
  • H04N 23/80 - Chaînes de traitement de la caméra; Leurs composants

95.

SOLID-STATE IMAGING ELEMENT AND IMAGING DEVICE

      
Numéro d'application 18260204
Statut En instance
Date de dépôt 2022-01-13
Date de la première publication 2024-02-29
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s) Asakura, Luonghung

Abrégé

Image quality enhancement in a solid-state imaging element with simultaneous pixel exposure is disclosed. In one example, a solid-state imaging element includes a first pixel with a first selection transistor that opens and closes a path between a first capacitive element holding a predetermined reset level and a predetermined node, and a second selection transistor that opens and closes a path between a second capacitive element holding a signal level corresponding to an exposure amount and the node. It also includes a second pixel with a third selection transistor that opens and closes a path between a third capacitive element holding a predetermined reset level and a predetermined node, and a fourth selection transistor that opens and closes a path between a fourth capacitive element holding a signal level corresponding to the exposure amount.

Classes IPC  ?

  • H04N 25/532 - Commande du temps d'intégration en commandant des obturateurs globaux dans un capteur SSIS CMOS
  • H04N 25/778 - Circuits de pixels, p.ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des amplificateurs partagés entre une pluralité de pixels, c. à d. qu'au moins une partie de l'amplificateur doit se trouver sur la matrice de capteurs elle-même
  • H04N 25/78 - Circuits de lecture pour capteurs adressés, p. ex. amplificateurs de sortie ou convertisseurs A/N

96.

MEMORY CONTROLLER AND MEMORY ACCESS METHOD

      
Numéro d'application 18261365
Statut En instance
Date de dépôt 2022-01-06
Date de la première publication 2024-02-29
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s) Sugimori, Yasufumi

Abrégé

The present disclosure relates to a memory controller and a memory access method that make it possible to suppress occurrence of useless access. The present disclosure relates to a memory controller and a memory access method that make it possible to suppress occurrence of useless access. A readout controlling section starts, in response to a burst access request for a memory, reading out of data from the memory without depending on completion of the burst access request. A buffer stores multiple pieces of data read out from the memory, and an output controlling section outputs the multiple pieces of data stored in the buffer, according to a protocol of an outputting destination. The technology according to the present disclosure can be applied, for example, to LSI that is built in a TWS for which Bluetooth is used.

Classes IPC  ?

  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

97.

SIGNAL PROCESSING CIRCUIT AND DISTRIBUTION CIRCUIT

      
Numéro d'application 18261442
Statut En instance
Date de dépôt 2021-12-09
Date de la première publication 2024-02-29
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s)
  • Murakami, Tomomichi
  • Sano, Eiichi
  • Ando, Takahiro
  • Murayama, Norihiro

Abrégé

Provided is a distribution circuit which has good pass characteristic and isolation characteristic over a wide band. A distribution circuit, in which Wilkinson-type distribution circuits configured with a coil, a capacitor, and a resistor are cascaded in two stages between an input terminal and at least three terminals, and a capacitor is connected in parallel with the resistor inserted between the output terminals in the latter-stage Wilkinson-type distribution circuits.

Classes IPC  ?

  • H01P 5/16 - Dispositifs à accès conjugués, c. à d. dispositifs présentant au moins un accès découplé d'un autre accès
  • H05K 1/02 - Circuits imprimés - Détails

98.

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM

      
Numéro d'application 18263657
Statut En instance
Date de dépôt 2022-01-14
Date de la première publication 2024-02-29
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s) Miyatani, Yoshitaka

Abrégé

The present disclosure relates to an information processing apparatus, an information processing method, and a program enabling to achieve more suitable vibration monitoring. The present disclosure relates to an information processing apparatus, an information processing method, and a program enabling to achieve more suitable vibration monitoring. A vibration detection unit generates vibration information representing a vibration state of a subject, on the basis of event data that is output from an EVS and includes a pixel position, a time, and a polarity at which an event that is a luminance change for each pixel has occurred. The technology according to the present disclosure can be applied to, for example, a vibration monitoring system.

Classes IPC  ?

  • H04N 25/47 - Capteurs d'images avec sortie d'adresse de pixel; Capteurs d'images commandés par événement; Sélection des pixels à lire en fonction des données d'image
  • G01H 9/00 - Mesure des vibrations mécaniques ou des ondes ultrasonores, sonores ou infrasonores en utilisant des moyens sensibles aux radiations, p.ex. des moyens optiques
  • H04N 23/63 - Commande des caméras ou des modules de caméras en utilisant des viseurs électroniques
  • H04N 25/40 - Extraction de données de pixels provenant d'un capteur d'images en agissant sur les circuits de balayage, p.ex. en modifiant le nombre de pixels ayant été échantillonnés ou à échantillonner

99.

OBJECT RECOGNITION METHOD AND TIME-OF-FLIGHT OBJECT RECOGNITION CIRCUITRY

      
Numéro d'application 18272100
Statut En instance
Date de dépôt 2022-01-13
Date de la première publication 2024-02-29
Propriétaire Sony Semiconductor Solutions Corporation (Japon)
Inventeur(s)
  • Ahl, Malte
  • Dal Zot, David
  • Arora, Varun

Abrégé

The present disclosure generally pertains to an object recognition method for time-of-flight camera data, including: recognizing a real object based on a pretrained algorithm, wherein the pretrained algorithm is trained based on time-of-flight training data, wherein the time-of-flight training data are generated based on a combination of real time-of-flight data being indicative of a background, and simulated time-of-flight data generated by applying a mask on synthetic overlay image data representing a simulated object, thereby generating a masked simulated object, the mask being generated based on the synthetic overlay image data.

Classes IPC  ?

  • G06V 40/10 - Corps d’êtres humains ou d’animaux, p.ex. occupants de véhicules automobiles ou piétons; Parties du corps, p.ex. mains
  • G01S 17/894 - Imagerie 3D avec mesure simultanée du temps de vol sur une matrice 2D de pixels récepteurs, p.ex. caméras à temps de vol ou lidar flash
  • G06T 11/00 - Génération d'images bidimensionnelles [2D]
  • G06V 10/14 - Caractéristiques optiques de l’appareil qui effectue l’acquisition ou des dispositifs d’éclairage
  • G06V 10/774 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant l’intégration et la réduction de données, p.ex. analyse en composantes principales [PCA] ou analyse en composantes indépendantes [ ICA] ou cartes auto-organisatrices [SOM]; Séparation aveugle de source méthodes de Bootstrap, p.ex. "bagging” ou “boosting”
  • G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
  • G06V 40/20 - Mouvements ou comportement, p.ex. reconnaissance des gestes

100.

SURFACE EMITTING LASER, SURFACE EMITTING LASER ARRAY, AND ELECTRONIC DEVICE

      
Numéro d'application 18284361
Statut En instance
Date de dépôt 2022-02-04
Date de la première publication 2024-02-29
Propriétaire SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japon)
Inventeur(s) Tokuda, Kota

Abrégé

The present technology provides a surface emitting laser capable of stabilizing emission characteristics against change in driving temperature. The present technology provides a surface emitting laser capable of stabilizing emission characteristics against change in driving temperature. The present technology provides a surface emitting laser including: first and second multilayer film reflectors; a plurality of active regions stacked between the first and second multilayer film reflectors; and a tunnel junction disposed between at least one set of two adjacent active regions, in which the plurality of active regions includes at least two of the active regions in which peak wavelengths of emission spectra are different from each other. According to the present technology, a surface emitting laser capable of stabilizing emission characteristics against change in driving temperature is provided.

Classes IPC  ?

  • H01S 5/06 - Dispositions pour commander les paramètres de sortie du laser, p.ex. en agissant sur le milieu actif
  • G01S 7/484 - Emetteurs
  • H01S 5/183 - Lasers à émission de surface [lasers SE], p.ex. comportant à la fois des cavités horizontales et verticales comportant uniquement des cavités verticales, p.ex. lasers à émission de surface à cavité verticale [VCSEL]
  • H01S 5/30 - Structure ou forme de la région active; Matériaux pour la région active
  • H01S 5/343 - Structure ou forme de la région active; Matériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p.ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p.ex. laser AlGaAs
  • H01S 5/42 - Réseaux de lasers à émission de surface
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