A system and method are provided on one or more companion chips having a plurality of cores. Each core has core circuitry and a test interface for carrying out tests in relation to the core circuitry. The test interface has an address register to hold an address of the core and address determination circuitry. The address determination circuitry is configured to compare an address received on an address line to the address held in the address register to determine whether a core is being addressed. The address determination circuitry is also configured to direct the test interface to carry out a testing operation in response to the determination.
An optical module for use in a device comprising: an array of pixels configured to capture image data; and a memory, said memory configured to store identification information associated with said optical module, said identification information enabling retrieval of information for controlling said optical module from a source outside said device.
A sensor includes an array (100) of Single-Photon Avalanche Diodes (SPADs) (110a - HOi). Each SPAD includes an active region (130) for the detection of incident radiation and a cover. The array is divided into two or more subsets of SPADs. The SPADs in the different subsets have covers which shield part of the active region from incident radiation to different degrees.
H01L 31/107 - Dispositifs sensibles au rayonnement infrarouge, visible ou ultraviolet caractérisés par une seule barrière de potentiel ou de surface la barrière de potentiel fonctionnant en régime d'avalanche, p.ex. photodiode à avalanche
H01L 27/148 - Capteurs d'images à couplage de charge
A method for detecting multi-path interference in a spread-spectrum signal. A variation of a first signal and a variation of a second signal is compared. The variation of the first signal corresponds to a correlation of the spread-spectrum signal and a spreading code having a first offset. The variation of the second signal corresponds to a correlation of the spread-spectrum signal and the spreading code having a second offset. Multi-path interference is detected in dependence on the comparison.
An optical navigation device for use with mobile telephones and the like is disclosed, which has a reduced height as compared with current designs. The navigation device comprises a laser such as a VCSEL laser, an exposed user surface and two other surfaces that provide for total internal reflection of the incident laser beam. The surfaces are constructed with shallower than normal angles, preserving the basic functionality of the device while reducing the height.
An optical navigation device is provided for detecting movement of a pointer, such as a finger, in three dimensions. A sensor obtains images of the pointer which have been illuminated by an illumination source, and an image scaling module determines the difference in size between images acquired by the image sensor to determine the difference in height of the pointer between images.
A sensor having an array of pixels, wherein the sensor includes a global shutter and each pixel (100) includes at least two storage elements (M8, M12) adapted to independently store two or more successive frames within a predetermined time period; and wherein each storage element is adapted to be independently read out.
Disclosed is an image sensor comprising: a plurality of pixels arranged in rows and columns to form a pixel array, each pixel column comprising at least two column bitlines, such that an output of each pixel is connected to one of the column bitlines of the column of which it is comprised; a readout input circuit comprising a plurality of first inputs and a second input, each of the first inputs and the second input being connected via a capacitance to a single comparator input node; and a readout comparator circuit connected to the single comparator input node. Each of the first inputs receives, in parallel, an analogue signal, the analogue signals being acquired from the signal output of one or more of the pixels via the column bitline to which the pixel is connected, the analogue signals varying during a pixel readout period and having a first level during a first calibration period and a second level during a second read period. The analogue signals at the first inputs and a reference signal from a time varying reference circuit on the second input are constantly read onto their respective capacitances during both the first calibration period and the second read period. The readout comparator circuit compares an average of the signals on each of the plurality of first inputs to the reference signal.
H04N 5/378 - Circuits de lecture, p.ex. circuits d’échantillonnage double corrélé [CDS], amplificateurs de sortie ou convertisseurs A/N
H04N 5/363 - Traitement du bruit, p.ex. détection, correction, réduction ou élimination du bruit appliqué au bruit de réinitialisation, p.ex. bruit de type KTC
H04N 5/347 - Extraction de données de pixels provenant d'un capteur d'images en agissant sur les circuits de balayage, p.ex. en modifiant le nombre de pixels ayant été échantillonnés ou à échantillonner en combinant ou en mélangeant les pixels dans le capteur SSIS
A radiation sensor is provided comprising: first and second pixels; and a radiation absorption filter positioned over the first pixel. The combined spectral response of the absorption filter and the first pixel have a first pixel pass-band and a first pixel stop-band. The radiation sensor further comprises an interference filter positioned over both the first and second pixels. The interference filter has a first interference filter pass-band substantially within the first pixel pass-band and a second interference filter pass-band substantially within the first pixel stop-band.
G01J 1/16 - Photométrie, p.ex. posemètres photographiques par comparaison avec une lumière de référence ou avec une valeur électrique de référence en utilisant des détecteurs électriques de radiations
G01J 1/32 - Photométrie, p.ex. posemètres photographiques par comparaison avec une lumière de référence ou avec une valeur électrique de référence l'intensité de la valeur mesurée ou de référence étant modifiée jusqu' à égalisation de leurs effets au niveau du détecteur, p.ex. en faisant varier l'angle d'incidence en utilisant une variation d'intensité ou de distance de la source en utilisant des détecteurs électriques de radiations adaptés en vue d'une variation automatique de la valeur mesurée ou de référence
A single photon avalanche diode (400) is disclosed, for use in a CMOS integrated circuit, the single photon avalanche diode, SPAD, comprising: a deep n-well region (406) formed above a p-type substrate (402); an n-well region (408) formed above and in contact with the deep n-well region (406); a cathode contact (412) connected to the n-well region (408) via a heavily doped n-type implant (410); a lightly doped region (428) forming a guard ring around the n-well and deep n-well regions; a p-well region (416, 422) adjacent to the lightly doped region; and an anode contact (420, 426) connected to the p-well region via a heavily doped p-type implant (418, 424); the junction (414) between the bottom of the deep n-well region and the substrate forming a SPAD multiplication region when an appropriate bias voltage is applied between the anode and cathode and the guard ring breakdown voltage being controlled with appropriate control of the lateral doping concentration gradient such that the breakdown voltage is higher than that of the planar SPAD multiplication region.
H01L 31/107 - Dispositifs sensibles au rayonnement infrarouge, visible ou ultraviolet caractérisés par une seule barrière de potentiel ou de surface la barrière de potentiel fonctionnant en régime d'avalanche, p.ex. photodiode à avalanche
H01L 31/0232 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails - Détails Éléments ou dispositions optiques associés au dispositif
A die for use in a package is provided. The package comprises the die and at least one further die. The die has an interface configured to receive a transaction from the further die via an interconnect and to transmit a response to said transaction to said further die via the interconnect. The die also has mapping circuitry which is configured to receive at least first source identity information of the received transaction, said first source identity information being associated with a source of the transaction. The mapping circuitry is configured to modify the transaction to comprise local source identity information as source identity information for the transaction. The mapping circuitry is configured to modify said received transaction to provide said first source identity information in a further field.
A die is provided for use in a package comprising said die and at least one further die. The die comprises an interface configured to receive a transaction from the further die via an interconnect and for transmitting a response to the further die via the interconnect. The die also has mapping circuitry configured to allocate to the received transaction a local source identity information as source identity information, the local source identity information comprising one of a set of reusable local source identity information. The arrangement ensures the order of transactions tagged with a same original source identity and target and allows transactions tagged with different source identifiers to be processed out of order.
A method of converting a periodic pulse width modulated input signal into a voltage output signal wherein the input signal is in an active state for a first portion of each of successive time periods and in an inactive state for a second portion of each time period. A first and second input is supplied to an integrator circuit and a first capacitor is coupled between a first output of the integrator circuit and the first input and a second capacitor is coupled between a second output and the second input of the integrator circuit during a first time period of the pulse width modulated signal. A third capacitor is coupled between a first output of the integrator circuit and the first input and a fourth capacitor is coupled between a second output of the integrator circuit and the second input during a successive second time period of the pulse width modulated signal. Said coupled capacitors are charged during the active state of the first and second time periods and discharged during the inactive state of the first and second time periods.
H03M 1/06 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques
H03K 9/08 - Démodulation d'impulsions qui ont été modulées par un signal à variation continue d'impulsions modulées en durée ou en largeur
G06G 7/161 - Dispositions pour l'exécution d'opérations de calcul, p.ex. amplificateurs spécialement adaptés à cet effet pour la multiplication ou la division avec modulation d'impulsions, p.ex. modulation d'amplitude, de largeur, de fréquence, de phase ou de forme
14.
PIXEL DEVICE FOR BIOLOGICAL ANALYSIS, CMOS BIOSENSOR AND CORRESPONDING FABRICATION METHODS
UNIVERSITE PAUL CEZANNE AIX-MARSEILLE III (France)
Inventeur(s)
Raynor, Jeffrey
Maurin, Michaël
Perley, Mitchell, O´neal
Lenne, Pierre-François
Rigneault, Hervé
Vincentelli, Renaud
Abrégé
The invention relates to a pixel device (10) for biological analysis, comprising a photosensitive layer (20), a capture mixture (12) for capturing target proteins, arranged on an external surface of the photosensitive layer and comprising a probe protein (14) grafted to a hydrogel (16, 18), means for collecting photoelectrons in the photosensitive layer, and means for reading and processing an electrical quantity provided by the collecting means, in order to provide a value characteristic of a light intensity detected by the photosensitive layer.
B01J 19/00 - Procédés chimiques, physiques ou physico-chimiques en général; Appareils appropriés
C40B 40/10 - Bibliothèques comprenant des peptides ou des polypeptides ou leurs dérivés
C40B 50/14 - Synthèse en phase solide, c. à d. dans laquelle au moins un bloc servant à créer la bibliothèque est lié à un support solide au cours de la création de la bibliothèque; Procédés particuliers de clivage à partir du support solide
15.
METHOD FOR THE FABRICATION OF A BIOSENSOR ON A SEMICONDUCTOR SUBSTRATE
UNIVERSITÉ PAUL CÉZANNE AIX MARSEILLE III (France)
Inventeur(s)
Raynor, Jeffrey, M.
Maurin, Michaël
Perley, Mitchell, O´neal
Lenne, Pierre-François
Rigneault, Hervé
Vincentelli, Renaud
Abrégé
The invention relates to a method for the fabrication of a biosensor on a semiconductor wafer, comprising steps which comprise the forming of a central photosensitive zone (114) comprising at least one pixel device for biological analysis comprising a photosensitive layer, and a first peripheral zone (116) surrounding the central photosensitive zone, comprising electronic circuits. The first peripheral zone (116) is covered with a hydrophilic coating, and the central photosensitive zone is covered with a hydrophobic coating. A barrier of a biocompatible resin (119) is formed on the second peripheral zone (118).
B01J 19/00 - Procédés chimiques, physiques ou physico-chimiques en général; Appareils appropriés
C40B 50/14 - Synthèse en phase solide, c. à d. dans laquelle au moins un bloc servant à créer la bibliothèque est lié à un support solide au cours de la création de la bibliothèque; Procédés particuliers de clivage à partir du support solide
C40B 40/10 - Bibliothèques comprenant des peptides ou des polypeptides ou leurs dérivés
Circuitry for decoding data from a pulsed signal received on a single line, the circuitry comprising receiving means for receiving a first edge and a second edge on the single line, the first and second edges being separated by a time period, the time period representing said data; decode circuitry comprising determining means arranged to determine a value of the time period and decoding means arranged to decode said data based on said determined value of the time period; a memory arranged to store a reference value; and calibration means for calibrating said decode circuitry based on a comparison between said determined value of the time period and said reference value, wherein the determining means comprises a plurality of sampling units for sampling said pulsed signal at different times, and selection means for selecting the output of one of said sampling units to be decoded.
Apparatus for transmitting a clock and data from a first module to a second module connected by a single outward line and a single return line, comprising: means for transmitting a data pulse on the single outward line comprising means for asserting a first edge on said single outward line, said first edge representing a timing edge for the clock and means for asserting a second edge on the single outward line a selectable time period after said first edge, said selectable time period representing said data; and means for receiving a return pulse on said single return path comprising means for receiving a first edge and a second edge on the single return line, the first and second edges being separated by a first time period, said first time period representing an acknowledgement.
H04L 25/49 - Circuits d'émission; Circuits de réception à au moins trois niveaux d'amplitude
H04L 5/14 - Fonctionnement à double voie utilisant le même type de signal, c. à d. duplex
H04L 1/16 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue en utilisant un canal de retour dans lesquelles le canal de retour transporte des signaux de contrôle, p.ex. répétition de signaux de demande
H04L 1/18 - Systèmes de répétition automatique, p.ex. systèmes Van Duuren
18.
PULSED SERIAL LINK TRANSMITTING DATA AND TIMING INFORMATION ON A SINGLE LINE
A method of encoding data and timing information on a single line comprising: asserting a first edge on the single line to encode said timing information; asserting a second edge on the single line a selectable time period after said first edge, said selectable time period representing said data, characterised in that: said step of asserting said first edge comprises supplying a clock signal to a clock input of a flip-flop; and the step of asserting the second edge comprises supplying the output of the flip-flop to an input of a programmable delay line having a data input connected to receive said data and an output connected to a reset input of the flip-flop, whereby an output of the flip-flop provides said encoded data and timing information on the single line.
H04L 25/493 - Circuits d'émission; Circuits de réception à au moins trois niveaux d'amplitude par codage de transition, c. à d. par codage avant transmission de la position temporelle ou du sens de la variation de la valeur d'un signal
H04L 25/49 - Circuits d'émission; Circuits de réception à au moins trois niveaux d'amplitude
A method of delaying successive first and second input signals by first and second different selectable time periods using a programmable delay line comprising a sequence of delay elements, each introducing a delay, the method comprising the steps of: providing a control signal to each delay element, the control signal selectively being in a first logic state or a second logic state wherein in a first logic state the delay element selects an input from an adjacent delay element thereby to select the delay elements as part of a set of delay elements introducing said selectable time period and in a second logic state the delay element is not selected in the set; setting the control signals for a first number of adjacent delay elements to the first logic state to introduce the first selectable time period wherein the control signals for the delay elements in the sequence not in the first number are set to the second logic state; and setting the control signals of a second number of adjacent delay elements to the first logic state to introduce a second selectable time period, wherein the control signals for the delay elements in the sequence not in the second number are set to the second logic state; whereby the reconfiguration time between the first and second input signals is less than the maximum delay introduced by the sequence of delay elements.
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