Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Chien, Chun-Hsien
Lee, Hsin-Hung
Lai, Hsuan-Yu
Hsieh, Yu-Chung
Abrégé
An inspection system and an inspection method of a bare circuit board are provided. The inspection system is used for inspecting a bare circuit board. The bare circuit board includes a chip pad and an antenna. The inspection system includes an adapter board, a test device and a measure device. The adapter board includes a chip and a contact structure. The chip is electrically connected to the contact structure. The contact structure touches the chip pad so that the chip is electrically connected to the chip pad. The test device includes a transceiver antenna. The test device and the bare circuit board separate. The measure device is electrically connected to the chip or the transceiver antenna.
UNIMICRON TECHNOLOGY CORP. (Taïwan, Province de Chine)
Inventeur(s)
Tsai, Chen-An
Abrégé
The present invention includes an aluminum board, an electromagnet core, and a coil. The aluminum board includes a first surface, a second surface opposite to the first surface, and multiple through vias in communication with the first surface and the second surface. The electromagnet core is mounted on the first surface, and the through vias are located on two opposite sides of the electromagnet core. The coil is mounted through the through vias to wrap around the electromagnet core. An inside wall of each of the through vias forms an anodic aluminum oxide (AAO) by an anodizing process. The present invention is able to decrease via size of a conductive through via of a vertically embedded inductor. This allows through vias to be more densely formed on a board, and thus increases an amount of the coil wrapped around the electromagnetic core and increases inductance of the inductor.
H05K 1/16 - Circuits imprimés comprenant des composants électriques imprimés incorporés, p.ex. une résistance, un condensateur, une inductance imprimés
H01F 17/00 - Inductances fixes du type pour signaux
H01F 41/04 - Appareils ou procédés spécialement adaptés à la fabrication ou à l'assemblage des aimants, des inductances ou des transformateurs; Appareils ou procédés spécialement adaptés à la fabrication des matériaux caractérisés par leurs propriétés magnétiques pour la fabrication de noyaux, bobines ou aimants pour la fabrication de bobines
H05K 1/11 - Eléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Tseng, Tzyy-Jang
Ko, Cheng-Ta
Lin, Pu-Ju
Kuo, Chi-Hai
Lee, Shao-Chien
Chen, Ming-Ru
Lo, Cheng-Chung
Abrégé
A manufacturing method of a circuit board structure includes the following steps. A first sub-circuit board having an upper surface and a lower surface opposite to each other and including at least one conductive through hole is provided. A second sub-circuit board including at least one conductive through hole is provided on the upper surface of the first sub-circuit board. A third sub-circuit board including at least one conductive through hole is provided on the lower surface of the first sub-circuit board. The first sub-circuit board, the second sub-circuit board, and the third sub-circuit board are laminated so that at least two of their conductive through holes are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first sub-circuit board, the second sub-circuit board, and the third sub-circuit board are electrically connected to one another.
Asia Pacific Microsystems, Inc. (Taïwan, Province de Chine)
Inventeur(s)
Hsieh, Jer-Wei
Yin, Hung-Lin
Abrégé
A carrier board includes a substrate having a first substrate surface, a second substrate surface, and a substrate hole that penetrates the first substrate surface and the second substrate surface; a magnet sheath disposed in the substrate hole to cover a hole boundary of the substrate hole, and including a first magnetic surface, a second magnetic surface, and an inner periphery that interconnects the first magnetic surface and the second magnetic surface; a first dielectric isolation layer and a second dielectric isolation layer respectively having outer surfaces facing away from the substrate; and a conductive metal layer covering the inner periphery of the magnet sheath and extending to overlie the outer surfaces of the first dielectric isolation layer and the second dielectric isolation layer.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lu, Chih-Chiang
Liu, Hsin-Ning
Huang, Jun-Rui
Wang, Pei-Wei
Chen, Ching Sheng
Cheng, Shih-Lian
Abrégé
A manufacturing method of the circuit board includes the following steps. A metal layer, a first substrate, a second substrate, and a third substrate are laminated. Multiple blind holes and a through hole are formed. A conductive material layer is formed, which covers the metal layer, the conductive layer of the third substrate, and an inner wall of the through hole, and fills the blind holes to define multiple conductive holes. The conductive material layer, the metal layer, and the conductive layer are patterned to form a first external circuit layer located on the first substrate and electrically connected to the conductive pillars, and a second external circuit layer located on the insulating layer and electrically connected to the conductive holes, and define a conductive through hole structure connecting the first external circuit layer and the second external circuit layer and located in the through hole.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lau, John Hon-Shing
Lin, Pu-Ju
Yang, Kai-Ming
Lin, Chen-Hao
Ko, Cheng-Ta
Tseng, Tzyy-Jang
Abrégé
Disclosed is a package structure including a circuit board, a co-packaged optics (CPO) substrate, an application specific integrated circuit (ASIC) assembly, a glass interposer, an electronic integrated circuit (EIC) assembly, a photonic integrated circuit (PIC) assembly, and an optical fiber assembly. The CPO substrate is configured on the circuit board, and the ASIC assembly is configured on the CPO substrate. The glass interposer is configured on the CPO substrate and includes an upper surface, a lower surface, a cavity, and at least one through glass via (TGV). The EIC assembly is configured on the upper surface of the glass interposer and electrically connected to the glass interposer. The PIC assembly is configured in the cavity of the glass interposer and electrically connected to the glass interposer. The optical fiber assembly is configured on the lower surface of the glass interposer and optically connected to the PIC assembly.
G02B 6/42 - Couplage de guides de lumière avec des éléments opto-électroniques
G02B 6/12 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES - Détails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p.ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
7.
CIRCUIT BOARD STRUCTURE AND MANUFACTURING METHOD THEREOF
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Yang, Kai-Ming
Lin, Chen-Hao
Wang, Chin-Sheng
Ko, Cheng-Ta
Lin, Pu-Ju
Abrégé
The invention provides a circuit board structure and a manufacturing method thereof. The circuit board structure includes a line portion, a first insulating layer, and a conductive terminal. The first insulating layer is disposed on the line portion. The conductive terminal is disposed on the first insulating layer and embedded in the first insulating layer to be electrically connected with the line portion. The conductive terminal includes a first portion, a second portion, and a third portion. The first portion protrudes from a surface of the first insulating layer. The second portion is embedded in the first insulating layer and connected to the first portion. The third portion is disposed between the line portion and the second portion. A width of the second portion is greater than a width of the third portion.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lin, Ping-Tsung
Yang, Kai-Ming
Peng, Chia-Yu
Lin, Pu-Ju
Ko, Cheng-Ta
Abrégé
A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a plurality of pads, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A plurality of first openings of the first dielectric layer expose part of the pads, and a first surface of the first dielectric layer is higher upper surfaces of the pads. The solder balls are disposed in a plurality of third openings of the third dielectric layer and are electrically connected to the second metal layer and the carrier. The surface treatment layer is disposed on the upper surfaces, and a top surface of the surface treatment layer is higher than the first surface.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Yang, Kai-Ming
Peng, Chia-Yu
Ko, Cheng-Ta
Lin, Pu-Ju
Abrégé
A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a first dielectric layer, pads, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A top surface of the first dielectric layer is higher than an upper surface of each pad. The first metal layer is disposed on a first surface of the first dielectric layer. The second dielectric layer has second openings exposing part of the first metal layer. The second metal layer extends into the second openings and is electrically connected to the first metal layer. The third dielectric layer has third openings exposing part of the second metal layer. The surface treatment layer is disposed on the upper surfaces.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lau, John Hon-Shing
Tseng, Tzyy-Jang
Abrégé
A chip package structure includes a package carrier, a plurality of chips, a bridge and a plurality of solder balls or C4 bumps. The package carrier includes a plurality of carrier pads. The chips are arranged side by side on the package carrier. Each of the chips includes a plurality of first pads and a plurality of second pads. The bridge is located between the chips and the package carrier and includes a plurality of bridge pads. Each of the first pads is hybrid bonded with each of the bridge pads to form a hybrid bonding pad, so that the chips are electrically connected to each other through the bridge. The solder balls are located between the package carrier and the chips. The second pads of each of the chips are electrically connected to the carrier pads of the package carrier through the solder balls.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
11.
CIRCUIT BOARD STRUCTURE AND MANUFACTURING METHOD THEREOF
UNIMICRON TECHNOLOGY CORP. (Taïwan, Province de Chine)
Inventeur(s)
Kuo, Chun Hung
Abrégé
A circuit board structure includes a build-up structure, a graphene layer disposed on the build-up structure, and at least one conductive pillar disposed on the graphene layer, the graphene layer includes an oxidized area not covered by the at least one conductive pillar and a non-oxidized area covered by the at least one conductive pillar, and the at least one conductive pillar is electrically connected to the build-up structure via the non-oxidized area.
UNIMICRON TECHNOLOGY CORP. (Taïwan, Province de Chine)
Inventeur(s)
Chen, Yi Ling
Ho, Wei Tse
Wang, Chin-Sheng
Lin, Pu-Ju
Ko, Cheng-Ta
Abrégé
An anti-diffusion substrate structure includes a substrate, a substrate circuit layer, and a chip. The substrate has multiple through holes. Within each of the through holes includes a first metal layer and an anti-diffusion layer plated on the first metal layer. The anti-diffusion layer is an Electroless Palladium Immersion Gold (EPIG) layer or an Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) layer. The substrate circuit layer is mounted on the substrate and extended on the anti-diffusion layer within each of the through holes. The substrate circuit layer is made of a second metal layer, and a composition of the second metal layer is different from a composition of the first metal layer. The chip is electrically connected to the substrate circuit layer. The anti-diffusion layer is able to better prevent material of the first metal layer from migrating or diffusing to the second metal layer.
C23C 18/16 - Revêtement chimique par décomposition soit de composés liquides, soit de solutions des composés constituant le revêtement, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement; Dépôt par contact par réduction ou par substitution, p.ex. dépôt sans courant électrique
C23C 18/32 - Revêtement avec l'un des métaux fer, cobalt ou nickel; Revêtement avec des mélanges de phosphore ou de bore et de l'un de ces métaux
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
13.
VAPOR CHAMBER STRUCTURE AND MANUFACTURING METHOD THEREOF
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Wang, Chin-Sheng
Tain, Ra-Min
Abrégé
A vapor chamber structure includes a first flexible substrate, a second flexible substrate, a spacer, a flexible sealing member, and a working fluid. The first flexible substrate includes a first organic material layer, a first copper foil layer, and a first capillary structure layer. The second flexible substrate includes a second organic material layer, a second copper foil layer, and a second capillary structure layer. The first copper foil layer, the first capillary structure layer, the spacer, the second copper foil layer, and the second capillary structure layer are retracted by a distance relative to the first and second organic material layers to form a space. The first and second organic material layers and the flexible sealing member define a sealed chamber. The working fluid is disposed in the sealed chamber and located among the first and second capillary structure layers and grooves of the spacer.
F28D 15/04 - Appareils échangeurs de chaleur dans lesquels l'agent intermédiaire de transfert de chaleur en tubes fermés passe dans ou à travers les parois des canalisations dans lesquels l'agent se condense et s'évapore, p.ex. tubes caloporteurs avec des tubes ayant une structure capillaire
F28D 15/02 - Appareils échangeurs de chaleur dans lesquels l'agent intermédiaire de transfert de chaleur en tubes fermés passe dans ou à travers les parois des canalisations dans lesquels l'agent se condense et s'évapore, p.ex. tubes caloporteurs
UNIMICRON TECHNOLOGY CORP. (Taïwan, Province de Chine)
National Taiwan University (Taïwan, Province de Chine)
Inventeur(s)
Wang, Chin-Hsun
Wu, Ruey-Beei
Chen, Ching-Sheng
Hung, Chun-Jui
Liao, Wei-Yu
Chang, Chi-Min
Abrégé
A transmission device for suppressing the glass-fiber effect includes a circuit board and a transmission line. The circuit board includes a plurality of glass fibers, so as to define a fiber pitch. The transmission line is disposed on the circuit board. The transmission line includes a plurality of non-parallel segments. Each of the non-parallel segments of the transmission line has an offset distance with respect to a reference line. The offset distance is longer than or equal to a half of the fiber pitch.
UNIMICRON TECHNOLOGY CORP. (Taïwan, Province de Chine)
National Taiwan University (Taïwan, Province de Chine)
Inventeur(s)
Wang, Yu-Kuang
Wu, Ruey-Beei
Chen, Ching-Sheng
Huang, Chun-Jui
Liao, Wei-Yu
Chang, Chi-Min
Abrégé
A transmission device includes a daisy chain structure composed of at least three daisy chain units arranged periodically and continuously. Each of the daisy chain units includes first, second and third conductive lines, and first and second conductive pillars. The first and second conductive lines at a first layer extend along a first direction and are discontinuously arranged. The third conductive line at a second layer extends along the first direction and is substantially parallel to the first and second conductive lines. The first conductive pillar extends in a second direction. The second direction is different from the first direction. A first part of the first conductive pillar is connected to the first and third conductive lines. The second conductive pillar extends in the second direction. A first part of the second conductive pillar is connected to the second and third conductive lines.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Chen, Jyun-Hong
Kuo, Chi-Hai
Lin, Pu-Ju
Ko, Cheng-Ta
Abrégé
A package structure includes a first substrate, a second substrate disposed on the first substrate, a third substrate disposed on the second substrate, and multiple chips mounted on the third substrate. A second coefficient of thermal expansion (CTE) of the second substrate is less than a first CTE of the first substrate. The third substrate includes a first sub-substrate, a second sub-substrate in the same level with the first sub-substrate, a third sub-substrate in the same level with the first sub-substrate. A CTE of the first sub-substrate, a CTE of the second sub-substrate, and a CTE of the third sub-substrate are less than the second CTE of the second substrate.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/13 - Supports, p.ex. substrats isolants non amovibles caractérisés par leur forme
H01L 23/14 - Supports, p.ex. substrats isolants non amovibles caractérisés par le matériau ou par ses propriétés électriques
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/10 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs ayant des conteneurs séparés
17.
CIRCUIT BOARD WITH LOW GRAIN BOUNDARY DENSITY AND FORMING METHOD THEREOF
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Chen, Chien Jung
Liang, Jia Hao
Lin, Ching Ku
Abrégé
The present disclosure provides a circuit board including a first circuit layer, a dielectric layer on the first circuit layer, and a seed layer on the dielectric layer and directly contacting the first circuit layer, in which a top surface of the seed layer includes a levelled portion. The circuit board also includes a second circuit layer on the levelled portion of the seed layer, in which a grain boundary density of the second circuit layer is lower than that of a portion of the seed layer directly contacting the first circuit layer.
UNIMICRON TECHNOLOGY CORP. (Taïwan, Province de Chine)
Inventeur(s)
Wu, Ming-Hao
Wang, Chia-Ching
Abrégé
A circuit board structure is provided. The circuit board structure includes a via hole, a conductive layer, and an alternate stacking of a plurality of circuit layers and a plurality of insulating layers. The via hole penetrates through the plurality of circuit layers and the plurality of insulating layers. The lateral ends of the plurality of insulating layers form the sidewall of the via hole. The conductive layer is conformally disposed within the via hole. The conductive layer exposes the first region of the sidewall and covers the second region of the sidewall. The sidewall extends in the longitudinal direction of the via hole and has no misalignments in the radial direction.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Chen, Yu-Shen
Tsai, I-Ta
Abrégé
The present disclosure provides a circuit board with an embedded chip, which includes a dielectric layer, a first circuit layer, a chip, a conductive connector, and an insulating protection layer. The first circuit layer includes at least one first trace in the dielectric layer. The chip is in the dielectric layer and adjacent to the first trace, where the chip includes a plurality of chip pads at an upper surface of the chip. The conductive connector is on the upper surface of the chip and on the first circuit layer, where a lower surface of the conductive connector contacts at least one chip pad of the chip pads and an upper surface of the first trace. The insulating protection layer is on the chip, the first circuit layer, and the conductive connector, where the insulating protection layer contacts the upper surface of the chip.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
20.
CIRCUIT BOARD ASSEMBLY AND MANUFACTURING METHOD THEREOF
UNIMICRON TECHNOLOGY CORP. (Taïwan, Province de Chine)
Inventeur(s)
Chen, Yu-Shen
Abrégé
This disclosure provides a circuit board assembly and a manufacturing method thereof. The circuit board assembly includes circuit board, embedded chip, heat dissipation assembly and temperature switch structure. The temperature switch structure includes a first metal layer and a second metal layer stacked on each other. The first metal layer of the temperature switch structure is electrically connected to the circuit board and is thermally coupled to the embedded chip. A thermal expansion coefficient of the first metal layer is different from a thermal expansion coefficient of the second metal layer so that the temperature switch structure is deformed in response to a temperature change of the embedded chip to be in contact with or spaced apart from the second electrically conductive contact of the heat dissipation assembly.
H05K 1/16 - Circuits imprimés comprenant des composants électriques imprimés incorporés, p.ex. une résistance, un condensateur, une inductance imprimés
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01H 37/52 - Interrupteurs actionnés thermiquement - Détails Éléments thermosensibles actionnés par la déviation d'un bilame
UNIMICRON TECHNOLOGY CORP. (Taïwan, Province de Chine)
Inventeur(s)
Lee, Shao-Chien
Chen, Ching-Sheng
Nien, Heng-Ming
Wang, Pei-Wei
Abrégé
A manufacturing method for circuit board structure includes steps of providing a carrier, forming a first build-up layer including a plurality of first circuits, forming a second build-up layer including a plurality of second circuits on a side of the first build-up layer located away from the carrier, attaching a side of the second build-up layer located away from the first build-up layer to a core layer, and removing the carrier from the first build-up layer, where the first circuits are finer than the second circuits.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Yang, Kai-Ming
Peng, Chia-Yu
Lau, John Hon-Shing
Abrégé
An integrated circuit (IC) package structure includes a chip, a redistribution layer (RDL) structure, a molding compound structure and an electromagnetic interference (EMI) shielding structure. The RDL structure is formed on the chip and electrically connected thereto. The molding compound layer is provided on outer surfaces of the chip and the RDL structure. The EMI shielding structure is provided on outer surfaces of the molding compound structure. The molding compound structure layer provided on outer surfaces of the chip and the RDL structure provide protection and reinforcement to multiple faces of the IC package structure; and the EMI shielding structure provided on outer surfaces of the molding compound structure provides EMI protection to multiple faces of the chip and the RDL structure.
H01L 23/552 - Protection contre les radiations, p.ex. la lumière
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
23.
MULTI-LAYERED RESONATOR CIRCUIT STRUCTURE AND MULTI-LAYERED FILTER CIRCUIT STRUCTURE
UNIMICRON TECHNOLOGY CORP. (Taïwan, Province de Chine)
TUNGHAI UNIVERSITY (Taïwan, Province de Chine)
Inventeur(s)
Chen, Chi-Feng
Yen, Po-Sheng
Wu, Ruey-Beei
Tain, Ra-Min
Wang, Chin-Sheng
Chen, Jun-Ho
Abrégé
A multi-layered resonator circuit structure and a multi-layered filter circuit structure. The multi-layered resonator circuit structure includes a multi-layered substrate, a plurality of resonators and a plurality of conductive components. The multi-layered substrate has a top surface, a bottom surface, and a ground layer. The top surface and the bottom surface face away from each other. The ground layer is located between the top surface and the bottom surface. A part of the plurality of resonators is/are disposed on the top surface. Another part of the plurality of resonators is/are disposed on the bottom surface. The plurality of conductive components is located in the multi-layered substrate. The plurality of resonators is electrically connected to the ground layer, respectively, via the plurality of conductive components.
Unimicron Technology Corporation (Taïwan, Province de Chine)
Inventeur(s)
Hsieh, Ching-Ho
Wu, Ming-Hsing
Wu, Kuei-Sheng
Abrégé
A circuit board assembly is provided and includes a first circuit board, a second circuit board and a first connecting module. The first connecting module includes a first connecting wire, a first connector and a second connector. The first circuit board includes a first processor, and the second circuit board includes a second processor. One end of the first connector is connected to one end of the first connecting wire, and the other end of the first connector is connected to the first circuit board. One end of the second connector is connected to the other end of the first connecting wire, and the other end of the second connector is connected to the second circuit board. The first connector is adjacent to the first processor, and the second connector is adjacent to the second processor.
H05K 1/14 - Association structurale de plusieurs circuits imprimés
H01R 12/79 - Dispositifs de couplage pour circuits imprimés flexibles, câbles plats ou à rubans ou structures similaires se raccordant à des circuits imprimés rigides ou à des structures similaires
Unimicron Technology Corporation (Taïwan, Province de Chine)
Inventeur(s)
Wang, Po-Hsiang
Wu, Ming-Hao
Abrégé
The present disclosure provides a printed circuit board and a method thereof. The printed circuit board has a first substrate, at least one first trace layer and at least one second trace layer. The first substrate has a first surface and a second surface. The first surface and the second surface are corresponding to each other along an axis. The first trace layer is formed on the first surface and/or the second surface of the first substrate. The first trace layer has at least one first trace and at least one first gap beside the first trace by etching. The second trace layer is formed on the first trace layer. The second trace layer has at least one second trace and at least one second gap beside the second trace by etching.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lau, John Hon-Shing
Tseng, Tzyy-Jang
Abrégé
A package structure includes a circuit board, a package substrate, a fine metal L/S RDL-substrate, an electronic assembly, a photonic assembly, a heat dissipation assembly, and an optical fiber assembly. The package substrate is disposed on and electrically connected to the circuit board. The fine metal L/S RDL-substrate is disposed on and electrically connected to the package substrate. The electronic assembly includes an application specific integrated circuit (ASIC) assembly, an electronic integrated circuit (EIC) assembly, and a photonic integrated circuit (PIC) assembly which are respectively disposed on the fine metal L/S RDL-substrate and electrically connected to the package substrate by the fine metal L/S RDL-substrate. The heat dissipation assembly is disposed on the electronic assembly. The optical fiber assembly is disposed on the package substrate and electrically connected to the package substrate and the PIC assembly. A packaging method of the VCSEL array chip is presented.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lau, John Hon-Shing
Tseng, Tzyy-Jang
Abrégé
A package structure includes a circuit board, a package substrate, an electronic/photonic assembly, a film redistribution layer, a heat dissipation assembly, and an optical fiber assembly. The package substrate is disposed on the circuit board and electrically connected to the circuit board. The electronic/photonic assembly includes an ASIC assembly, an EIC assembly, and a PIC assembly. The EIC assembly and the PIC assembly are stacked and disposed on the package substrate and electrically connected to the package substrate via the film redistribution layer. An orthographic projection of the EIC assembly on the film redistribution layer is overlapped with an orthographic projection of the PIC assembly on the film redistribution layer. The heat dissipation assembly is disposed on the electronic/photonic assembly. The optical fiber assembly is disposed on the package substrate and optically connected to the PIC assembly.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des groupes principaux , ou dans une seule sous-classe de , , p.ex. circuit hybrides
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p.ex. dissipateurs de chaleur
H01L 23/38 - Dispositifs de refroidissement utilisant l'effet Peltier
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
G02B 6/42 - Couplage de guides de lumière avec des éléments opto-électroniques
28.
PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Chen, Ying-Chu
Li, Jeng-Ting
Kuo, Chi-Hai
Ko, Cheng-Ta
Lin, Pu-Ju
Abrégé
A manufacturing method of a package structure includes: forming a redistribution layer on a top surface of a glass substrate; forming a protective layer on the top surface of the glass substrate; cutting the glass substrate and the protective layer such that the glass substrate has a cutting edge, in which a crack is formed in the cutting edge of the glass substrate; and heating the protective layer such that a portion of the protective layer flows towards a bottom surface of the glass substrate to cover the cutting edge of the glass substrate and fill the crack in the cutting edge of the glass substrate.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/29 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par le matériau
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lu, Chih-Chiang
Nien, Heng-Ming
Chen, Ching-Sheng
Chang, Ching
Chang, Ming-Ting
Chang, Chi-Min
Lee, Shao-Chien
Huang, Jun-Rui
Cheng, Shih-Lian
Abrégé
Provided is a manufacturing method of circuit board, including a first substrate, a second substrate, a third substrate, a fourth substrate, multiple conductive structures, and a conductive via structure. The third substrate has an opening and includes a first dielectric layer. The opening penetrates the third substrate, and the first dielectric layer fills the opening. Multiple conductive structures are formed so that the first substrate, the second substrate, the third substrate, and the fourth substrate are electrically connected through the conductive structures to define a ground path. A conductive via structure is formed to penetrate the first substrate, the second substrate, the first dielectric layer of the third substrate, and the fourth substrate. The conductive via structure is electrically connected to the first substrate and the fourth substrate to define a signal path, and the ground path surrounds the signal path.
H05K 1/11 - Eléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
H05K 1/16 - Circuits imprimés comprenant des composants électriques imprimés incorporés, p.ex. une résistance, un condensateur, une inductance imprimés
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Kuo, Chun-Hung
Abrégé
A method for manufacturing a circuit board includes providing a composite material film including a metal film and a polymeric film, disposing a dielectric layer on the polymeric film to form a stacked structure, forming a circuit layer with a contact pad on a substrate, bonding the stacked structure onto the substrate and the circuit layer, and forming a first opening extending through the metal film to form a patterned metal film. The dielectric layer directly contacts the substrate and entirely covers the circuit layer. The method further includes plasma etching the dielectric layer with the patterned metal film as a mask to form a second opening in the dielectric layer and expose the contact pad in the second opening, removing the composite material film, and depositing a conductive material in the second opening to form a conductive blind hole electrically connected to the contact pad.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Wang, Chin-Sheng
Tain, Ra-Min
Chan, Chih-Kai
Chen, Jun-Ho
Abrégé
An electronic packaging structure including a first circuit structure, a second circuit structure and at least one electronic device is provided. The bottom side of the first circuit structure has at least one cavity. The first circuit structure is disposed on the second circuit structure. The first circuit structure and the second circuit structure are electrically connected to each other. The electronic device is disposed on the second circuit structure. The electronic device is disposed corresponding to the cavity of the first circuit structure.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Wang, Chin-Sheng
Tain, Ra-Min
Chan, Chih-Kai
Abrégé
An electronic packaging structure including a first circuit structure, a second circuit structure and at least one electronic device is provided. The first circuit structure includes a bottom conductive plate having at least one cavity. The first circuit structure is disposed on the second circuit structure. The first circuit structure and the second circuit structure are electrically connected to each other. The electronic device is disposed on the second circuit structure. The electronic device is disposed corresponding to the cavity of the first circuit structure.
H01L 21/52 - Montage des corps semi-conducteurs dans les conteneurs
H01Q 1/22 - Supports; Moyens de montage par association structurale avec d'autres équipements ou objets
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
UNIMICRON TECHNOLOGY CORP. (Taïwan, Province de Chine)
Inventeur(s)
Wang, Chin-Sheng
Peng, Chia-Yu
Yang, Kai-Ming
Lin, Pu-Ju
Ko, Cheng-Ta
Abrégé
The present invention provides an etching device which comprises an oxygen supplier, so that the etching device of the present invention can etch copper gently by means of the dissolved oxygen in the etching solution to accurately control the etching degree so as to fulfill the stricter requirements of microcircuit manufacturing. The present invention further provides an etching method. Finally, the etching waste solution of the present invention can be recycled to further ameliorate the environmental pollution and reduce the production cost, so the present invention is widely applicable in integrated circuit packaging.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Kuo, Chun-Hung
Abrégé
The present disclosure provides a circuit board and its manufacturing method. The circuit board includes a first circuit layer, a first conductive post, and a second circuit layer. The first circuit layer includes a first pad and a first seed layer covering a sidewall of the first pad. The first conductive post is on the first pad and directly connected to the first pad. The second circuit layer includes a second pad and a second seed layer covering a sidewall of the second pad. The second pad is on a first connecting end of the first conductive post. The first connecting end is embedded in the second pad, and the second pad is connected to and directly contacts the first connecting end. The first seed layer and the second seed layer do not extend on a sidewall of the first conductive post.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Kuo, Chun-Hung
Wang, Tzu-Hsuan
Abrégé
An electronic device including a light-emitting element, an IC chip, a substrate, an optical waveguide layer, and an optical signal outlet is provided. The IC chip is configured to control the light-emitting element to emit an optical signal. The light-emitting element is disposed on a first surface of the substrate, and the IC chip is disposed on a second surface of the substrate. The optical waveguide layer is disposed on the first surface of the substrate, and the optical waveguide layer includes a core layer, a cladding layer, and a metal layer. The metal layer is disposed on at least a portion of an interface between the core layer and the cladding layer. The optical signal outlet corresponds to the light-emitting element, and the optical signal reaches the optical signal outlet after being transmitted in the core layer.
G02B 6/42 - Couplage de guides de lumière avec des éléments opto-électroniques
G02B 6/43 - Dispositions comprenant une série d'éléments opto-électroniques et d'interconnexions optiques associées
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des groupes principaux , ou dans une seule sous-classe de , , p.ex. circuit hybrides
H04B 10/80 - Aspects optiques concernant l’utilisation de la transmission optique pour des applications spécifiques non prévues dans les groupes , p.ex. alimentation par faisceau optique ou transmission optique dans l’eau
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Hsieh, Ching-Ho
Wu, Ming-Hsing
Wu, Keui-Sheng
Abrégé
A connector includes a substrate, a coverlay and a spring contact. The substrate has a first surface, a second surface opposite to the first surface and a conductive through hole extending between the first and second surfaces. The coverlay is disposed on the first surface and includes a first opening. The spring contact includes an anchor member, a rising member and a pin. The anchor member is disposed between the substrate and the coverlay. The rising member extends from the anchor member and through the first opening in a direction away from the substrate. A first portion of the rising member is in the first opening, and a second portion of the rising member is out of the first opening. The pin extends from the anchor member to an inside of the conductive through hole, and is electrically connected to the conductive through hole.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lin, Ai Jing
Lan, Chung-Yu
Liang, Jia Hao
Abrégé
A circuit board includes a conductive metal layer, at least one insulating layer, at least one thermally conductive insulating layer and a heat dissipation element. The conductive metal layer is mainly used to transmit electronic signals. The insulating layer is connected to the conductive metal layer. The thermally conductive insulating layer is sandwiched between the conductive metal layer and the insulating layer, and thermally contacts the conductive metal layer, and is used for thermally conducting the heat of the conductive metal layer. The heat dissipation element is in thermal contact with the thermally conductive insulating layer, and is used to conduct the heat of the thermally conductive insulating layer to the outside through a heat dissipation channel.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Kuo, Chun-Hung
Abrégé
An electronic circuit assembly includes an interposer substrate, a wiring substrate, an electrical connective part and an electronic component. The interposer substrate with a first coefficient of thermal expansion (CTE) includes a first surface, a second surface opposite to the first surface, and a first side surface connecting to the first surface and the second surface. The wiring substrate with a second CTE is disposed below the second surface. The first CTE is lower than the second CTE. The electrical connective part is disposed in the interposer substrate and extends to the first side surface. The electronic component is attached to the first side surface and is electrically connected to the electrical connective part.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Wang, Chin-Sheng
Tain, Ra-Min
Lin, Wen-Yu
Wang, Tse-Wei
Chen, Jun-Ho
Ma, Guang-Hwa
Abrégé
An electronic package structure and manufacturing method thereof. The electronic package structure includes a circuit board, an interposer, a chip, a circuit structure, and a coaxial conductive element. The interposer is disposed on the circuit board. The interposer has a through groove. The chip is disposed in the through groove and located on the circuit board to electrically connect with the circuit board. The circuit structure is disposed on the interposer. The coaxial conductive element penetrates the interposer to electrically connect the circuit structure and the circuit board. The coaxial conductive element includes a first conductive structure, a second conductive structure, and a first insulating structure. The second conductive structure surrounds the first conductive structure. The first insulating structure is disposed between the first conductive structure and the second conductive structure.
H01L 23/13 - Supports, p.ex. substrats isolants non amovibles caractérisés par leur forme
H01L 23/552 - Protection contre les radiations, p.ex. la lumière
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H05K 1/14 - Association structurale de plusieurs circuits imprimés
H05K 1/11 - Eléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
40.
ELECTRONIC PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Wang, Chin-Sheng
Tain, Ra-Min
Lin, Wen-Yu
Wang, Tse-Wei
Chen, Jun-Ho
Ma, Guang-Hwa
Abrégé
An electronic package structure and its manufacturing method are provided. The electronic package structure includes an interposer, a circuit board, a chip, and a circuit structure. The interposer includes an interposer substrate and a coaxial conductive element located in the interposer substrate. The interposer substrate includes a cavity. The coaxial conductive element includes a first conductive structure, a second conductive structure surrounding the first conductive structure, and a first insulation structure. The first insulation structure is disposed between the first and second conductive structures. The circuit board is disposed on a lower surface of the interposer substrate and electrically connected to the coaxial conductive element. The chip is disposed in the cavity and located on the circuit board, so as to be electrically connected to the circuit board. The circuit structure is disposed on an upper surface of the interposer substrate and electrically connected to the coaxial conductive element.
H01Q 1/38 - Forme structurale pour éléments rayonnants, p.ex. cône, spirale, parapluie formés par une couche conductrice sur un support isolant
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lu, Chih-Chiang
Huang, Jun-Rui
Wu, Ming-Hao
Lin, Tung-Chang
Abrégé
Provided is a circuit board structure including a substrate, a loop-wrapping ground layer, an insulating structure, a first build-up layer, a top wiring layer, a bottom wiring layer, a first conductive via, and a plurality of second conductive vias. The aforementioned structure defines a signal transmitting structure. An equivalent circuit of the signal transmitting structure at least includes a first equivalent circuit, a second equivalent circuit, a third equivalent circuit and a fourth equivalent circuit, which correspond to different uniform transmitting sections respectively. The first equivalent circuit, the second equivalent circuit, the third equivalent circuit and the fourth equivalent circuit are connected in series with each other according to an ABCD transmission matrix series connection principle.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lu, Chih-Chiang
Chang, Chi-Min
Wu, Ming-Hao
Lin, Yi-Pin
Lin, Tung-Chang
Huang, Jun-Rui
Abrégé
A circuit board structure includes a substrate, a first build-up structure layer, first and second external circuit layers, at least one first conductive via, and second conductive vias. The first build-up structure layer is disposed on a first circuit layer of the substrate. The first external circuit layer is disposed on the first build-up structure layer. The second external circuit layer is disposed on a second circuit layer and a portion of a third dielectric layer of the substrate. The first conductive via is electrically connected to the first external circuit layer and the second external circuit layer to define a signal path. The second conductive vias surround the first conductive via, and the first external circuit layer, the second conductive vias, the first circuit layer, the outer conductive layer, and the second external circuit layer define a first ground path. The first ground path surrounds the signal path.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Chien, Chun-Hsien
Lee, Hsin-Hung
Lai, Hsuan-Yu
Hsieh, Yu-Chung
Yu, Hung-Pin
Abrégé
A bare circuit board is provided, in which the bare circuit board includes a substrate, an antenna, a chip pad, a ground pattern and a trace. The substrate includes a surface. The antenna and the chip pad are formed on the substrate. The ground pattern is formed on the surface. The trace is formed on the surface and isn’t connected to the ground pattern. A measuring gap is formed between the trace and an edge of the ground pattern, and the trace includes a first end and a second end. The first end is electrically connected to the chip pad, whereas the second end is electrically connected to the antenna. The bare circuit board is adapted to transmit a signal. The width of the measuring gap is smaller than a quarter of an equivalent wavelength of the signal.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lu, Chih-Chiang
Huang, Jun-Rui
Wu, Ming-Hao
Lin, Yi-Pin
Lin, Tung-Chang
Abrégé
A circuit board, including a first dielectric material, a second dielectric material, a third dielectric material, a fourth dielectric material, a first external circuit layer, a second external circuit layer, a conductive structure, a first conductive via, and multiple second conductive vias, is provided. The first conductive via at least passes through the first dielectric material and the fourth dielectric material, and is electrically connected to the first external circuit layer and the second external circuit layer to define a signal path. The second conductive vias pass through the first dielectric material, the second dielectric material, the third dielectric material, and a part of the conductive structure, and surround the first conductive via. The second conductive vias are electrically connected to the first external circuit layer, the conductive structure, and the second external circuit layer to define a ground path, and the ground path surrounds the signal path.
UNIMICRON TECHNOLOGY CORP. (Taïwan, Province de Chine)
Inventeur(s)
Wang, Tzu Hsuan
Lin, Yu Cheng
Abrégé
A method of a circuit signal enhancement of a circuit board comprises the following steps: forming a first substrate body with a first signal transmission circuit layer and a second substrate body with a second signal transmission circuit layer; forming a first signal enhancement circuit layer and a second signal enhancement circuit layer on the first substrate body and the second substrate body; forming a third substrate body with a third signal transmission circuit layer and a fourth substrate body with a fourth signal transmission circuit layer on the carrier; separating the third substrate body and the fourth substrate body from the carrier; combining the first signal transmission circuit layer and the third signal transmission circuit layer through the first signal enhancement circuit layer; and combining the second signal transmission circuit layer and the fourth signal transmission circuit layer through the second signal enhancement circuit layer.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lin, Wen-Yu
Yang, Kai-Ming
Lin, Chen-Hao
Lin, Pu-Ju
Ko, Cheng-Ta
Wang, Chin-Sheng
Ma, Guang-Hwa
Tseng, Tzyy-Jang
Abrégé
A circuit board structure includes a circuit substrate having opposing first and second sides, a redistribution structure disposed at the first side, and a dielectric structure disposed at the second side. The circuit substrate includes a first circuit layer disposed at the first side and a second circuit layer disposed at the second side. The redistribution structure is electrically coupled to the circuit substrate and includes a first leveling dielectric layer covering the first circuit layer, a first thin-film dielectric layer disposed on the first leveling dielectric layer and having a material different from the first leveling dielectric layer, and a first redistributive layer disposed on the first thin-film dielectric layer and penetrating through the first thin-film dielectric layer and the first leveling dielectric layer to be in contact with the first circuit layer. The dielectric structure includes a second leveling dielectric layer disposed below the second circuit layer.
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/488 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes formées de structures soudées
H01L 23/544 - Marques appliquées sur le dispositif semi-conducteur, p.ex. marques de repérage, schémas de test
H05K 1/11 - Eléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Wu, Ming-Hao
Cheng, Shih-Lian
Abrégé
A printed circuit board stack structure includes a first printed circuit board, a second printed circuit board, and a filling glue layer. The first printed circuit board has at least one overflow groove, and includes first pads and a retaining wall surrounding the first pads. The second printed circuit board is disposed on the first printed circuit board, and includes second pads and conductive pillars located on some of the second pads. The conductive pillars are respectively connected to some of the first pads to electrically connect the second printed circuit board to the first printed circuit board. The filling glue layer fills between the first and the second printed circuit boards, and covers the first pads, the second pads, and the conductive pillars. The retaining wall blocks the filling glue layer so that a portion of the filling glue layer is accommodated in the overflow groove.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Tseng, Hao-Wei
Kuo, Chi-Hai
Li, Jeng-Ting
Chen, Ying-Chu
Lin, Pu-Ju
Ko, Cheng-Ta
Abrégé
A package structure includes a substrate, a plurality of conductive pads, a light-emitting diode, a photo imageable dielectric material, and a black matrix. The substrate includes a top surface. The conductive pads are located on the top surface of the substrate. The light-emitting diode is located on the conductive pads. The photo imageable dielectric material is located between the light-emitting diode and the top surface of the substrate and between the conductive pads. An orthogonal projection of the light-emitting diode on the substrate is overlapped with an orthogonal projection of the photo imageable dielectric material on the substrate. The black matrix is located on the top surface of the substrate and the conductive pads.
H01L 33/54 - Encapsulations ayant une forme particulière
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/075 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
49.
Circuit board structure and manufacturing method thereof
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Fan, Kuang-Ching
Hsieh, Chih-Peng
Wang, Cheng-Hsiung
Abrégé
A circuit board structure includes a circuit substrate, a first circuit layer, and a second circuit layer. The circuit substrate has a surface and includes at least one conductive structure and at least one patterned circuit layer. The conductive structure is electrically connected to the patterned circuit layer, and an upper surface of the conductive structure is aligned with the surface. The first circuit layer is directly disposed on the surface of the circuit substrate and electrically connected to the conductive structure. A line width of the first circuit layer is less than or equal to 1/4 of a line width of the patterned circuit layer. The second circuit layer is directly disposed on the first circuit layer and electrically connected to the first circuit layer.
UNIMICRON TECHNOLOGY CORP. (Taïwan, Province de Chine)
Inventeur(s)
Lin, Wen Yu
Yang, Kai-Ming
Lin, Pu-Ju
Abrégé
The invention discloses a glass carrier having a protection structure, comprising a glass body and a protection layer. The glass body has a top surface, a bottom surface, and a lateral surface. The protection layer covers the lateral surface of the glass body. The protection layer is a hard material with a stiffness coefficient higher than a stiffness coefficient of the glass body. The invention further discloses a manufacturing method of a glass carrier having a protection structure, comprising the following steps: covering the protection layer around the lateral surface of the glass body, wherein the protection layer is the hard material with the stiffness coefficient higher than the stiffness coefficient of the glass body.
C03C 17/00 - Traitement de surface du verre, p.ex. du verre dévitrifié, autre que sous forme de fibres ou de filaments, par revêtement
C03C 17/42 - Traitement de surface du verre, p.ex. du verre dévitrifié, autre que sous forme de fibres ou de filaments, par revêtement avec au moins deux revêtements ayant des compositions différentes un revêtement au moins étant une substance organique et un revêtement au moins étant un non-métal
C03C 17/22 - Traitement de surface du verre, p.ex. du verre dévitrifié, autre que sous forme de fibres ou de filaments, par revêtement par d'autres matières inorganiques
H01L 23/10 - Conteneurs; Scellements caractérisés par le matériau ou par la disposition des scellements entre les parties, p.ex. entre le couvercle et la base ou entre les connexions et les parois du conteneur
H01L 23/29 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par le matériau
51.
LIGHT-EMITTING DIODE PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lin, Wen-Yu
Yang, Kai-Ming
Abrégé
A light-emitting diode package structure includes a heat dissipation substrate, a redistribution layer, and multiple light-emitting diodes. The heat dissipation substrate includes multiple copper blocks and a heat-conducting material layer. The copper blocks penetrate the heat-conducting material layer. The redistribution layer is disposed on the heat dissipation substrate and electrically connected to the copper blocks. The light-emitting diodes are disposed. on the redistribution layer and are electrically connected to the redistribution layer. A side of the light-emitting diodes away from the redistribution layer is not in contact with any component.
H01L 33/64 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les éléments du boîtier des corps semi-conducteurs Éléments d'extraction de la chaleur ou de refroidissement
H01L 25/075 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 33/22 - Surfaces irrégulières ou rugueuses, p.ex. à l'interface entre les couches épitaxiales
H01L 33/48 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les éléments du boîtier des corps semi-conducteurs
H01L 33/62 - Dispositions pour conduire le courant électrique vers le corps semi-conducteur ou depuis celui-ci, p.ex. grille de connexion, fil de connexion ou billes de soudure
52.
LIGHT-EMITTING DIODE PACKAGE AND MANUFACTURING METHOD THEREOF
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lin, Wen-Yu
Yang, Kai-Ming
Lin, Chen-Hao
Abrégé
A light-emitting diode package includes a redistribution layer, a light-emitting diode, a first dielectric layer, a plurality of wavelength conversion structures, and a transparent encapsulant. The light-emitting diode is disposed on and electrically connected to the redistribution layer. The light-emitting diode includes a first light-emitting diode, a second light-emitting diode, and a third light-emitting diode. The first dielectric layer is disposed on the redistribution layer and covers the light-emitting diode. The wavelength conversion structures are disposed on the first dielectric layer and respectively in contact with the second light-emitting diode and the third light-emitting diode. The transparent encapsulant is disposed on the first dielectric layer and covers the plurality of wavelength conversion structures. In addition, a manufacturing method of the light-emitting diode package is provided.
H01L 25/075 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 33/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Liao, Chun-Lin
Huang, Pei-Chang
Abrégé
A circuit board includes an insulation part, a support layer disposed on the insulation part, a metal case disposed in the insulation part, a heat-exchanging fluid distributed within the enclosed space, and a first porous material distributed within the enclosed space. The metal case is thermally coupled to the support layer and includes a first inner surface, a second inner surface opposite to the first inner surface and positioned between the first inner surface and the support layer, a third inner surface connecting the first inner surface and the second inner surface, and an enclosed space surrounded by the first inner surface, the second inner surface and the third inner surface. The first porous material is disposed on the first inner surface.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Ko, Cheng-Ta
Lin, Pu-Ju
Chen, Shih-Chieh
Kuo, Chi-Hai
Li, Jeng-Ting
Abrégé
A flexible circuit board and a manufacturing method thereof are provided. The flexible circuit board includes a circuit structure, a first cover layer, and a second cover layer. The circuit structure has a top surface and a bottom surface opposite to the top surface. The circuit structure includes multiple circuit layers and multiple insulating layers stacked alternately. A material of the insulating layers is a photosensitive dielectric material and a Young's modulus of the insulating layers is between 0.36 GPa and 8 GPa. The first cover layer is disposed on the top surface of the circuit structure. The second cover layer is disposed on the bottom surface of the circuit structure.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Tseng, Tzyy-Jang
Lau, John Hon-Shing
Lin, Pu-Ju
Ko, Cheng-Ta
Abrégé
A chip packaging structure and a manufacturing method thereof are provided. The chip packaging structure includes a substrate, at least one first chip, an adhesive material, a redistribution circuit structure, and multiple second chips. The substrate has a first surface, a second surface opposite to the first surface, and at least one cavity. The at least one first chip is disposed in the at least one cavity. The adhesive material is disposed in the at least one cavity and located between the substrate and the at least one first chip. The redistribution circuit structure is disposed on the first surface of the substrate, and is electrically connected to the at least one first chip. The second chips are disposed on the redistribution circuit structure, and are electrically connected to the redistribution circuit structure.
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Cheng, Shih-Lian
Abrégé
A circuit board structure includes a substrate, a third dielectric layer, a fourth dielectric layer, a first external circuit layer, a second external circuit layer, a conductive through hole, a first annular retaining wall, and a second annular retaining wall. The conductive through hole penetrates through the third dielectric layer, a second dielectric layer, and the fourth dielectric layer. The conductive through hole is electrically connected to the first external circuit layer and the second external circuit layer. The first annular retaining wall is disposed in the third dielectric layer, surrounds the conductive through hole, and is electrically connected to the first external circuit layer and the first inner circuit layer. The second annular retaining wall is disposed in the fourth dielectric layer, surrounds the conductive through hole, and connects to the second external circuit layer and the second inner circuit layer electrically.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Cheng, Shih-Lian
Abrégé
A circuit board structure includes a substrate, a third dielectric layer, a fourth dielectric layer, a first external circuit layer, a second external circuit layer, a conductive through hole electrically connected to the first and second external circuit layers, a first annular retaining wall surrounding the conductive through hole, and a second annular retaining wall surrounding the conductive through hole. The first annular retaining wall is electrically connected to the first external circuit layer and a first inner circuit layer. The second annular retaining wall is electrically connected to the second external circuit layer and a second inner circuit layer. A first ground circuit, the first annular retaining wall, and the first inner circuit layer define a first ground path surrounding a first signal circuit. A second ground circuit, the second annular retaining wall, and the second inner circuit layer define a second ground path surrounding a second signal circuit.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Cheng, Shih-Lian
Abrégé
A circuit board structure includes a first dielectric layer, first and second inner circuit layers, a conductive connection layer, a second dielectric layer, two third dielectric layers, third and fourth inner circuit layers, two conductive through vias, first and second annular retaining walls, two fourth dielectric layers, first and second external circuit layers, and third and fourth annular retaining walls. The conductive through vias penetrate the third and second dielectric layers and electrically connect the third and fourth inner circuit layers. The first and second annular retaining walls surround the conductive through vias and electrically connect the third and first and the fourth and second inner circuit layers. The third and fourth annular retaining walls are respectively disposed in the fourth dielectric layers and electrically connect the first external circuit layer and the third inner circuit layer and the second external circuit layer and the fourth inner circuit layer.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lau, John Hon-Shing
Tain, Ra-Min
Ko, Cheng-Ta
Tseng, Tzyy-Jang
Chien, Chun-Hsien
Abrégé
A circuit carrier includes a substrate, a first build-up circuit structure, a second build-up circuit structure, a fine redistribution structure and at least one conductive through hole. The substrate has a top surface and a bottom surface opposite to each other. The first build-up circuit structure is disposed on the top surface of the substrate and electrically connected to the substrate. The second build-up circuit structure is disposed on the bottom surface of the substrate and electrically connected to the substrate. The fine redistribution structure is directly attached on the first build-up circuit structure, wherein a line width and a line spacing of the fine redistribution structure are smaller than those of the first build-up circuit structure. The conductive through hole penetrates the fine redistribution structure and a portion of the first build-up circuit structure and is electrically connected to the fine redistribution structure and the first build-up circuit structure.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Nien, Heng-Ming
Lu, Chih-Chiang
Chan, Chih-Kai
Cheng, Shih-Lian
Abrégé
An electroplating apparatus includes an anode and a cathode, a power supply, a regulating plate, and a controller. The power supply is electrically connected to the anode and the cathode. The regulating plate is disposed between the anode and the cathode. The regulating plate includes an insulation grid plate and a plurality of wires. The controller is electrically connected to the plurality of wires to control a state of an electromagnetic field around the plurality of wires. An electroplating method is also provided.
H05K 3/18 - Appareils ou procédés pour la fabrication de circuits imprimés dans lesquels le matériau conducteur est appliqué au support isolant de manière à former le parcours conducteur recherché utilisant la technique de la précipitation pour appliquer le matériau conducteur
Unimicron Technology Corporation (Taïwan, Province de Chine)
Inventeur(s)
Hsieh, Ching-Ho
Wu, Ming-Hsing
Wu, Kuei-Sheng
Abrégé
A circuit board assembly is provided and includes a first circuit board, a second circuit board and a first connecting module. The first connecting module includes a first connecting wire, a first connector and a second connector. The first circuit board includes a first processor, and the second circuit board includes a second processor. One end of the first connector is connected to one end of the first connecting wire, and the other end of the first connector is connected to the first circuit board. One end of the second connector is connected to the other end of the first connecting wire, and the other end of the second connector is connected to the second circuit board. The first connector is adjacent to the first processor, and the second connector is adjacent to the second processor.
H01R 12/79 - Dispositifs de couplage pour circuits imprimés flexibles, câbles plats ou à rubans ou structures similaires se raccordant à des circuits imprimés rigides ou à des structures similaires
62.
Electroplating apparatus and electroplating method
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Nien, Heng-Ming
Lu, Chih-Chiang
Wu, Cho-Ying
Cheng, Shih-Lian
Abrégé
An electroplating apparatus including an anode and a cathode, a power supply, and a regulating plate is provided. The power supply is electrically connected to the anode and the cathode. The regulating plate is arranged between the anode and the cathode. The regulating plate includes an insulating grid plate and a plurality of magnetic components. The plurality of magnetic components are uniformly and randomly arranged on the insulating grid plate. An electroplating method is also provided.
C25D 5/00 - Dépôt électrochimique caractérisé par le procédé; Prétraitement ou post-traitement des pièces
C25D 17/00 - PROCÉDÉS POUR LA PRODUCTION ÉLECTROLYTIQUE OU ÉLECTROPHORÉTIQUE DE REVÊTEMENTS; GALVANOPLASTIE; JONCTION DE PIÈCES PAR ÉLECTROLYSE; APPAREILLAGES À CET EFFET Éléments structurels, ou leurs assemblages, des cellules pour revêtement électrolytique
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Chen, Ming-Ru
Tseng, Tzyy-Jang
Lo, Cheng-Chung
Abrégé
A manufacturing method of a light emitting diode (LED) package structure includes the following steps. A carrier is provided. A redistribution layer is formed on the carrier. A plurality of active devices are formed on the carrier. A plurality of LEDs are transferred on the redistribution layer. The LEDs and the active devices are respectively electrically connected to the redistribution layer. The active devices are adapted to drive the LEDs, respectively. A molding compound is formed on the redistribution layer to encapsulate the LEDs. The carrier is removed to expose a bottom surface of the redistribution layer.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des groupes principaux , ou dans une seule sous-classe de , , p.ex. circuit hybrides
H01L 33/56 - Matériaux, p.ex. résine époxy ou silicone
H01L 33/62 - Dispositions pour conduire le courant électrique vers le corps semi-conducteur ou depuis celui-ci, p.ex. grille de connexion, fil de connexion ou billes de soudure
64.
Package structure with interconnection between chips and packaging method thereof
UNIMICRON TECHNOLOGY CORP. (Taïwan, Province de Chine)
Inventeur(s)
Chen, Jia Shiang
Lan, Chung-Yu
Chen, Yu-Shen
Abrégé
A packaging method includes steps of: forming first and second wiring layers electrically connected to each other on two opposite surfaces of a substrate; then configuring mother substrate interconnecting bumps on the first wiring layer and along perimeter of a daughter substrate unit, and then cutting along the perimeter of the daughter substrate unit to expose lateral faces of the mother substrate interconnecting bumps and configuring solder materials thereon; then configuring first and second chips on the first and the second wiring layers to form electrical interconnection between the two chips. A package structure enables interconnecting two chips through one single daughter substrate unit with its wiring layers directly connecting with lateral face contacts of the mother carrier substrate through the mother substrate interconnecting bumps. Hence, area of the daughter substrate unit is reduced; lengths of the interconnection paths are shortened, and qualities of communication and space utilization are enhanced.
H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/498 - Connexions électriques sur des substrats isolants
H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
65.
Method of improving wire structure of circuit board and improving wire structure of circuit board
UNIMICRON TECHNOLOGY CORP. (Taïwan, Province de Chine)
Inventeur(s)
Kuo, Chun Yi
Liang, Jia Hao
Lin, Ching Ku
Abrégé
A circuit board, comprising a multi-layer circuit board, a first conductive circuit, a first circuit layer, an adhesion promoter layer, a second conductive circuit, and a second circuit layer. The multi-layer circuit board comprises an inner circuit and an opening. The opening exposes the inner circuit. The first conductive circuit is disposed in the opening and on the inner circuit. The first circuit layer is disposed on the first conductive circuit in the opening and lower than the depth of the opening. The adhesion promoter layer is disposed in the opening and on the surface of the multi-layer circuit board and connected to the first conductive circuit. The second conductive circuit is disposed on the adhesion promoter layer and on the first circuit layer in the opening. The second circuit layer is disposed on the second conductive circuit in the opening and on the second conductive circuit.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Tain, Ra-Min
Lau, John Hon-Shing
Lin, Pu-Ju
Ye, Wei-Ci
Kuo, Chi-Hai
Ko, Cheng-Ta
Tseng, Tzyy-Jang
Abrégé
A vapor chamber structure includes a thermally conductive shell, a capillary structure layer, and a working fluid. The thermally conductive shell includes a first thermally conductive portion and a second thermally conductive portion. The first thermally conductive portion and the second thermally conductive portion are a thermally conductive plate that is integrally formed, and the thermally conductive shell is formed by folding the thermally conductive plate in half and then sealing the thermally conductive plate. The first thermally conductive portion has at least one first cavity, the second thermally conductive portion has at least one second cavity. At least one sealed chamber is defined between the thermally conductive plate, the first cavity and the second cavity. A pressure in the sealed chamber is lower than a standard atmospheric pressure. The capillary structure layer covers an inner wall of the sealed chamber. The working fluid is filled in the sealed chamber.
F28D 15/04 - Appareils échangeurs de chaleur dans lesquels l'agent intermédiaire de transfert de chaleur en tubes fermés passe dans ou à travers les parois des canalisations dans lesquels l'agent se condense et s'évapore, p.ex. tubes caloporteurs avec des tubes ayant une structure capillaire
F28D 15/02 - Appareils échangeurs de chaleur dans lesquels l'agent intermédiaire de transfert de chaleur en tubes fermés passe dans ou à travers les parois des canalisations dans lesquels l'agent se condense et s'évapore, p.ex. tubes caloporteurs
B23P 15/26 - Fabrication d'objets déterminés par des opérations non couvertes par une seule autre sous-classe ou un groupe de la présente sous-classe d'échangeurs de chaleur
F28F 21/08 - Structure des appareils échangeurs de chaleur caractérisée par l'emploi de matériaux spécifiés de métal
67.
Substrate with buried component and manufacture method thereof
UNIMICRON TECHNOLOGY CORP. (Taïwan, Province de Chine)
Inventeur(s)
Chen, Yu-Shen
Lan, Chung-Yu
Abrégé
A substrate is manufactured by drilling a chip containing groove in a composite inner layer circuit structure, having a component connecting end of a circuit layer protruding from a mounting side wall in the chip containing groove, mounting a chip component in the chip containing groove, and connecting the surface bonding pad to the component connecting end. The chip component in the present invention penetrates at least two circuit layers, and the surface bonding pad is bonded to the component connecting end of the circuit layer directly, reducing the occupied area of the chip component in each one of the circuit layers, and increasing the area for circuit disposing and the possible amount of chip components that may be mounted in the substrate.
H05K 3/02 - Appareils ou procédés pour la fabrication de circuits imprimés dans lesquels le matériau conducteur est appliqué à la surface du support isolant et est ensuite enlevé de zones déterminées de la surface, non destinées à servir de conducteurs de courant ou d'éléments de blindage
H01L 23/13 - Supports, p.ex. substrats isolants non amovibles caractérisés par leur forme
H01L 23/485 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées formées de structures en couches comprenant des couches conductrices et isolantes, p.ex. contacts planaires
H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
H05K 3/32 - Connexions électriques des composants électriques ou des fils à des circuits imprimés
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Ma, Guang-Hwa
Wang, Chin-Sheng
Tain, Ra-Min
Abrégé
A circuit board structure includes a dielectric substrate, at least one embedded block, at least one electronic component, at least one first build-up circuit layer, at least one second build-up circuit layer, at least one conductive through hole, and a fine redistribution layer (RDL). The embedded block is fixed in a through cavity of the dielectric substrate. The electronic component is disposed in an opening of the embedded block. The first build-up circuit layer is disposed on a top surface of the dielectric substrate and electrically connected with the electronic component. The second build-up circuit layer is disposed on a bottom surface of the dielectric substrate and covers the embedded block. The conductive through hole is disposed in a via of the embedded block and electrically connects the first and the second build-up circuit layers. The fine RDL is disposed on and electrically connected to the first build-up circuit layer.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lee, Hsin-Hung
Chien, Chun-Hsien
Hsieh, Yu-Chung
Fang, Yi-Hsiu
Tseng, Tzyy-Jang
Abrégé
An inspection apparatus used for inspecting a bare circuit board is provided, where the bare circuit board includes an antenna. The inspection apparatus includes a holding stage, a probing device, and a measurement device. The holding stage can hold the bare circuit board. The measurement device is electrically connected to the probing device and electrically connected to the antenna via the probing device. The measurement device can input a first testing signal to the antenna. The antenna can input a second testing signal to the measurement device after receiving the first testing signal. The measurement device can measure the antenna according to the second testing signal, where the first testing signal and the second testing signal both pass through no active component.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Li, Ke-Chien
Kuo, Chun-Hung
Liang, Chih-Chun
Abrégé
A circuit board includes a substrate, a build-up circuit structure, a graphene oxide layer, a graphene layer, and an insulating material layer. The build-up circuit structure is disposed on the substrate, including at least one inner circuit, at least one dielectric layer, an outer circuit, and multiple conductive vias. The dielectric layer is disposed on the inner circuit. The outer circuit is disposed on the dielectric layer. The conductive vias penetrate the dielectric layer and electrically connect the inner circuit and the outer circuit. The graphene oxide layer and the graphene layer are disposed on the build-up circuit structure at an interval. The graphene oxide layer and the graphene layer are respectively disposed in correspondence to the dielectric layer and the outer circuit. The insulating material layer is disposed on the graphene oxide layer and the graphene layer. The insulating material layer has an opening, which exposes the graphene layer.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Tseng, Tzyy-Jang
Wang, Chin-Sheng
Tain, Ra-Min
Abrégé
A circuit board structure includes a dielectric substrate, at least one embedded block, at least one electronic component, at least one first build-up circuit layer, and at least one second build-up circuit layer. The dielectric substrate includes a through cavity penetrating the dielectric substrate. The embedded block is fixed in the through cavity. The embedded block includes a first through hole and a second through hole. The electronic component is disposed in the through hole of the embedded block. The first build-up circuit layer is disposed on the top surface of the dielectric substrate and covers the embedded block. The second build-up circuit layer is disposed on the bottom surface of the dielectric substrate and covers the embedded block.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Chang, Chi-Min
Chen, Ching-Sheng
Huang, Jun-Rui
Liao, Wei-Yu
Lin, Yi-Pin
Abrégé
An interlayer connective structure is suitable for being formed in a wiring board, in which the wiring board includes two traces and an insulation part between the traces. The insulation part has a through hole. The interlayer connective structure located in the through hole is connected to the traces. The interlayer connective structure includes a column and a pair of protuberant parts. The protuberant parts are located at two ends of the through hole respectively and connected to the column and the traces. The protuberant parts stick out from the outer surfaces of the traces respectively. Each of the protuberant parts has a convex curved surface, in which the distance between the convex curved surface and the axis of the through hole is less than the radius of the through hole.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Peng, Chia-Yu
Lau, John Hon-Shing
Yang, Kai-Ming
Lin, Pu-Ju
Ko, Cheng-Ta
Tseng, Tzyy-Jang
Abrégé
A circuit board structure includes a redistribution structure layer, a build-up circuit structure layer, and a connection structure layer. The redistribution structure layer has a first and second surface, and includes an inner and outer dielectric layer, first connecting pads, and chip pads. A bottom surface of each first connecting pad is aligned with the first surface, and the chip pads are protruded from and located on the second surface. The build-up circuit structure layer includes second connecting pads. The connection structure layer is disposed between the redistribution structure layer and the build-up circuit structure layer and includes a substrate and conductive paste pillars penetrating the substrate. The first connecting pads are electrically connected to the second connecting pads via the conductive paste pillars, respectively. A top surface of each conductive paste pillar is aligned with the first surface of the redistribution structure layer.
H01R 12/52 - Connexions fixes pour circuits imprimés rigides ou structures similaires se raccordant à d'autres circuits imprimés rigides ou à des structures similaires
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Wang, Chin-Sheng
Huang, Pei-Chang
Abrégé
A method of manufacturing a circuit board is provided. The method includes forming an open substrate, in which the open substrate includes a substrate body having a top surface and a bottom surface; an opening in the substrate body, in which the opening has a first sidewall and a second sidewall opposite to the first sidewall; and at least one first fixing portion and at least one second fixing portion extending from the substrate body toward the opening, in which the first fixing portion and the second fixing portion are respectively protruded from the first sidewall and the second sidewall. A heat dissipation block is inserted in the opening to clamp the heat dissipation block between the first fixing portion and the second fixing portion, in which the heat dissipation block includes the heat dissipation block comprises a ceramic or a composite material.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Yang, Kai-Ming
Lin, Chen-Hao
Ko, Cheng-Ta
Lau, John Hon-Shing
Chen, Yu-Hua
Tseng, Tzyy-Jang
Abrégé
A method of manufacturing package structure with following steps is disclosed herein. An insulating composite layer is formed on a metal layer of a carrier board. A chip packaging module including a sealant and a first chip embedded therein is disposed on the insulating composite layer, in which the first chip has a plurality of conductive pads. A first circuit layer module including a dielectric layer and a circuit layer is formed on the chip packaging module, in which the circuit layer is on the dielectric layer and electrically connected to the conductive pads through a conductive vias in the dielectric layer. A second chip is disposed on the first circuit layer module. A second circuit layer module is formed on the first circuit layer module and the second chip. A protecting layer is formed on the second circuit layer module.
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lin, Pu-Ju
Yang, Kai-Ming
Ko, Cheng-Ta
Abrégé
A manufacturing method of a chip package structure includes the following steps. A plurality of chips is disposed on a first insulating layer. The back surface of each of the chips is in direct contact with the first insulating layer. A stress buffer layer is formed to extend and cover the active surface and the peripheral surface of each of the chips, and a bottom surface of the stress buffer layer is aligned with the back surface of each of the chips. The stress buffer layer has an opening exposing a part of the active surface of each of the chips, and the redistribution layer is electrically connected to each of the chips through the opening. A plurality of solder balls is electrically connected to the redistribution layer exposed by the blind holes. A singularizing process is performed to form a plurality of chip package structures separated from each other.
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lau, John Hon-Shing
Ko, Cheng-Ta
Lin, Pu-Ju
Yang, Kai-Ming
Kuo, Chi-Hai
Peng, Chia-Yu
Tseng, Tzyy-Jang
Abrégé
A package structure includes a redistribution layer, a chip assembly, a plurality of solder balls, and a molding compound. The redistribution layer includes redistribution circuits, photoimageable dielectric layers, conductive through holes, and chip pads. One of the photoimageable dielectric layers located on opposite two outermost sides has an upper surface and openings. The chip pads are located on the upper surface and are electrically connected to the redistribution circuits through the conductive through holes. The openings expose portions of the redistribution circuits to define solder ball pads. Line widths and line spacings of the redistribution circuits decrease in a direction from the solder ball pads towards the chip pads. The chip assembly is disposed on the chip pads and includes at least two chips with different sizes. The solder balls are disposed on the solder ball pads, and the molding compound at least covers the chip assembly.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
79.
Package structure and manufacturing method thereof
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lau, John Hon-Shing
Ko, Cheng-Ta
Lin, Pu-Ju
Yang, Kai-Ming
Peng, Chia-Yu
Kuo, Chi-Hai
Tseng, Tzyy-Jang
Abrégé
A package structure includes at least one first redistribution layer, at least one second redistribution layer, a chip pad, a solder ball pad, a chip, a solder ball, and a molding compound. The first redistribution layer includes a first dielectric layer and a first redistribution circuit that fills a first opening and a second opening of the first dielectric layer. The first dielectric layer is aligned with the first redistribution circuit. The second redistribution layer includes a second and a third dielectric layers and a second redistribution circuit. The third dielectric layer is aligned with the second redistribution circuit. The chip pad and the solder ball pad are electrically connected to the first and the second redistribution circuits respectively. The chip and the solder ball are disposed on the chip pad and the solder ball pad respectively. The molding compound at least covers the chip and the chip pad.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
80.
Circuit board structure and manufacturing method thereof
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Kuo, Chun-Hung
Chen, Kuo-Ching
Abrégé
A circuit board structure, including a circuit layer, a first dielectric layer, a first graphene layer, a first conductive via, and a first built-up circuit layer, is provided. The circuit layer includes multiple pads. The first dielectric layer is disposed on the circuit layer and has a first opening. The first opening exposes the pads. The first graphene layer is conformally disposed on the first dielectric layer and in the first opening, and has a first conductive seed layer region and a first non-conductive seed layer region. The first conductive via is disposed in the first opening. The first built-up circuit layer is disposed corresponding to the first conductive seed layer region. The first built-up circuit layer exposes the first non-conductive seed layer region and is electrically connected to the pads through the first conductive via and the first conductive seed layer region.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Tseng, Tzyy-Jang
Chen, Yu-Hua
Chien, Chun-Hsien
Yeh, Wen-Liang
Tain, Ra-Min
Abrégé
An embedded component structure includes a board, an electronic component, and a dielectric material layer. The board has a through cavity. The board includes an insulating core layer and a conductive member. The insulating core layer has a first surface and a second surface opposite thereto. The through cavity penetrates the insulating core layer. The conductive member extends from a portion of the first surface along a portion of the side wall of the through cavity to a portion of the second surface. The electronic component includes an electrode. The electronic component is disposed in the through cavity. The dielectric material layer is at least filled in the through cavity. The connection circuit layer covers and contacts the conductive member and the electrode. A manufacturing method of an embedded component structure is also provided.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Peng, Yan-Jia
Chen, Kuo-Ching
Lin, Pu-Ju
Abrégé
A method of fabricating a wiring board with an embedded interposer substrate includes preparing a main substrate, forming a recess on the main substrate, placing an interposer substrate into the recess, electrically connecting a second pad of the interposer substrate and the first pad of the main substrate, and filling a gap between the interposer substrate and the main substrate with an underfill. The recess exposes a first pad of the main substrate. A second pad of interposer substrate and the first pad of the main substrate are made of the same metal and formed in different outer surface profiles. The underfill entirely touches side surfaces and a bottom surface of the interposer substrate.
H01L 23/12 - Supports, p.ex. substrats isolants non amovibles
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/16 - Matériaux de remplissage ou pièces auxiliaires dans le conteneur, p.ex. anneaux de centrage
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/50 - Assemblage de dispositifs à semi-conducteurs en utilisant des procédés ou des appareils non couverts par l'un uniquement des groupes
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
83.
Light emitting diode package structure and manufacturing method thereof and manufacturing method of display device
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Li, Jeng-Ting
Kuo, Chi-Hai
Ko, Cheng-Ta
Lin, Pu-Ju
Abrégé
A light emitting diode (LED) package structure includes a glass substrate, conductive through holes, active elements, an insulating layer, LEDs and pads. The glass substrate has an upper surface and a lower surface. The conductive through holes penetrate the glass substrate and connect the upper and the lower surfaces. The active elements are disposed on the upper surface of the glass substrate and electrically connected to the conductive through holes. The insulating layer is disposed on the upper surface and covers the active elements. The LEDs are disposed on the insulating layer and electrically connected to at least one of the active elements. The pads are disposed on the lower surface of the glass substrate and electrically connected to the conductive through holes. A source of at least one active elements is directly electrically connected to at least one of the corresponding pads through the corresponding conductive through hole.
H01L 33/62 - Dispositions pour conduire le courant électrique vers le corps semi-conducteur ou depuis celui-ci, p.ex. grille de connexion, fil de connexion ou billes de soudure
H01L 27/15 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants semi-conducteurs avec au moins une barrière de potentiel ou une barrière de surface, spécialement adaptés pour l'émission de lumière
H01L 33/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails
84.
Circuit board structure and manufacturing method thereof
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lau, John Hon-Shing
Ko, Cheng-Ta
Lin, Pu-Ju
Kuo, Chi-Hai
Yang, Kai-Ming
Peng, Chia-Yu
Lee, Shao-Chien
Tseng, Tzyy-Jang
Abrégé
A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.
H05K 1/03 - Emploi de matériaux pour réaliser le substrat
H05K 1/09 - Emploi de matériaux pour réaliser le parcours métallique
H05K 1/11 - Eléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
H05K 1/14 - Association structurale de plusieurs circuits imprimés
H05K 1/16 - Circuits imprimés comprenant des composants électriques imprimés incorporés, p.ex. une résistance, un condensateur, une inductance imprimés
H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
H05K 3/20 - Appareils ou procédés pour la fabrication de circuits imprimés dans lesquels le matériau conducteur est appliqué au support isolant de manière à former le parcours conducteur recherché par apposition d'un parcours conducteur préfabriqué
H05K 3/36 - Assemblage de circuits imprimés avec d'autres circuits imprimés
H05K 3/38 - Amélioration de l'adhérence entre le substrat isolant et le métal
H05K 3/40 - Fabrication d'éléments imprimés destinés à réaliser des connexions électriques avec ou entre des circuits imprimés
H05K 3/02 - Appareils ou procédés pour la fabrication de circuits imprimés dans lesquels le matériau conducteur est appliqué à la surface du support isolant et est ensuite enlevé de zones déterminées de la surface, non destinées à servir de conducteurs de courant ou d'éléments de blindage
85.
Package structure and manufacturing method thereof
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Tseng, Tzyy-Jang
Ko, Cheng-Ta
Lin, Pu-Ju
Kuo, Chi-Hai
Yang, Kai-Ming
Abrégé
A manufacturing method of a package structure is provided, which includes the following steps. A carrier having a surface is provided. A copper foil layer is laminated on the surface of the carrier. A subtractive process is performed on the copper foil layer to form a copper foil circuit layer on the carrier. The copper foil circuit layer exposes a part of the surface of the carrier. A build-up structure layer is formed on the copper foil circuit layer and the surface of the carrier. A first surface of the copper foil circuit layer is aligned with a second surface of the build-up structure layer. At least one electronic component is disposed on the build-up structure layer. A package colloid is formed to cover the electronic component and the build-up structure layer. The carrier is removed to expose the first surface of the copper foil circuit layer.
H01L 33/62 - Dispositions pour conduire le courant électrique vers le corps semi-conducteur ou depuis celui-ci, p.ex. grille de connexion, fil de connexion ou billes de soudure
H01L 33/06 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les corps semi-conducteurs ayant une structure à effet quantique ou un superréseau, p.ex. jonction tunnel au sein de la région électroluminescente, p.ex. structure de confinement quantique ou barrière tunnel
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 33/54 - Encapsulations ayant une forme particulière
86.
Metal bump structure and manufacturing method thereof and driving substrate
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Tseng, Tzyy-Jang
Chen, Ming-Ru
Lo, Cheng-Chung
Wang, Chin-Sheng
Tang, Wen-Sen
Abrégé
A manufacturing method of a metal bump structure is provided. A driving base is provided. At least one pad and an insulating layer are formed on the driving base. The pad is formed on an arrangement surface of the driving base and has an upper surface. The insulating layer covers the arrangement surface of the driving base and the pad, and exposes a part of the upper surface of the pad. A patterned metal layer is formed on the upper surface of the pad exposed by the insulating layer, and extends to cover a part of the insulating layer. An electro-less plating process is performed to form at least one metal bump on the patterned metal layer. A first extension direction of the metal bump is perpendicular to a second extension direction of the driving base.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/075 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 33/62 - Dispositions pour conduire le courant électrique vers le corps semi-conducteur ou depuis celui-ci, p.ex. grille de connexion, fil de connexion ou billes de soudure
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Wang, Pei-Wei
Nien, Heng-Ming
Chen, Ching-Sheng
Lin, Yi-Pin
Cheng, Shih-Liang
Abrégé
A co-axial structure includes a substrate, a first conductive structure, a second conductive structure, and an insulating layer. The substrate includes a first surface. The first conductive structure includes a first circuit deposited on the first surface and a first via penetrating the substrate. The second conductive structure includes a second circuit deposited on the first surface and a second via penetrating the substrate. The first via and the second via extend along a first direction. The first circuit and the second circuit extend along a second direction, and the second direction is perpendicular to the first direction. The insulating layer is located between the first via and the second via. The insulating layer includes a filler. The first conductive structure and the second conductive structure are electrically insulated. The first circuit and the second circuit are coplanar.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lu, Chih-Chiang
Chang, Chi-Min
Lee, Shao-Chien
Huang, Jun-Rui
Chang, Ming-Ting
Abrégé
A circuit board includes a first dielectric material, a second dielectric material, a third dielectric material, a first external circuit layer, a second external circuit layer, multiple conductive structures, and a conductive via structure. Dielectric constants of the first, the second and the third dielectric materials are different. The first and the second external circuit layers are respectively disposed on the first and the third dielectric materials. The conductive via structure at least penetrates the first and the second dielectric materials and is electrically connected to the first and the second external circuit layers to define a signal path. The conductive structures are electrically connected to each other and surround the first, the second and the third dielectric materials. The conductive structures are electrically connected to the first and the second external circuit layers to define a ground path surrounding the signal path.
H05K 1/11 - Eléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
H05K 3/00 - Appareils ou procédés pour la fabrication de circuits imprimés
H05K 3/10 - Appareils ou procédés pour la fabrication de circuits imprimés dans lesquels le matériau conducteur est appliqué au support isolant de manière à former le parcours conducteur recherché
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lu, Chih-Chiang
Liu, Hsin-Ning
Huang, Jun-Rui
Wang, Pei-Wei
Chen, Ching Sheng
Cheng, Shih-Lian
Abrégé
A circuit board includes a first external circuit layer, a first substrate, a second substrate, a third substrate, and a conductive through hole structure. The first substrate includes conductive pillars electrically connecting the first external circuit layer and the second substrate. The second substrate has an opening and includes a first dielectric layer. The opening penetrates the second substrate, and the first dielectric layer fills the opening. The third substrate includes an insulating layer, a second external circuit layer, and conductive holes. A conductive material layer of the conductive through hole structure covers an inner wall of a through hole and electrically connects the first and the second external circuit layers to define a signal path. The first external circuit layer, the conductive pillars, the second substrate, the conductive holes and the second external circuit layer are electrically connected to define a ground path surrounding the signal path.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
90.
CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF AND ELECTRONIC DEVICE
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Huang, Jun-Rui
Lu, Chih-Chiang
Lin, Yi-Pin
Chen, Ching-Sheng
Abrégé
A circuit board includes a first substrate, a second substrate, a third substrate, a plurality of conductive structures and a conductive via structure. The second substrate is disposed between the first substrate and the third substrate. The third substrate has an opening and includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The opening penetrates the first dielectric layer and the second dielectric layer, and the third dielectric layer fully fills the opening. The conductive via structure penetrates the first substrate, the second substrate, the third dielectric layer of the third substrate, and is electrically connected to the first substrate and the third substrate to define a signal path. The first substrate, the second substrate, and the third substrate are electrically connected through the conductive structures to define a ground path, and the ground path surrounds the signal path.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Yu, Yunn-Tzu
Hsieh, Ching-Ho
Tsai, Wang-Hsiang
Abrégé
A circuit board structure includes a body, multiple first pads, a conductive assembly, multiple first engaging components, and multiple second engaging components. The body includes a first portion and a second portion integrally formed. A first surface of the first portion directly contacts a second surface of the second portion. A first region of the first surface protrudes from the second portion, and a second region of the second surface protrudes from the first portion. The first pads and the first engaging components are disposed on the first portion of the body and located in the first region of the first surface. The conductive assembly and the second engaging components are disposed on the second portion of the body and located in the second region of the second portion. The first pads are located between the first engaging components, and the conductive assembly is located between the second engaging components.
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lu, Chih-Chiang
Nien, Heng-Ming
Chen, Ching-Sheng
Chang, Ching
Chang, Ming-Ting
Chang, Chi-Min
Lee, Shao-Chien
Huang, Jun-Rui
Cheng, Shih-Lian
Abrégé
Provided is a circuit board, including a first substrate, a second substrate, a third substrate, a fourth substrate, multiple conductive structures, and a conductive via structure. The second substrate is disposed between the first substrate and the third substrate. The third substrate is disposed between the second substrate and the fourth substrate. The third substrate has an opening penetrating the third substrate and includes a first dielectric layer filling the opening. The conductive via structure penetrates the first substrate, the second substrate, the first dielectric layer of the third substrate, and the fourth substrate, and is electrically connected to the first substrate and the fourth substrate to define a signal path. The first substrate, the second substrate, the third substrate and the fourth substrate are electrically connected through the conductive structures to define a ground path, and the ground path surrounds the signal path.
H05K 1/16 - Circuits imprimés comprenant des composants électriques imprimés incorporés, p.ex. une résistance, un condensateur, une inductance imprimés
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Chen, Ming-Ru
Tseng, Tzyy-Jang
Lo, Cheng-Chung
Abrégé
A manufacturing method of a light emitting diode (LED) package structure includes the following steps. A carrier is provided. A redistribution layer is formed on the carrier. A plurality of active devices are formed on the carrier. A plurality of LEDs are transferred on the redistribution layer. The LEDs and the active devices are respectively electrically connected to the redistribution layer. The active devices are adapted to drive the LEDs, respectively. A molding compound is formed on the redistribution layer to encapsulate the LEDs. The carrier is removed to expose a bottom surface of the redistribution layer.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des groupes principaux , ou dans une seule sous-classe de , , p.ex. circuit hybrides
H01L 33/62 - Dispositions pour conduire le courant électrique vers le corps semi-conducteur ou depuis celui-ci, p.ex. grille de connexion, fil de connexion ou billes de soudure
H01L 33/56 - Matériaux, p.ex. résine époxy ou silicone
94.
Device and method for measuring thickness of dielectric layer in circuit board
Unimicron Technology Corporation (Taïwan, Province de Chine)
Inventeur(s)
Chang, Cheng-Jui
Chang, Hung-Lin
Abrégé
A method for measuring a thickness of a dielectric layer in a circuit board is provided. The method for measuring the thickness of the dielectric layer includes the following steps. First, a circuit board including at least one dielectric layer and at least two circuit layers is provided. The dielectric layer is between the circuit layers, and the circuit board further includes a test area including a test pattern and a through hole. The test pattern includes at least two metal layers. Next, a measuring device including a main body, at least one light source and a lens module is provided. When the main body is moved into the through hole, the light source emits light to the dielectric layer and the metal layer, and the lens module shoots the dielectric layer and the metal layer to form a captured image. The thickness of the dielectric layer is obtained via the captured image.
G01B 11/06 - Dispositions pour la mesure caractérisées par l'utilisation de techniques optiques pour mesurer la longueur, la largeur ou l'épaisseur pour mesurer l'épaisseur
95.
Device and method for measuring thickness of dielectric layer in circuit board
Unimicron Technology Corporation (Taïwan, Province de Chine)
Inventeur(s)
Chang, Cheng-Jui
Chang, Hung-Lin
Chiang, Jeng-Wey
Abrégé
A method for measuring thickness of dielectric layer in circuit board includes the following steps: First, circuit board including dielectric layer and circuit layers is provided. The dielectric layer is between the circuit layers, and the circuit board further includes test area including test pattern and through hole. The test pattern includes first conductor and second conductors. The distance between the side of the through hole and the second conductor is less than the distance between the side of the through hole and the first conductor. Next, measuring device including conductive pin and sensing element is provided. Next, the conductive pin is powered, and one end of the conductive pin is electrically connected to the second conductor. Next, the sensing element is moved along the through hole to obtain sensing curve, and the thickness of the dielectric layer is calculated via variations of the sensing curve.
G01B 7/06 - Dispositions pour la mesure caractérisées par l'utilisation de techniques électriques ou magnétiques pour mesurer la longueur, la largeur ou l'épaisseur pour mesurer l'épaisseur
Unimicron Technology Corporation (Taïwan, Province de Chine)
Inventeur(s)
Chang, Cheng-Jui
Chang, Hung-Lin
Abrégé
An electromagnetic measuring probe device for measuring a thickness of a dielectric layer of a circuit board and a method thereof are disclosed. The circuit board has at least one dielectric layer, at least two conductive layers and a test area. The test area has a test pattern and a through hole. The electromagnetic measuring probe device has a probe-measuring unit, an external conductive element, plural magnetic powder groups, and a maintaining unit. The probe-measuring unit has a transparent tube and an internal conductive pin. The external conductive element electrically connects with the test pattern. The conductive layers and the internal conductive pin generate a magnetic field while the probe-measuring unit enters into the through hole. The magnetic powder groups magnetically attracted are gathered to positions corresponding to thickness-range positions of the conductive layers and held by the maintaining unit, thus a gap between the two dielectric layers is obtained.
G01B 7/06 - Dispositions pour la mesure caractérisées par l'utilisation de techniques électriques ou magnétiques pour mesurer la longueur, la largeur ou l'épaisseur pour mesurer l'épaisseur
H05K 1/11 - Eléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
UNIMICRON TECHNOLOGY CORP. (Taïwan, Province de Chine)
Inventeur(s)
Kuo, Chun Hung
Chen, Kuo Ching
Abrégé
A circuit board is manufactured by mounting a first circuit layer, mounting a conductive bump on the first circuit layer, covering the first circuit layer with a first dielectric layer which exposes the conductive bump, mounting a second dielectric layer on the first dielectric layer with a second dielectric layer opening that exposes the conductive bump, and finally, mounting a second circuit layer on the surface of the second dielectric layer and in the second dielectric layer opening. Since the surface roughness of the second dielectric layer and the second dielectric layer opening is low, it is unlikely to form nano voids between the second dielectric layer and the second circuit layer, and the second circuit layer may be attached to the second dielectric layer firmly, which is an advantage for fine line circuit disposal.
H05K 1/11 - Eléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
H05K 3/20 - Appareils ou procédés pour la fabrication de circuits imprimés dans lesquels le matériau conducteur est appliqué au support isolant de manière à former le parcours conducteur recherché par apposition d'un parcours conducteur préfabriqué
98.
Chip packaging structure and manufacturing method thereof
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Yang, Kai-Ming
Peng, Chia-Yu
Chen, Pei-Chi
Lin, Pu-Ju
Ko, Cheng-Ta
Abrégé
A chip packaging structure includes a chip, a redistribution layer, a solder ball, an encapsulant, and a stress buffer layer. The chip has an active surface and a back surface opposite to each other, and a peripheral surface connected to the active surface and the back surface. The redistribution layer is disposed on the active surface of the chip. The solder ball is disposed on the redistribution layer, and the chip is electrically connected to the solder ball through the redistribution layer. The encapsulant encapsulates the active surface and the back surface of the chip, the redistribution layer, and part of the solder ball. The stress buffer layer at least covers the peripheral surface of the chip. An outer surface of the stress buffer layer is aligned with a side surface of the encapsulant.
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
99.
Chip package structure and manufacturing method thereof
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Lin, Pu-Ju
Yang, Kai-Ming
Ko, Cheng-Ta
Abrégé
A chip package structure including a chip, a stress buffer layer, a first insulating layer, a redistribution layer, a second insulating layer, and a solder ball is provided. The chip has an active surface, a back surface and a peripheral surface. The stress buffer layer covers the active surface and the peripheral surface, and the first insulating layer is disposed on the back surface. A bottom surface of the stress buffer layer is aligned with the back surface of the chip. The redistribution layer is electrically connected to the chip through an opening of the stress buffer layer. The second insulating layer covers the stress buffer layer and the redistribution layer. The solder ball is disposed in a blind hole of the second insulating layer and electrically connected to the redistribution layer. A top surface of the solder ball protrudes from an upper surface of the second insulating layer.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
Unimicron Technology Corp. (Taïwan, Province de Chine)
Inventeur(s)
Chen, Chun-Hao
Lin, Chia-Lung
Chou, Chien-Hsiang
Chiang, Yi-Lin
Lin, Chien-Chen
Abrégé
A wiring board includes an insulating layer, a wiring layer and a plurality of conductive columns. The insulating layer has a first surface and a second surface opposite to the first surface. The wiring layer is disposed in the insulating layer and has a third surface and a fourth surface opposite to the third surface. The insulating layer covers the third surface, and the second surface of the insulating layer is flush with the fourth surface of the wiring layer. The conductive columns are disposed in the insulating layer and connected to the wiring layer. The conductive columns extend from the third surface of the wiring layer to the first surface of the insulating layer, and protrude from the first surface.
H05K 1/11 - Eléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
H05K 3/40 - Fabrication d'éléments imprimés destinés à réaliser des connexions électriques avec ou entre des circuits imprimés
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H05K 3/06 - Elimination du matériau conducteur par voie chimique ou électrolytique, p.ex. par le procédé de photo-décapage