A data storage device processes a mixed workload including a plurality of superblocks to be written to and read from a plurality of memory dies, where each of the plurality of superblocks to be apportioned among the plurality of memory dies. The data storage device writes a first data stripe associated with a first superblock to the plurality of memory dies according to a sequential write pattern, and reads the first data stripe associated with the first superblock from the plurality of memory dies according to a sequential read pattern. The sequential write pattern causes the controller to write to the plurality of memory dies in a first order of memory dies. The sequential read pattern causes the controller to read from the plurality of memory dies in a second order of memory dies different from the first order of memory dies, thereby reducing read collisions.
C10M 105/54 - Compositions lubrifiantes caractérisées en ce que le matériau de base est un composé organique non macromoléculaire contenant des halogènes contenant du carbone, de l'hydrogène, des halogènes et de l'oxygène
G11B 5/725 - Revêtements protecteurs, p.ex. antistatiques contenant un lubrifiant
C10N 40/18 - Usages électriques ou magnétiques en relation avec des enregistrements sur bandes ou disques magnétiques
3.
HOLD-UP CAPACITOR FAILURE HANDLING IN DATA STORAGE DEVICES
A data storage device includes a plurality of hold-up capacitors configured to provide back-up power for a non-volatile memory, a controller, and a write cache. The controller is configured to detect one or more failed hold-up capacitors of the plurality of hold-up capacitors; and in response to detecting the one or more failed hold-up capacitors: perform one or more quiesce operations and determine a count of the one or more failed hold-up capacitors. Based on the count of the one or more failed hold-up capacitors, the controller is configured to reallocate the write buffers of the write cache for use in one or more subsequent write operations.
The present disclosure generally relates to improving memory management. When valid mSets are relocated via mBlock compaction, the uLayer will have some updates for the mSet and consolidation of the mSet will write the mSet to mBlock once more. The disclosure herein reduces the impact of the problem that the same more frequently updated mSets uRegions are consolidated many times and written to flash where the less updated mSets uRegions become trapped uRegions in the uLayer reducing the uLayer capacity and efficacy. The disclosure provides guidance on how to synchronize the uLayer consolidations efficiently and preventing trapping of unused uRegions in the uLayer that reduces the uLayer capacity and efficiency. The synchronizing is between the uLayer consolidation to the mLayer and the mBlock compaction process such that the smaller uLayer efficacy will not be reduced due to trapped uRegions that are less frequently updated.
Embodiments of the present disclosure relate to a cobalt-boron (CoB) layer for magnetic recording devices, memory devices, and storage devices. In one or more embodiments, the CoB layer is part of a spin-orbit torque (SOT) device. In one or more embodiments, the SOT device is part of an SOT based sensor, an SOT based writer, a memory device (such as a magnetoresistive random-access memory (MRAM) device), and/or a storage device (such as a hard disk drive (HDD) or a tape drive). In one embodiment, an SOT device includes a seed layer, and a cap layer spaced from the seed layer. The SOT device includes a spin-orbit torque (SOT) layer, and a nano layer (NL) between the seed layer and the cap layer. The SOT device includes a cobalt-boron (CoB) layer between the seed layer and the cap layer, and the CoB layer is ferromagnetic.
A glass sheet configured to be cut into glass substrates for magnetic recording disks is described. The glass sheet includes a first surface. For surface features of the first surface with a feature wavelength of 60 to 500 micrometers (μm), a root mean square of a surface topography of the surface features determined using a surface analysis on the first surface with incident and reflected light is given as a microwaviness. A maximum value of the microwaviness of any arbitrary region of the first surface may be between 1.2 nanometers (nm) and 2.8 nm, inclusive of 1.2 nm and 2.8 nm. After the surface analysis, the glass sheet may be cut into the glass substrates in response to determining that the maximum value of the microwaviness is in the noted range. Further, a method of fabricating glass substrates from a glass sheet is described.
The present disclosure generally relates to improved host memory buffer (HMB) segment selection at the initialization phase. Rather than selecting an HMB segment strictly on one parameter, the selection process will consider multiple factors of the HMB segments. Instead of just selecting a HMB segments based on the size of the HMB segment, the data storage device will perform some basic performance measurements on the provided HMB segments before selecting HMB segments. The selection will be based also on the performance results from the various experiments. The experiments are performed in the initialization phase so the performance of the solid state drive (SSD) will not be impacted. The basic experiments include read, write, and mixed operations toward the HMB segments while measuring the performance and QoS.
Various devices, such as storage devices or systems are configured to efficiently process and update logical maps within control table sets. Control table sets are often groupings of logical map corresponding to the logical locations of data requested by a host-computing device and the physical locations of the data within the memory array. As data is written and erased, these maps must be updated within the control table set. Received changes to these maps are typically stored and updated in two locations: a cache memory and a control table update list. By tracking and marking various control table sets as dirty or having undergone multiple changes, additional received updates can be stored and updated in only the cache memory, bypassing the second control table change list. By only utilizing one method of updating control table sets, processing overhead is reduced and various read or write activities are more efficiently done.
A data storage device includes a memory device and a controller coupled to the memory device. The controller and the memory device communicate using a plurality of flash channels, where each channel is mapped to one or more dies of the memory device. Each of the one or more dies of the memory device are associated with one or more strobes of a strobe cycle of a respective flash channel, where a die is provided power during a respective strobe. The controller is configured to, using a time division peak power management (TD-PPM) operation, change an association of a strobe from a first channel to a strobe of a second channel, which may adjust an amount of power provided to each of the channels and improve performance and latency of the data storage device.
G06F 1/3234 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise
G06F 1/3225 - Surveillance de dispositifs périphériques de mémoires
G06F 1/3228 - Surveillance d’exécution de tâches, p.ex. par utilisation de temporisations d’attente, de commandes d’arrêt ou de commandes d’attente
A data storage device includes a controller. The controller includes a controller memory buffer (CMB). The controller is configured to associate both the CMB and a host memory buffer (HMB) of a host device as a single buffer pool with a plurality of CMB buffers and a plurality of HMB buffers. The controller is further configured to allocate either a CMB buffer or a HMB buffer based on a tradeoff between latency and performance between using the CMB or using the HMB to store data. By leveraging the benefits of both the CMB and the HMB to store data, the overall performance of the data storage device may be improved.
The present disclosure generally relates partial speed changes to improve in-order data transfer. Rather than determining an ECC decoder on a first available decoder basis, the ECC decoder may be based on the ECC decoder level. A memory device will have at least one FMU that has a syndrome weight (SW). The disclosure proposes assigning FMU's based on the SW rate. At the time the command is read, the data storage device determines which level of decoder will be assigned to the FMU. The determination will then be checked according to different system environment parameters to maintain performance or reduce power consumption. The arrangement allows a more flexible system design that can adapt according to the current system status.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G11C 29/42 - Dispositifs de vérification de réponse utilisant des codes correcteurs d'erreurs [ECC] ou un contrôle de parité
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
Processing commands received from a host computing device by a storage device can require a large amount of processing overhead. This demand for ever greater processing power increases as the size of storage devices increase. Traditional methods have added an increasing number of processors or CPUs to handle these requirements. However, by utilizing a fast path accelerated processing pipeline, additional processors may not be necessary. An accelerated processing pipeline can be configured to bypass one or more steps that are required by non-priority processing pipelines. Each received command can be parsed to determine if it is suitable for accelerated processing. The command can be required to access data in a limited region of the memory device, or to have any data necessary to process the command already in a cache memory. Upon completion of verifications, commands can be placed in a priority queue that is processed before a non-priority queue.
Aspects of a storage device are provided that requests L2P address translation data from an HMB for execution of an associated host command using a dynamically determined HMB transfer size. The storage device includes a volatile memory and a controller. The controller allocates, in the volatile memory, multiple memory locations for L2P address translation data from an HMB. The controller receives a command indicating a host data length, and transmits a request for a portion of the L2P address translation data stored in the HMB for the command. The HMB transfer size associated with the request may be based on the host data length of the associated host command, a quantity of free and contiguous memory locations available in the HMB read buffer, or a minimum between a size of the portion and a total size of the free and contiguous memory locations. Thus, HMB transfer latency may be reduced.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
The present disclosure generally relates to improved access to the DRAM using namespace mapping. The PMR address range is mapped to LBA address space. Mapping the PMR address range in LBA address space allows the host to access the PMR indirectly using NVMe commands. The host device may hold in the namespace the most frequently accessed data and obtain highest performance and low latency. Implementation of the Power Loss Protection (PLP) feature over the PMR makes the system prefer storing the data in PMR rather in host memory. All internal SRAMs (e.g. Transfer RAMs, XOR RAMs, etc.) may be mapped in the LBA address space so the host device can access mainly for debug purposes. Some internal flops that hold important data are mapped in the LBA address space as well.
The present disclosure generally relates to improving space efficiency when storing logical to physical (L2P) entries. Rather than writing a physical block address (PBA) spanning multiple entries, the PBA is split between a first portion stored in the buffer with the remaining bits of the PBA added to the metadata buffer. The metadata buffer is sub-optimal due to the small size of the metadata relative to the entry and therefore, adding extra bits to the metadata buffer will make the metadata buffer more optimal. In this scheme, the alignment is preserved, the system becomes more optimal in terms of DRAM access, and the metadata buffer can be easily optimized and adapted.
G06F 12/02 - Adressage ou affectation; Réadressage
G06F 11/08 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle
16.
METADATA MANAGEMENT IN KEY VALUE DATA STORAGE DEVICE
A data storage device includes a memory device and a controller to the memory device. The controller is configured to receive key value (KV) pair data having a key and a value from a host device and generate a mapping in a key-to-physical (K2P) table corresponding to the received KV pair data. The mapping includes a first slot for storing a physical address corresponding to the value and a second slot for storing a physical address corresponding to metadata associated with the KV pair data. When the associated metadata is sent to the data storage device, which may be non-concurrent to transferring the KV pair data, the mapping of the associated metadata is linked to a same key as the mapping of the KV pair data. Thus, using the mapping, the key of the KV pair data is associated with the KV pair data and the associated metadata.
A data storage device includes a memory device and a controller. The controller is configured to assert a strobe cycle having a plurality of strobes to the memory device, where a die of the memory device may be associated with one or more strobes of the plurality of strobes. The controller is further configured to determine whether the die of the memory device requires additional power and adjust a strobe length of time of the corresponding strobe when the die of the memory device requires additional power. The controller is further configured to decrease a strobe length of time of one or more strobes that do not require additional power. By utilizing a time division peak power management (TD-PPM) feature by dynamically changing a strobe length of time of each strobe of the plurality of strobes, performance and latency of the data storage device may be improved.
G06F 1/3234 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise
G06F 1/3228 - Surveillance d’exécution de tâches, p.ex. par utilisation de temporisations d’attente, de commandes d’arrêt ou de commandes d’attente
G06F 1/329 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par planification de tâches
The present disclosure generally relates to aligning non-aligned data for more efficient data reading. Data for write commands does not always perfectly align, yet the data is written in order of write command receipt. In such cases, aligned chunks of data may be split into two word lines (WLs) due to the presence of previously received smaller chunks of data. Rather than writing the data in order, the smaller chunks of data, which are non-aligned, are held in a buffer and written later to ensure that any aligned chunks of data remain aligned when written to the memory device. Once sufficient smaller chunks or data have accumulated to be aligned, or upon a need to write the smaller chunks upon reaching a threshold, the smaller chunks are written together in a single WL so as to not cause non-alignment of aligned data.
The present disclosure generally relates to improving adaptive tuning of different clock rates of a memory device. Rather than clock rates only being determined off of one parameter such as workload, the clock rates now will be determined using multiple parameters. The tuning may be based on system parameters to allow the system to withstand challenges that arise during the operation. The clock frequency table is maintained in the device controller. The table holds the clock frequency of each component. The disclosure proposes modifying the table according to different system environment parameters to maintain performance or reduce power consumption. Adaptive tuning allows a more flexible system design that can adapt according to the current system status. Adaptive tuning also reduces peak power consumption, improves performance, and better quality of service (QoS) compatibility characteristics.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 16/14 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
Disclosed are systems and methods for accelerating commands from accelerators in data storage devices using accelerator queues. A data storage device includes accelerator interfaces, each accelerator interface couples a controller to a respective accelerator. The device also includes a device memory comprising one or more memories and one or more sets of queues. Each set of queues corresponds to a respective memory, at least one queue is configured to queue one or more tasks associated with an accelerator, and each queue is associated with a respective priority level of a plurality of priority levels. A controller is configured to: receive an accelerator command, identify a first memory corresponding to a task for the accelerator command; and enqueue the task to a first queue corresponding to the first memory, the first queue configured to queue one or more tasks associated with the first accelerator corresponding to the first accelerator interface.
Zone Write Groups (ZWGs) to assist data storage devices and host devices with data recovery. In one embodiment, a data storage device includes a memory storing a Zoned NameSpace (ZNS). The ZNS includes a ZWG including host zones and parity zones. An interface connects the data storage device with a host device. The data storage device includes a data storage device controller including an electronic processor and a memory. The data storage device controller populates the ZWG with buffers received from the host device. The data storage device controller detects corrupted data associated with the ZNS and requests one or more buffers stored in the ZWG. Once the data storage device controller receives the one or more buffers from the ZWG, the data storage device controller performs a recovery event with the one or more buffers.
A data storage device includes a host interface for coupling the data storage device to a host system. The data storage device also includes a device memory and a controller. The controller is configured to determine if a retrim is needed for the data storage device. In accordance with a determination that the retrim is needed, the controller is configured to identify a time to initiate a new trim on the data storage device, and cause the new trim on the data storage device at the time identified.
Disclosed are systems and methods for large write planning for performance consistency and resource usage efficiency. A method is implemented using one or more controllers for one or more storage devices. The method includes receiving, via a host interface, a notification of a write data burst. The method also includes computing available spaces in a plurality of memories and a write ratio, to handle the write data burst to the plurality of memories, based on the notification. The method also includes receiving, via the host interface, the write data burst. The method also includes, in response to receiving the write data burst, toggling writes between the plurality of memories, based on the available spaces and the write ratio.
A heat‑assisted magnetic recording (HAMR) head has a slider with a gas-bearing-surface (GBS). The slider supports a near-field transducer (NFT) with an output tip at the GBS and a main magnetic pole that has a recess in the NFT-facing surface that contains plasmonic material. The plasmonic recess has a front edge at the GBS that has a cross-track width equal to or less than the cross-track width of the widest portion of the NFT output tip, and a back edge recessed from the GBS. A thermal shunt is located between the NFT and the main pole to allow heat to be transferred away from the optical spot generated by the NFT output tip, and is in contact with a region of the plasmonic recess near the back edge.
G11B 5/00 - Enregistrement par magnétisation ou démagnétisation d'un support d'enregistrement; Reproduction par des moyens magnétiques; Supports d'enregistrement correspondants
A semiconductor device having one or more bifacial semiconductor wafers. The bifacial semiconductor wafer includes a first array of semiconductor dies on a first planar surface and a second array of semiconductor dies on a second planar surface that is opposite the first planar surface. The first array of semiconductor dies are electrically coupled via a first redistribution layer and the second array of semiconductor dies are electrically coupled via a second redistribution layer. One or more through silicon vias electrically couple the first array of semiconductor dies with the second array of semiconductor dies.
H10B 41/20 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
H10B 43/20 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to compare a first copy of a boot partition to a second copy of the boot partition. The first copy of the boot partition and the second copy of the boot partition each comprises a same number of a plurality of boot chunks. The boot partition corresponds to data of a boot operation of a host device. The controller is further configured to mark one or more of the compared boot chunks that equals or exceeds a similarity threshold and update a reliability index based on the marking. Based on the marking and the reliability index, the controller may increase or decrease an amount of error correction needed for the boot data.
1f1f22222n2222n22322222mn2222n11 is the functional group. A lubricant is formed from a multiple ether segments according to formula: Re1-Rb1-Ri-Rc-Ri-Rb2-Re2; where Rc includes perfluoroalkyl ether, Rb1and Rb2are, independently, a sidechain segment including a perfluoroalkyl ether, optional Ri independently is a divalent linking segment including a functional group including elements from periodic table Group 13–17, and of Re1and Re2 are phosphonic acid, silanol or carboxylic acid. Lubricant synthesis includes reacting a perfluorinated polyether with a halogenated functional group, selected from phosphonic acid, silanol or carboxylic acid.
The present disclosure generally relates to improved handling of write commands. The host memory buffer (HMB) or other storage space can be utilized to delay execution of host write commands which will improve write performance in different use cases and will also allow having more concurrent streams than open blocks without impacting write or read performance. Generally, once a write command is received, the write command is revised as a new write command that is logically equivalent to the original write command. The revised write command is moved to the HMB along with the data. In so doing, the write command is coalesced and write command handling is improved.
Technology is disclosed herein for detecting leaky word lines in a non-volatile storage system. The exact leaky word line may be located very rapidly using a divide and conquer approach. Fist a determination may be made whether at least one word line in a group such as any of the word lines in a block is leaky. This initial determination can be made very quickly. If no word line in the group is leaky, the search can end. However, responsive to a determination that at least one word line in the group is leaky, a divide and conquer search may be performed in which the group of the word lines is repeatedly divided into smaller sub-groups with selected smaller sub-groups tested for a short circuit until the leaky word line is located.
Technology is disclosed herein for detecting grown bad blocks in a non-volatile storage system. A stress test may accelerate stressful conditions on the memory cells and thereby provide for early detection of grown bad blocks. The stress test may include applying a program voltage to a selected word line and a stress voltage that is less than a nominal boosting voltage to a word line adjacent one side of the selected word line. The combination of the program voltage and the stress voltage may generate an e-field that is stronger than an e-field that would be generated in a normal program operation, thereby accelerating the stress on the memory cells. The stress test mat further include programming all of the memory cells to a relatively high threshold voltage, which may create additional stress on the memory cells.
G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p.ex. compteurs de rafraîchissement défectueux
G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
G11C 8/14 - Organisation de lignes de mots; Disposition de lignes de mots
G11C 16/16 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p.ex. des réseaux, des mots, des groupes
G11C 29/12 - Dispositions intégrées pour les tests, p.ex. auto-test intégré [BIST]
A data storage device includes a controller. The controller is coupled to a host device. The controller is configured to determine a quality of a peripheral component interconnect express (PCIe) link, wherein the quality of the PCIe link is either greater than or less than a threshold quality, and transmit an error notification to the host device via a sideband when the quality of the PCIe link is less than the threshold quality. The sideband is a different communication channel than the PCIe link. The error notification includes additional information regarding events occurring in the data storage device resulting in the quality of the PCIe link.
A storage system is provided that performs a defragmentation operation or proactive garbage collection in its memory based on a command from a host. The command specifies which blocks in the memory should take part in the defragmentation operation by specifying a maximum amount of valid data that a block can have to qualify for defragmentation. That way, the storage system only performs defragmentation on those blocks that meet the validity criteria provided by the host. This can help improve performance of the storage system while reducing the degree of negative tradeoffs that may come with defragmentation or proactive garbage collection.
The present disclosure generally relates to spin-orbit torque (SOT) devices comprising a bismuth antimony (BiSb) layer. The SOT devices further comprises a nonmagnetic buffer layer, a nonmagnetic interlayer, a ferromagnetic layer, and a nonmagnetic barrier layer. One or more of the barrier layer, interlayer, and buffer layer comprise a polycrystalline non-Heusler alloy material, or a Heusler alloy and a material selected from the group consisting of: Cu, Ag, Ge, Mn, Ni, Co, Mo, W, Sn, B, and In. The Heusler alloy is a full Heusler alloy comprising X2YZ or a half Heusler alloy comprising XYZ, where X is one of: Mn, Fe, Co, Ni, Cu, Ru, Rh, Pd, Ag, Ir, Pt, and Au, Y is one of: Ti, V, Cr, Mn, Fe, Co, Ni, Zn, Y, Zr, Nb, Mo, Hf, and W, and Z is one of: B, Al, Si, Ga, Ge, As, In, Sn, Sb, and Bi.
The present disclosure generally relates to a XTS cache operation during a power down event. Upon detection of power loss, data that is waiting to be encrypted needs to be flushed to the memory device. For any unaligned data or data less than a flash management unit (FMU) size, the data is grouped together and, if necessary, padded to reach the FMU size and then encrypted, merged with other data FMUs, and written to the memory device. Grouping the unaligned data reduces the amount of padding necessary to reach FMU size and also reduces the amount of data to be encrypted. As such, data flushing can be accomplished using the limited amount of remaining power during the power loss event.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache
Multi-signal vias for use with differential pair signals in electronic devices. The electronic devices include a printed circuit board having a first side and a second side opposite the first side, a first conductive trace on the first side of the substrate and a second conductive trace on the first side of the substrate. The printed circuit board also includes a shared via, which includes a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are separated by a non-conductive portion. The first conducive trace is coupled to the first conductive portion of the shared via and the second conductive trace is coupled to the second conductive portion of the shared via.
A data storage device having a flash translation layer configured to handle file-system defragmentation in a manner that avoids, reduces, and/or optimizes physical data movement in flash memory. In an example embodiment, the memory controller maintains in a volatile memory thereof a lookaside table that supplants pertinent portions of the logical-to-physical table. Entries of the lookaside table are configured to track source and destination addresses of the host defragmentation requests and are logically linked to the corresponding entries of the logical-to-physical table such that end-to-end data protection including the use of logical-address tags to the user data can be supported by logical means and without physical data rearrangement in the flash memory. In some embodiments, physical data rearrangement corresponding to the file-system defragmentation is performed in the flash memory in response to certain trigger events, which can improve the input/output performance of the data-storage device.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/1027 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p.ex. un répertoire de pages actives [TLB]
37.
LOGICAL-TO-PHYSICAL MAPPING FOR DEFRAGMENTATION OF HOST FILE SYSTEM IN A DATA STORAGE DEVICE
A data storage device having a flash translation layer configured to handle file-system defragmentation in a manner that substantially avoids physical data movement in a flash memory. In an example embodiment, a memory controller operates to update a logical-to-physical table thereof to change association of physical addresses of sections of user data from being associated with source logical addresses to being associated with destination logical addresses of the host defragmentation requests without moving the user data in the flash memory. Such updates can reduce the number of instances in which the host addresses a non-contiguous logical-address range, which results in a beneficial reduction of the number of input/output commands sent to the data storage device and of the associated processing overhead.
Disclosed are systems and methods detecting and isolating faulty hold-up capacitors and performing corrective actions for a data storage device. A hardware circuit is coupled to a micro-controller and non-volatile memory dies. The method includes, at the hardware circuit: providing a back-up power for the non-volatile memory dies and the micro-controller; and detecting whether a hold-up capacitor of the hardware circuit is faulty and isolating the hold-up capacitor in accordance with a detection that the hold-up capacitor is faulty. The method also includes, at the micro-controller: obtaining a status of an interface coupled to the hardware circuit; determining a status of the hardware circuit based on the status of the interface; and performing a corrective action for the data storage device in accordance with a determination that the status of hardware circuit corresponds to one or more faulty hold-up capacitors.
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to segment a key to physical (K2P) table into two or more segments, wherein each segment of the two or more segments corresponds to a caching priority of key value (KV) pair data, organize the K2P table by storing and relocating one or more K2P table entries into a respective segment of the two or more segments, wherein the storing and relocating comprises moving a K2P table entry based on the caching priority of the KV pair data into the respective segment having the caching priority, and utilize the K2P table to manage KV pair data stored in the memory device, wherein utilizing the K2P table comprises applying a same management operation, such as prefetching, to each K2P table entry of a same segment.
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
G06F 12/0862 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec pré-lecture
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
A data storage device comprising a non-volatile storage medium configured to store user data, a data port configured to transmit data between a host computer system and the data storage device, a display system, and a controller. The controller is configured to receive and execute one or more commands from the host computer system to cause a data transfer between the host computer system and the storage medium of the data storage device. The controller generates performance data representing the performance of the data storage device, wherein the performance data includes an efficiency ratio value representing a relative utilization of an operational capability of the data storage device in conducting the data transfer. The controller generates one or more control signals to cause the display system to visually indicate at least the efficiency ratio value of the performance data.
A data storage device comprises a non-volatile storage medium configured to store user data, a data port configured to transmit data between a host computer system and the data storage device, a beacon component, and a power manager configured to provide electrical energy to the beacon component. The beacon component is configured to wirelessly transmit a signal in accordance with a beacon configuration, and, in response to determining a power availability level associated with the power manager, adjust the beacon configuration to change a rate of consumption of electrical energy by the beacon component.
H02J 50/40 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant plusieurs dispositifs de transmission ou de réception
42.
AUDIO SENSORS FOR CONTROLLING SURVEILLANCE VIDEO DATA CAPTURE
Systems, video cameras, and methods for using audio sensors to control surveillance video capture are described. A video camera and audio sensor are deployed so that the audio sensor has an audio field that is at least partially outside the field of view of the video camera. The audio sensor collects audio data from the audio field and a controller for the video camera uses audio events from the audio data for modifying the video capture operations of the video camera. Video data is then captured based on the modified video capture operations, such as initiating video capture, changing the video capture rate, or changing the camera position.
H04N 7/18 - Systèmes de télévision en circuit fermé [CCTV], c. à d. systèmes dans lesquels le signal vidéo n'est pas diffusé
H04N 23/58 - Moyens permettant de modifier le champ de vision de la caméra sans déplacer le corps de la caméra, p. ex. par nutation ou pivotement des optiques ou des capteurs d'images
H04N 23/69 - Commande de moyens permettant de modifier l'angle du champ de vision, p. ex. des objectifs de zoom optique ou un zoom électronique
H04N 23/695 - Commande de la direction de la caméra pour modifier le champ de vision, p. ex. par un panoramique, une inclinaison ou en fonction du suivi des objets
G10L 25/57 - Techniques d'analyses de la parole ou de la voix qui ne se limitent pas à un seul des groupes spécialement adaptées pour un usage particulier pour comparaison ou différentiation pour le traitement des signaux vidéo
G10L 25/27 - Techniques d'analyses de la parole ou de la voix qui ne se limitent pas à un seul des groupes caractérisées par la technique d’analyse
Example storage systems, data storage devices, and methods provide redundant array of independent disk (RAID) control among peer storage devices. A master storage device among peer storage devices receives host commands and determines, based on a peer RAID configuration, data blocks for redundantly storing the host data unit among the peer storage devices. The master storage device allocates the data blocks among the peer storage devices and sends them to the peer storage devices using a peer communication channel.
A data storage device comprising a non-volatile storage medium configured to store user data, a data port configured to transmit data between a host computer system and the data storage device, a data security indicator, and a controller. The controller is configured to selectively control access of the host computer system to the user data based on security configuration data of the data storage device. The controller is further configured to respond to the occurrence of one or more operations, the operations being any of: (i) a data access operation requested or performed, by the host computer system, on the data storage device to access the storage medium via the data port; and (ii) a security control operation requested or performed, by an external device, on the data storage device to store, retrieve or update the security configuration data of the data storage device. The response of the controller includes generating an indicator control signal to cause the data security indicator to indicate one or more security parameters associated with the one or more operations.
In some situations, a leak on a wordline may be a localized problem that causes data loss in a block that contains the wordline. In other situations, such as when the leak occurs near a peripheral wordline routing area, the leak can affect the entire memory die. The storage system provided herein has a fatal wordline leak detector that determines the type of leak and, accordingly, whether just the block should be retired or whether related blocks should be retired.
The present disclosure generally relates to spin-orbit torque (SOT) device comprising a first bismuth antimony (BiSb) layer having a (001) orientation. The SOT device comprises a first BiSb layer having a (001) orientation and a second BiSb layer having a (012) orientation. The first BiSb layer having a (001) orientation is formed by depositing an amorphous material selected from the group consisting of: B, Al, Si, SiN, Mg, Ti, Sc, V, Cr, Mn, Y, Zr, Nb, AlN, C, Ge, and combinations thereof, on a substrate, exposing the amorphous material to form an amorphous oxide surface on the amorphous material, and depositing the first BiSb layer on the amorphous oxide surface. By utilizing a first BiSb layer having a (001) orientation and a second BiSb having a (012) orientation, the signal through the SOT device is balanced and optimized to match through both the first and second BiSb layers.
Devices and techniques are disclosed wherein an end user can remotely trigger direct data management activities of a data storage device (DSD), such as creating a data snapshot, resetting a snapshot, and setting permissions at the DSD via a remote mobile device app interface.
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
H04W 4/80 - Services utilisant la communication de courte portée, p.ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
G06F 12/1009 - Traduction d'adresses avec tables de pages, p.ex. structures de table de page
A data storage device comprises a non-volatile storage medium configured to store user data, a data port configured to transmit data between a host computer system and the data storage device, an energy harvesting component configured to produce electrical energy from an ambient energy source, and a beacon component, configured to wirelessly transmit a signal. The beacon component is configured to consume the electrical energy to wirelessly transmit the signal. The data storage device may further comprise an energy store configured to store the electrical energy produced by the energy harvesting component as stored energy.
G06F 13/14 - Gestion de demandes d'interconnexion ou de transfert
G06F 13/38 - Transfert d'informations, p.ex. sur un bus
H04W 4/80 - Services utilisant la communication de courte portée, p.ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
H01L 31/042 - Modules PV ou matrices de cellules PV individuelles
Various illustrative aspects are directed to a data storage device, comprising one or more disks; at least one actuator mechanism configured to position at least a first head proximate to a first disk surface and a second head proximate to a second disk surface; and one or more processing devices. The one or more processing devices are configured to: assign logical tracks to physical tracks of the disk surfaces such that a respective logical track comprises: at least a portion of sectors of a primary physical track, the primary physical track being on the first disk surface; and at least a portion of sectors of a donor physical track, the donor physical track being on the second disk surface. The one or more processing devices are configured to perform, using the first head and the second head, a data access operation with at least one of the logical tracks.
G11B 19/14 - Commande de fonctionnement, p.ex. commutation "enregistrement–reproduction" par détection du déplacement ou de la position de la tête, p.ex. moyens se déplaçant en correspondance avec les mouvements de la tête
G11B 25/04 - Appareils caractérisés par la forme du support d'enregistrement employé mais non spécifiques du procédé d'enregistrement ou de reproduction utilisant des supports d'enregistrement plats, p.ex. disques, cartes
DOPED BISB (012) OR UNDOPED BISB (001) TOPOLOGICAL INSULATOR WITH GENIFE BUFFER LAYER AND/OR INTERLAYER FOR SOT BASED SENSOR, MEMORY, AND STORAGE DEVICES
The present disclosure generally relates to a magnetic recording device having a magnetic recording head comprising a spintronic device. The spintronic device is disposed between a main pole and a trailing shield at a media facing surface. The spintronic device comprises a spin torque layer (STL) and a multilayer seed layer disposed in contact with the STL. The spintronic device may further comprise a field generation layer disposed between the trailing shield and the STL. The multilayer seed layer comprises an optional high etch rate layer, a heat dissipation layer comprising Ru disposed in contact with the optional high etch rate layer, and a cooling layer comprising Cr disposed in contact with the heat dissipation layer and the main pole. The high etch rate layer comprises Cu and has a high etch rate to improve the shape of the spintronic device during the manufacturing process.
The present disclosure generally relates to a magnetic recording head comprising a spintronic device. The spintronic device is disposed between a main pole and a trailing shield of the magnetic recording head. The spintronic device comprises a multilayer spacer layer comprising a Cu layer in contact with a spin torque layer and a spin transparent texture layer disposed on the Cu layer, the spin transparent texture layer comprising AgSn or AgZn. A multilayer notch comprising a CoFe layer is disposed over the spin transparent texture layer of the multilayer spacer layer and a Heusler alloy layer is disposed on the CoFe layer, the Heusler alloy layer comprising CoMnGe, CoFeGe, or CoFeMnGe. The multilayer spacer layer and the multilayer notch result in the spintronic device having a high spin polarization and a reduced critical current.
G11B 5/31 - Structure ou fabrication des têtes, p.ex. têtes à variation d'induction utilisant des films minces
G11B 5/127 - Structure ou fabrication des têtes, p.ex. têtes à variation d'induction
G11B 5/00 - Enregistrement par magnétisation ou démagnétisation d'un support d'enregistrement; Reproduction par des moyens magnétiques; Supports d'enregistrement correspondants
Disclosed are systems and methods for proactively recovering files stored in flash storage devices. The method may be performed at a flash file system. The method may include receiving a write command targeting a first file in a flash memory. The method may also include generating a reference hash corresponding to the first file, and storing the reference hash in the flash memory. The method may also include receiving a read command targeting the first file. In response to receiving the read command, the method may also include: providing a request for a logical block address corresponding to the first file to the flash manager, and receiving a response for the read command. The method may also include, in accordance with a determination that one or more hashes do not map to the first file, performing a file recovery operation for a second file based on the one or more hashes.
Example storage systems, data storage devices, and methods provide rate levelling among peer storage devices. A master storage device among peer storage devices receives host commands, determines the workload states of the peer storage devices, divides the data units in the host commands into data blocks for data striping, allocates the data blocks among the peer storage devices, and sends the data blocks to the peer storage devices using a peer communication channel.
Disclosed are systems and methods providing active time-based prioritization in host-managed stream devices. The method includes receiving a plurality of host commands from a host system. The method also includes computing active times of open memory regions. The method also includes determining one or more regions that have remained open for more than a threshold time period, based on the active times. The method also includes prioritizing one or more host commands from amongst the plurality of host commands for completion, the one or more host commands having corresponding logical addresses belonging to the one or more regions, thereby (i) minimizing risk to data and (ii) releasing resources corresponding to the one or more regions.
Various illustrative aspects are directed to a data storage device, comprising: one or more disks; an actuating mechanism comprising one or more heads, and configured to position the one or more heads proximate to disk surfaces of the one or more disks; and one or more processing devices. The one or more processing devices are configured to: determine a first burst value based on an averaged value of a first set of one or more bursts; determine a second burst value based on an averaged value of a second set of one or more bursts; generate a position error signal (PES) based on the determined first burst value and the determined second burst value; and control a position of at least one head among the one or more heads based on the PES.
The devices, methods, and apparatuses of the present disclosure address a lack of parallelism in a typical approach by eliminating the static mapping of the two or more low-density parity check (LDPC) engines to a plurality of flash controllers. The devices, methods, and apparatuses of the present disclosure include a dynamic LDPC mapping to the plurality of flash controllers.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
58.
STORAGE SYSTEM AND METHOD FOR INFERENCE OF READ THRESHOLDS BASED ON MEMORY PARAMETERS AND CONDITIONS
A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service.
A data storage device and method for enabling metadata-based seek points for media access are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to identify a plurality of frames in video data that differ from surrounding frames by more than a threshold amount; store identifiers of the plurality of frames in the memory; and send the identifiers to the host to enable quick playback of the video data by the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
H04N 21/472 - Interface pour utilisateurs finaux pour la requête de contenu, de données additionnelles ou de services; Interface pour utilisateurs finaux pour l'interaction avec le contenu, p.ex. pour la réservation de contenu ou la mise en place de rappels, pour la requête de notification d'événement ou pour la transformation de contenus affichés
H04N 21/433 - Opération de stockage de contenu, p.ex. opération de stockage en réponse à une requête de pause ou opérations de cache
H04N 21/432 - Opération de récupération de contenu d'un support de stockage local, p.ex. disque dur
H04N 21/845 - Structuration du contenu, p.ex. décomposition du contenu en segments temporels
60.
SEMICONDUCTOR WAFER THINNED BY HORIZONTAL STEALTH LASING
A method includes the step of thinning a semiconductor wafer by a horizontal stealth lasing process, and semiconductor wafers, dies and devices formed thereby. After formation of an integrated circuit layer on a semiconductor wafer, the wafer may be thinned by supporting an active surface of the wafer on a rotating chuck, and focusing a horizontally-oriented laser in multiple cycles at different radii within the rotating wafer. Upon completion of the multiple cycles, a portion of the wafer substrate may be removed, leaving the wafer thinned to its final thickenss. Thereafter, a vertical stealth lasing process may be performed to cut individual semicondcutor dies from the thinned wafer.
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
H01L 21/268 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée les radiations étant électromagnétiques, p.ex. des rayons laser
H01L 21/304 - Traitement mécanique, p.ex. meulage, polissage, coupe
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive key value (KV) pair data from a host device, where the KV pair data includes a key and a value, determine whether the KV pair data corresponds to a first tier or a second tier, where the second tier has a lower performance requirement than the first tier, and program the value of the KV pair data as padding data when the KV pair data corresponds to the second tier. The determining is based on a received hint of the KV pair data, a relative performance of the KV pair data, and a length of the KV pair data. The controller is configured reclassify the KV pair data based on a read frequency of the KV pair data.
G06F 12/0864 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant des moyens pseudo-associatifs, p.ex. associatifs d’ensemble ou de hachage
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
A data storage device having improved protections for in-flight data during a safety event, such as an autonomous-driving-vehicle collision. In an example embodiment, in response to a distress-mode indication signal, the device controller operates to prioritize more-recent data with respect to older counterparts of the same data stream for flushing from the volatile-memory buffers to the non-volatile memory. In addition, the device controller may operate to positively bias the flushed data towards better survivability and/or more-reliable routing.
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to generate a first mapping portion and a second mapping portion, where the first mapping portion and the second mapping portion correspond to a same data set, and where the first mapping portion and the second mapping portion includes one or more parity bits, receive an update for the same data set, update the first mapping portion and the second mapping portion based on the update, where the second mapping portion is updated non-concurrently to updating the first mapping portion, and where the updating includes flipping a parity bit of the one or more parity bits, and determine whether the one or more parity bits of the first mapping portion matches the one or more parity bits of the second mapping portion.
A data storage device and method for host buffer management are provided. In one embodiment, a data storage device is provided comprising a non-volatile memory and a controller. The controller is configured to receive a read command from a host; read data from the non-volatile memory; identify a location in a host memory buffer (HMB) in the host that is available to store the data; write the data to the location in the HMB; and inform the host of the location in the HMB that stores the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
Systems and methods for data migration via a peer communication channel between data storage devices are disclosed. The data storage devices include a host interface configured to connect to at least one host system and a peer interface to connect to the peer communication channel, where the host interface and the peer interface and separate physical interfaces. A source data storage device establishes peer communication with a destination data storage device over the peer communication channel, determines a set of host data, and sends the set of host data to the destination data storage device, while continuing to receive and process host storage operations through the host interface.
The present disclosure generally relates to ensuring a plasma plume or cloud that forms during a laser cutting process does not lead to undesired re-deposition of material onto the substrate. At least one electrode is biased to draw the electrons of the plasma plume or cloud towards the electrode and away from the substrate. A vacuum port and/or a blower may be strategically located to ensure proper gas flow away from the substrate and hence, directing of the electrons away from the substrate. In so doing, material re-deposition is less likely to occur.
B23K 26/38 - Enlèvement de matière par perçage ou découpage
B23K 26/354 - Travail par rayon laser, p.ex. soudage, découpage ou perçage pour le traitement de surface par fusion
B23K 26/142 - Travail par rayon laser, p.ex. soudage, découpage ou perçage en utilisant un écoulement de fluide, p.ex. un jet de gaz, associé au faisceau laser; Buses à cet effet pour l'enlèvement de résidus
B23K 26/402 - Enlèvement de matière en tenant compte des propriétés du matériau à enlever en faisant intervenir des matériaux non métalliques, p.ex. des isolants
A storage system receives an instruction to cancel an in-progress read/write command. The storage system allows data associated with the command to continue to be processed by a data path in the storage system even though the command was cancelled. However, before the data is actually transferred out of the data path, a controller determines that the command was cancelled and prevents the data from being transferred out, while internally indicating that the transfer was complete. This provides a faster cancellation process than methods that attempt to stop the data from being processed by the data path.
Systems and methods for managing write stream workload of video surveillance systems through playback workload triggered dynamic capture are described. A video camera may include a video image sensor for receiving video data. The video data may be written to a storage device. A request for access to the video data may then be received. An impact on a standard data write stream may be determined based on the time window determined for the access to the video data. At least one mitigation option may be initiated at the video image sensor as a result.
H04N 7/18 - Systèmes de télévision en circuit fermé [CCTV], c. à d. systèmes dans lesquels le signal vidéo n'est pas diffusé
H04N 21/274 - Stockage de contenu ou données additionnelles spécifiques aux utilisateurs finaux en réponse aux requêtes des utilisateurs finaux
H04N 5/77 - Circuits d'interface entre un appareil d'enregistrement et un autre appareil entre un appareil d'enregistrement et une caméra de télévision
H04N 5/92 - Transformation du signal de télévision pour l'enregistrement, p.ex. modulation, changement de fréquence; Transformation inverse pour le surjeu
H04N 23/54 - Montage de tubes analyseurs, de capteurs d'images électroniques, de bobines de déviation ou de focalisation
69.
SYSTEMS AND METHODS OF IMPROVED MODULAR INVERSION WITH DIGITAL SIGNATURES
A method includes receiving a message and a digital signature associated with a signing party and the message, verifying authenticity of the digital signature using elliptic curve cryptography (ECC), and authenticating use of the message based, at least in part, on the confirmed authenticity of the digital signature. The verifying includes one or more computations involving computing modular inverses. Computing modular inverses includes identifying first and second integer of a modular inverse operation, performing a first iterative process that, at each iteration: (i) initializes a third integer with a pre-defined number of most significant bits of the first integer and a fourth integer with the pre-defined number of most significant bits of the second integer and (ii) computes a quotient and a remainder, determining a resultant inverse value using the quotient; and confirming the authenticity of the digital signature based, at least in part, on the resultant inverse value.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
H04L 9/30 - Clé publique, c. à d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
70.
VARIABLE LENGTH ECC CODE ACCORDING TO DATA ENTROPY IN NVME KEY VALUE PAIR DEVICES
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive key value (KV) pair data, determine an entropy value of the received KV pair data, select an error correction code (ECC) code rate based on the determined entropy value, and program the KV pair data to a codeword (CW). The KV pair data includes a key and a value. The programming includes encoding the KV pair data using the selected ECC code rate. The controller is further configured to aggregate a portion of another KV pair data and the KV pair data and program the aggregated KV pair data to the CW using a selected ECC code rate.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 11/08 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle
71.
DIE SEPARATION RING FOR WAFERS HAVING A LARGE DIE ASPECT RATIO
A die separation ring that causes non-uniform expansion of a semiconductor wafer during a semiconductor wafer expansion process. The die separation ring includes an annular body that extends about a central axis. The annular body of the die separation ring includes a first portion having a first elevation and a second portion having a second elevation that is lower than the first elevation. A third portion extends between the first portion and the second portion forming a transition between the first portion and the second portion.
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
H01L 21/687 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension en utilisant des moyens mécaniques, p.ex. mandrins, pièces de serrage, pinces
A flexible fastener captivator includes a flange comprising an orifice configured to enable a fastener to pass through and an adhesive, and a flexible cap coupled with the flange and configured to provide operational access to a fastener encapsulated within the cap, where the cap includes a retaining structure configured to hold a separate fastener within the cap. The retaining structure may be configured as a plurality of flexible ledges extending from an inner surface of the cap and having a planar surface configured to support a head of a separate fastener, such as a standard off-the-shelf screw or bolt. Such a captivator can be dimensioned commensurate with the fastener type and size for which its use is intended, and/or captivator strips may be constructed in Rack Units of length.
F16B 5/02 - Jonction de feuilles ou de plaques soit entre elles soit à des bandes ou barres parallèles à elles par organes de fixation utilisant un filetage
B25B 23/00 - OUTILS OU OUTILLAGE D'ÉTABLI NON PRÉVUS AILLEURS, POUR FIXER, JOINDRE, DÉSENGAGER OU TENIR - Parties constitutives ou accessoires des clés à écrous, clés anglaises, tournevis
B25B 23/08 - Dispositions pour manipuler les vis ou écrous pour tenir ou présenter la vis ou l'écrou avant ou pendant sa rotation
73.
ALIGNMENT OPTIMIZATION OF KEY VALUE PAIR DATA STORAGE
A data storage device includes a memory device and a controller coupled to the memory device. The controller is further configured to receive a key value (KV) pair data, determine a size of a value length and a size of a target wordline of the memory device for programming of the KV pair data, determine a size of residual data, store the residual data in a location separate from the target wordline and the KV pair data minus the residual data to the target wordline, and read the residual data from the location separate and the target wordline data in response to a read command for the KV pair data. The size of the value length is greater than the size of the target wordline. The size of the residual data is the size of the value length minus the size of the target wordline.
Aspects of a storage device are thermal management of a non-volatile storage device are provided. In various embodiments, a storage device includes corresponding memory locations on two or more dies. Corresponding memory locations on each die form an addressable group. A controller in thermal communication with each of the dies may detect an excess temperature on one of the dies while performing sequential host writes. Upon such detection, the controller may disable all writes to the detected die while continuing to perform writes to the memory locations of the other dies without throttling the other dies. The controller may then reactivate writes to the detected die when the temperature drops below a threshold.
Aspects of a storage device are provided that apply advanced thermal throttling with multi-tier extreme thermal throttling. Initially, a controller determines whether a first temperature measurement indicates that a temperature of the memory meets a first thermal threshold associated with a first-tier extreme thermal throttling or a second thermal threshold associated with a second-tier extreme thermal throttling. Subsequently, the controller enables the first-tier extreme thermal throttling when the temperature measurement indicates that the temperature of the memory meets the first thermal threshold, or the controller enables the second-tier extreme thermal throttling when the temperature measurement indicates that the temperature of the memory meets the second thermal threshold. The controller then determines whether a second temperature measurement indicates that the temperature of the memory has decreased to avoid thermal shutdown of the storage device. Storage device performance is thus improved through advanced thermal throttling without compromising data integrity.
G11C 7/04 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les effets perturbateurs thermiques
Aspects of a storage device are provided which apply advanced thermal throttling in response to temperature changes based on multiple thermal power states for different types of cells, such as SLCs and MLCs. Initially, a controller determines that a temperature of the memory meets a thermal throttling threshold of a plurality of thermal throttling thresholds. Subsequently, the controller transitions into a thermal power state of a plurality of thermal power states when the temperature meets the thermal throttling threshold. The controller applies a thermal mitigation configuration associated with the thermal power state. The controller then determines that the temperature of the memory has reached a thermal equilibrium in the thermal power state based on the thermal mitigation configuration. Storage device performance is thus improved through advanced thermal throttling without compromising data integrity.
G06F 1/3237 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par désactivation de la génération ou de la distribution du signal d’horloge
G06F 9/50 - Allocation de ressources, p.ex. de l'unité centrale de traitement [UCT]
77.
SURFACE MOUNT TECHNOLOGY METHOD AND MAGNETIC CARRIER SYSTEM
A method of soldering one or more components to a substrate includes providing a substrate and applying an amount of solder material to the top planar surface of the substrate. One or more electrical components are mounted to the solder material in a predetermined position and orientation. A carrier is provided having one or more magnets embedded therein. The substrate is positioned above the carrier such that each of the one or more magnets is positioned directly below a corresponding electrical component. A carrier cover is positioned above the substrate and the electrical components. The solder material is heated to a predetermined temperature for a predetermined amount of time during which each of the magnets exerts a magnetic force on a corresponding electrical component to maintain its orientation relative to the substrate. The magnets reduce the occurrence of tombstoning of the electrical components during heating of the solder material.
Systems and methods for site-based estimation of storage requirements, such as for surveillance video cameras, are described. Product information, a data retention policy, and an intended recording mode about a camera of a surveillance system may be received through a user interface of a user device. A baseline storage value is determined based on the received product information and the data retention policy. A storage requirement may be calculated based on the baseline data storage value and a determined recording co-efficient value based on a sample scene at the camera location. Scene descriptors may be generated based on the sample scene to retrieve the recording co-efficient value from a lookup table.
H04N 7/18 - Systèmes de télévision en circuit fermé [CCTV], c. à d. systèmes dans lesquels le signal vidéo n'est pas diffusé
H04N 5/77 - Circuits d'interface entre un appareil d'enregistrement et un autre appareil entre un appareil d'enregistrement et une caméra de télévision
H04N 5/92 - Transformation du signal de télévision pour l'enregistrement, p.ex. modulation, changement de fréquence; Transformation inverse pour le surjeu
G06F 16/78 - Recherche de données caractérisée par l’utilisation de métadonnées, p.ex. de métadonnées ne provenant pas du contenu ou de métadonnées générées manuellement
79.
DEVICES AND METHODS FOR PROVIDING PORT MATCHING FEATURES FOR USB-C CABLES AND PORTS
Systems and methods are disclosed for providing port matching features for storage devices and cables. In certain embodiments, a data storage device includes a non-volatile memory, a controller configured to process data storage requests, a plurality of ports associated with different protocols, wherein the plurality of ports have the same connector type, and each port includes a port matching feature indicative of a protocol associated with the port, and a plurality of cables associated with the different protocols, wherein the plurality of cables have the same connector type and are configured to connect to the plurality of ports, and each cable includes a port matching feature indicative of a protocol associated with the cable, wherein the port matching feature of the cable corresponds to the port matching feature of a port of the plurality of ports that is associated with the same protocol.
H01R 24/60 - Contacts espacés le long de la paroi latérale plane transversalement par rapport à l'axe longitudinal d’engagement
H01R 33/76 - Supports avec alvéoles, pinces ou contacts analogues, adaptés pour l'engagement axial par glissement, avec des broches, lames ou contacts analogues disposés parallèlement sur la pièce complémentaire, p.ex. support pour tube électronique
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a dataset management (DSM) hint, determine if a second physical memory range associated with a next read operation is located within a threshold number of physical block addresses (PBAs) to a first physical memory range associated with a current read operation, where the next read operation is provided by the DSM hint, and utilize at least a portion of a latency budget associated with the current read operation to optimize a read parameter of the first physical memory range.
The present disclosure generally relates to reducing link-up time between an upstream device and a downstream device. Rather than re-coordinating the link between devices each time, knowledge gained from a previous link-up is used to speed up the link-up. Typically, when both the upstream device and the downstream device have not changed, then the coefficient values for downstream port (DSP) transmission (Tx) equilibrium (EQ) that resulted in a desired bit error rate (BER) should not have changed either. Hence, rather than exchanging coefficients, the previous values can be reused with confidence eliminating the need to exchange coefficients. In so doing, the link-up process is much faster and system resources are not wasted on unnecessary coefficient exchanges
A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to concurrently program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die.
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
H10B 41/50 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région limite entre la région noyau et la région de circuit périphérique
H10B 43/50 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région limite entre la région noyau et la région de circuit périphérique
H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
83.
CLAMPED SEMICONDUCTOR WAFERS AND SEMICONDUCTOR DEVICES
Clamped semiconductor wafers and clamped semiconductor devices include reservoirs filled with a flowable metal which hardens to allow the wafers/devices to be shipped or stored. The hardened metal may also be reflowed to a liquid to allow clamping of the semiconductor wafers together and to allow clamping of the semiconductor packages together. The flowable metal may be filled into the reservoirs as a liquid or paste. Thereafter, the flowable metal may be cooled to harden the flowable metal into a clamping member.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
The present disclosure generally relates to detecting command identification (CID) collisions in host commands. Host commands stored in submission queues are supposed to have unique CIDs. The host device selects the CID and attaches the CID to the command. Once the command is executed, the host device may reuse the CID. Sometimes, the host device reuses a CID before a command already using the CID is executed, which is a collision. Rather than search all CIDs to find a collision, redundancy bits can be created for each command, and the redundancy can be the same for multiple pending commands. The redundancy bits can be checked first to see if there is a match, followed by comparing CIDs for only those commands that have matching redundancy bits. In so doing, CID collisions are detected earlier and easier.
A data storage device includes a memory device, a random access memory (RAM) device, and a controller coupled to the memory device and the RAM device. The controller is configured to determine a workload type of the data storage device, determine to store at least a portion of a compressed logical to physical translation table (ZCAT) in the RAM device based on the workload type, and utilize a remaining portion of the RAM device to perform background operations. The controller is further configured to determine a persistence or temperature of the ZCAT, where the portion of the ZCAT stored to the RAM device is based on the persistence and/or the temperature of the ZCAT. The remaining portion of the ZCAT is stored in the HMB, where the remaining portion may update any out-of-date ZCAT entries.
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a deallocation command corresponding to a plurality of deallocation requests, where each of the plurality of deallocation requests corresponds to a logical block address (LBA) range, determine that at least one of the plurality of deallocation requests is an unaligned deallocation request, generate a tag for metadata for the unaligned deallocation request, wherein the tag for the metadata includes a direction bit and a length bit, concatenate the metadata including the tag to an LBA range of the unaligned deallocation request, and complete the deallocation command using the metadata including the tag. Aligned deallocation requests are stored in a buffer. The concatenated unaligned deallocation requests are completed prior to completing the aligned deallocation requests from the buffer.
A storage system includes two or more data storage devices and a controller coupled to the two or more data storage devices. Each data storage device of the two or more data storage devices includes zoned namespace (ZNS) architecture. The controller is configured to collect thermal statistics for each data storage device of the two or more data storage devices, analyze the collected thermal statistics, and designate a zone by selecting one or more dies within at least one data storage device of the two or more data storage devices based on the analyzed collected thermal statistics. The data storage device includes a memory device having a plurality of dies and a controller coupled to the memory device. The controller is configured to collect thermal statistics for each die of the plurality of dies, analyze the collected statistics, and allocate one or more dies to form a zone.
Systems and methods are disclosed for providing an indication of the data transfer protocol that is operative during a data transfer operation between a data storage device capable of supporting a plurality of data transfer protocols and a host computer. A protocol controller of the data storage device is configured to determine a data transfer protocol based on a data cable used and to generate a selector signal used to provide the indication.
A system and method for calibrating read threshold voltages includes performing a plurality of read operations, determining to perform a read level tracking method, and performing the read level tracking method. The determining may be based on a temperature change or a bit error rate (BER). The read level tracking method includes determining the BER of an indicative word line, determining an adjusted read threshold level based on the BER, and adjusting read threshold levels according to the adjusted read threshold level.
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
G11C 7/04 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les effets perturbateurs thermiques
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
Micro solder joint and stencil design. In one embodiment, a stencil for depositing solder on a printed circuit board (PCB) includes a plurality of stencil apertures, a first stencil aperture of the plurality of apertures having an aperture wall defining an aperture perimeter. The aperture wall is configured to not extend beyond an outer edge of a PCB pad provided on the printed circuit board, the aperture wall is also configured to not extend beyond an outer edge of a terminal of a surface mount component, and the first stencil aperture is configured to receive solder paste to form a non-convex solder joint between the PCB pad and the terminal.
H05K 3/12 - Appareils ou procédés pour la fabrication de circuits imprimés dans lesquels le matériau conducteur est appliqué au support isolant de manière à former le parcours conducteur recherché utilisant la technique de l'impression pour appliquer le matériau conducteur
H05K 1/11 - Eléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
H05K 1/09 - Emploi de matériaux pour réaliser le parcours métallique
91.
PRINTED CIRCUIT BOARD FOR GALVANIC EFFECT REDUCTION
Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.
H05K 1/09 - Emploi de matériaux pour réaliser le parcours métallique
H05K 1/11 - Eléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
H05K 3/18 - Appareils ou procédés pour la fabrication de circuits imprimés dans lesquels le matériau conducteur est appliqué au support isolant de manière à former le parcours conducteur recherché utilisant la technique de la précipitation pour appliquer le matériau conducteur
H05K 3/40 - Fabrication d'éléments imprimés destinés à réaliser des connexions électriques avec ou entre des circuits imprimés
A hard disk drive enclosure base includes a non-uniform disk shroud surface extending from a top to a floor, the shroud surface including a first portion having a first radius and clearance along the circumference of the shroud surface and a second portion having a lesser second radius and clearance. The second portion of the shroud surface may be positioned at multiple locations where the drive form factor is especially constraining and in view of the need for a sufficient seal land surface for applying a gasket seal around the perimeter of the inner cavity of the base part. Widening the disk shroud clearance where possible can reduce the shear stress exerted at the disk edges thereby reducing the windage drag and associated disk spindle motor power consumption, especially in the context of helium-filled drives in which disk flutter is less of an issue.
G11B 5/48 - Disposition ou montage des têtes par rapport aux supports d'enregistrement
G11B 33/02 - ENREGISTREMENT DE L'INFORMATION BASÉ SUR UN MOUVEMENT RELATIF ENTRE LE SUPPORT D'ENREGISTREMENT ET LE TRANSDUCTEUR - Éléments de structure, détails ou accessoires non prévus dans les autres groupes de la présente sous-classe Ébénisterie; Boîtiers; Bâtis; Disposition des appareils dans ou sur ceux-ci
G11B 33/08 - Isolation ou absorption des sons ou des vibrations indésirables
G11B 33/14 - Diminution de l'influence des paramètres physiques, p.ex. changements de température, humidité, poussière
G11B 5/596 - Disposition ou montage des têtes par rapport aux supports d'enregistrement comportant des dispositions pour déplacer la tête dans le but de maintenir l'alignement relatif de la tête et du support d'enregistrement pendant l'opération de transduction, p.ex. pour compenser les irrégularités de surface ou pour suivre les pistes pour suivre les pistes d'un disque
The present disclosure generally relates to a magnetic recording head for a magnetic media drive. The magnetic recording head comprises a near field transducer (NFT), a vertical cavity surface emitting laser (VCSEL) device, and a waveguide structure coupled between the NFT and the VCSEL device. The waveguide structure comprises a plurality of waveguide channels and a multimodal interference (MMI) combiner coupled to the waveguide channels. One or more of a curvature, a path length, and a propagation length of each of the waveguide channels is optimized such that each waveguide channel is controllable, or otherwise phase coherent with adjacent waveguide channels. The VCSEL device is capable of emitting a plurality of lasers through the plurality of waveguide channels, and the plurality of lasers are phase coherent when input into the MMI combiner. The MMI combiner combines a power of the plurality of lasers, which is output to the NFT.
G11B 7/125 - Sources de faisceau lumineux correspondantes, p.ex. circuits de commande de lasers spécialement adaptés pour les dispositifs d'enregistrement optique; Modulateurs, p.ex. moyens de commande de la taille ou de l'intensité des spots optiques ou traces optiques
94.
DETECTION OF MALICIOUS OPERATIONS FOR DISTRIBUTED CACHE
A node includes a memory configured to be used at least in part as a shared cache in a distributed cache. A network interface of the node is configured to communicate with one or more other nodes in a network. Each of the one or more other nodes is configured to provide a respective shared cache for the distributed cache. At least one processor of the node is configured to execute a kernel of an Operating System (OS) for allocating resources of the node. The kernel is used to collect cache access information for the shared cache for identifying malicious operations in the distributed cache.
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to relocate first valid data from a first source block to a destination block, relocate second valid data from a second source block to the destination block, determine that the destination block is closed, re-mark the first and second source block with a second indication, and erase the source blocks that have the second indication. The first source block and the second source block are marked with a first indication after each respective data is relocated. The first indication indicates that the source block cannot be freed. The second indication indicates that the destination block is closed and the associated source blocks can be erased. Prior to closing the destination block, parity data may be generated for the data of the destination block and programmed to the destination block.
Described herein are sliders and data storage devices that promote particle mobility to improve particle robustness. In some embodiments, a data storage device includes a recording medium and a slider. A surface of the slider air-bearing surface near the leading edge includes at least one roughening feature that causes the surface to be rougher than other surfaces of the slider to promote particle mobility. The roughening feature may include a regular or irregular pattern, and it may be created using a photoresist mask during the manufacturing process so that the surface is deliberately made rougher (e.g., has a higher friction coefficient) than the surface of a leading pad of the slider.
Disclosed herein are sliders with deep holes, data storage devices including such sliders, and methods of manufacturing such sliders. The holes can be situated near the edges of the slider to improve the stability and/or damping of the slider. The holes may be created, for example, using ion milling. In some embodiments, a slider comprises a leading pad comprising a first medium-facing surface that includes at least a first hole and a second hole, a first side pad comprising a second medium-facing surface that includes at least a third hole, and a second side pad comprising a third medium-facing surface that includes at least a fourth hole. In some embodiments, a trailing pad of the slider comprises a fourth medium-facing surface that includes at least a fifth hole and a sixth hole.
Various illustrative aspects are directed to a data storage device, comprising: one or more disks; an actuator assembly comprising a head, and configured to position the head over a corresponding disk surface; and one or more processing devices, the head comprising: a write element; a laser unit; and a fly height control element, and wherein the one or more processing devices are configured to: iteratively perform spiral write operations of spiral patterns comprising a plurality of sync marks with the head on the corresponding disk surface, wherein the spiral write operations are performed at: a plurality of values of laser pre-bias current, write backoff, and/or start disk phase; detect pattern signal amplitudes of the spiral patterns on the corresponding disk surface; and determine a relation of write backoff to laser pre-bias current for the head, based on the pattern signal amplitudes of the spiral patterns.
G11B 5/60 - Maintien dynamique de l'écartement entre têtes et supports d'enregistrement à l'aide d'un fluide
G11B 7/126 - Circuits, procédés ou dispositions pour la commande ou la stabilisation du laser
G11B 25/04 - Appareils caractérisés par la forme du support d'enregistrement employé mais non spécifiques du procédé d'enregistrement ou de reproduction utilisant des supports d'enregistrement plats, p.ex. disques, cartes
99.
PARASITIC COMMANDS FOR EQUALIZING LOGICAL UNIT CAPACITY IN ASYMMETRIC MULTIPLE ACTUATOR HARD DISK DRIVE
A multiple-actuator hard disk drive includes a first actuator associated with a first logical unit and configured to operate on a first set of disk surfaces, a second actuator associated with a second logical unit and configured to operate on a second set of disk surfaces greater than the first set, and a controller accessing a mapping of logical memory addresses to physical memory locations. The mapping maps the first logical unit to the physical memory locations of the first set of surfaces and a parasitic portion of the second set of surfaces, and maps the second logical unit to the physical memory locations of the second set of surfaces exclusive of the parasitic portion of the second set of surfaces. Thus, data transfer commands performed on the parasitic portion are executed by one actuator while credit is given to the logical unit associated with the other actuator.
Disclosed herein are sliders with at least one notch-cut in the trailing pad, methods of making them, and data storage devices comprising them. In some embodiments, a slider comprises a leading-edge surface, a trailing-edge surface, and an air-bearing surface (ABS) that includes a trailing pad situated closer to the trailing-edge surface than to the leading-edge surface, wherein the trailing pad comprises at least one notch-cut (e.g., two notch-cuts) in a trailing side of the trailing pad. The at least one notch-cut provides higher pressure at the recording head situated in the trailing pad and higher thermal flight control efficiency without a commensurate increase in touch-down power. As a result, the temperature around the recording head is lower than without the at least one notch-cut, thereby improving the lifetime of the recording head and data storage device.
brevets
