A method and apparatus for wireless communications are disclosed which includes announcing R-TWT support from a first wireless station to a second wireless station in a broadcast PPDU, negotiating R-TWT schedule membership with the second wireless station, the negotiating comprising sending a low latency indication and identifying low latency TIDs of a R-TWT schedule, and sending frames in accordance with the R-TWT schedule in the identified low latency TIDs.
One example discloses a method of interference estimation for communications between WLAN (wireless local area network) devices, including: adding a set of interference estimation attributes to a PPDU; transmitting the PPDU from and receiving the PPDU at a WLAN device; and estimating a set of interference statistics, by the WLAN device, by comparing the set of interference estimation attributes to a corresponding set of predefined attribute values.
Roaming for an ultra-high reliability (UHR) non-access point (non-AP) device with a distributed access point (AP) multi-link device (MLD), wherein the distributed AP MLD includes a plurality of AP MLDs in different devices at different locations having one medium access control (MAC) service access point (SAP), includes: receiving, by the non-AP device, an announcement from the distributed AP MLD configured to indicate that the distributed AP MLD is a distributed AP MLD with the plurality of AP MLDs in different devices wherein the non-AP device is configured to roam among the plurality of AP MLDs in different devices; associating, by the non-AP device, with a first AP MLD of the plurality of AP MLDs in different devices; and roaming, by the non-AP device, to a second AP MLD of the plurality of AP MLDs in different devices without a reassociation.
H04W 76/15 - Gestion de la connexion Établissement de la connexion Établissement de connexions à liens multiples sans fil
H04W 8/02 - Traitement de données de mobilité, p.ex. enregistrement d'informations dans un registre de localisation nominal [HLR Home Location Register] ou de visiteurs [VLR Visitor Location Register]; Transfert de données de mobilité, p.ex. entre HLR, VLR ou réseaux externes
4.
WIRELESS COMMUNICATIONS THROUGH WIRELESS RELAY DEVICE
Embodiments of a method and apparatus for wireless communications are disclosed. In an embodiment, a wireless device includes a controller configured to select a wireless relay device from multiple wireless relay devices for data exchanges between the wireless device and a second wireless device and a wireless transceiver configured to exchange data with the second wireless device through the selected wireless relay device.
H04W 40/22 - Sélection d'itinéraire ou de voie de communication, p.ex. routage basé sur l'énergie disponible ou le chemin le plus court utilisant la retransmission sélective en vue d'atteindre une station émettrice-réceptrice de base [BTS Base Transceiver Station] ou un point d'accès
5.
RANDOM ACCESS RESOURCE UNITS (RA-RUs) FOR LOW-LATENCY (LL) TRAFFIC
One example discloses a method for low-latency (LL) traffic frame communication between WLAN (wireless local area network) devices, including: sending a trigger frame from an access point (AP) configured to allocate a random access resource unit (RA-RU) to a non-access point station (non-AP STA); wherein the RA-RU enables the non-AP STA to transmit its low latency (LL) traffic information; and receiving, from the non-AP STA, an uplink LL traffic frame using the RA-RU that was allocated.
H04W 72/512 - Critères d’affectation ou de planification des ressources sans fil sur la base des propriétés du terminal ou du dispositif lorsqu’un faible temps de latence est requis, p.ex. URLLC
H04W 74/08 - Accès non planifié, p.ex. accès aléatoire, ALOHA ou accès multiple par détection de porteuse [CSMA Carrier Sense Multiple Access]
A power-meter includes a digital signal processor (DSP) configured to determine a respective consumed energy within each of a plurality of predetermined contiguous time intervals, a dequantizer, and a pulse generator. The dequantizer is configured to, for each time interval, determine a sum of a remainder and the consumed energy, calculate an integer pulse-count by dividing the sum of the remainder and the consumed energy by a predetermined pulse-quantum, calculate a new remainder by subtracting the product of the integer pulse-count and the pulse-quantum from the sum, and replace the remainder by the new remainder The pulse generator is configured to, for each time interval, generate the integer pulse-count number of pulses of an indicator signal.
One example discloses a current limited power device, including: a switch; an output coupled to the switch; a sensor coupled to sense a voltage across a parasitic diode within the switch; and an output current limiter circuit coupled to reduce a output current (Iout) from the output of the power device if the voltage across the parasitic diode exceeds a threshold level.
H02H 9/02 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de courant
H02H 1/00 - CIRCUITS DE PROTECTION DE SÉCURITÉ - Détails de circuits de protection de sécurité
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
8.
AMPLIFIER DEVICE WITH PHASE SLOPE ADJUSTMENT CIRCUITRY
An amplifier device having multiple amplification paths, such as a Doherty amplifier device, may include phase slope adjustment circuitry configured to adjust the frequency-dependent slope of the phase of an input carrier signal along a carrier path of the amplifier. By adjusting the phase slope of the input carrier signal in this way, the phase difference between carrier and peaking signals at an output combining node of the amplifier may be reduced, thereby reducing output power ripple of the amplifier. The phase slope adjustment circuitry may be a constant-k bandpass filter. The phase slope adjustment circuitry may have a zero-degree insertion phase at the center frequency of the amplifier. The phase slope adjustment circuitry may be implemented using surface mount inductors and capacitors.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p.ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 1/56 - Modifications des impédances d'entrée ou de sortie, non prévues ailleurs
H03F 3/24 - Amplificateurs de puissance, p.ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
A charge pump control system for a battery management system, wherein: the battery management system comprises: a plurality of cell-balancing-switches, one for each of a plurality of battery cells, wherein each cell-balancing-switch is in parallel with a respective one of the battery cells; a plurality of switch-drivers, one for each of the cell-balancing-switches, wherein each switch-driver is for providing a drive signal to selectively close a respective one of the cell-balancing-switches; and a charge pump that is configured to provide an output voltage to each of the plurality of switch-drivers. The charge pump is operable at a switching frequency that sets the maximum output current. The charge pump control system is configured to set the switching frequency of the charge pump based on the number of switch-drivers that are providing their respective cell-balancing-switches with a drive signal to close the cell-balancing-switch.
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
H02M 1/15 - Dispositions de réduction des ondulations d'une entrée ou d'une sortie en courant continu utilisant des éléments actifs
H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p.ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
10.
PROCESSING WAKEUP REQUESTS USING IN A PROCESSING SYSTEM HAVING POWER MANAGEMENT CIRCUITRY AND A PROCESSING CIRCUITRY
Power management circuitry includes a power management circuitry having a handshake watchdog (HWD) timer and configured to, upon a reset, set the HWD timer to a maximum delay time allowed between an initial wakeup request received at a first input and a qualified wakeup request expected at a second input and configured to start the HWD timer counting in response to the initial wakeup request. Processing circuitry includes a wakeup signal aggregator configured to receive wakeup signals from internal and external wakeup events and to provide a notification of an occurrence of a wakeup event. The notification is provided as the initial wakeup request. A low power mode sequencer configured to initiate a low power mode exit sequence in response to the notification from the wakeup signal aggregator and to provide the qualified wakeup request as a result of performing at least a portion of the exit sequence.
G06F 1/3296 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par diminution de la tension d’alimentation ou de la tension de fonctionnement
An embodiment of an accelerometer front-end device includes a substrate and a first proof mass coupled to the substrate and electrically coupled to a first movable electrode and electrically coupled to a first fixed electrode having a first potential and electrically coupled to a second fixed electrode having a second potential. A shield structure is coupled to the substrate, and adjacent the first proof mass, wherein the shield structure is electrically coupled to a fixed ground potential. A second proof mass is coupled to the substrate that includes a second movable electrode that is electrically coupled to a third fixed electrode having a third potential and is electrically coupled to a fourth fixed electrode having a fourth potential, wherein the second proof mass is electrically coupled to the fixed ground potential.
G01P 15/125 - Mesure de l'accélération; Mesure de la décélération; Mesure des chocs, c. à d. d'une variation brusque de l'accélération en ayant recours aux forces d'inertie avec conversion en valeurs électriques ou magnétiques au moyen de capteurs à capacité
12.
POWER AMPLIFIER PACKAGES CONTAINING ELECTRICALLY-ROUTED LIDS AND METHODS FOR THE FABRICATION THEREOF
Power amplifier (PA) packages having air cavities enclosed by electrically-routed lids, as well as to method for fabricating such power amplifier packages, are disclosed. In embodiments, the PA package includes a package body having a package topside surface and a package bottomside surface. The package body is defined, at least in part, by a package substrate and an electrically-routed lid bonded to the package substrate to sealingly enclose an air cavity. The electrically-routed lid includes, in turn, an upper lid wall, peripheral lid sidewalls, and sidewall-embedded vias contained in the peripheral lid sidewalls and each extending essentially in a package height direction. Radio frequency (RF) circuitry is attached to the package substrate and located within the air cavity, while a topside input/output interface is provided on the upper lid wall and electrically interconnected with the RF circuitry through the sidewall-embedded vias of the electrically-routed lid.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/053 - Conteneurs; Scellements caractérisés par la forme le conteneur étant une structure creuse ayant une base isolante qui sert de support pour le corps semi-conducteur
H01L 23/10 - Conteneurs; Scellements caractérisés par le matériau ou par la disposition des scellements entre les parties, p.ex. entre le couvercle et la base ou entre les connexions et les parois du conteneur
H01L 23/16 - Matériaux de remplissage ou pièces auxiliaires dans le conteneur, p.ex. anneaux de centrage
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H03F 3/24 - Amplificateurs de puissance, p.ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
13.
MULTI-LINK COMMUNICATIONS WITH MILLIMETER WAVE (MMWAVE) LINK
Embodiments of a method and apparatus for wireless communications are disclosed. In an embodiment, a wireless multi-link device (MILD) includes a controller configured to generate a millimeter wave (mmWave) beacon and a wireless transceiver configured to transmit the mmWave beacon to a second wireless MILD through an mmWave link between the wireless MLD and the second wireless MLD.
A GPIO includes a transmitter having an output stage connected to the I/O pad and adapted to supply transmit data to an I/O pad in response to output data generated by a low voltage core logic operating within a functional voltage range for transmit operations; a receiver adapted to supply receive data to the low voltage core logic operating within the functional voltage range in response to input data received at the I/O pad for receive operations; a VLV transmitter adapted to supply VLV transmit data to the output stage of the transmitter and not directly to the I/O pad in response to output test data generated by the low voltage core logic; and a VLV receiver adapted to supply VLV receive data to the low voltage core logic operating within a low core supply voltage range in response to input data received from the output stage of the transmitter.
H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
H03K 19/0185 - Dispositions pour le couplage; Dispositions pour l'interface utilisant uniquement des transistors à effet de champ
15.
DISTANCE QUALITY INDICATOR (DQI) FOR PHASE-BASED DISTANCE ESTIMATION USING NARROWBAND RADIOS
Systems and methods for producing quality indicators for phase-based distance estimations using narrowband radios are described. In an illustrative, non-limiting embodiment, a device may include: a processor; and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution by the processor, cause the device to: measure a transfer function of a radio frequency (RF) channel between the device and another device using narrowband radios; estimate a distance between the device and the other device based, at least in part, upon the transfer function; and determine a Distance Quality Indicator (DQI) corresponding to the distance based, at least in part, upon an evaluation of a spectral lobe of the transfer function.
A semiconductor device has first and second current terminals and a control terminal that can be biased to form an electrically conductive path from the first current terminal to the second current terminal through a channel region is provided with a temperature-sensitive current limiting device. The current-limiting device is integrally formed from semiconductor material of the control terminal and is configured to cause a reduction in electrical current flowing through the channel region when the temperature of the device in the channel region exceeds a predetermined threshold temperature.
H01L 23/62 - Protection contre l'excès de courant ou la surcharge, p.ex. fusibles, shunts
H03K 17/082 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension par réaction du circuit de sortie vers le circuit de commande
17.
CAPTURING OF ON-CHIP RESETS IN AN INTEGRATED CIRCUIT
A system includes a first reset capture register configured to receive a plurality of reset signals, a last reset capture register configured to receive the plurality of reset signals, and a reset control circuit. The reset control circuit is configured to perform a startup procedure in response to assertion of a first reset signal of the plurality of rest signals. The startup procedure beings with a start state and ends in an active state in which the system operates in normal operation, and the first reset signal is asserted while the system is in the active state. The first reset capture register is configured to capture a first state of the plurality of reset signals in response to assertion of the first reset signal, and the last reset capture register is configured to capture a final state of the plurality of reset signals prior to completing the startup procedure.
An electronic component includes a device die and a substrate. The device die includes conductive contacts with conductive pillars conductively affixed to conductive contact. The conductive pillars include a cavity formed in an end of the conductive pillar opposite the conductive contact. The substrate includes of conductive pads that are each associated with one of the conductive contacts. The conductive pads include a conductive pad conductively affixed to the substrate, and a conductive ring situated within a cavity in the end conductive rings have a capillary formed along an axis of the conductive ring. A solder material fills the capillary of each of the conductive rings and the cavity formed in the end of the associated conductive pillars to form a conductive joint between the pillars and the conductive pads.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
19.
SEMICONDUCTOR DEVICE WITH RESIN BLEED CONTROL STRUCTURE AND METHOD THEREFOR
A method of manufacturing a semiconductor device is provided. The method includes forming a package leadframe including a die pad, a first ridge formed at a first outer edge of the die pad, a second ridge formed at a second outer edge of the die pad opposite of the first outer edge and separate from the first ridge, and a plurality of leads surrounding the die pad. A semiconductor die is attached to the die pad by way of a die attach material. The semiconductor die is located on the die pad between the first ridge and the second ridge. An encapsulant encapsulates the semiconductor die and at least a portion of the package leadframe.
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
20.
SELF-BIASED, CLOSED LOOP, LOW CURRENT FREE RUNNING OSCILLATOR
A self-biased, closed loop, low current free running oscillator clock generator method and apparatus are provided with a current mode comparator connected to a trimming resistor and configured to compare an internally generated voltage reference VREF signal to a voltage feedback signal VFB, where the current mode comparator comprises a common gate amplifier connected to a current mirror circuit in a negative self-biased closed loop to generate a control current signal for controlling a current controlled oscillator to produce an output clock signal having a clock frequency based on the control current signal, where a frequency-to-voltage converter is connected in a feedback path to receive the output clock signal and is configured to produce the voltage feedback signal VFB for input to the current mode comparator, wherein the clock frequency of the output clock signal is tuned to a nominal locked output frequency fOUT by the trimming resistor.
H03B 5/04 - Modifications du générateur pour compenser des variations dans les grandeurs physiques, p.ex. alimentation, charge, température
H03B 5/24 - Elément déterminant la fréquence comportant résistance, et soit capacité, soit inductance, p.ex. oscillateur à glissement de phase l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
21.
DEVICE, SYSTEM, AND METHOD FOR COORDINATING RESTRICTED TARGET WAKE TIME SERVICE PERIODS OF A PLURALITY OF ACCESS POINTS
An AP receives a frame comprising an indication of a restricted target wake up time schedule service period (r-TWT SP) from a wireless device. The AP one or more of adjusts an r-TWP SP of the AP based on the indication of the r-TWT SP indicated in the received frame and announcing that an STA associated with the AP is to terminate a transmit opportunity (TXOP) before the r-TWT SP indicated in the received frame begins.
A method of broadcasting a beacon by a relay device in a basic service set, including: receiving an announcement from a first device indicating whether the relay device is to forward a received beacon to a second device; receiving a beacon from the first device; and forwarding the beacon to the second device based upon the announcement.
H04W 48/10 - Distribution d'informations relatives aux restrictions d'accès ou aux accès, p.ex. distribution de données d'exploration utilisant des informations radiodiffusées
A programmable gain amplifier that comprises: a transconductance amplifier, a switch leakage compensation circuit and a transimpedance amplifier. The transconductance amplifier provides a transconductance amplifier current signal and includes a switchable resistance network. The switch leakage compensation circuit provides a compensation current signal and comprises a switchable compensation resistance network. The transimpedance amplifier provides the output voltage signal based on the difference between the transconductance amplifier current signal and the compensation current signal. The switchable compensation resistance network comprises a plurality of branches in parallel with each other, wherein each branch includes: a gain-mimicking switch that has a corresponding gain-setting switch in the switchable resistance network; and a leakage-current-conducting switch in series with the gain-mimicking switch. The leakage-current-conducting switch is openable and closable in accordance with the complement of a switch control signal that is used to control the gain-mimicking switch in the same branch.
An apparatus for determining a disconnection of a device from a bus, the apparatus comprising: a detection unit configured to periodically poll the bus, to detect an occurrence of an indicator of disconnection; and a handling unit configured to, in response to detecting the occurrence of an indicator of disconnection a predetermined number of times within a predetermined interval, make a determination that the device is disconnected from the bus. A method for determining a disconnection of a device from a bus is also presented.
G06F 13/38 - Transfert d'informations, p.ex. sur un bus
G06F 13/366 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès centralisée utilisant un arbitre d'interrogation centralisé
A transistor device includes one or more conductive structures on which a cladding layer is formed, where the cladding layer has low miscibility with conductive material of the conductive structures at temperatures below a threshold. Such conductive structures may include gate (control) electrodes or drain and source (current-carrying) electrodes. Forming such a cladded conductive structure for a transistor device may include forming photoresist layers on a substrate, selectively patterning the photoresist layers to form openings therein, forming conductive material over the photoresist layers and on the substrate in openings in the photoresist layers, and forming a cladding layer over the conductive material, then preforming a lift-off process in which the photoresist layers are removed along with portions of the conductive material and cladding layer that are not disposed in the openings in the photoresist layers.
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
26.
SEMICONDUCTOR DEVICE WITH ACTIVE MOLD PACKAGE AND METHOD THEREFOR
A method of forming a semiconductor device is provided. The method includes forming a conductive die connector having a first end connected to a die pad of a semiconductor die. A first encapsulant formulated for selective activation by way of a laser encapsulates at least a portion of the semiconductor die. A first conductive trace of a redistribution layer is formed by plating a conductive material on a first laser activated path on a first major surface of the first encapsulant. The first conductive trace is directly connected to a second end of the die connector. A second encapsulant formulated for selective activation by way of a laser encapsulates at least the first conductive trace and exposed portions of the first major surface of the first encapsulant.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
27.
NETWORK ALLOCATION VECTOR (NAV) OPERATION IN MULTI-ACCESS POINT (AP) COORDINATION
Embodiments of a method and apparatus for wireless communications are disclosed. In an embodiment, a wireless device includes a wireless transceiver configured to receive a first frame from a first wireless access point (AP) for multi-AP coordination that is not associated with the wireless device and a second frame from a second wireless AP for multi-AP coordination that is associated with the wireless device and a controller configured to set a network allocation vector (NAV) timer of the wireless device to a non-zero value in response to the first frame and the second frame. The wireless transceiver is further configured to transmit a physical protocol data unit (PPDU) to the second wireless AP even if the NAV timer of the wireless device is non-zero.
Embodiments of a method and apparatus for wireless communications are disclosed. In an embodiment, a wireless relay device includes a wireless transceiver configured to receive, from a first wireless device, a first multi-station (STA) block acknowledgement (BA) frame, and a controller configured to generate a second multi-STA BA frame in response to the first multi-STA BA frame. The wireless transceiver is further configured to transmit the second multi-STA BA frame to a second wireless device.
An integrated circuit includes a plurality of analog inputs, and an analog multiplexer (MUX). The MUX includes a common output node configured to provide a MUX output, a plurality of analog switches, and a shared buffer. Each switch includes a corresponding bootstrap circuit coupled to a control electrode of a corresponding pass transistor in which the corresponding bootstrap circuit includes a corresponding boosting capacitor. Each analog switch of the plurality of analog switches has a first input coupled to a corresponding analog input of the plurality of analog inputs, a second input, and an output coupled to the common output node. The shared buffer has an input coupled to the common output node and coupled to provide a common buffered MUX output to the second input of each of the plurality of analog switches.
H03K 19/173 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants
H03K 17/081 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension sans réaction du circuit de sortie vers le circuit de commande
H03K 19/17784 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels pour l'adaptation des paramètres physiques pour la tension d'alimentation
Embodiments of a method and apparatus for wireless communications are disclosed. In an embodiment, a method includes selecting backoff 20 MHz channels of an operating channel bandwidth (BW) of a Basic Service Set (BSS), and announcing to a second wireless device the operating channel BW of the BSS for use in communicating between the wireless device and the second wireless device, subchannels of the operating channel bandwidth, and backoff 20 MHz channels of each subchannel, wherein one subchannel is a primary subchannel and one subchannel is a non-primary subchannel. A data unit is transmitted to the second wireless device in a backoff 20 MHz channel of the non-primary subchannel.
A multiphase digital frequency synthesizer including a multiphase ring oscillator that provides phased clock signals, a clock divider that divides a phased clock signal by an integer value and a carry value to provide a divided clock signal, positive select circuitry that determines and updates a positive select value with accumulation and a modulo function based on a fractional division factor updated with successive cycles of the divided clock signal, carry circuitry that determines the carry value based on a number of the phased clock signals, positive multiplex circuitry that selects from among the phased clock signal using the positive select value for providing a positive multiplexed clock signal, and fractional phase addition circuitry that provides a first output clock signal based on a selected phased clock signal, the divided clock signal, and the positive multiplexed clock signal. Similar negative select circuitry and duty cycle correction circuitry may be included.
H03K 19/20 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion caractérisés par la fonction logique, p.ex. circuits ET, OU, NI, NON
32.
COMMUNICATION DEVICE AND METHOD FOR MONITORING A WIRELESS COMMUNICATION EXCHANGE
A communication exchange between two wireless communication devices is monitored. A communication device configured to function as a Sniffer device synchronizes the communication device to a frequency and a timing employed between the two wireless communication devices on a main wireless communication channel. The wireless communication exchanges are monitored, in which the wireless communication exchanges are packet-based data exchanges or tone-based data exchanges. The operations for wireless communication exchanges are repeated across a plurality of different frequencies. The communication device then combines a plurality of phase and/or magnitude measurements and determines a value of phase and/or magnitude error introduced by each device based on the combined plurality of phase and/or magnitude measurements.
A method of forming a semiconductor device is provided. The method includes encapsulating with an encapsulant at least a portion of a semiconductor die and a package substrate, the encapsulant including an additive selectively activated by way of a laser. A first opening is formed in the encapsulant, the first opening exposing a predetermined first portion of the package substrate. The additive is activated at the sidewalls of the first opening. A second opening is formed in the encapsulant, the second opening encircling the first opening and exposing a predetermined second portion of the package substrate. The additive is activated at the sidewalls the second opening. A conductive material is plated on the additive activated portions of the encapsulant.
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/552 - Protection contre les radiations, p.ex. la lumière
H01P 11/00 - Appareils ou procédés spécialement adaptés à la fabrication de guides d'ondes, résonateurs, lignes ou autres dispositifs du type guide d'ondes
H01Q 1/22 - Supports; Moyens de montage par association structurale avec d'autres équipements ou objets
plurality of objects that comprise an input to a cryptographic signing function. For each object in the plurality of objects, an output value yi of a hash function is calculated, where the value i is equal to an index value of the object, a compressed output value xi of a compression function is calculated, the output value yi from the computer readable memory, and the compressed output value xi is stored. For each object in the plurality of objects, an output value y′i of the hash function is calculated, where the value i is equal to the index value of the object, a compressed output value x′i of the compression function executed on the output value y′i is calculated, the output value x′i is determined to be equal to the output value xi, and the output value y′i is transmitted in an output data stream.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
35.
ANALOG-TO-DIGITAL CONVERTER (ADC) AUTO-SEQUENTIAL CANNING WITH EXPANSION MULTIPLEXER(S) AND AUXILIARY CIRCUIT CONFIGURATION CONTROL(S)
Systems and methods for Analog-to-Digital Converter (ADC) auto-sequential scanning with expansion multiplexer(s) and auxiliary circuit configuration control(s). In some embodiments, an electronic circuit may include: a multiplexer; an Analog-to-Digital Converter (ADC) coupled to the multiplexer; and a control circuit coupled to the ADC and to the multiplexer, where the control circuit is configured to, as part of an auto-sequential scan, select one of a plurality of input channels coupled to the multiplexer via an expansion multiplexer.
A sigma-delta ADC comprising: a first-input-resistor connected in series between a first-input-terminal and a first-feedback-node; a second-input-resistor connected in series between a second-input-terminal and a second-feedback-node; a third-input-resistor connected in series between a third-input-terminal and a third-feedback-node; a first-multiplexer-switch connected in series between the first-feedback-node and a first-amplifier-second-input-terminal; a second-multiplexer-switch connected in series between the second-feedback-node and a first-amplifier-first-input-terminal; a third-multiplexer-switch connected in series between the third-feedback-node and the first-amplifier-second-input-terminal; a first-feedback-current-source having a first terminal and second terminal, wherein the second terminal is connected to a reference-terminal; a second-feedback-current-source having a first terminal and second terminal, wherein the second terminal is connected to the reference-terminal; a first-feedback-selection-switch connected in series between the first-feedback-node and the first terminal of the first-feedback-current-source; a second-feedback-selection-switch connected in series between the second-feedback-node and the first terminal of the second-feedback-current-source; and a third-feedback-selection-switch connected in series between the third-feedback-node and the first terminal of the first-feedback-current-source.
A method for forming a transistor with an emitter, intrinsic base, and collector. The base includes a semiconductor layer doped with a conductivity dopant to provide for a lower resistivity path to the intrinsic base. After the formation of a layer over a substrate, an emitter window opening is formed in the layer. The semiconductor layer is formed through the opening by a deposition process. A portion of the semiconductor layer is then removed. An emitter electrode is formed that includes at least a portion located in the opening. A remaining portion of the semiconductor layer is in a conductive path to the intrinsic base.
A device includes a computer readable memory storing a plurality of one-time signature (OTS) keypairs and a processor that is configured to execute a hash function on a message using a first private key of a first OTS keypair of the plurality of OTS keypairs to determine a message signature, execute the hash function to calculate a leaf node value of a hash tree using the first OTS keypair, determine a plurality of authentication path nodes in the hash tree, retrieve, from the computer readable memory, values of a first subset of the plurality of authentication path nodes, calculate values for each node in a second subset of the plurality of authentication path nodes, and store, in the computer readable memory, the values for each node in the authentication path and the value of the leaf node.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
H04L 9/00 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité
A receiver circuit comprising: an input-pin; a receiver-input-node; a ground-pin; an internal-node that is connected to the input-pin; and a MOSFET. The MOSFET has a conduction channel connected in series between the internal-node and the receiver-input-terminal; and a gate terminal, the voltage at which sets the conductivity of the conduction channel. The receiver circuit also includes an amplifier that: has an input terminal that is connected to the internal-node; and provides a voltage control signal to the gate terminal of the MOSFET such that the voltage at the internal-node with respect to the ground-pin is constant.
H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
H03K 17/06 - Modifications pour assurer un état complètement conducteur
H03K 17/10 - Modifications pour augmenter la tension commutée maximale admissible
A power amplifier device includes a substrate, a power transistor die, and one or more surface mount components. The substrate has substrate die contacts exposed at a first substrate surface, and additional substrate contacts exposed at a second substrate surface. The power transistor die includes an integrated transistor. The transistor includes a control terminal and a first current conducting terminal coupled, respectively, to first and second die contacts at the first die surface, and a second current conducting terminal coupled to a third die contact at a second die surface. The surface-mount components are connected to the additional substrate components, and the surface-mount components are electrically coupled through the substrate to the first and second die contacts. The power amplifier device also includes an encapsulation material layer covering the surface-mount components and the second substrate surface.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p.ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 3/195 - Amplificateurs à haute fréquence, p.ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H03F 3/24 - Amplificateurs de puissance, p.ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
41.
Packaged power amplifier device with air cavity over die
A power amplifier device includes a substrate formed from a stack of alternating dielectric and patterned conductive layers and conductive vias electrically connecting the patterned conductive layers. The substrate has a set of substrate die contacts exposed at a first substrate surface, and an air cavity extending into the substrate through a portion of the first substrate surface that is located between the set of substrate die contacts. A power transistor die has first and second die contacts at a first die surface, which are connected to the substrate die contacts. The power transistor die also includes an integrated transistor in an active area of the die. The integrated transistor includes a control terminal coupled to the first die contact, and a first current conducting terminal coupled to the second die contact. The active area is aligned with the first air cavity.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p.ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 3/195 - Amplificateurs à haute fréquence, p.ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
42.
FRAME FORWARDING FOR RANGE EXTENSION IN A WIRELESS NETWORK
Embodiments of a method and apparatus for wireless communications are disclosed. In an embodiment, a wireless relay device includes a wireless transceiver configured to receive, from a first wireless device, communications data, and a controller configured to determine whether to forward the received communications data to a second wireless device.
One example discloses a communications device, including: an interface port, configured to couple the communications device to another device; a transmitter configured to transmit signals on the interface port; a receiver configured to receive signals on the interface port; and a switch configured to short the interface port to a reference potential after the transmitter transmits signals on the interface port.
A power amplifier device includes first and second power transistor dies and a substrate. Each die includes an elongated bondpad and an integrated transistor with a terminal that is coupled to the elongated bondpad. The substrate is formed from a stack of multiple dielectric layers and multiple patterned conductive layers in an alternating arrangement, and a plurality of conductive vias electrically coupling portions of the conductive layers. The substrate includes elongated first and second die contacts exposed at a first substrate surface and connected to the first and second elongated bondpads, respectively. The substrate also includes a conductive structure connected between the first and second die contacts. The conductive structure is formed from portions of the patterned conductive layers and at least two vias of the plurality of conductive vias.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p.ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 3/195 - Amplificateurs à haute fréquence, p.ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
A Doherty amplifier includes first and second input terminals, first and second amplifiers, and an output combiner circuit. The first amplifier includes a first amplifier input coupled to the first input terminal, and a first amplifier output. The second amplifier includes a second amplifier input coupled to the second input terminal, and a second amplifier output. The output combiner circuit is coupled between the first amplifier output, the second amplifier output, and a final summing node. The output combiner circuit includes a first inductive element, a first capacitor integrated within an integrated passive device (IPD), and a second inductive element. The first inductive element is coupled between the first amplifier output and a first terminal of the first capacitor, and the second inductive element is coupled between a combining node and the first terminal of the first capacitor. A second terminal of the first capacitor is coupled to ground.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p.ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 3/195 - Amplificateurs à haute fréquence, p.ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H03F 1/56 - Modifications des impédances d'entrée ou de sortie, non prévues ailleurs
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des groupes principaux , ou dans une seule sous-classe de , , p.ex. circuit hybrides
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
Embodiments of a method and apparatus for wireless communications are disclosed. In an embodiment, a wireless device includes a controller configured to generate a beacon frame and a beacon extension frame that follows the beacon frame and a wireless transceiver configured to transmit the beacon frame and the beacon extension frame to devices that are compatible with a wireless communications protocol. The beacon frame carries an indication that the beacon extension frame follows the beacon frame.
Embodiments of a method and apparatus for wireless communications are disclosed. In an embodiment, a wireless device includes a wireless transceiver configured to communicate within a transmit opportunity (TXOP), where the wireless transceiver is further configured to receive a low latency (LL) buffered frame indication from a first wireless device with an inter frame space that is equal to a Short Interframe Spacing (SIFS), and a controller configured to implement an inter frame space that is bigger than the SIFS between transmission of two consecutive frames through the wireless transceiver.
A method for a serial protocol-based event trigger includes detecting a condition of a Device Under Test (DUT) with a first text pattern, wherein the condition indicates an enabled function of the DUT. A command is transmitted to the DUT to perform a first action with the enabled function in response to detecting the condition of the DUT. A second text pattern received from the DUT is detected in response to the first action. The second text pattern indicates a successful completion of an event by the enabled function. A second action is performed in response to detecting the second text pattern.
A calibration apparatus for a communication system. The calibration apparatus is configured to: a) set a variable termination-resistance at a receiver to a predetermined value; b) cause a transmitter to send a calibration pattern to the receiver by: setting the differential voltage on the line to a non-zero value during a non-zero-phase; and setting the differential voltage on the line to zero during a subsequent zero-phase; c) compare the differential voltage on the line during the zero-phase with a reduced-bit-value-threshold, wherein the reduced-bit-value-threshold is less than a bit-value-threshold that is used during active communication. If the differential voltage on the line during the zero-phase exceeds the reduced-bit-value-threshold, then the calibration apparatus adjusts the value of the variable termination-resistance and returns to step b). If the differential voltage on the line during the zero-phase does not exceed the reduced-bit-value-threshold, then the calibration apparatus stores the current value of the variable termination-resistance for subsequent use during active communication.
Methods, systems, and apparatus for power consumption control in an electronic system is disclosed. A voltage of a voltage rail coupled between a power management system and the electronic system to a power consumption trigger voltage is compared. Based on the voltage of the voltage rail being below the power consumption trigger voltage, power consumption by the electronic system is increased to reduce the voltage of the voltage rail during a power down of the electronic system. A voltage output by a power source which is provided as an input to the power management system is detected to be at a nominal voltage after increasing the power consumption. Based on the detection, a regulated voltage is provided to the voltage rail to power up the electronic system.
H02M 3/04 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques
One example discloses a method of preemption for latency-sensitive traffic for communications between WLAN (wireless local area network) devices, including: receiving, by an access point (AP), a first frame from a first non-access point station (non-AP STA); transmitting, by the AP, a second frame indicating Transmission Opportunity (TXOP) pre-emption information to the first non-AP STA; and transmitting, to a second non-AP STA, a third frame; wherein the third frame includes latency-sensitive frame.
H04W 72/20 - Canaux de commande ou signalisation pour la gestion des ressources
H04W 72/1263 - Jumelage du trafic à la planification, p.ex. affectation planifiée ou multiplexage de flux
H04W 72/512 - Critères d’affectation ou de planification des ressources sans fil sur la base des propriétés du terminal ou du dispositif lorsqu’un faible temps de latence est requis, p.ex. URLLC
52.
POWER-ON-RESET REQUEST FUNCTIONALITY IN SEMICONDUCTOR DEVICES AND POWER MANAGEMENT ICS
A semiconductor circuit is disclosed, comprising: a processor; a supply-voltage terminal arranged to receive a supply voltage; an out-of-range-voltage-detection circuit, coupled to the supply-voltage terminal and configured to output a voltage-out-of-range indicator in response to detecting that the supply voltage is out-of-range; a PWM signal generator configured to generate a PWM signal; a power-on-reset request terminal arranged to output the PWM signal during a normal operation of the processor; and logic circuitry between the signal generator and the POR request terminal and configured to modify the PWM signal in response receiving the voltage-out-of-range indicator. A microcontroller circuit incorporating such a semiconductor circuit, and a PMIC circuit for use in conjunction, are also disclosed.
A method of managing power in a first wireless device associated with an additional wireless device includes receiving power management information for a first link of the first wireless device via any of a plurality of links of the first wireless device. Power consumption of the first link of the first wireless device is then managed, based on the power management information that was received from any of the links.
A semiconductor device package may include a package substrate, mold material formed over the package substrate, and a mold-embedded inductor that is embedded in the mold material. The mold-embedded inductor may be coupled to a die, such as a power management integrated circuit die, which may also be embedded in the mold material. The mold-embedded inductor may be formed by forming conductive traces and an inductor core in the mold material. For example, an active mold packaging (AMP) process and corresponding laser direct structuring (LDS) processes may be performed to form openings in the mold material and to activate surfaces of the mold material to facilitate subsequent plating of conductive material. Activated surfaces of the mold material may have micro-rough texture and may include bulk conductive material formed via the application of laser energy to additives in the mold material during the LDS process(es).
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des groupes principaux , ou dans une seule sous-classe de , , p.ex. circuit hybrides
H01L 49/02 - Dispositifs à film mince ou à film épais
H01F 41/04 - Appareils ou procédés spécialement adaptés à la fabrication ou à l'assemblage des aimants, des inductances ou des transformateurs; Appareils ou procédés spécialement adaptés à la fabrication des matériaux caractérisés par leurs propriétés magnétiques pour la fabrication de noyaux, bobines ou aimants pour la fabrication de bobines
One example discloses a test-point access structure within a semiconductor, including: a target test-point configured to be coupled to a circuit within the semiconductor; a first doped region within the semiconductor configured to generate a first signal in response to an energy beam transmitted by a circuit editing (CE) tool; a second doped region within the semiconductor configured to generate a second signal in response to the energy beam transmitted by the CE tool; and a target pad coupling the target test-point to the first doped region; wherein the CE tool is configured to remove material from the semiconductor in response to the first signal and the second signal.
An integrated circuit comprises a substrate that includes a first surface and a second surface. A first through substrate via (TSV) is formed between the first surface and the second surface and a first conductive material is arranged within the first TSV to form a conductive path between the first surface and the second surface through the substrate. A second TSV is formed between the first surface and the second surface and a second conductive material arranged within the second TSV to form a conductive path between the first surface and the second surface through the substrate. In examples the first TSV has a larger cross-sectional area than the second TSV, the cross-section of the first TSV and second TSV being in a plane parallel to the first surface or the second surface.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
G01R 27/02 - Mesure de résistances, de réactances, d'impédances réelles ou complexes, ou autres caractéristiques bipolaires qui en dérivent, p.ex. constante de temps
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
Provided is a current-sensing circuit that includes a power-supply line providing electrical power to a high side of a load, a high-side field-effect transistor (FET) component between the power-supply line and the high side of the load, and a low-side FET component coupled to a low side of the load. Gate signals continually repeat a cycle that includes: a first part in which the high-side FET component is turned on and the low-side FET component is turned off, and a second part in which the high-side FET component is turned off and the low-side FET component is turned on. In addition, a single transconductance stage is configured to: input signals indicating a voltage drop across whichever one of the high-side FET component or the low-side FET component currently is on, and output a signal indicating a current flow that corresponds to such voltage drop.
The disclosure relates to a communications system having a transmitter and receiver connected via a transmission line. An example communications receiver (202) comprises: a pair of input connections (211, 212) for connecting to a transmission line (203); a termination resistance (213) equal to a characteristic impedance (Zc) of the transmission line (203); an air core transformer (205) having an input coil (206) connected to the pair of input connections (211, 212) via the termination resistance (213); and a comparator circuit (208) connected to an output coil (207) of the air core transformer (205), the comparator circuit (208) configured to provide an output signal (504) responsive to detection of voltage pulses across the output coil (207).
The disclosure relates to a communications system having a transmitter and receiver connected via a transmission line. An example communications receiver (202) comprises: a pair of input connections (211, 212) for connecting to a transmission line (203); a termination resistance (213) equal to a characteristic impedance (Zc) of the transmission line (203); an air core transformer (205) having an input coil (206) connected to the pair of input connections (211, 212) via the termination resistance (213); and a comparator circuit (208) connected to an output coil (207) of the air core transformer (205), the comparator circuit (208) configured to provide an output signal (504) responsive to detection of voltage pulses across the output coil (207).
[FIG. 3]
A packaged die including a first and a second power supply pad configured to provide a first and a second power supply voltage, respectively, and circuitry powered by the first power supply voltage. A power pad handling circuitry includes a selectively enablable pull-down path coupled between the first power supply pad and the second power supply pad, a storage circuit configured to store a pull-down path enable bit, a clock input coupled to receive a boot clock, and an asynchronous input coupled to receive a power-on-reset (POR) signal. In response to assertion of the POR signal, the pull-down pat is enabled regardless of any signal received at the clock input and regardless the value of the pull-down path enable bit. When reset has completed, a value of the pull-down path enable bit is provided upon an active edge of the boot clock to selectively enable the pull-down path.
G05F 1/56 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final
A method and system comprises receiving a signal over an air interface. A binary sequence is detected in the signal. A legacy signal (L-SIG) field of a physical layer protocol data circuit (PPDU) is decoded based on the detected binary sequence and based on decoding the L-SIG field, two spoofing symbols which directly follow the L-SIG field is checked in the PPDU, wherein the two spoofing symbols comprise binary phase shift keying (BPSK) symbols. Based a presence of the two spoofing symbols, a long range portion of the PPDU is processed; and based on an absence of the two spoofing symbols, the PPDU is processed as a legacy PPDU.
An analog amplitude pre-distortion circuit and method. The circuit includes an RF input for receiving an RF signal. The circuit also includes an amplifier stage comprising an amplifier stage input coupled to the RF input, wherein the amplifier stage is operable to amplify the RF signal to produce an amplified RF signal. The circuit further includes a bias circuit. The bias circuit includes a transistor having a first current terminal, a second current terminal and a control terminal, wherein the first current terminal is coupled to the amplifier stage input and wherein the second current terminal is coupled to a reference potential. The bias circuit also includes a resistor coupled between the amplifier stage input and the control terminal. The bias circuit also includes a variable reactance component coupled to the control terminal. The bias circuit further includes a capacitor coupled between the control terminal and the reference potential.
A method for self-ordering Fast Fourier Transform for Single Instruction Multiple Data engines includes performing a butterfly operation on a first input vector and a second input vector to generate a first output vector and a second output vector, wherein the first input vector, the second input vector, the first output vector and the second output vector are each comprised of complex numbers, and a first order of the complex numbers of the first output vector is non-linear and a second order of the complex numbers of the second output vector is non-linear. A combination of complex numbers is reordered and exchanged between the first output vector and the second output vector to partially linearize the first order of the first output vector and to partially linearize the second order of the second output vector.
A method and apparatus are disclosed for a multi-processor system on a chip which includes at least a first execution domain processor that is configured to run a first execution domain by accessing one or more system-on-chip (SoC) resources using virtual addresses; a control point processor that is physically and programmatically independent from the first execution domain processor and that is configured to generate a runtime virtualization isolation control data stream for controlling access to the SoC resources by identifying at least a first SoC resource that the first execution domain is allowed to access; and an access control circuit connected between the first execution domain and the SoC resources and configured to provide, in response to the runtime virtualization isolation control data stream, a dynamic runtime virtualization isolation barrier which maps a virtual address for the first SoC resource to a physical address for the first SoC resource.
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
64.
System on Chip with Pre-Exemption Interrupts for Partition Execution Control
A method and apparatus are disclosed for a multi-processor SoC which includes an execution domain processor for running an execution domain which hosts independent software partitions by accessing, for each software partition, one or more SoC resources; a control point processor that generates control data with pre-emption vectors for controlling access to the SoC resources by identifying at least a first SoC resource that each software partition is allowed to access; and an access control circuit connected between the execution domain and the SoC resources and configured to provide, in response to the control data, a dynamic runtime isolation barrier which enables the execution domain processor to switch between software partitions in response to a pre-emption interrupt trigger by fetching partition instructions from a corresponding pre-emption interrupt vector address in memory that is associated with the pre-emption interrupt trigger.
G06F 21/53 - Contrôle des usagers, programmes ou dispositifs de préservation de l’intégrité des plates-formes, p.ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p.ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par exécution dans un environnement restreint, p.ex. "boîte à sable" ou machine virtuelle sécurisée
A method and apparatus are disclosed for a multi-processor SoC which includes an execution domain processor for running an execution domain; a control point processor that is physically and programmatically independent from the execution domain processor and configured to generate control data for controlling access by the execution domain to one or more SoC resources by identifying at least a first SoC resource that the execution domain is allowed to access; and an access control circuit connected between the execution domain and the SoC resources and including a programmable front end which is connected to receive the control data from the control point processor, and a signals-based back end which is configured to provide a dynamic runtime isolation barrier in response to the control data, thereby controlling access to the one or more system-on-chip resources by the execution domain.
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
66.
ANALOG AMPLITUDE PRE-DISTORTION CIRCUIT AND METHOD
An analog amplitude pre-distortion circuit and method. The circuit includes a Radio Frequency, RF, input for receiving an RF signal. The circuit also includes an amplifier stage comprising an amplifier stage input for receiving the RF signal from the RF input, wherein the amplifier stage is operable to amplify the RF signal to produce an amplified RF signal. The circuit further includes a bias circuit. The bias circuit includes a detector stage for detecting an amplitude of the RF signal, and for producing a correction signal based on the amplitude of the RF signal. The bias circuit also includes a bias application stage coupled to the amplifier stage input.
H03F 1/32 - Modifications des amplificateurs pour réduire la distorsion non linéaire
H03F 1/06 - Modifications des amplificateurs pour augmenter leur rendement, p.ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire dans les amplificateurs à tubes à décharge pour augmenter le rendement des amplificateurs fonctionnant aussi en modulateurs
H03F 1/30 - Modifications des amplificateurs pour réduire l'influence des variations de la température ou de la tension d'alimentation
A method and apparatus are disclosed for a multi-processor system on a chip which includes at least a first execution domain processor that is configured to run a first execution domain by accessing one or more system-on-chip resources; a first control point processor that is physically and programmatically independent from the first execution domain processor and that is configured to generate a first runtime isolation control data stream for controlling access to the one or more system-on-chip resources by the first execution domain; and an access control circuit connected between the first execution domain processor and the one or more system-on-chip resources and configured to provide a dynamic runtime isolation barrier in response to the first runtime isolation control data stream, thereby controlling access to the one or more system-on-chip resources by the first execution domain.
A method and apparatus are disclosed for a multi-processor SoC which includes an execution domain processor for running an execution domain which hosts n partitions by accessing, for each partition, one or more SoC resources; a control point processor that generates control data with n JTAG debug enable signals corresponding to the n partitions for controlling access to the SoC resources by identifying at least a first SoC resource that each partition is allowed to access; and an access control circuit connected between the execution domain and the SoC resources and configured to provide, in response to the control data, a dynamic runtime isolation barrier which allows access by the JTAG debugging tool to only a specified partition running on the execution domain which has a JTAG debug enable signal set to a first active value and prevents access to the other n-1 partitions running on the execution domain, and for the partition under debug (debug signal set to a first active value), the dynamic runtime isolation barrier can be configured to block debugger access to selected memory regions accessible by the partition under debug.
One example discloses a first-device: wherein the first-device is configured to be coupled to a second-device over an IEEE 802.11 communications link; and wherein the first-device is configured to, store a current setup between the first-device and the second-device; identify a unique identifier of the second-device; transmit a request frame to a third-device; wherein at least one of the second-device and third-device is a multi-link-device (MLD); wherein the request frame is configured to request an association with the third-device and includes the unique identifier of the second-device; receive a response frame from the third-device; and wherein the response frame includes an indication that request was successful.
One example discloses an access point (AP) device for use within a wireless local area network (WLAN), including: a controller configured to send a client-to-client sounding subvariant sensing trigger frame (TF) over the WLAN to first client station (STA1) device and a second client station (STA2) device; wherein the STA1 is configured to send a sensing message in response to receiving the client-to-client sounding subvariant sensing TF; wherein the AP controller is configured to send a reporting subvariant sensing TF to the STA2 after the sensing message is sent by the STA1; wherein the STA2 is configured to send a measurement report frame to the AP in response to receiving the reporting subvariant sensing TF; and wherein the measurement report frame includes a set of channel state information (CSI) that characterizes a WLAN channel between the STA1 and the STA2.
A method and system for generating an extended range (ER) physical layer protocol data unit (PPDU) is disclosed. The PPDU has a legacy portion of the ER PPDU which comprises one or more of a legacy short training field (L-STF), a legacy long training field (L-LTF), and a universal signaling (U-SIG) field and an ER portion of the ER PPDU which is appended to the legacy portion. The ER portion comprises one or more repetitions of a ER short training field (ER-STF), a ER long training field (ER-LTF), a ER-signal (ER-SIG) field, and a ER data field. In an example, signals indicative of the one or more repetitions for a same field are combined by a receiver to increase a signal to noise ratio of a field.
In an 802.11be wireless system, a receiving station device signals a packet padding capability in a wireless area network in accordance with an Extremely High Throughput (EHT) communication protocol by constructing a MAC control management frame to include an EHT capability element indicating whether a packet extension value longer than 16 μs is supported by the receiving station device, where one or more fields in the EHT capability element include (1) a common nominal packet padding field having a plurality of values to signal different packet extension values for use with all transmission constellations, spatial streams NSS, and resource unit (RU) allocations supported by the first STA device, including at least one packet extension value longer than 16 μs; and/or (2) a PHY packet extension threshold (PPET) field comprising a plurality of PPET values to signal packet extension values including at least one packet extension value longer than 16 μs.
A semiconductor device substrate is provided. The substrate includes an embedded trace substrate (ETS) portion. The ETS portion includes a first conductive layer embedded in the ETS portion at a first major surface. A portion of the first conductive layer is patterned to form a signal line. A non-conductive layer is disposed between the first conductive layer and a second conductive layer second embedded in the ETS portion. A third conductive layer is formed over the first major surface of the ETS portion. The third conductive layer is configured to form a stripline with the signal line of the first conductive layer.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
74.
Testing of on-chip analog-mixed signal circuits using on-chip memory
N possible DAC input codes for the DAC in an on-chip memory. The first set of ADCs is tested using the pairs of calibration codes stored in the on-chip memory and a full N-bit resolution of the DAC. Subsequently, the second set of ADCs is tested using pairs of calibration codes corresponding to a reduced M-bit resolution of the DAC, in which M is less than N. During the testing of the second set of ADCs, a portion of the calibration codes stored in the on-chip memory is overwritten.
G11C 7/16 - Emmagasinage de signaux analogiques dans des mémoires numériques utilisant une disposition comprenant des convertisseurs analogiques/numériques [A/N], des mémoires numériques et des convertisseurs numériques/analogiques [N/A]
G11C 29/18 - Dispositifs pour la génération d'adresses; Dispositifs pour l'accès aux mémoires, p.ex. détails de circuits d'adressage
H03M 1/46 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p.ex. du type à approximations successives avec convertisseur numérique/analogique pour fournir des valeurs de référence au convertisseur
75.
CLOSED LOOP POWER LOSS CONTROL OF WIRELESS POWER TRANSMISSION, AND METHODS FOR WIRELESS POWER TRANSMISSION
Power transmission associated with wireless charging of a battery of an electronic device or powering of the electronic device comprises determining a power loss associated with transmitting a power signal having a transmitted power from the wireless power transmitter to a wireless power receiver. A closed loop power loss control based on the power loss is performed which comprises outputting a target transmit power to meet a power loss limit. The power signal having the target transmit power is wirelessly transmitted to the wireless power receiver to charge the battery of the electronic device or power the electronic device and balance charging performance and safety.
H02J 50/80 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique mettant en œuvre l’échange de données, concernant l’alimentation ou la distribution d’énergie électrique, entre les dispositifs de transmission et les dispositifs de réception
H02J 50/10 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage inductif
H04B 5/00 - Systèmes de transmission à induction directe, p.ex. du type à boucle inductive
76.
METHOD AND APPARATUS FOR EXCHANGING FRAMES USING SECONDARY CHANNELS
A method and an apparatus for operating a Basic Service Set (BSS) are disclosed. A method involves announcing, by a first wireless device to a second wireless device, a BSS operating channel, wherein the first wireless device has at least one of a first transmission power capability and a first bandwidth capability, the second wireless device has at least one of a second transmission power capability that is less than the first transmission power capability and a second bandwidth capability that is narrower than the first bandwidth capability, and wherein the BSS operating channel is at least one of a punctured operating channel and an unpunctured operating channel, associating, by the second wireless device, with the first wireless device via the announcement of the BSS operating channel from the first wireless device, and exchanging frames between the first wireless device and the second wireless device in the BSS operating channel.
H04W 74/08 - Accès non planifié, p.ex. accès aléatoire, ALOHA ou accès multiple par détection de porteuse [CSMA Carrier Sense Multiple Access]
H04W 48/12 - Distribution d'informations relatives aux restrictions d'accès ou aux accès, p.ex. distribution de données d'exploration utilisant un canal de commande descendant
77.
METHOD FOR DIAGNOSING SWITCH FAULT AND/OR PHASE LOSS IN INVERTER
Methods of testing, diagnosing, or assessing the functionality of switches of an electric motor control system and/or a phase loss of an electric motor, and electric motor systems/motor control systems employing such methods, are disclosed herein. In one example embodiment, a method of diagnosing a fault includes detecting respective phase voltage signals communicated from the first, second, and third output nodes indicative of respective phase voltages occurring at the first, second, and third output nodes, respectively, and determining whether the respective phase voltages indicate that a first fault has occurred, either with respect to one or more transistors of pairs of switching transistors or with respect to one or more of first, second, and third phase windings. The determining is based upon whether the respective phase voltage signals indicate that respective phase voltages present respectively at the output nodes are equal or substantially equal to an intermediate output voltage.
Embodiments of a method and apparatus for wireless communications are disclosed. In an embodiment, a wireless device includes a wireless transceiver configured to communicate with a first device that is compatible with a first wireless communications protocol and a second device that is compatible with a second wireless communications protocol and a controller configured to announce different channel configurations for the first device that is compatible with the first wireless communications protocol and the second device that is compatible with the second wireless communications protocol when performing channel switch.
A method includes making a semiconductor die that includes a transistor with a control terminal, and two current terminals. The two current terminals include portions located in a semiconductor layer formed by an epitaxial process on a substrate with semiconductor material and dielectric material. At least some of the portions of the current terminals located in the semiconductor layer are characterized as monocrystalline and are located directly over dielectric material of the substrate. The channel region is located in a monocrystalline portion of the semiconductor layer as well.
An encapsulant compound apparatus, includes a mechanical operator, and an insert disposed on a surface of the mechanical operator. The insert operates to capture foreign material in the encapsulant compound.
B29C 48/27 - Moulage par extrusion, c. à d. en exprimant la matière à mouler dans une matrice ou une filière qui lui donne la forme désirée; Appareils à cet effet - Éléments constitutifs, détails ou accessoires; Opérations auxiliaires Évitement de la contamination
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
B29C 48/39 - Plastificateurs, homogénéisateurs ou dispositifs d’alimentation à plusieurs étages une première extrudeuse alimentant une seconde extrudeuse en matière fondue dans un lieu intermédiaire
B29C 48/375 - Plastificateurs, homogénéisateurs ou dispositifs d’alimentation à plusieurs étages
81.
MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) WITH END OF LIFE MARGIN SENSOR
A magnetoresistive random access memory (MRAM) array includes a data array and a sensor array. Each MRAM cell includes a Magnetic Tunnel Junction (MTJ). Each MRAM cell of the data array stores a data bit. A first and second column of the sensor array are connected to form a sensor column which includes sensor cells, each formed by a first MRAM cell in the first column together with a second MRAM cell in the second column along a same word line. Only one of a first MTJ of the first MRAM cell or second MTJ of the second MRAM cell is used as an MTJ of the sensor cell, and drain electrodes of select transistors of the first and second MRAM cells are electrically connected. Read circuitry provides read data from the data array and a sensor output indicative of a rupture state of an MTJ of the sensor array.
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
82.
TRANSISTOR DIE WITH PRIMARY AND ANCILLARY TRANSISTOR ELEMENTS
A transistor die includes input and output terminals and a source through-substrate via (TSV) between the input and output terminals. First and second primary drain contacts extend from the output terminal toward the input terminal past first and second sides, respectively, of the source TSV. An ancillary region is located adjacent to the source TSV, and boundaries of the ancillary region are defined by the source TSV, the first and second drain contacts, and one of the input terminal or the output terminal. The transistor further includes a primary transistor element, including a primary drain contact, a primary source contact, and a primary gate structure, located outside of the first ancillary region, and an ancillary transistor element, including an ancillary drain contact, an ancillary source contact, and an ancillary gate structure, located within the ancillary region.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
83.
FREQUENCY-MODULATED CONTINUOUS-WAVE (FMCW) RADAR INTERFERENCE MITIGATION USING AN AUTOREGRESSIVE MOVING AVERAGE (ARMA) MODEL
Systems and methods for mitigating interference in Frequency-Modulated Continuous-Wave (FMCW) radars using an Autoregressive Moving Average (ARMA) model are described. In an illustrative, non-limiting embodiment, a device includes a processor and a memory coupled to the processor, the memory having program instructions stored thereon that, upon execution by the processor, cause the device to: receive a first frame captured by a radar; receive a second frame, captured after the first frame, by the radar; and reconstruct zeroed samples in the second frame with information obtained from the first frame to mitigate interference in the second frame caused by another radar.
G01S 7/02 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe
G01S 13/58 - Systèmes de détermination de la vitesse ou de la trajectoire; Systèmes de détermination du sens d'un mouvement
G01S 13/32 - Systèmes pour mesurer la distance uniquement utilisant la transmission d'ondes continues, soit modulées en amplitude, en fréquence ou en phase, soit non modulées
One example discloses a signal driver circuit, including: an input configured to receive an input signal; an output configured to transmit an output signal; a low drop-out voltage regulator (LDO) having a regulated voltage output; a set of voltage-modulated amplifiers having a first input coupled to the regulated voltage output, and a second input configured to receive the input signal; wherein the voltage-modulated amplifier is configured to amplify the input signal and transmit an amplified input signal on the output of the signal driver circuit; a de-emphasis controller, including a set of de-emphasis levels; wherein the de-emphasis controller is configured to selectively switch-on a first subset of the set of voltage-modulated amplifiers and switch-off a second subset of the set of voltage-modulated amplifiers based on the de-emphasis levels.
G05F 1/56 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final
H03K 3/013 - Modifications du générateur en vue d'éviter l'action du bruit ou des interférences
85.
SEMICONDUCTOR DEVICE WITH ENCLOSED CAVITY AND METHOD THEREFOR
A method of forming a semiconductor device is provided. The method includes placing a semiconductor die and an RF sub-assembly on a carrier substrate. The RF sub-assembly includes a sacrificial blank, a conductive radiant element, and a conductive shield. At least a portion of the semiconductor die and the RF sub-assembly is encapsulated with an encapsulant. The carrier substrate is separated from the encapsulated semiconductor die and RF sub-assembly to expose a side of the sacrificial blank. The sacrificial blank is removed to form a cavity in the RF sub-assembly such that the conductive radiant element and the conductive shield are exposed through the cavity. A package lid is affixed on the encapsulated semiconductor die and RF sub-assembly and configured to serve as a signal reflector for propagation of an RF signal.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/552 - Protection contre les radiations, p.ex. la lumière
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
A battery management communication system comprising:
a control unit configured to receive information from each of a plurality of battery cells, and generate instructions to control the battery cells;
a plurality of segment communication units comprising at least a first and a second segment communication unit;
the first segment communication unit is configured to provide for communication between the control unit and a first cell group; and
wherein the second segment communication unit is configured to provide for communication between the control unit and a second cell group; and
a main communication unit configured to couple to the control unit and the plurality of segment communication units;
wherein said information and instructions are routed through the main communication unit and appropriate segment communication unit.
In one embodiment, a semiconductor die includes a polycrystalline semiconductor resistor structure (poly resistor structure). The poly resistor structure includes a resistive path between a first terminal and a second terminal. The poly resistor structure includes a first region having a net first conductivity type dopant concentration located in the resistance path and a second region having a net second conductivity type dopant concentration located in the resistance path. A silicide structure is located on both a first portion of the first region and a first portion of the second region to electrically connect the first portion of the first region and the first portion of the second region. In some embodiments, poly resistor structures with different conductivity type regions can be connected together.
A transistor with an emitter, base, and collector. The base includes a monocrystalline base layer. A sacrificial material is formed on the monocrystalline base layer. The sacrificial material is removed to expose a portion of the monocrystalline base layer. A base silicide includes a portion formed on the portion of the base monocrystalline base layer that was exposed by the removal of the sacrificial material.
The present invention relates to a DC-DC boost converter which ensures a fast start until the desired output voltage is reached without causing a high input current during the start phase. In particular, the limitation of the input current is influenced according to the initial output voltage. The invention also relates to a method for the boost converter.
H02M 1/36 - Moyens pour mettre en marche ou arrêter les convertisseurs
H02M 3/156 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation
One example discloses an open-circuit detector, comprising: a first current source configured to inject a current at an output of a closed-loop circuit; a detector configured to monitor a voltage of the closed-loop circuit; wherein the detector is configured to indicate whether the voltage monitored exceeds a predetermined threshold voltage; a controller configured to regulate the current injected by the first current source; wherein the controller is configured to set an open-circuit flag if the current injected caused the voltage to exceed the predetermined threshold voltage.
A wireless network includes a client device and an access point (AP). The client device generates a data packet having a physical layer protocol data unit frame format. The client device transmits the data packet to the AP such that a plurality of long training fields (LTFs) of the data packet is transmitted at higher power as compared to a data field of the data packet, and a preamble portion of the data packet is transmitted at higher power as compared to the plurality of LTFs. Further, the data field includes various resource units (RUs) and one such RU is utilized for data transmission between the client device and the AP. The transmission of the data packet from the client device to the AP in the aforementioned manner results in the range extension of the wireless network.
An electronic device substrate with a substantially planar surface formed from an electrically non-conductive material is provided with one or more metalized pads on the substantially planner surface. Each of the one or more metalized pads is surrounded by and coplanar with the first electrically nonconductive material along an outer boundary of the metalized pad. The metalized pad is patterned such that portions of the metalized pad form metalized fingers that extend radially from the outer boundary of the metalized pad in an interdigitated arrangement with the first electrically nonconductive material. The metalized pad has a solderable surface.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
93.
COLLISION PREVENTION SYSTEM AND METHOD FOR A VEHICLE
A collision prevention system for a vehicle. A collision prevention method for a vehicle. The system includes a first sensor operable to monitor a dimension (e.g. height) of the vehicle. The system also includes a second sensor for detecting a dimension (e.g. height) of an approaching obstacle. The system further includes a controller couplable to the first sensor and the second sensor. The controller is operable to compare the dimension of the vehicle monitored by the first sensor with the dimension of the approaching obstacle detected by the second sensor. The controller is also operable to, in response to a determination that the comparison of the dimension of the vehicle with the dimension of the approaching obstacle indicates a collision between the vehicle and the obstacle is possible, perform a collision prevention action.
B60W 30/09 - Entreprenant une action automatiquement pour éviter la collision, p.ex. en freinant ou tournant
B60W 40/02 - Calcul ou estimation des paramètres de fonctionnement pour les systèmes d'aide à la conduite de véhicules routiers qui ne sont pas liés à la commande d'un sous-ensemble particulier liés aux conditions ambiantes
B60W 50/14 - Moyens d'information du conducteur, pour l'avertir ou provoquer son intervention
B60W 50/10 - Interprétation des requêtes ou demandes du conducteur
A method of manufacturing a semiconductor device packaging panel is provided. The method includes forming a panel having an active side and a backside. The panel includes a plurality of semiconductor die encapsulated with an encapsulant. An active surface of the semiconductor die is exposed on the active side of the panel. A warpage control carrier is attached onto the backside of the panel. The warpage control carrier includes an electroactive element configured for substantially flattening the panel while a control voltage is applied to the electroactive element.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
One example discloses a security device, including: a bulk security capacitance, including a first endpoint and a second endpoint, and having, a first layer including a first set of conductive elements, the first endpoint, and the second endpoint; and a second layer including a second set of conductive elements; wherein the first set of conductive elements and the second set of conductive elements together form at least two bulk capacitors in series; wherein the first and second layers are separated by a distance; and wherein the first and second endpoints are configured to be coupled to a tamper detection circuit configured to detect a change in the bulk security capacitance.
G06K 19/077 - Supports d'enregistrement avec des marques conductrices, des circuits imprimés ou des éléments de circuit à semi-conducteurs, p.ex. cartes d'identité ou cartes de crédit avec des puces à circuit intégré - Détails de structure, p.ex. montage de circuits dans le support
G06K 19/07 - Supports d'enregistrement avec des marques conductrices, des circuits imprimés ou des éléments de circuit à semi-conducteurs, p.ex. cartes d'identité ou cartes de crédit avec des puces à circuit intégré
Memory built-in self-test (MBIST) circuitry for a disruptive memory includes an address sequencer configured to select an address with the disruptive memory as a test location, and control circuitry configured to direct a test sequence including a plurality of test operations on the test location. The control circuitry includes a first fault counter and a second fault counter, in which the control circuitry is configured to, after each test operation of the test sequence, determine whether to selectively update a first fault counter and whether to selectively update a second fault counter. The address sequencer, after completion of the test sequence, selects a next address within the disruptive memory as a next test location.
G11C 29/36 - Dispositifs de génération de données, p.ex. inverseurs de données
G11C 29/12 - Dispositions intégrées pour les tests, p.ex. auto-test intégré [BIST]
G11C 29/20 - Dispositifs pour la génération d'adresses; Dispositifs pour l'accès aux mémoires, p.ex. détails de circuits d'adressage utilisant des compteurs ou des registres à décalage à rétroaction linéaire [LFSR]
97.
TRANSISTOR CIRCUITS WITH SHIELDED REFERENCE TRANSISTORS
A device having a reference transistor fabricated within the same semiconductor substrate as a primary transistor (e.g., configured for use in a radiofrequency amplifier or other active circuit) has a shared metallization area coupled to a current terminal of both transistors configured to shield a control terminal of the reference transistor from coupling of alternating current interference from alternating currents within the primary transistor.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 25/10 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs ayant des conteneurs séparés
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
One example discloses a relay device, including: a controller configured to receive an original WLAN (wireless local area network) standards compliant message signal, that includes an embedded WLAN message, from a receiver; wherein the controller is configured to command a transmitter to transmit a copy of the original WLAN message signal, if the original message signal or the embedded WLAN message has a set of predetermined attributes; and wherein the controller is configured to command the transmitter without decoding select portions of the embedded WLAN message.
A device assembly includes a functional substrate having one or more electronic components formed there. The functional substrate has a cavity extending from a first surface toward a second surface of the functional substrate at a location that lacks the electronic components. The device assembly further includes a semiconductor die placed within the cavity with a pad surface of the semiconductor die being opposite to a bottom of the cavity. The functional substrate may be formed utilizing a first fabrication technology and the semiconductor die may be formed utilizing a second fabrication technology that differs from the first fabrication technology.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
100.
HARMONIC TRAP FILTER WITH NON-UNIFORM RESONANCE FREQUENCY DISTRIBUTION
An RF amplifier includes at least one harmonic trap filter with an array of shunt filter legs having a non-uniform resonance frequency distribution. The harmonic trap filter is configured to suppress frequencies in a suppression frequency range that includes harmonic frequencies of carrier frequencies in a range of carrier frequencies. Each of the shunt filter legs includes a capacitor and inductor coupled in series, and an intermediate node coupled between the capacitor and the inductor. Each intermediate node of the shunt filter leg is coupled to at least one other intermediate node of another shunt filter leg of the filter with a dampening resistor. Shunt filters at or near edges of the array are configured to have lower resonance frequencies than those at or near the center of the array to suppress excess current flow at edges of the RF amplifier.
