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Résultats pour
brevets
1.
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IMAGE OUTPUTTING DEVICE AND IMAGE OUTPUTTING METHOD
Numéro d'application |
18221895 |
Statut |
En instance |
Date de dépôt |
2023-07-14 |
Date de la première publication |
2024-03-28 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
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Inventeur(s) |
- Peng, Kang
- Shen, Gang
- Lu, Yang
- He, Dong-Yu
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Abrégé
An image outputting device includes a sensing circuit for generating an image signal according to a configuration; a processing circuit, coupled to the sensing circuit, for performing an image processing on the image signal according to the configuration to generate an image processing result; and a controlling circuit, coupled to the sensing circuit and the processing circuit, for setting the configuration and entering an operating system after setting the configuration.
Classes IPC ?
- G06V 10/56 - Extraction de caractéristiques d’images ou de vidéos relative à la couleur
- G06T 5/00 - Amélioration ou restauration d'image
- G06T 9/00 - Codage d'image
- H04N 9/69 - Circuits pour modifier les signaux de couleur par correction de gamma
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2.
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ADDRESS CONVERSION SYSTEM AND ADDRESS CONVERSION METHOD
Numéro d'application |
18320185 |
Statut |
En instance |
Date de dépôt |
2023-05-18 |
Date de la première publication |
2024-03-28 |
Propriétaire |
Realtek Semiconductor Corporation (Taïwan, Province de Chine)
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Inventeur(s) |
- Wu, Kuo-Jung
- Chen, Yi-Cheng
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Abrégé
The address conversion system includes a storage device, a memory bus, and a processor. The processor is configured to execute the following steps: generating a real buffer on the storage device; generating a fake buffer in a fake capacity of the storage device by a fake buffer algorithm; establishing a coupling relationship between the real buffer and the fake buffer through a coupling algorithm by the coupler of the memory bus; receiving a compressed data from a first device by the real buffer; when a second device wants to read the fake buffer, the coupler guides the second device to the real buffer through the coupling relationship for reading; transmitting the compressed data of the real buffer to the coupler by the memory bus; decompressing the compressed data into a decompressed data by the coupler; and transmitting the decompressed data to the second device by the memory bus.
Classes IPC ?
- G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
- G06F 13/40 - Structure du bus
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3.
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Duty cycle adjustment circuit and method thereof
Numéro d'application |
17938360 |
Numéro de brevet |
11942943 |
Statut |
Délivré - en vigueur |
Date de dépôt |
2022-10-06 |
Date de la première publication |
2024-03-26 |
Date d'octroi |
2024-03-26 |
Propriétaire |
REALTEK SEMICONDUCTOR CORP. (Taïwan, Province de Chine)
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Inventeur(s) |
Lin, Chia-Liang (leon)
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Abrégé
A method of duty cycle adjustment includes conditionally inverting an input clock into a conditionally inverted clock; and adjusting a duty cycle of the conditionally inverted clock in one direction in accordance with an integer that represents an amount of duty cycle adjustment, using an uneven clock buffer and a plurality of uneven clock multiplexers that are cascaded and incrementally activated as a value of the integer increments.
Classes IPC ?
- H03K 7/08 - Modulation de durée ou de largeur
- H03K 3/017 - Réglage de la largeur ou du rapport durée période des impulsions
- H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
- H03K 17/693 - Dispositifs de commutation comportant plusieurs bornes d'entrée et de sortie, p.ex. multiplexeurs, distributeurs
- H03K 19/20 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion caractérisés par la fonction logique, p.ex. circuits ET, OU, NI, NON
- H03M 7/16 - Conversion en, ou à partir de codes à distance unitaire, p.ex. code de Gray, code binaire réfléchi
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4.
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PROGRAMMABLE SECURE MANAGEMENT DEVICE AND CONTROL METHOD FOR PERFORMING KEY FORWARDING BETWEEN SECURE DEVICES
Numéro d'application |
18367989 |
Statut |
En instance |
Date de dépôt |
2023-09-13 |
Date de la première publication |
2024-03-21 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
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Inventeur(s) |
Chiang, Ya-Han
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Abrégé
A programmable secure management device and a control method for performing key forwarding between secure devices are provided. The programmable secure management device includes a key generating device, a key accepting device and a forwarding controller circuit, wherein the forwarding controller circuit is electrically coupled to the key generating device and the key accepting device. The key generating device is configured to output a source key, and the key accepting device is configured to accept a destination key, wherein the forwarding controller circuit is configured to receive a forwarding command from a host device outside the programmable secure management device, to allow the host device to request the forwarding controller circuit via the forwarding command for taking the source key as the destination key to be loaded in the key accepting device.
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5.
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METHOD FOR FAST STARTING UP TELEVISION DISPLAY FUNCTION AND TELEVISION SYSTEM
Numéro d'application |
18369270 |
Statut |
En instance |
Date de dépôt |
2023-09-18 |
Date de la première publication |
2024-03-21 |
Propriétaire |
REALTEK SEMICONDUCTOR CORP. (Taïwan, Province de Chine)
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Inventeur(s) |
- Wu, Yen-Hsing
- Tsao, Chih-Ming
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Abrégé
A method for fast starting up a television display function and a television system are provided. In the method, when a television device is powered on, the television system operated in the television device performs a hardware initialization and a fast start-up procedure. In the fast start-up procedure, a set of picture-quality parameters is loaded to the television system from a storage circuit. Display parameters of the television device are configured according to the picture-quality parameters, accordingly, a display of the television device starts to display a picture. The picture can be produced from image signals received through an external source such as a high-definition multimedia interface (HDMI) or a Display Port, a type-C interface, or other sources of the television device. The picture-quality parameters are collected and stored in the storage circuit during operation of the television system after the operating system booting procedure is completed.
Classes IPC ?
- H04N 21/443 - Procédés de système d'exploitation, p.ex. démarrage d'un boîtier décodeur STB, implémentation d'une machine virtuelle Java dans un boîtier décodeur STB ou gestion d'énergie dans un boîtier décodeur STB
- H04N 21/4363 - Adaptation du flux vidéo à un réseau local spécifique, p.ex. un réseau IEEE 1394 ou Bluetooth®
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6.
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Signal transmission device
Numéro d'application |
18367661 |
Statut |
En instance |
Date de dépôt |
2023-09-13 |
Date de la première publication |
2024-03-21 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
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Inventeur(s) |
- Yeh, Chih-Yuan
- Li, Huan-Chun
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Abrégé
A signal transmission device has an initial signal stabilization mechanism and includes a driver and a bypass circuit. The driver includes: a first current source circuit coupled between a high voltage terminal and a first node; a second current source circuit coupled between a low voltage terminal and a second node; and a driving circuit coupled between the first node and the second node. The driving circuit outputs an output signal according to a first bias voltage of the first node, a second bias voltage of the second node, and an input signal during a signal output operation. The bypass circuit is coupled between the first node and the second node. In the beginning of the signal output operation, the bypass circuit conducts a current from the first node to the second node to assist in establishing the first and second bias voltages and thereby stabilize the output signal.
Classes IPC ?
- H04L 25/02 - Systèmes à bande de base - Détails
- H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
- H03K 19/0185 - Dispositions pour le couplage; Dispositions pour l'interface utilisant uniquement des transistors à effet de champ
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7.
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Circuit layout for improving power supply rejection ratio
Numéro d'application |
18209156 |
Statut |
En instance |
Date de dépôt |
2023-06-13 |
Date de la première publication |
2024-03-21 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
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Inventeur(s) |
- Shih, Kuan-Yu
- Su, Ying-Rong
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Abrégé
A circuit layout for improving the power supply rejection ratio includes a radio frequency (RF) choke and an inductor. The RF choke receives a supply voltage and includes: a first choke coil positioned in an ultra-thick metal (UTM) layer, the coil including a first choke electrode; and a second choke coil positioned in a redistribution layer (RDL), the coil including a second choke electrode. The inductor belongs to a main circuit and includes: a primary-side coil surrounding the first choke coil in the UTM layer, and being coupled to the first/second chock electrode and the main circuit's signal input circuit; and a secondary-side coil surrounding the first choke coil in the UTM layer and surrounding the second choke coil in the RDL, and being used for signal output. The inductor and the RF choke jointly form mutual induction to suppress the noise of the supply voltage.
Classes IPC ?
- G05F 1/46 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu
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8.
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SELF-LOOPBACK RADIO TRANSMITTER
Numéro d'application |
18046216 |
Statut |
En instance |
Date de dépôt |
2022-10-13 |
Date de la première publication |
2024-03-21 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
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Inventeur(s) |
- Lin, Chia-Liang (leon)
- Chien, Ting-Hsu
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Abrégé
A self-loopback radio transmitter having a transmitter with a modulator configured to up-convert a first baseband signal into a first RF (radio frequency) signal in accordance with a first LO (local oscillator) signal, and a power amplifier configured to receive the first RF signal and output a second RF signal to be emitted by an antenna and a third RF signal to be looped back, wherein the third RF signal is magnetically coupled from the second RF signal; and a loopback network having a shielded serial inductor configured to receive the third RF signal and output a fourth RF signal, and a demodulator configured to down-convert the fourth RF signal into a second baseband signal in accordance with a second LO signal, wherein the shielded serial inductor has a serial inductor of spiral topology and a coil laid out on a lower metal layer.
Classes IPC ?
- H04B 1/04 - Circuits
- H03F 3/24 - Amplificateurs de puissance, p.ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
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9.
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VIDEO SWITCHING METHOD AND VIDEO PROCESSING SYSTEM
Numéro d'application |
18206300 |
Statut |
En instance |
Date de dépôt |
2023-06-06 |
Date de la première publication |
2024-03-14 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
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Inventeur(s) |
- Liu, Qing
- Yin, Zhao-Dong
- Li, Ming-Rui
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Abrégé
A video switching method includes the following operations: decoding second video data during a period when a panel is driven to display image content corresponding to first video data to generate frame parameter data and image data; and processing the image data according to the frame parameter data in response to a control command to drive the panel to display image content corresponding to the second video data.
Classes IPC ?
- H04N 19/423 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques - caractérisés par les détails de mise en œuvre ou le matériel spécialement adapté à la compression ou à la décompression vidéo, p.ex. la mise en œuvre de logiciels spécialisés caractérisés par les dispositions des mémoires
- H04N 5/268 - Distribution ou commutation du signal
- H04N 19/172 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c. à d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p.ex. un objet la zone étant une image, une trame ou un champ
- H04N 19/30 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant des techniques hiérarchiques, p.ex. l'échelonnage
- H04N 19/44 - Décodeurs spécialement adaptés à cet effet, p.ex. décodeurs vidéo asymétriques par rapport à l’encodeur
- H04N 19/463 - Inclusion d’information supplémentaire dans le signal vidéo pendant le processus de compression par compression des paramètres d’encodage avant la transmission
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10.
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Waterproof-state recognition and processing method and device applicable to capacitive touch screen
Numéro d'application |
18244542 |
Statut |
En instance |
Date de dépôt |
2023-09-11 |
Date de la première publication |
2024-03-14 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
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Inventeur(s) |
Bian, Xiao-Wei
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Abrégé
A waterproof-state recognition and processing method and device is applicable to a capacitive touch screen. The method and device can differentiate a water-affected region from a water-free region, and allow a touch-responding operation for the water-free region when the water-affected region exists. The method includes: scanning the screen to obtain data of multiple channels of the screen; determining whether any of the data reaches a waterproof threshold; when any of the data reaches the waterproof threshold, performing a waterproof-state process; when none of the data reaches the waterproof threshold, determining whether any of the data reaches a finger-touch threshold; when any of the data reaches the finger-touch threshold, performing a finger-touch-state process; and when none of the data reaches the finger-touch threshold, performing an idle-state process.
Classes IPC ?
- G06F 3/041 - Numériseurs, p.ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction
- G06F 3/01 - Dispositions d'entrée ou dispositions d'entrée et de sortie combinées pour l'interaction entre l'utilisateur et le calculateur
- G06F 3/044 - Numériseurs, p.ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction par des moyens capacitifs
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11.
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COMMUNICATION SYSTEM, ELECTRONIC DEVICE, AND DETERMINATION METHOD FOR DETERMINING ECHO NOISE CANCELLING ABILITY
Numéro d'application |
18341777 |
Statut |
En instance |
Date de dépôt |
2023-06-27 |
Date de la première publication |
2024-03-07 |
Propriétaire |
Realtek Semiconductor Corporation (Taïwan, Province de Chine)
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Inventeur(s) |
- Li, Cheng-Hsien
- Huang, Bo-Rong
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Abrégé
An electronic device includes a processor circuit, a frequency-domain-to-time-domain conversion circuit, a transmitter circuit, a hybrid circuit, a receiver circuit, and a time-domain-to-frequency-domain conversion circuit. The processor circuit generates a frequency-domain transmitting signal. The frequency-domain-to-time-domain conversion circuit converts the frequency-domain transmitting signal into a first time-domain transmitting signal. The transmitter circuit generates a second time-domain transmitting signal. The hybrid circuit includes an echo noise cancelling path and an echo noise path. When the echo noise cancelling path is turned off, the processor circuit receives a first frequency-domain receiving signal. When the echo noise cancelling path is turned on, the processor circuit receives a second frequency-domain receiving signal. The processor circuit determines an echo noise cancelling ability of the hybrid circuit according to the first frequency-domain receiving signal and the second frequency-domain receiving signal.
Classes IPC ?
- H04L 5/14 - Fonctionnement à double voie utilisant le même type de signal, c. à d. duplex
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12.
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MEMORY DEVICE OF REDUCING THE NUMBER OF CALIBRATION RESISTORS AND CONTROL METHOD THEREOF
Numéro d'application |
18116823 |
Statut |
En instance |
Date de dépôt |
2023-03-02 |
Date de la première publication |
2024-02-29 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
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Inventeur(s) |
- Lin, Wen-Wei
- Cheng, Ching-Sheng
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Abrégé
A memory device includes a resistor and a controller chip. The controller chip includes a first controller, a second controller, a first set of input/output (I/O) circuits, a second set of I/O circuits, a first calibration circuit, a second calibration circuit, and an arbitration circuit. The first controller transmits a first controller calibration request. The second controller transmits a second controller calibration request. The arbitration circuit instructs the first calibration circuit to perform a first controller calibration on the first set of I/O circuits using the resistor in response to the first controller calibration request, and instructs the second calibration circuit to perform a second controller calibration on the second set of I/O circuits using the resistor in response to the second controller calibration request. A first time interval of performing the first controller calibration and a second time interval of performing the second controller calibrations are non-overlapping.
Classes IPC ?
- G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
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13.
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Clock management circuit and clock management method
Numéro d'application |
18236713 |
Statut |
En instance |
Date de dépôt |
2023-08-22 |
Date de la première publication |
2024-02-29 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
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Inventeur(s) |
Liang, Yu-Jie
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Abrégé
A clock management circuit and a clock management method are used for managing an operating clock of a processor circuit, and the processor circuit changes the level of a state signal according to an interrupt signal. The clock management circuit includes a delay circuit for delaying a wake-up interrupt to generate a delayed wake-up interrupt; and a clock control circuit for generating the operating clock according to a reference clock, generating the wake-up interrupt according to the state signal, and adjusting the frequency of the operating clock according to the delayed wake-up interrupt.
Classes IPC ?
- G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
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14.
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Amplifier circuit having reset mechanism
Numéro d'application |
18237921 |
Statut |
En instance |
Date de dépôt |
2023-08-25 |
Date de la première publication |
2024-02-29 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
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Inventeur(s) |
Huang, Shih-Hsiung
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Abrégé
The present disclosure discloses an amplifier circuit having reset mechanism. A pair of upper-half branches are electrically coupled between a first supply voltage and a pair of differential output terminals, are symmetrical and each includes at least one P-type transistor. A pair of lower-half branches are electrically coupled between the pair of differential output terminals and a second supply voltage, are symmetrical and each includes at least one N-type transistor. The P-type transistors and the N-type transistors are categorized into transistor groups that perform differential signal receiving process in turn in an interlaced manner under an interlaced input mode and perform reset signal receiving process to be turned on and be AC grounded when the differential signal receiving process is not performed such that the differential output terminals generate differential outputs.
Classes IPC ?
- H03F 3/45 - Amplificateurs différentiels
- H03K 5/24 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p.ex. la pente, l'intégrale la caractéristique étant l'amplitude
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15.
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NETWORK CONTROL METHOD AND NETWORK INTERFACE CARD
Numéro d'application |
18452541 |
Statut |
En instance |
Date de dépôt |
2023-08-20 |
Date de la première publication |
2024-02-29 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
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Inventeur(s) |
Hong, Yuan
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Abrégé
A network control method is configured to balance the loading of a plurality of processes. The method includes obtaining an IP address of a packet; deleting a portion of bits of the IP address to generate a series according to an IP address entropy distribution; performing a hash function to the series to generate a hash value; performing a modulo operation to the hash value to obtain a remainder; and assigning the packet to a processor of the plurality of processes corresponding to the remainder.
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16.
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UNIVERSAL SERIAL BUS DEVICE AND SYSTEM TYPE DETERMINING METHOD THEREOF
Numéro d'application |
18453920 |
Statut |
En instance |
Date de dépôt |
2023-08-22 |
Date de la première publication |
2024-02-29 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
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Inventeur(s) |
- Huang, Po-Chao
- Huang, Li-Wei
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Abrégé
The present disclosure provides an USB device and a system type determining method thereof. The system type determining method includes: determining, by the USB device, whether an USB host transmit at least one of an HID interrupt signal and an UAC1 status interrupt signal; and determining, by the USB device, a system type of the USB host according to the result of determining whether the USB host transmit at least one of the HID interrupt signal and the UAC1 status interrupt signal.
Classes IPC ?
- G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation
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17.
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DISPLAY DEVICE AND IMAGE DISPLAY METHOD
Numéro d'application |
18165924 |
Statut |
En instance |
Date de dépôt |
2023-02-07 |
Date de la première publication |
2024-02-29 |
Propriétaire |
Realtek Semiconductor Corporation (Taïwan, Province de Chine)
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Inventeur(s) |
- Lee, Wan Jou
- Yang, Sheng Ju
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Abrégé
An image display method, comprising the following steps: receiving an image signal from a graphics processor by an image processor, wherein the image signal is configured to drive a display panel to display a main image; enlarging a target area in the main image to form a first enlarged image according to an enlargement command; modifying the first enlarged image into a non-rectangular image to use the non-rectangular image as a second enlarged image; and driving the display panel to display the main image and the second enlarged image simultaneously by the image processor, wherein the second enlarged image is overlapped on the main image.
Classes IPC ?
- G06T 3/40 - Changement d'échelle d'une image entière ou d'une partie d'image
- G06T 7/62 - Analyse des attributs géométriques de la superficie, du périmètre, du diamètre ou du volume
- G06T 7/68 - Analyse des attributs géométriques de la symétrie
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18.
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Image processing apparatus and method having lens color-shading correction mechanism
Numéro d'application |
18224309 |
Statut |
En instance |
Date de dépôt |
2023-07-20 |
Date de la première publication |
2024-02-29 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
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Inventeur(s) |
- Chen, Sheng-Kai
- Lien, Hui-Chun
- Huang, Wen-Tsung
- Yen, Shih-Hsiang
- Huang, Szu-Po
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Abrégé
The present disclosure discloses an image processing apparatus having lens color-shading correction mechanism. A first and a second calibration circuits perform lens color-shading correction on an input image according to a first and a second calibration parameters to generate a first and a second calibrated images. A first and a second statistic circuits perform statistic on the first and the second calibrated images to generate a first and a second statistic results. A calibration operation circuit adjusts the second calibration parameters when the first calibrated image is determined to have a color-shading condition according to the first statistic result and when the second calibrated image is determined to not satisfy a color-shading criteria, and sets the second calibration parameters as the first calibration parameters when the second calibration parameters satisfies the color-shading criteria such that the first calibrated image generated by the first calibration circuit is outputted as an output calibrated image.
Classes IPC ?
- H04N 25/611 - Correction de l'aberration chromatique
- G06T 5/00 - Amélioration ou restauration d'image
- G06T 7/80 - Analyse des images capturées pour déterminer les paramètres de caméra intrinsèques ou extrinsèques, c. à d. étalonnage de caméra
- G06T 7/90 - Détermination de caractéristiques de couleur
- G06V 10/56 - Extraction de caractéristiques d’images ou de vidéos relative à la couleur
- G06V 10/75 - Appariement de motifs d’image ou de vidéo; Mesures de proximité dans les espaces de caractéristiques utilisant l’analyse de contexte; Sélection des dictionnaires
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19.
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Image processing circuit and method having output timing adjustment mechanism
Numéro d'application |
18224339 |
Statut |
En instance |
Date de dépôt |
2023-07-20 |
Date de la première publication |
2024-02-29 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
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Inventeur(s) |
- Yeh, Tzu-Min
- Chang, Kai-Cho
- Wu, Po-Hsien
- Tung, Hsu-Jung
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Abrégé
The present disclosure discloses an image processing circuit having output timing adjustment mechanism. An image enhancement circuit performs image enhancement on an input image to generate an enhanced image. A first image processing path and a second image processing path respectively perform processing on the enhanced image having a first timing and the enhanced image having a second timing to generate a first output image and a second output image. A timing control circuit adjusts the timing of the enhanced image according to requirements of the first image processing path and the second image processing path to generate the enhanced image having the first timing and the enhanced image having the second timing. A first image output interface outputs the first output image. A second image output interface outputs the second output image.
Classes IPC ?
- G06T 5/00 - Amélioration ou restauration d'image
- G06T 3/40 - Changement d'échelle d'une image entière ou d'une partie d'image
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20.
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NEURAL NETWORK SYSTEM AND OPERATION METHOD FOR NEURAL NETWORK SYSTEM
Numéro d'application |
18107806 |
Statut |
En instance |
Date de dépôt |
2023-02-09 |
Date de la première publication |
2024-02-22 |
Propriétaire |
REALTEK SEMICONDUCTOR CORP. (Taïwan, Province de Chine)
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Inventeur(s) |
Lee, Cheng-Hao
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Abrégé
A neural network system and an operation method for a neural network system are provided. The neural network system includes at least one edge device and a server. Each edge device stores a neural network architecture. The neural network architecture includes at least one operator and a model identifier, and the at least one operator of the neural network architecture stored in the each edge device includes an operator identifier. The server is connected to the each edge device. The each edge device is configured to, upon being powered on, transmit the operator identifier of each operator to the server to request the server to return parameters for the each operator; receive the parameters of the each operator and combine the parameters of the each operator with the neural network architecture to obtain a neural network model; and execute a predetermined task based on the neural network model.
Classes IPC ?
- G06N 3/04 - Architecture, p.ex. topologie d'interconnexion
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21.
|
PACKET PROCESSING DEVICE AND PACKET PROCESSING METHOD
Numéro d'application |
18182386 |
Statut |
En instance |
Date de dépôt |
2023-03-13 |
Date de la première publication |
2024-02-22 |
Propriétaire |
Realtek Semiconductor Corporation (Taïwan, Province de Chine)
|
Inventeur(s) |
- Lu, Kuo Cheng
- Liu, Chun-Ming
- Lo, Sheng Wen
|
Abrégé
A first packet flow and a second packet flow support a first protocol, a third packet flow and a fourth packet flow support a second protocol, and a priority of the first protocol is lower than a priority of the second protocol. The first packet flow and the third packet flow are transmitted from a first ingress port to a first egress port. The second packet flow and the fourth packet flow are transmitted from a second ingress port to a second egress port. When the packet processing device is in a congested state, a bandwidth modulator performs a first suppression process on the first packet flow at the first ingress port, and the bandwidth modulator performs a second suppression process on the second packet flow at the second egress port or on the third packet flow at the first ingress port.
Classes IPC ?
- H04L 47/12 - Prévention de la congestion; Récupération de la congestion
- H04L 47/24 - Trafic caractérisé par des attributs spécifiques, p.ex. la priorité ou QoS
|
22.
|
SIGNAL COMPENSATION DEVICE AND ASSOCIATED METHOD
Numéro d'application |
18225166 |
Statut |
En instance |
Date de dépôt |
2023-07-24 |
Date de la première publication |
2024-02-22 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
|
Inventeur(s) |
Chen, Chun-Yi
|
Abrégé
A signal compensation device includes a first receiving circuit, a second receiving circuit, a first buffer, a second buffer, a third buffer, and a processing circuit. The first receiving circuit receives a first video signal from a first video source. The second receiving circuit receives a second video signal from a second video source, wherein both the first video signal and the second video signal correspond to a same program. The first buffer stores a first transport stream (TS) packet group corresponding to the first video signal. The second buffer stores a second TS packet group corresponding to the second video signal. The processing circuit dynamically stores a first TS packet of the first TS packet group or a second TS packet of the second TS packet group to the third buffer according to a predetermined source in response to TS packet status.
Classes IPC ?
- H04L 49/9047 - Dispositions de mémoires tampon comprenant plusieurs mémoires tampon, p.ex. des réservoirs de mémoires tampon
- H04L 65/752 - Gestion des paquets du réseau multimédia en adaptant les médias aux capacités du réseau
- H04N 21/462 - Gestion de contenu ou de données additionnelles, p.ex. création d'un guide de programmes électronique maître à partir de données reçues par Internet et d'une tête de réseau ou contrôle de la complexité d'un flux vidéo en dimensionnant la résolution o
- H04N 21/44 - Traitement de flux élémentaires vidéo, p.ex. raccordement d'un clip vidéo récupéré d'un stockage local avec un flux vidéo en entrée ou rendu de scènes selon des graphes de scène MPEG-4
- H04N 21/438 - Interfaçage de la voie descendante du réseau de transmission provenant d'un serveur, p.ex. récupération de paquets MPEG d'un réseau IP
- H04N 21/239 - Interfaçage de la voie montante du réseau de transmission, p.ex. établissement de priorité des requêtes de clients
|
23.
|
METHOD AND APPARATUS FOR SIMULATING BREAKDOWN OF ELECTRONIC COMPONENT
Numéro d'application |
18234884 |
Statut |
En instance |
Date de dépôt |
2023-08-17 |
Date de la première publication |
2024-02-22 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Liao, Shih-Hsin
- Liu, Rui-Hong
- Tsaur, Tay-Her
- Lin, Po-Ching
|
Abrégé
A method and apparatus for simulating breakdown of an electronic component are provided. The method includes: when a terminal of an equivalent circuit model receives test charges, pulling up a voltage level of a first node of the equivalent circuit model; when the voltage level of the first node reaches a first threshold, turning on a first voltage controlled switch to pull up a voltage level of a second node of the equivalent circuit model; when the voltage level of the second mode reaches a second threshold, turning on a second voltage controlled switch to pull down a voltage level of the terminal to a holding voltage level to simulate snapback breakdown of the electronic component; and turning on a third voltage controlled switch to pull down the voltage level of the second node to turn off the second voltage controlled switch, thereby simulating second breakdown of the electronic component.
Classes IPC ?
- H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
- G06F 30/367 - Vérification de la conception, p.ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
|
24.
|
REAL-TIME AUDIO PROCESSING SYSTEM, REAL-TIME AUDIO PROCESSING PROGRAM, AND METHOD FOR TRAINING SPEECH ANALYSIS MODEL
Numéro d'application |
17972030 |
Statut |
En instance |
Date de dépôt |
2022-10-24 |
Date de la première publication |
2024-02-08 |
Propriétaire |
REALTEK SEMICONDUCTOR CORP. (Taïwan, Province de Chine)
|
Inventeur(s) |
Chu, Yen-Hsun
|
Abrégé
An audio real-time processing system, an audio real-time processing program product and method for training speech analysis model are provided. The speech analysis model is firstly trained to obtain, from an original audio, mask information which is used to mask the original audio to get a target audio. The system obtains a plurality of analyzed audio according to the target audio and the original audio, obtains repeated audio section according to the plurality of the analyzed and output the repeated audio section.
Classes IPC ?
- G10L 21/0272 - Séparation du signal de voix
- G10L 21/0356 - Amélioration de l'intelligibilité de la parole, p.ex. réduction de bruit ou annulation d'écho en changeant l’amplitude pour la synchronisation avec d’autres signaux, p.ex. signaux vidéo
|
25.
|
Image processing method and image processing device for enhancing image processing efficiency
Numéro d'application |
18135195 |
Statut |
En instance |
Date de dépôt |
2023-04-17 |
Date de la première publication |
2024-02-08 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Wu, Po-Hsien
- Tseng, Yi-Chen
|
Abrégé
An image processing method includes receiving an image frame, retrieving luminance information and chrominance information from the image frame, respectively, encoding the luminance information to generate an encoded luminance frame, encoding the chrominance information to generate an encoded chrominance frame, writing the encoded luminance frame to a first memory portion of a memory, and writing the encoded chrominance frame to a second memory portion of the memory. The image processing method further includes reading the encoded luminance frame from the first memory portion and decoding the encoded luminance frame to generate decoded luminance information, and reading the encoded chrominance frame from the second memory portion and decoding the encoded chrominance frame to generate decoded chrominance information.
Classes IPC ?
- H04N 19/186 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c. à d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une couleur ou une composante de chrominance
- H04N 19/423 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques - caractérisés par les détails de mise en œuvre ou le matériel spécialement adapté à la compression ou à la décompression vidéo, p.ex. la mise en œuvre de logiciels spécialisés caractérisés par les dispositions des mémoires
- H04N 19/172 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c. à d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p.ex. un objet la zone étant une image, une trame ou un champ
- H04N 9/77 - Circuits pour le traitement l'un par rapport à l'autre des signaux de luminance et de chrominance, p.ex. ajustement de la phase du signal de luminance par rapport au signal de couleur, correction différentielle du gain ou de la phase
|
26.
|
IMAGE PROCESSING CIRCUIT AND IMAGE PROCESSING METHOD
Numéro d'application |
18164635 |
Statut |
En instance |
Date de dépôt |
2023-02-06 |
Date de la première publication |
2024-02-08 |
Propriétaire |
Realtek Semiconductor Corporation (Taïwan, Province de Chine)
|
Inventeur(s) |
- Lee, Kung Ho
- Cheng, Yu Cheng
- Wu, Jia Wei
|
Abrégé
An image processing circuit includes a first buffer circuit, a first selector circuit, a processor circuit, a second buffer circuit, and an assigning circuit. The first buffer circuit receives pixels in a sliding window of an image. The first selector circuit outputs the pixels according to a mode signal. The processor circuit performs a first filtering process on the pixels to generate first processed pixels. The assigning circuit transmits the first processed pixels to a back-end circuit or transmits the first processed pixels to the second buffer circuit. When the assigning circuit transmits the first processed pixels to the second buffer circuit, the first selector circuit transm its the first processed pixels to the processor circuit, the processor circuit performs a second filtering process on the first processed pixels to generate second processed pixels, and the assigning circuit transmits the second processed pixels to the back-end circuit.
Classes IPC ?
- G06T 1/20 - Architectures de processeurs; Configuration de processeurs p.ex. configuration en pipeline
- G06T 5/00 - Amélioration ou restauration d'image
- G06T 5/20 - Amélioration ou restauration d'image en utilisant des opérateurs locaux
|
27.
|
SoC with UART interface
Numéro d'application |
18229359 |
Statut |
En instance |
Date de dépôt |
2023-08-02 |
Date de la première publication |
2024-02-08 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
- Lai, Chao-Min
- Lin, Yu-Jen
- Wang, Hung-Wei
- Kuo, Huang-Lin
|
Abrégé
A system on a chip (SoC) with a Universal Asynchronous Receiver/Transmitter (UART) interface includes a UART interface circuit, a detection circuit, and a control circuit. The UART interface circuit includes: a plurality of UART signal pads for receiving and transmitting signals; and a UART voltage pad for receiving an external operating voltage. The detection circuit is configured to detect the magnitude of the external operating voltage and thereby generate a detection result. The control circuit is configured to determine setting of a supply voltage for the plurality of UART signal pads according to the detection result. The control circuit makes the setting of the supply voltage be compatible with the external operating voltage according to the detection result, wherein the external operating voltage is a lower first voltage or a higher second voltage, and the first lower voltage is equal to an internal device operating voltage of the SoC.
Classes IPC ?
- G06F 13/38 - Transfert d'informations, p.ex. sur un bus
|
28.
|
Image processing method and image processing device for enhancing image processing efficiency
Numéro d'application |
18135192 |
Statut |
En instance |
Date de dépôt |
2023-04-17 |
Date de la première publication |
2024-02-08 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Tseng, Yi-Chen
- Wu, Po-Hsien
|
Abrégé
An image processing device includes an image encoder, a memory and an image decoder. The image encoder receives an input image frame, retrieves luminance information and chrominance information from the input image frame, respectively, encodes the luminance information to generate an encoded luminance frame, and encodes the chrominance information to generate an encoded chrominance frame. The memory includes a first memory portion, a second memory portion and a third memory portion. The first memory portion stores the encoded luminance frame, and the second memory portion or the third memory portion stores the encoded chrominance frame. The image decoder reads the encoded luminance frame from the first memory portion to perform decoding, and reads the encoded chrominance frame from the second memory portion or the third memory portion for decoding.
Classes IPC ?
- H04N 19/423 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques - caractérisés par les détails de mise en œuvre ou le matériel spécialement adapté à la compression ou à la décompression vidéo, p.ex. la mise en œuvre de logiciels spécialisés caractérisés par les dispositions des mémoires
- H04N 19/186 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c. à d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une couleur ou une composante de chrominance
- H04N 19/172 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c. à d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p.ex. un objet la zone étant une image, une trame ou un champ
|
29.
|
BALL GRID ARRAY AND CONFIGURATION METHOD OF THE SAME
Numéro d'application |
18210157 |
Statut |
En instance |
Date de dépôt |
2023-06-15 |
Date de la première publication |
2024-02-08 |
Propriétaire |
REALTEK SEMICONDUCTOR CORP. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Lo, Chin-Yuan
- Lo, Hsin-Hui
|
Abrégé
A ball grid array and a configuration method of the same are provided. The ball grid array is formed on a printed circuit board and includes an inner row region and an outer row region. The inner row region includes a plurality of first solder balls that are arranged by a first ball pitch. The first solder balls respectively correspond to a plurality of predetermined vias, and the first ball pitch is determined according to a minimum trace width that is relative to a via size of the predetermined vias. The outer row region surrounds the inner row region and includes a plurality of second solder balls that are arranged by a second ball pitch. The second ball pitch is smaller than the first ball pitch.
Classes IPC ?
- H01L 23/498 - Connexions électriques sur des substrats isolants
- H05K 3/34 - Connexions soudées
- H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
|
30.
|
IMAGE PROCESSING METHOD AND DISPLAY DEVICE
Numéro d'application |
18228985 |
Statut |
En instance |
Date de dépôt |
2023-08-01 |
Date de la première publication |
2024-02-08 |
Propriétaire |
REALTEK SEMICONDUCTOR CORP. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Lin, Yuh-Wey
- Huang, Chun-Hao
|
Abrégé
An image processing method and a display device are provided. The image processing method is suitable for the display device. The display device includes an image processor and a panel module. The image processing method includes: when the image processor receives a notification signal from a source to switch the display format, the image processor stores a current image frame in a memory. The image processor provides the current image frame to the panel module, so that the panel module displays the current image frame. The image processor is re-handshaking with the source and the panel module to receive a new image frame provided by the source, and the image processor transmits the new image frame to the panel module, so that the panel module displays the new image frame.
Classes IPC ?
- G09G 3/20 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p.ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice
- G09G 3/34 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p.ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice en commandant la lumière provenant d'une source indépendante
|
31.
|
INDUCTOR DEVICE AND CONTROL METHOD THEREOF
Numéro d'application |
18489867 |
Statut |
En instance |
Date de dépôt |
2023-10-19 |
Date de la première publication |
2024-02-08 |
Propriétaire |
Realtek Semiconductor Corporation (Taïwan, Province de Chine)
|
Inventeur(s) |
Deng, Ping-Yuan
|
Abrégé
An inductor device includes an 8-shaped inductor and a ring-type wire. The ring-type wire is disposed around an outer side of the 8-shaped inductor. The 8-shaped inductor includes an input terminal and a center-tapped terminal. The input terminal of the 8-shaped inductor is located on a first side of the inductor device, and the center-tapped terminal is located on a second side of the inductor device. The ring-type wire includes an input terminal and a ground terminal. The input terminal of the ring-type wire is located on the first side of the inductor device, and the ground terminal is located on the second side of the inductor device. The input terminal of the ring-type wire is coupled to the input terminal of the 8-shaped inductor.
Classes IPC ?
- H01F 27/29 - Bornes; Aménagements de prises
- H04B 15/02 - Réduction des perturbations parasites dues aux appareils électriques avec des moyens disposés sur ou à proximité de la source de perturbation
- H04B 1/04 - Circuits
|
32.
|
TELEVISION
Numéro d'application |
17972061 |
Statut |
En instance |
Date de dépôt |
2022-10-24 |
Date de la première publication |
2024-02-08 |
Propriétaire |
REALTEK SEMICONDUCTOR CORP. (Taïwan, Province de Chine)
|
Inventeur(s) |
Chu, Yen-Hsun
|
Abrégé
A television includes a remote control, a receiving element, a speaker, a speech analysis model, and a processor. The processor analyzes video sound to get a repeated audio section after receiving a volume adjustment command from the remote control. Then, the speaker outputs the repeated audio. So that, according to user needs, the television adjusts the video sound before outputting.
Classes IPC ?
- G10L 15/22 - Procédures utilisées pendant le processus de reconnaissance de la parole, p.ex. dialogue homme-machine
- H04R 3/00 - Circuits pour transducteurs
|
33.
|
SINGLE SIDEBAND MIXER
Numéro d'application |
17816106 |
Statut |
En instance |
Date de dépôt |
2022-07-29 |
Date de la première publication |
2024-02-01 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
|
Inventeur(s) |
Lin, Chia-Liang (leon)
|
Abrégé
A SSB (single sideband) mixer is configured to mix a first signal with a second signal, both the first signal and the second signal being a four-phase signal, and comprises eight gated inverters, each receiving a respective phase of the first signal and conditionally outputting a respective current in accordance with a control of a respective phase of the second signal, wherein currents output from the eight gated inverters are summed to establish a third signal that is a two-phase signal.
|
34.
|
Digital filtering method for photoplethysmography device
Numéro d'application |
18215190 |
Statut |
En instance |
Date de dépôt |
2023-06-28 |
Date de la première publication |
2024-02-01 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
Wu, Meng-Hsuan
|
Abrégé
A digital filtering method is applicable to a photoplethysmography (PPG) device. The PPG device samples a mixed-light signal M time(s) to obtain M mixed-light digital value(s), and samples an ambient-light signal N time(s) to obtain N ambient-light digital value(s), wherein each mixed-light digital value includes a controllable-light component and an ambient-light component. The method includes: preparing a digital filter whose filter order is (M+N−1); using the digital filter to multiply the M mixed-light digital value(s) by M coefficient(s) respectively and thereby generate M value(s); using the digital filter to multiply N ambient-light digital value(s) by N coefficient(s) respectively and thereby generate N value(s); and using the digital filter to add up the M value(s) and the N value(s) and thereby generate an output value.
Classes IPC ?
- A61B 5/00 - Mesure servant à établir un diagnostic ; Identification des individus
- A61B 5/024 - Mesure du pouls ou des pulsations cardiaques
|
35.
|
VIDEO PROCESSING METHOD ARRANGED TO PERFORM PARTIAL HIGHLIGHTING WITH AID OF HAND GESTURE DETECTION AND ASSOCIATED SYSTEM ON CHIP
Numéro d'application |
18226236 |
Statut |
En instance |
Date de dépôt |
2023-07-25 |
Date de la première publication |
2024-02-01 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
|
Inventeur(s) |
Cheng, Chia-Chun
|
Abrégé
A video processing method for performing partial highlighting with the aid of hand gesture detection and an associated SoC are provided. The SoC includes a person recognition circuit, a hand gesture detection circuit, a sound detection circuit and a processing circuit. The person recognition circuit obtains image data from an image capturing device, and performs person recognition on the image data to generate a recognition result. The hand gesture detection circuit performs hand gesture detection on hand gesture image data to generate a hand gesture detection result. The sound detection circuit receives multiple sound signals from multiple microphones, and determines a voice characteristic value of a main sound. The processing circuit determines a specific region in the image data according to the recognition result, the hand gesture detection result, and the voice characteristic value, and processes the image data to highlight the specific region.
Classes IPC ?
- G06V 40/20 - Mouvements ou comportement, p.ex. reconnaissance des gestes
- G06V 40/10 - Corps d’êtres humains ou d’animaux, p.ex. occupants de véhicules automobiles ou piétons; Parties du corps, p.ex. mains
- G06V 10/25 - Détermination d’une région d’intérêt [ROI] ou d’un volume d’intérêt [VOI]
- G06T 3/40 - Changement d'échelle d'une image entière ou d'une partie d'image
- G10L 17/02 - Opérations de prétraitement, p.ex. sélection de segment; Représentation ou modélisation de motifs, p.ex. fondée sur l’analyse linéaire discriminante [LDA] ou les composantes principales; Sélection ou extraction des caractéristiques
- G10L 25/78 - Détection de la présence ou de l’absence de signaux de voix
- G10L 17/10 - Systèmes multimodaux, c. à d. basés sur l’intégration de moteurs multiples de reconnaissance ou de fusion de systèmes experts
|
36.
|
METHOD FOR ACQUIRING TELECOMMUNICATION REGULATIONS AND SYSTEM APPLYING THE SAME
Numéro d'application |
18359027 |
Statut |
En instance |
Date de dépôt |
2023-07-26 |
Date de la première publication |
2024-02-01 |
Propriétaire |
REALTEK SEMICONDUCTOR CORP. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Wu, Jiun-Le
- Chiu, Ting-Yao
|
Abrégé
A method for acquiring telecommunication regulations and a system applying the same are provided. The method allows a wireless communication device to acquire the telecommunication regulations, and the system is applicable in the wireless communication device. In the method, a driver installed in the wireless communication device is executed to drive a wireless communication module of the wireless communication device. In the meantime, the driver can obtain location data from a BIOS or an operating system, or through environment detection. The driver uses the location data to compare the multiple telecommunication regulations recorded in program codes of the driver, so as to obtain the telecommunication regulation corresponding to the location data. Therefore, the system having the wireless communication module can operate according to the telecommunication regulation corresponding to the location data.
Classes IPC ?
- H04W 48/04 - Restriction d'accès effectuée dans des conditions spécifiques sur la base des données de localisation ou de mobilité de l'utilisateur ou du terminal, p.ex. du sens ou de la vitesse de déplacement
- H04W 64/00 - Localisation d'utilisateurs ou de terminaux pour la gestion du réseau, p.ex. gestion de la mobilité
|
37.
|
VIDEO PROCESSING METHOD FOR PERFORMING PARTIAL HIGHLIGHTING WITH AID OF AUXILIARY INFORMATION DETECTION, AND ASSOCIATED SYSTEM ON CHIP
Numéro d'application |
18221891 |
Statut |
En instance |
Date de dépôt |
2023-07-14 |
Date de la première publication |
2024-02-01 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
|
Inventeur(s) |
Cheng, Chia-Chun
|
Abrégé
A system on chip (SoC) for performing partial highlighting with the aid of auxiliary information detection includes a person recognition circuit, a sound detection circuit, an auxiliary information detection circuit and a processing circuit. The person recognition circuit obtains image data from an image capturing device, and performs person recognition on the image data to generate a recognition result. The sound detection circuit receives a plurality of sound signals from a plurality of microphones, and determines a voice characteristic value of a main sound. The auxiliary information detection circuit generates auxiliary information for calibrating the voice characteristic value of the main sound. The processing circuit determines a specific region in the image data according to the recognition result, the auxiliary information, and the voice characteristic value, and processes the image data to highlight the specific region.
Classes IPC ?
- H04N 5/262 - Circuits de studio, p.ex. pour mélanger, commuter, changer le caractère de l'image, pour d'autres effets spéciaux
- G06V 40/16 - Visages humains, p.ex. parties du visage, croquis ou expressions
- G10L 17/06 - Techniques de prise de décision; Stratégies d’alignement de motifs
- G10L 25/78 - Détection de la présence ou de l’absence de signaux de voix
- G06V 40/20 - Mouvements ou comportement, p.ex. reconnaissance des gestes
|
38.
|
SIGNAL RECEIVER AND SIGNAL RECEIVING METHOD
Numéro d'application |
18357152 |
Statut |
En instance |
Date de dépôt |
2023-07-23 |
Date de la première publication |
2024-02-01 |
Propriétaire |
Realtek Semiconductor Corporation (Taïwan, Province de Chine)
|
Inventeur(s) |
- Su, Ying-Rong
- Chen, I-Ju
- Shih, Kuan-Yu
|
Abrégé
A signal receiving method, comprising: receiving a first communication signal and/or a second communication signal through an antenna; when the antenna receives the first communication signal and the second communication signal simultaneously, transmitting, by a first receiving circuit, the first communication signal to a first amplifying circuit, and receiving the second communication signal by a second receiving circuit; and When the antenna does not receive the first communication signal and the second communication signal simultaneously, transmitting, by the first receiving circuit, the first communication signal to the first amplifying circuit, and transmitting, by the first receiving circuit, the second communication signal to a second amplifying circuit. The first communication signal and the second communication signal correspond to different communication protocols respectively.
Classes IPC ?
- H04B 1/16 - Circuits
- H04B 1/12 - Montages de neutralisation, d'équilibrage ou de compensation
|
39.
|
AMPLIFICATION CIRCUIT
Numéro d'application |
18360467 |
Statut |
En instance |
Date de dépôt |
2023-07-27 |
Date de la première publication |
2024-02-01 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
Huang, Shih-Hsiung
|
Abrégé
The present application discloses an amplification circuit. The amplification circuit includes an amplifier, a feedback unit, a second feedback unit, a first correlated double sampling unit, and a second correlated double sampling unit. The amplifier has a first positive input terminal, a second positive input terminal, a first negative input terminal, a second negative input terminal, a positive output terminal, and a negative output terminal. First terminals of the first feedback unit and the second feedback unit are coupled to the positive output terminal. The first correlated double sampling unit is coupled to the first negative input terminal and a second terminal of the first feedback unit, and performs a sample operation and an output operation. The second correlated double sampling unit is coupled to the second negative input terminal and a second terminal of the second feedback unit, and performs the sample operation and the output operation.
|
40.
|
STATIC TIMING ANALYSIS METHOD AND STATIC TIMING ANALYSIS SYSTEM
Numéro d'application |
17990799 |
Statut |
En instance |
Date de dépôt |
2022-11-21 |
Date de la première publication |
2024-02-01 |
Propriétaire |
REALTEK SEMICONDUCTOR CORP. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Chen, Ying-Chieh
- Yu, Mei-Li
- Lo, Yu-Lan
|
Abrégé
A static timing analysis method and a static timing analysis system are provided. The static timing analysis methods includes: obtaining a standard cell library file for describing a plurality of standard cells; performing topology mapping on the standard cell library file to find out a target sequential cell from the standard cells, in which the sequential cell includes a logic gate, a selection circuit and a register circuit; executing a logic test process to find out a pin combination that has a mutual non-controllable relationship, and removing timing constraints related to the pin combination that are taken as redundant timing constraints from the standard cell library file, so as to generate an optimized standard library file; and perform a static timing analysis on a target circuit design according to the optimized standard cell library file.
Classes IPC ?
- G06F 30/3315 - Vérification de la conception, p.ex. simulation fonctionnelle ou vérification du modèle utilisant une analyse temporelle statique [STA]
|
41.
|
AUDIO-VISUAL DATA MANAGING SYSTEM, AUDIO-VISUAL DATA MANAGING METHOD
Numéro d'application |
18225163 |
Statut |
En instance |
Date de dépôt |
2023-07-24 |
Date de la première publication |
2024-01-25 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
|
Inventeur(s) |
Chen, Chien-Chang
|
Abrégé
An audio-visual managing system, applied to at least one data receiving circuit which receives audio-visual data and outputs processed audio-visual data, each of the data receiving circuit comprising a tuner or a demodulator, the audio-visual managing system comprising: a plurality of transmitting circuits, configured to stream the processed audio-visual data; wherein the processed audio-visual data output by a first data receiving circuit of the data receiving circuit can be used by a first transmitting circuit and a second transmitting circuit of the transmitting circuits simultaneously, when the first transmitting circuit and the second transmitting circuit receive the processed audio-visual data output by the first data receiving circuit.
Classes IPC ?
- H04N 21/426 - Structure de client; Structure de périphérique de client Éléments internes de client
- H04N 21/438 - Interfaçage de la voie descendante du réseau de transmission provenant d'un serveur, p.ex. récupération de paquets MPEG d'un réseau IP
|
42.
|
SIGNAL GENERATING CIRCUIT AND SIGNAL GENERATING METHOD
Numéro d'application |
18225463 |
Statut |
En instance |
Date de dépôt |
2023-07-24 |
Date de la première publication |
2024-01-25 |
Propriétaire |
REALTEK SEMICONDUCTOR CORP. (Taïwan, Province de Chine)
|
Inventeur(s) |
Yeh, Chih-Yuan
|
Abrégé
A signal generating circuit and a signal generating method are provided. The signal generating circuit includes a first synchronization circuit configured to synchronize a beacon signal and a first signal edge of a clock signal to generate a first synchronization signal; a frequency dividing circuit configured to receive the clock signal and perform frequency division operation on the clock signal to generate a frequency division signal, wherein the duty cycle of the frequency division signal is 50%; a second synchronization circuit configured to receive the first synchronization signal and the frequency division signal and synchronize the first synchronization signal and a second signal edge of frequency division signal to generate a second synchronization signal; and a synthesis circuit configured to receive the second synchronization signal and the frequency division signal and perform AND operation on the second synchronization signal and the frequency division signal to output full-cycle signals.
Classes IPC ?
- H03L 7/07 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase utilisant plusieurs boucles, p.ex. pour la génération d'un signal d'horloge redondant
- H03K 3/037 - Circuits bistables
- H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe
|
43.
|
TRANSMISSION DEVICE AND SIGNAL PREDISTORTION METHOD THEREOF
Numéro d'application |
18347566 |
Statut |
En instance |
Date de dépôt |
2023-07-06 |
Date de la première publication |
2024-01-25 |
Propriétaire |
Realtek Semiconductor Corporation (Taïwan, Province de Chine)
|
Inventeur(s) |
Chang, Yuan-Shuo
|
Abrégé
A signal predistortion method applied to a transmission device. The transmission device includes a signal processing circuit, a transmission chain and a power amplifier, the power amplifier is configured to amplify a radio-frequency (RF) input signal outputted by the transmission chain to generate a RF output signal. The signal predistortion method includes: performing a first signal processing operation on a baseband signal by the signal processing circuit, to generate an in-band predistortion output; performing a second signal processing operation on the in-band predistortion output by the signal processing circuit, to generate an out-of-band predistortion output; and generating a full-band predistortion signal to the transmission chain according to the in-band predistortion output and the out-of-band predistortion output by the signal processing circuit, so that the transmission chain generates the RF input signal according to the full-band predistortion signal.
Classes IPC ?
- H04B 1/62 - TRANSMISSION - Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission pour produire une prédistorsion du signal à l'émission et une correction correspondante à la réception, p.ex. pour améliorer le rapport signal/bruit
- H04B 1/04 - Circuits
|
44.
|
Image brightness adjusting method and image brightness adjusting device
Numéro d'application |
18206092 |
Numéro de brevet |
11881142 |
Statut |
Délivré - en vigueur |
Date de dépôt |
2023-06-06 |
Date de la première publication |
2024-01-23 |
Date d'octroi |
2024-01-23 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Li, Yi-Chu
- Hsieh, Chun-Hsing
- Tsai, Yi-Lin
|
Abrégé
An image brightness adjusting method, comprising: (a) computing or predicting a first input frame rate according to at least one first input image; (b) generating a first brightness according to a first brightness curve and the first input frame rate, wherein the first brightness curve corresponds to a first frame rate; (c) generating a second brightness according to a second brightness curve and the first input frame rate, wherein the second brightness curve corresponds to a second frame rate; (d) generating a first brightness compensating curve according to the first input frame rate and a brightness difference between the first brightness and the second brightness; and (e) setting a first compensating brightness of at least one second input image according to the first brightness compensating curve.
Classes IPC ?
- G09G 3/20 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p.ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice
|
45.
|
Network packet transmission device and network packet transmission method thereof
Numéro d'application |
18167498 |
Numéro de brevet |
11882030 |
Statut |
Délivré - en vigueur |
Date de dépôt |
2023-02-10 |
Date de la première publication |
2024-01-23 |
Date d'octroi |
2024-01-23 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
- Wang, Mei Yue
- Liu, Juan
- Chi, Hang
|
Abrégé
The present disclosure provides a network packet transmission device and a network packet transmission method thereof. The network packet transmission method includes: receiving a network packet, wherein the network packet has at least one packet attribute; determining at least one destination VID for the network packet according to the at least one packet attribute; determining a transmission speed corresponding to the at least one destination VID based on at least one LAN speed table; and transmitting the network packet to a VLAN corresponding to the at least one destination VID according to the transmission speed.
Classes IPC ?
- H04L 45/00 - Routage ou recherche de routes de paquets dans les réseaux de commutation de données
- H04L 12/46 - Interconnexion de réseaux
- H04L 45/121 - Routage ou recherche de routes de paquets dans les réseaux de commutation de données Évaluation de la route la plus courte en minimisant les retards
|
46.
|
Transmitter circuit, compensation value calibration device and method for calibrating compensation values
Numéro d'application |
18140617 |
Statut |
En instance |
Date de dépôt |
2023-04-28 |
Date de la première publication |
2024-01-18 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Chang, Yuan-Shuo
- Kao, Tzu-Ming
|
Abrégé
A method for calibrating compensation values utilized by a compensation device in a transmitter includes: obtaining a plurality of output signals sequentially generated by the transmitter by processing a pair of input signals based on a plurality of pairs of compensation values as a plurality of feedback signals, where each feedback signal corresponds to one of the plurality of pairs of compensation values; obtaining a signal component of the feedback signals at a predetermined frequency as a portion of the feedback signals; determining a pair of equivalent impairment parameters in a calibration operation according to the plurality of pairs of compensation values and the portion of the feedback signals; and determining a pair of calibrated compensation values according to the pair of equivalent impairment parameters and providing the pair of calibrated compensation values to the compensation device.
|
47.
|
ELECTRONIC SYSTEM, MONITORING CHIP, AND OPERATION METHOD
Numéro d'application |
18348360 |
Statut |
En instance |
Date de dépôt |
2023-07-07 |
Date de la première publication |
2024-01-18 |
Propriétaire |
Realtek Semiconductor Corporation (Taïwan, Province de Chine)
|
Inventeur(s) |
- Zeng, Jian Jhong
- Chi, Shih Chin
- Lu, Meng Yang
- Lin, Neng Hsien
|
Abrégé
An electronic system includes a first electronic device and a second electronic device. The first electronic device includes a monitoring chip and a hub chip. The monitoring chip is coupled to an upstream port of the hub chip through a first connection and is coupled to the hub chip through a second connection. The second electronic device is configured to couple a downstream port of the hub chip. The monitoring chip is configured to acquire connection information of the second electronic device through the first connection, and acquire status information of the second electronic device through the second connection. The first electronic device is configured to control at least one third electronic device according to the connection information and the status information.
Classes IPC ?
- G06F 11/30 - Surveillance du fonctionnement
- G06F 11/32 - Surveillance du fonctionnement avec indication visuelle du fonctionnement de la machine
|
48.
|
ANALOG TO DIGITAL CONVERTER HAVING MECHANISM OF DETECTING INPUT VOLTAGE RANGE AND SIGNAL CONVERSION METHOD THEREOF
Numéro d'application |
18132993 |
Statut |
En instance |
Date de dépôt |
2023-04-11 |
Date de la première publication |
2024-01-18 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
- Chan, Chun-Chieh
- Chen, Heng-Yi
- Lin, Yi-Cheng
|
Abrégé
An analog to digital converter includes voltage divider circuits, front-end circuits, at least one converter circuit, and a controller circuit. The voltage divider circuits are configured to divide an input signal to generate first signals, in which the first signals have different levels. The front-end circuits are configured to respectively sample the first signals to generate second signals. The at least one converter circuit is configured to generate at least one digital output according to the second signals and a reference voltage. The controller circuit is configured to determine a level of the input signal according to the at least one digital output and select one of the at least one digital output according to the level of the input signal.
Classes IPC ?
- H03M 1/12 - Convertisseurs analogiques/numériques
- H03M 1/38 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p.ex. du type à approximations successives
|
49.
|
ACCESS POINT AND SCHEDULING METHOD THEREOF FOR ENHANCING THE POWER SAVING EFFICIENCY
Numéro d'application |
18195370 |
Statut |
En instance |
Date de dépôt |
2023-05-09 |
Date de la première publication |
2024-01-18 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
|
Inventeur(s) |
Lin, Yu-Ling
|
Abrégé
A scheduling method of scheduling a target wake time (TWT) communication between an access point and at least one station. The scheduling method includes the access point adjusting a broadcast TWT schedule according to a power saving setting, and the access point transmitting the broadcast TWT schedule. The broadcast TWT schedule includes a broadcast TWT SP start time, a broadcast TWT service period and a broadcast TWT interval.
|
50.
|
METHOLD FOR TRAINING SUPER-RESOLUTION MODEL, SUPER-RESOLUTION METHOD, AND SYSTEM
Numéro d'application |
18220858 |
Statut |
En instance |
Date de dépôt |
2023-07-12 |
Date de la première publication |
2024-01-18 |
Propriétaire |
REALTEK SEMICONDUCTOR CORP. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Bao, Yi-Ting
- Yu, Chia-Wei
- Wang, Hao-Ran
- Lin, Tien-Hung
|
Abrégé
A method for training a super-resolution model, a super-resolution method, and a system are provided, and the super-resolution method and the system are implemented through an AI super-resolution model that is trained by the method. In the method, an input image is provided, and a magnification ratio and an image quality threshold are set. Pixel values of the input image are retrieved, and image features of the input image are extracted. Multiple channel images are obtained through a super-resolution model based on the image features and the magnification ratio. Phase information can be obtained according to the magnification ratio and positions of output pixels, and the phase information is used to obtain masks mapping to the channel images. Therefore, an output image can be reshuffled. After a comparison with the image quality threshold, model parameters of the output image can be assessed for training the AI super-resolution model.
Classes IPC ?
- G06T 3/40 - Changement d'échelle d'une image entière ou d'une partie d'image
- G06T 5/50 - Amélioration ou restauration d'image en utilisant plusieurs images, p.ex. moyenne, soustraction
- G06T 1/60 - Gestion de mémoire
- G06T 5/20 - Amélioration ou restauration d'image en utilisant des opérateurs locaux
- G06T 5/00 - Amélioration ou restauration d'image
|
51.
|
OUTPUT CONTROL INTERFACE CIRCUIT FOR STATIC RANDOM ACCESS MEMORY AND OUTPUT CONTROL METHOD FOR THE SAME
Numéro d'application |
18221642 |
Statut |
En instance |
Date de dépôt |
2023-07-13 |
Date de la première publication |
2024-01-18 |
Propriétaire |
REALTEK SEMICONDUCTOR CORP. (Taïwan, Province de Chine)
|
Inventeur(s) |
Wu, Kuo-Chi
|
Abrégé
An output control interface circuit for a static random access memory (SRAM) and an output control method for the same are provided. The output control interface circuit includes an SRAM control detector circuit and an SRAM data controller circuit. The SRAM control detector circuit receives a control signal, determines whether the control signal is stable, and outputs an indication signal correspondingly. The SRAM data controller circuit receives the indication signal and the SRAM output data signal output by the SRAM control detector circuit, and outputs an output data signal according to the indication signal. In response to determining that the control signal is not stable, the SRAM data controller circuit correspondingly outputs the output data signal with a preset value. In response to determining that the control signal is stable, the SRAM data controller circuit outputs the SRAM output data signal as the output data signal correspondingly.
Classes IPC ?
- G11C 7/20 - Circuits d'initialisation de cellules de mémoire, p.ex. à la mise sous ou hors tension, effacement de mémoire, mémoire d'image latente
- G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
- G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
|
52.
|
Data transmission apparatus and method having clock gating mechanism
Numéro d'application |
17861424 |
Statut |
En instance |
Date de dépôt |
2022-07-11 |
Date de la première publication |
2024-01-11 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
- Tsai, Fu-Chin
- Chou, Ger-Chih
- Yu, Chun-Chi
- Chang, Chih-Wei
- Lin, Shih-Han
|
Abrégé
The present invention discloses a data transmission apparatus having clock gating mechanism. Each of data transmission circuits has a flip-flop depth of N and receives a write clock signal and one of read clock signals to receive and output one of data signals. A write clock gating circuit receives a write clock gating enabling signal to transmit the write clock signal to the data transmission circuits. Each of read clock gating circuits receives one of read clock gating enabling signals to transmit one of the read clock signals. The gating signal transmission circuit has a flip-flop depth of N+M and receives the write and the read clock signals to receive the write clock gating enabling signal and output the read clock gating enabling signals. A largest timing difference among the read clock signals is P clock cycles and M is at least [P].
Classes IPC ?
- G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
- G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
|
53.
|
INPUT/OUTPUT PORT CIRCUIT AND CHIP THEREOF
Numéro d'application |
17941377 |
Statut |
En instance |
Date de dépôt |
2022-09-09 |
Date de la première publication |
2024-01-11 |
Propriétaire |
REALTEK SEMICONDUCTOR CORP. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Yu, Sz-Ying
- Ku, Chen-Hsuan
- Lin, Shang-Hung
- Tai, Kun-Yu
|
Abrégé
An input/output port circuit includes an input/output pad, a transistor, and a conductive routing wire. The transistor has a first connection terminal and a second connection terminal. The first connection terminal of the transistor is electrically connected to the input/output pad through a conductive connection wire, and the second connection terminal is electrically connected to another transistor. The conductive routing wire is electrically connected to the first terminal of the transistor. The conductive routing wire is configured to provide a serial resistance, thereby forcing a surge current to flow toward the another transistor when the surge current is inputted in the input/output circuit through the input/output pad.
Classes IPC ?
- H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
|
54.
|
BLUETOOTH NETWORK ESTABLISHING SYSTEM AND METHOD
Numéro d'application |
18147005 |
Statut |
En instance |
Date de dépôt |
2022-12-28 |
Date de la première publication |
2024-01-11 |
Propriétaire |
Realtek Semiconductor Corporation (Taïwan, Province de Chine)
|
Inventeur(s) |
- Mao, Weifeng
- Lu, Zhuwei
- Chen, Jidong
- Li, Zuomin
|
Abrégé
A Bluetooth network establishing system and method are provided. The system includes a plurality of node devices and a gateway device. The gateway device is used to connect a Bluetooth network to an external network. A first node device of the node devices broadcasts a first inquiry operation. In response to the first inquiry operation, the gateway device in a first inquiry scan state sends a first extended inquiry response and executes a first page scan state. The first node device executes a first page operation, wherein the first page operation determines whether to establish a first communication connection with the gateway device to join the Bluetooth network according to the first extended inquiry response. After the first node device joins the Bluetooth network, the first node device executes a second inquiry scan state.
Classes IPC ?
- H04W 76/10 - Gestion de la connexion Établissement de la connexion
- H04W 8/00 - Gestion de données relatives au réseau
|
55.
|
BLUETOOTH NETWORK ESTABLISHING SYSTEM AND METHOD
Numéro d'application |
18147713 |
Statut |
En instance |
Date de dépôt |
2022-12-29 |
Date de la première publication |
2024-01-11 |
Propriétaire |
Realtek Semiconductor Corporation (Taïwan, Province de Chine)
|
Inventeur(s) |
- Mao, Weifeng
- Lu, Zhuwei
- Chen, Jidong
- Li, Zuomin
|
Abrégé
A Bluetooth network establishing system and method are provided. The system includes a plurality of node devices and a gateway device. The gateway device is used to connect a Bluetooth network to an external network and broadcast a first connectable undirected advertising packet. A first node device among the node devices executes a first scan operation to receive a first advertising packet, wherein the first advertising packet includes the first connectable undirected advertising packet. The first node device determines whether to establish a first communication connection with the gateway devices to join the Bluetooth network according to the first advertising packet. After joining the Bluetooth network, the first node device broadcasts a second connectable undirected advertising packet.
Classes IPC ?
- H04W 76/10 - Gestion de la connexion Établissement de la connexion
- H04W 40/24 - Gestion d'informations sur la connectabilité, p.ex. exploration de connectabilité ou mise à jour de connectabilité
|
56.
|
BLUETOOTH INTERNET PROTOCOL PACKET TRANSMITTING DEVICE AND METHOD
Numéro d'application |
18173072 |
Statut |
En instance |
Date de dépôt |
2023-02-23 |
Date de la première publication |
2024-01-11 |
Propriétaire |
Realtek Semiconductor Corporation (Taïwan, Province de Chine)
|
Inventeur(s) |
- Mao, Weifeng
- Lu, Zhuwei
- Chen, Jidong
- Li, Zuomin
|
Abrégé
A Bluetooth internet protocol packet transmitting device and method are provided. The device includes a Bluetooth protocol stack, a Bluetooth controller and a host control interface. The Bluetooth protocol stack is configured to store an internet protocol stack and a host control interface driver. The Bluetooth controller generates at least one data packet based on an internet protocol packet, wherein the at least one data packet corresponds to an asynchronous connection data format. The Bluetooth controller transmits the at least one data packet to the host control interface driver. The host control interface driver determines whether the at least one data packet is an asynchronous connection data packet. When the host control interface driver determines that the at least one data packet is the asynchronous connection data packet, the at least one data packet is transmitted to the internet protocol stack.
Classes IPC ?
- H04L 69/30 - Définitions, normes ou aspects architecturaux des piles de protocoles par couches
|
57.
|
Signal relay apparatus and method having frequency locking mechanism
Numéro d'application |
18206096 |
Statut |
En instance |
Date de dépôt |
2023-06-06 |
Date de la première publication |
2024-01-11 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
- Chan, Chun-Chieh
- Wu, Tai-Jung
- Chang, Chia-Hao
|
Abrégé
The present disclosure discloses a signal relay apparatus having frequency locking mechanism that includes a receiving circuit, a frequency generation circuit, a frequency tracking circuit and a transmission circuit. The receiving circuit receives a receiving signal to retrieve data included therein according a corresponding receiving frequency signal. The frequency generation circuit receives a source clock signal and generates a target frequency signal according to a conversion parameter. The frequency tracking circuit calculates a frequency difference between the receiving frequency signal and the target frequency signal to adjust the conversion parameter accordingly. The transmission circuit generates a transmission signal that includes the data according to the target frequency signal.
Classes IPC ?
- H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p.ex. en utilisant une boucle verrouillée en phase
- H03L 7/08 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase
|
58.
|
Transceiver apparatus having self-calibration mechanism and self-calibration method thereof
Numéro d'application |
18206262 |
Statut |
En instance |
Date de dépôt |
2023-06-06 |
Date de la première publication |
2024-01-11 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
- Yang, Hung-Yuan
- Lin, Hung-Min
- Huang, Yun-Ru
|
Abrégé
The present disclosure discloses a transceiver apparatus having self-calibration mechanism that includes a signal transmission path, a signal receiving path, a path switching circuit, a transceiver circuit and a self-calibration circuit. The path switching circuit includes a switch to switch a connection relation among an antenna, the signal transmission path and the signal receiving path. The transceiver circuit is coupled to the signal transmission path and the signal receiving path. The self-calibration circuit controls the transceiver circuit to transmit a transmission signal through the signal transmission path to the path switching circuit and receives a leakage signal generated according to the transmission signal through the signal receiving path, so as to perform a self-calibration process on the transceiver circuit based on the transmission signal and the leakage signal. The leakage signal has a leakage signal strength larger than a predetermined level.
Classes IPC ?
- H04B 1/44 - Commutation transmission-réception
|
59.
|
INTEGRATED CIRCUIT AND LAYOUT METHOD THEREOF
Numéro d'application |
18346261 |
Statut |
En instance |
Date de dépôt |
2023-07-02 |
Date de la première publication |
2024-01-11 |
Propriétaire |
Realtek Semiconductor Corporation (Taïwan, Province de Chine)
|
Inventeur(s) |
Lin, Tien-Kuo
|
Abrégé
An integrated circuit includes a functional circuit and a first power switch chain. The first power switch chain includes a first power switch circuit and a second power switch circuit and is coupled between a power source and the functional circuit. The first power switch chain is configured to receive a first control signal, and the first control signal is configured to turn on or turn off the first power switch circuit and the second power switch circuit. A first resistance value of the first power switch circuit is different from a second resistance value of the second power switch circuit.
Classes IPC ?
- G06F 30/367 - Vérification de la conception, p.ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
- G06F 30/392 - Conception de plans ou d’agencements, p.ex. partitionnement ou positionnement
- H03K 17/14 - Modifications pour compenser les variations de valeurs physiques, p.ex. de la température
- H03K 17/693 - Dispositifs de commutation comportant plusieurs bornes d'entrée et de sortie, p.ex. multiplexeurs, distributeurs
|
60.
|
DEVICE AND METHOD FOR HANDLING LOW LATENCY TRANSMISSION
Numéro d'application |
18144237 |
Statut |
En instance |
Date de dépôt |
2023-05-07 |
Date de la première publication |
2024-01-11 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Fan, Wei-Kang
- Yeh, Ling-Fan
|
Abrégé
A controlling device for handling a low latency transmission includes: a storage module, for maintaining a list, wherein the list includes a plurality of transmission information of a plurality of transmitting devices, and the plurality of transmission information includes a plurality of statuses, a plurality of priorities and a plurality of airtime resources, wherein each of the plurality of priorities indicates a priority level of a plurality of priority levels; and a scheduling module, coupled to the storage module, for generating a high priority window, and selecting a transmitting device from the plurality of transmitting devices in the high priority window according to the plurality of statuses, the plurality of priorities and the plurality of airtime resources to control the transmitting device to perform a transmission.
Classes IPC ?
- H04W 72/56 - Critères d’affectation ou de planification des ressources sans fil sur la base de critères de priorité
- H04W 72/1263 - Jumelage du trafic à la planification, p.ex. affectation planifiée ou multiplexage de flux
|
61.
|
AMPLIFIER SYSTEM
Numéro d'application |
18218775 |
Statut |
En instance |
Date de dépôt |
2023-07-06 |
Date de la première publication |
2024-01-11 |
Propriétaire |
REALTEK SEMICONDUCTOR CORP. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Liao, Chen-Fong
- Tu, Yi-Chang
|
Abrégé
An amplifier system includes an output circuit, a processor circuit, a feedback circuit, and a controller circuit. The output circuit outputs an output signal and returns a digital output feedback signal. The processor circuit receives a filtered error audio signal and outputs a pulse width modulation control signal to the output circuit. An addition unit of the feedback circuit adds the negative value of the digital output feedback signal to the digital input signal to obtain the error audio signal. A variable filter unit of the feedback circuit filters the error audio signal and outputs the filtered error audio signal. A compensation unit of the variable filter unit changes the gain characteristics of the variable filter unit. The controller circuit adjusts one or more parameters of the compensation unit according to a pre-compensation signal so as to change the gain characteristics of the variable filter unit.
Classes IPC ?
- H03G 3/30 - Commande automatique dans des amplificateurs comportant des dispositifs semi-conducteurs
- H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p.ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
- H03F 3/181 - Amplificateurs à basse fréquence, p.ex. préamplificateurs à fréquence musicale
- H04R 3/04 - Circuits pour transducteurs pour corriger la fréquence de réponse
|
62.
|
AMPLIFIER
Numéro d'application |
18333234 |
Statut |
En instance |
Date de dépôt |
2023-06-12 |
Date de la première publication |
2024-01-11 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
Huang, Shih-Hsiung
|
Abrégé
An amplifier includes a first stage of amplification circuit and a second stage of amplification circuit. The first stage of amplification circuit includes a first transistor, a second transistor, and a voltage gap generation unit. The first transistor has a first terminal, a second terminal for outputting an amplified signal, and a control terminal for receiving an input signal. The second transistor has a first terminal, a second terminal, and a control terminal for receiving a bias voltage. The voltage gap generation unit provides a voltage gap between a first terminal and a second terminal of the voltage gap generation unit according to a current flowing through the first transistor and the second transistor. The second stage of amplification circuit uses the voltages at the first terminal and the second terminal of the voltage gap generation unit as input signals.
Classes IPC ?
- H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p.ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
- H03F 3/45 - Amplificateurs différentiels
|
63.
|
Data Accessing Method and Data Accessing System Capable of Providing High Data Accessing Performance and Low Memory Utilization
Numéro d'application |
17984211 |
Statut |
En instance |
Date de dépôt |
2022-11-09 |
Date de la première publication |
2024-01-11 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
|
Inventeur(s) |
Liu, Chih-Hao
|
Abrégé
A data accessing method includes providing a first memory including a plurality of memory pages, acquiring a usage order value of each memory page of the plurality of memory pages, acquiring a first usage order value having a highest priority from a plurality of usage order values corresponding to the plurality of memory pages in the first memory, updating the first memory after a first memory page having the first usage order value is used, acquiring a second usage order value having a highest priority from the updated first memory after the first memory is updated, and using a second memory page having the second usage order.
Classes IPC ?
- G06F 12/0882 - Mode de page
- G06F 12/126 - Commande de remplacement utilisant des algorithmes de remplacement avec maniement spécial des données, p.ex. priorité des données ou des instructions, erreurs de maniement ou repérage
- G06F 12/0804 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec mise à jour de la mémoire principale
|
64.
|
RECEIVER OF COMMUNICATION SYSTEM AND EYE DIAGRAM MEASURING METHOD
Numéro d'application |
17938050 |
Statut |
En instance |
Date de dépôt |
2022-10-05 |
Date de la première publication |
2024-01-04 |
Propriétaire |
Realtek Semiconductor Corporation (Taïwan, Province de Chine)
|
Inventeur(s) |
- Chen, Shih-Chang
- Chang, Chih-Wei
- Yu, Chun-Chi
|
Abrégé
An eye diagram measuring method includes: sampling a compensated input signal according to a reference voltage and a reference clock to obtain a first sampling result; and sampling a to-be-compensated input signal according to a scan voltage and a scan clock to obtain a second sampling result, including: (b1) storing a minimum phase and a voltage level which render the first sampling result identical to the second sampling result; (b2) increasing the voltage level and repeating operation (b1); (b3) decreasing the voltage level and repeating operation (b1); (b4) storing a maximum phase and the voltage level which render the first sampling result identical to the second sampling result; (b5) increasing the voltage level and repeating operation (b4); and (b6) decreasing the voltage level and repeating operation (b4). Voltage levels, maximum phases and minimum phases that are stored are for adjusting the reference voltage and the reference clock.
|
65.
|
ELECTRONIC SYSTEM AND DISPLAY METHOD
Numéro d'application |
18097069 |
Statut |
En instance |
Date de dépôt |
2023-01-13 |
Date de la première publication |
2023-12-28 |
Propriétaire |
REALTEK SEMICONDUCTOR CORP. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Chen, Yi-Cheng
- Chiu, Yao-Ching
|
Abrégé
An electronic system and a display method are provided. The following steps are performed by central processing units: a first central processing unit loads and checks a display firmware; a second central processing unit determines whether the electronic system is in a first connected state based on the display firmware; in response to that the electronic system is in the first connected state, the first central processing unit and the second central processing unit, together with collaborating central processing units of the central processing units, execute a first pre-defined procedure and an external device display procedure based on settings stored in a data area to display a content transmitted by the external device corresponding to the first connected state; and, in response to that the electronic system is not in the first connected state, the first central processing unit executes a second pre-defined procedure.
|
66.
|
CONTROL DEVICE AND RELATED DISPLAY SYSTEM
Numéro d'application |
18191459 |
Statut |
En instance |
Date de dépôt |
2023-03-28 |
Date de la première publication |
2023-12-28 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
- Wu, Cian-Rou
- Chen, Cheng Yueh
- Chan, Chun-Chieh
|
Abrégé
A control device is configured to control a display panel according to a trigger signal transmitted from an input device to a host. The control device includes a connector unit and a signal capture unit. The connector unit is configured to receive the trigger signal, and transmit the same to the host. The signal capture unit is configured to capture the trigger signal, and control the display panel according to the trigger signal while the connector unit is transmitting the trigger signal to the host.
Classes IPC ?
- G09G 5/00 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation
- G09G 5/18 - Circuits de synchronisation pour l'affichage à balayage par trame
|
67.
|
Computation circuit used in DCT, DST, IDCT and IDST
Numéro d'application |
18211605 |
Statut |
En instance |
Date de dépôt |
2023-06-20 |
Date de la première publication |
2023-12-28 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
- Chang, Szu-Chun
- Tseng, Yi-Chen
|
Abrégé
The present invention discloses a computation circuit. Each of a first and a second term computation circuits includes higher bit computation circuits, a lowest bit computation circuit and a first adder. Each of the higher bit computation circuits left-shifts a multiplier, outputs the effective shifted multiplier having a sign determined and further performs left-shifts without performing 2's complement computation to generate a higher bit computation result. The lowest bit computation circuit outputs the effective multiplier having the sign determined to generate a lowest bit computation result. The first adder adds the bit computation results to generate a term computation result. The third term computation circuit outputs an effective addend having the sign determined and adds the addend to the summation of a number of 2's complement to generate a third term computation result. The second adder adds the term computation results and the third term computation result to generate a total computation result.
Classes IPC ?
- G06F 7/523 - Multiplication uniquement
- G06F 7/501 - Semi-additionneurs ou additionneurs complets, c. à d. cellules élémentaires d'addition pour une position
- G06F 5/01 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour le décalage, p.ex. la justification, le changement d'échelle, la normalisation
|
68.
|
Successive approximation analog to digital conversion circuit and method having optimized linearity
Numéro d'application |
18211852 |
Statut |
En instance |
Date de dépôt |
2023-06-20 |
Date de la première publication |
2023-12-28 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
- Wang, Wei-Jyun
- Liu, Kai-Yin
- Huang, Shih-Hsiung
- Wu, Chien-Ming
|
Abrégé
The present invention discloses a SAADC circuit having optimized linearity. A lower-bit capacitor array includes lower-bit capacitors. A higher-bit capacitor array includes unit capacitors. In an initializing mode, a control circuit sorts the unit capacitors according to unit capacitances thereof such that the unit capacitors are configured to be higher-bit capacitors having a linearity parameter within a predetermined range. In an operation mode, the capacitor array receives an analog input signal and a reference voltage to generate an analog output signal, a comparator generates a comparison result according to the analog output signal and the control circuit generates an enabling signal according to the comparison result based on the successive approximation mechanism to selectively enable the higher-bit and the lower-bit capacitors to connect to the reference voltage by using the capacitor enabling circuit and outputs a digital output signal according to the final comparison result.
Classes IPC ?
- H03M 1/06 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques
|
69.
|
METHOD AND CONTROL CIRCUIT FOR PERFORMING SYNCHRONIZATION ON PLAYBACK OF MULTIPLE ELECTRONIC DEVICES
Numéro d'application |
18214511 |
Statut |
En instance |
Date de dépôt |
2023-06-26 |
Date de la première publication |
2023-12-28 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Hung, Tien-Chiu
- Chu, Chung-Shih
- Ting, Wei-Chung
- Lin, Tse-En
|
Abrégé
A method and a control circuit for performing synchronization on playback of multiple electronic devices are provided, where the multiple electronic devices include a master device and a slave device. The method includes: utilizing the master device to receive audio data from a far-end device to be master audio data, and transmitting the master audio data to the slave device to be slave audio data, where the slave device generates ultrasound data according to the slave audio data, to make the slave device play the slave audio data and the ultrasound data; utilizing a calibration circuit to estimate a delay value between the ultrasound data received by a microphone of the master device and the master audio data; and utilizing a delay circuit to control a delay of the master audio data according to the delay value, to generate master output audio data for being played by the master device.
Classes IPC ?
- H04R 3/12 - Circuits pour transducteurs pour distribuer des signaux à plusieurs haut-parleurs
- H04R 29/00 - Dispositifs de contrôle; Dispositifs de tests
|
70.
|
Electronic device and antenna control method
Numéro d'application |
18201997 |
Statut |
En instance |
Date de dépôt |
2023-05-25 |
Date de la première publication |
2023-12-28 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
- Zhou, Jian-Jun
- Yu, Jie-Hong
|
Abrégé
An electronic device and an antenna control method are provided. The electronic device includes an antenna, a line switching circuit, a first communication chip, a second communication chip, and a logic circuit. The line switching circuit is coupled to the antenna. The first communication chip is coupled to the antenna through the line switching circuit and configured to generate a slot allocation signal. The second communication chip is coupled to the antenna through the line switching circuit and configured to generate a packet transceiving request signal. The first communication chip and the second communication chip are communication chips of different types. The logic circuit is coupled to the first communication chip and the second communication chip and configured to control the line switching circuit according to the slot allocation signal and the packet transceiving request signal.
Classes IPC ?
- H04B 1/00 - TRANSMISSION - Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission
- H04B 1/04 - Circuits
|
71.
|
Electronic device, antenna control method and communication chip
Numéro d'application |
18202020 |
Statut |
En instance |
Date de dépôt |
2023-05-25 |
Date de la première publication |
2023-12-28 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
- Zhou, Jian-Jun
- Yu, Jie-Hong
|
Abrégé
An electronic device, an antenna control method, and a communication chip are provided. The electronic device includes an antenna, a line switching circuit, a first communication chip, and a second communication chip. The line switching circuit is coupled to the antenna. The first communication chip is coupled to the antenna through the line switching circuit and configured to generate a slot allocation signal. The second communication chip is coupled to the antenna through the line switching circuit and configured to generate a packet distribution signal. The first communication chip and the second communication chip are communication chips of different types. The line switching circuit switches the antenna to the first communication chip or the second communication chip according to the packet distribution signal.
Classes IPC ?
- H04B 1/00 - TRANSMISSION - Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission
- H04W 72/0446 - Ressources du domaine temporel, p.ex. créneaux ou trames
|
72.
|
TRANSMITTER AND POWER CALIBRATION METHOD
Numéro d'application |
18204399 |
Statut |
En instance |
Date de dépôt |
2023-06-01 |
Date de la première publication |
2023-12-28 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
- Huang, Chia-Wei
- Lu, Yi-Hua
|
Abrégé
A transmitter includes a transmitter circuit, a calibration circuit, and a transmitter signal strength indicator circuit. The transmitter circuit is coupled to a power node to receive a supply voltage and transmits an output signal via an antenna. The calibration circuit senses a current of the power node when the transmitter circuit operates in a first frequency band and operates in a second frequency band to generate a signal having different values and generates a calibration signal according to the signals having the different values. The transmitter signal strength indicator circuit detects power of the output signal to generate a first detection signal, and generate a second detection signal according to the calibration signal and the first detection signal. The transmitter circuit adjusts the power of the output signal to be target power according to the second detection signal.
Classes IPC ?
- H04B 17/12 - Surveillance; Tests d’émetteurs pour l’étalonnage d’antennes d’émission, p.ex. de l’amplitude ou de la phase
- H04B 17/10 - Surveillance; Tests d’émetteurs
- H04B 17/318 - Force du signal reçu
|
73.
|
SEMICONDUCTOR PACKAGING EMI SHIELDING STRUCTURE AND MANUFACTURING METHOD OF THE SAME
Numéro d'application |
18322453 |
Statut |
En instance |
Date de dépôt |
2023-05-23 |
Date de la première publication |
2023-12-28 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
Chou, Chia Jen
|
Abrégé
The present application discloses a semiconductor packaging structure and a manufacturing method of the same that could be commonly used for lead frame products and substrate products. The semiconductor packaging structure includes: a base layer (lead frame or organic substrate); a die, disposed on the base layer; a molding compound, filled over the base layer and surrounding the die; a shielding layer, covering the top surface and a side surface of the molding compound; and a bonding wire, having a first terminal and a second terminal, wherein the bonding wire extends the side surface of the molding compound, thus allowing the first terminal of the bonding wire to contact an inner side of the shielding layer.
Classes IPC ?
- H01L 23/552 - Protection contre les radiations, p.ex. la lumière
- H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
- H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
- H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
|
74.
|
Task abnormality detection system and embedded device detection method
Numéro d'application |
18165925 |
Numéro de brevet |
11853151 |
Statut |
Délivré - en vigueur |
Date de dépôt |
2023-02-07 |
Date de la première publication |
2023-12-26 |
Date d'octroi |
2023-12-26 |
Propriétaire |
Realtek Semiconductor Corporation (Taïwan, Province de Chine)
|
Inventeur(s) |
- Jiang, Siwei
- Wu, Kun-Hsuan
- Zhang, Hong
- Deng, Shuyu
|
Abrégé
An embedded device detection method, comprising the following steps: executing a task by an embedded device, wherein the task comprises multiple functions; when an abnormal interruption occurs to the task, obtaining a stack pointer and a program counter corresponding to the abnormal interruption by a detection device, wherein the program counter is configured to record a memory address in use when the abnormal interruption occurs to the task; obtaining a stack space corresponding to a first target function being executed according to the program counter when the abnormal interruption occurs to the task; finding out a second target function before the first target function is executed according to the stack pointer and the stack space; and correcting the task according to the second target function.
Classes IPC ?
- G06F 11/00 - Détection d'erreurs; Correction d'erreurs; Contrôle de fonctionnement
- G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
- G06F 11/28 - Détection d'erreurs; Correction d'erreurs; Contrôle de fonctionnement en vérifiant que l'ordre du traitement est correct
|
75.
|
METHOD FOR RESUMING TOPOLOGY OF SINGLE LOOP NETWORK AND SWITCH NETWORK SYSTEM
Numéro d'application |
18092788 |
Statut |
En instance |
Date de dépôt |
2023-01-03 |
Date de la première publication |
2023-12-21 |
Propriétaire |
REALTEK SEMICONDUCTOR CORP. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Chiu, Chih-Ming
- Cheng, Kai-Wen
- Lin, Yu-Yi
|
Abrégé
A method for resuming topology of a single loop network and a network switch system are provided. The network switch system includes one or more first network switches each having a first port and a second port and a second network switch having a third port and a fourth port. When the first port of one of the first network switches is abnormal, a recovery control frame is transmitted through the second port. The second network switch sets the third port in a disabled state to an enabled state. When the abnormal port is resumed, the first network switch transmits a block control frame through the second port. The second network switch sets the third port in the enabled state to the disabled state and transmits a forward control frame through the fourth port. The first network switch sets the first port in the disabled state to the enabled state.
Classes IPC ?
- H04L 41/12 - Découverte ou gestion des topologies de réseau
|
76.
|
ELECTRONIC DEVICE AND METHOD FOR TRANSMITTING VIDEO DATA AND AUDIO DATA
Numéro d'application |
18162643 |
Statut |
En instance |
Date de dépôt |
2023-01-31 |
Date de la première publication |
2023-12-21 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
Sung, Lien-Hsiang
|
Abrégé
An electronic device includes a receiving unit, a signal processing unit, a transmitting unit, and an audio timing unit. The receiving unit receives audio data and first video data. The signal processing unit generates second video data and a pixel clock signal for playing the second video data according to the first video data. The transmitting unit transmits the second video data, the audio data, the pixel clock signal, and a cycle time stamp (CTS) to a receiver. The audio timing unit generates an internal reference signal adjusts a frequency of the internal reference signal according to a receiving speed of the audio data, and generates the CTS according to the internal reference signal and the pixel clock signal so that the receiver can generate an audio clock signal for playing the audio data according to the pixel clock signal and the CTS.
Classes IPC ?
- H04N 7/06 - Systèmes pour la transmission simultanée d'un seul signal de télévision, c. à d. l'image et le son transmis par plus d'une porteuse
|
77.
|
LOW-DROPOUT REGULATOR AND OPERATION METHOD THEREOF
Numéro d'application |
18317107 |
Statut |
En instance |
Date de dépôt |
2023-05-15 |
Date de la première publication |
2023-12-21 |
Propriétaire |
Realtek Semiconductor Corporation (Taïwan, Province de Chine)
|
Inventeur(s) |
|
Abrégé
A low-dropout regulator includes an amplifier circuit, a buffer circuit, a control circuit, a power transistor, and a feedback circuit. The amplifier circuit is configured to operate based on an input voltage and generate a first voltage at a first node according to a reference voltage and a feedback voltage. The buffer circuit is configured to generate a second voltage at a second node according to the first voltage. The control circuit is configured to work with the buffer circuit to form a noise canceller. The noise canceller is coupled between the first node, the second node, and a voltage terminal. The power transistor is configured to generate an output voltage according to the input voltage and the second voltage. The feedback circuit is configured to generate the feedback voltage according to the output voltage.
Classes IPC ?
- G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
- G05F 1/59 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de réglage final pour une charge unique
- G05F 1/46 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu
|
78.
|
TRANSMITTER AND RELATED GAIN CONTROL METHOD
Numéro d'application |
18318450 |
Statut |
En instance |
Date de dépôt |
2023-05-16 |
Date de la première publication |
2023-12-21 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
Chou, Chien-I
|
Abrégé
A transmitter includes an analog transmission circuit, a power amplifier, a voltage detector, a comparator, and a control circuit. The analog transmission circuit is configured to provide a first gain to a first analog signal, so as to generate a second analog signal. The power amplifier is configured to provide a second gain to the second analog signal, so as to generate an output signal to an antenna. The voltage detector is configured to detect a voltage level of the second analog signal. The comparator is configured to generate an indication signal according to the voltage level and a reference level. The control circuit is configured to adjust the first gain of the analog transmission circuit according to the indication signal.
Classes IPC ?
- H04B 1/04 - Circuits
- H03F 3/24 - Amplificateurs de puissance, p.ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
- H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p.ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
|
79.
|
METHOD FOR SYSTEM PROFILING AND CONTROLLING AND COMPUTER SYSTEM PERFORMING THE SAME
Numéro d'application |
18323422 |
Statut |
En instance |
Date de dépôt |
2023-05-25 |
Date de la première publication |
2023-12-21 |
Propriétaire |
REALTEK SEMICONDUCTOR CORP. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Wu, Yi-Kuan
- Hung, Sheng-Kai
- Wu, Tsai-Wei
- Cheng, Tsai-Chin
- Wu, Yu-Kuen
|
Abrégé
A method for system profiling and controlling and a computer system performing the same are provided. In the method, an operating system is operated after the computer system is booted, in which a profiling-controlling system is operated. When the operating system loads and executes a system profiling-controlling program, the profiling-controlling system that simultaneously operates a profiling routine and a controlling routine is initiated. The profiling routine is used to retrieve system kernel data that is generated during operation of the operating system and analyze the system kernel data through a kernel tracing tool. When it is determined that controlling is required, the profiling routine notifies the controlling routine. The controlling routine controls operating parameters of the operating system in real time according to an analysis result generated by the profiling routine.
Classes IPC ?
- G06F 11/34 - Enregistrement ou évaluation statistique de l'activité du calculateur, p.ex. des interruptions ou des opérations d'entrée–sortie
- G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
|
80.
|
SYSTEM ON A CHIP AND DISPLAY SYSTEM
Numéro d'application |
18137432 |
Statut |
En instance |
Date de dépôt |
2023-04-20 |
Date de la première publication |
2023-12-21 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Wu, Cheng-Hung
- Kung, Wen-Hsia
|
Abrégé
A system on a chip (SoC) includes an on-screen display (OSD) circuit, a memory control circuit, and an audio processor. The OSD circuit is arranged to control OSD of a text message. The memory control circuit is coupled to a memory, and is arranged to read a text-to-speech (TTS) data corresponding to the text message from the memory. The audio processor is coupled to the memory control circuit, and includes a TTS circuit, wherein the TTS circuit is arranged to: receive the TTS data from the memory control circuit, and generate an audio output according to at least the TTS data.
Classes IPC ?
- G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
- G06F 9/448 - Paradigmes d’exécution, p.ex. implémentation de paradigmes de programmation
|
81.
|
Wireless communication apparatus and wireless communication method thereof having transmission strategy adjusting mechanism
Numéro d'application |
18201789 |
Statut |
En instance |
Date de dépôt |
2023-05-25 |
Date de la première publication |
2023-12-21 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
- Li, Wei-Shin
- Chang, Chun-Chu
|
Abrégé
The present invention discloses a wireless communication apparatus having transmission strategy adjusting mechanism that includes a receiving circuit, a detection circuit, a statistics circuit, a strategy determining circuit and a transmission circuit. The receiving circuit receives communication behaviors of external apparatuses. The detection circuit detects inter frame spaces (IFS) corresponding to the communication behaviors and records related time lengths and a set of communication parameters. The statistics circuit performs statistics on the inter frame space according to a plurality of time intervals to generate Inter frame space statistics data. The strategy determining circuit analyzes at least one of the time lengths, communication parameters and Inter frame space statistics data according to at least one application requirement to generate a transmission parameter adjusting signal. The transmission circuit receives the transmission parameter adjusting signal to adjust transmission parameters related to the IFS length to perform data transmission.
|
82.
|
BOOT DATA READING SYSTEM, BOOT DATA READING METHOD, AND PROCESSOR CIRCUIT
Numéro d'application |
18314128 |
Statut |
En instance |
Date de dépôt |
2023-05-08 |
Date de la première publication |
2023-12-21 |
Propriétaire |
Realtek Semiconductor Corporation (Taïwan, Province de Chine)
|
Inventeur(s) |
- Rong, Kui
- Zeng, Hua
- Li, Mingrui
|
Abrégé
A boot data reading system includes a storage circuit and a processor circuit. The storage circuit is configured to store first boot data and second boot data. The first boot data includes a first segment and a second segment. The second boot data includes a third segment, and the third segment corresponds to the first segment. The processor circuit is coupled to the storage circuit. The processor circuit reads the first segment and determines whether the first segment is correct or not. When the first segment is correct, the processor circuit reads the second segment and determines whether the second segment is correct or not. When the first segment is incorrect, the processor circuit reads the third segment and determines whether the third segment is correct or not.
Classes IPC ?
- G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p.ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
- G06F 9/4401 - Amorçage
|
83.
|
ORTHOGONAL FREQUENCY DIVISION MULTIPLE ACCESS POWER CONTROL METHOD AND RELATED ACCESS POINT
Numéro d'application |
18329352 |
Statut |
En instance |
Date de dépôt |
2023-06-05 |
Date de la première publication |
2023-12-14 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
- Yu, Cho-Han
- Tseng, Chun-Kai
- Lee, Wen-Yung
- Lin, Jhe-Yi
- Cheng, Shau-Yu
|
Abrégé
An OFDMA power control method includes: transmitting a first trigger frame to a station, wherein the first trigger frame includes a first target RSSI; receiving a first TB-PPDU from the station, wherein the first TB-PPDU is transmitted by the station using a first power according to the first target RSSI; measuring a first power of the first TB-PPDU to obtain a first measured RSSI; and generating a second the target RSSI according to the first measured RSSI.
Classes IPC ?
- H04W 52/24 - Commande de puissance d'émission [TPC Transmission power control] le TPC étant effectué selon des paramètres spécifiques utilisant le rapport signal sur parasite [SIR Signal to Interference Ratio] ou d'autres paramètres de trajet sans fil
- H04W 52/36 - Commande de puissance d'émission [TPC Transmission power control] utilisant les limitations de la quantité totale de puissance d'émission disponible avec une plage ou un ensemble discrets de valeurs, p.ex. incrément, variation graduelle ou décalages
|
84.
|
Layout of signal traces
Numéro d'application |
18206101 |
Statut |
En instance |
Date de dépôt |
2023-06-06 |
Date de la première publication |
2023-12-14 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
Chen, Yung-Chung
|
Abrégé
A layout of signal traces includes a first set of signal traces and a second set of signal traces that are used for transmitting a first differential signal and a second differential signal respectively. Each set of signal traces includes a first part, a second part, and a third part along the direction of signal transmission. Different parts of the same signal trace as a whole is not straight. All the first parts are in a first signal layer and parallel. The second parts of the two sets of signal traces are in a second signal layer and the first signal layer, respectively, and are across each other. The second part of the first/second set of signal traces is coupled with the first and third parts of the first/second set of signal traces. All the third parts are in the first signal layer and parallel.
|
85.
|
EMBEDDED ELECTRONIC DEVICE AND BOOT METHOD THEREOF
Numéro d'application |
18204618 |
Statut |
En instance |
Date de dépôt |
2023-06-01 |
Date de la première publication |
2023-12-07 |
Propriétaire |
REALTEK SEMICONDUCTOR CORP. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Zhang, Tian-Yuan
- Lu, Yang
- Shen, Gang
- He, Dong-Yu
|
Abrégé
An embedded electronic device and a boot method are provided. A processor of the embedded electronic device is configured to execute following steps based on a first boot procedure: verifying whether a second memory device safely corresponds to a first memory controller; in response to that the second memory device safely corresponds to the first memory controller, deciphering and verifying stored data of the second memory device through the first memory controller; and in response to that the second memory device does not safely correspond to the first memory controller, verifying whether the second memory device safely corresponds to a second memory controller.
Classes IPC ?
- G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
- G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
|
86.
|
MEMORY CONTROL SYSTEM AND MEMORY CONTROL METHOD
Numéro d'application |
18196620 |
Statut |
En instance |
Date de dépôt |
2023-05-12 |
Date de la première publication |
2023-12-07 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
- Lai, Chi-Shao
- Shih, Hsu-Tung
|
Abrégé
A memory control system includes a front-end circuitry, a back-end circuitry, and a traffic scheduling circuitry. The front-end circuitry is configured to receive a plurality of access requests from a plurality of devices, and adjust an order of the plurality of devices to access a memory according to a plurality of control signals. The traffic scheduling circuitry is configured to generate a plurality of traffic data based on the plurality of access requests and analyze the plurality of traffic data based on a neural network model and a predetermined rule, in order to determine the plurality of control signals. The back-end circuitry is configured to adjust a task schedule of the memory according to the plurality of control signals.
Classes IPC ?
- H04L 47/24 - Trafic caractérisé par des attributs spécifiques, p.ex. la priorité ou QoS
- H04L 47/56 - Ordonnancement des files d’attente en implémentant un ordonnancement selon le délai
- H04L 41/16 - Dispositions pour la maintenance, l’administration ou la gestion des réseaux de commutation de données, p.ex. des réseaux de commutation de paquets en utilisant l'apprentissage automatique ou l'intelligence artificielle
|
87.
|
CAPACITIVE SENSING DEVICE AND CAPACITIVE SENSING METHOD
Numéro d'application |
18197750 |
Statut |
En instance |
Date de dépôt |
2023-05-16 |
Date de la première publication |
2023-12-07 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
Tsai, Hsu-Ming
|
Abrégé
A capacitive sensing device includes a switch circuitry, a counter circuit, a comparator circuit, an amplifier circuit including first and second input terminals and an output terminal, and a feedback capacitor coupled between the output terminal and the first input terminal. The switch circuitry transmits a reference voltage to the second input terminal and couples the first input terminal to the output terminal during a first phase, transmits another reference voltage to the second input terminal during a second phase, and adjusts a voltage of the output terminal during a third phase. The counter circuit starts counting and the comparator circuit generates the control signal according to the output voltage and the second reference voltage during the third phase. The counter circuit stops counting according to the control signal to generate a count value indicating a capacitance value change of a capacitor under-test coupled to the first input terminal.
Classes IPC ?
- G06F 3/044 - Numériseurs, p.ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction par des moyens capacitifs
- G01R 19/00 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe
- G06F 3/041 - Numériseurs, p.ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction
|
88.
|
METHOD AND ELECTRONIC DEVICE FOR PROCESSING VIDEO CODING
Numéro d'application |
17829739 |
Statut |
En instance |
Date de dépôt |
2022-06-01 |
Date de la première publication |
2023-12-07 |
Propriétaire |
REALTEK SEMICONDUCTOR CORP. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Zeng, Wei-Min
- Chai, Chi-Wang
- Li, Wei
- Wang, Jing
- Chen, Wu-Jun
|
Abrégé
A method and an electronic device for processing video coding are provided. The electronic device for processing video coding includes a storage unit, a coding tree generation module, and a decision tree module. The storage unit stores an input video. The input video includes a plurality of frames. The electronic device for processing video performs following steps of: acquiring a target block in each of the frames, where the target block has at least one coding unit; loading the target block to the coding tree generation module to output a first coding tree and a second coding tree; generating an output decision tree according to the first coding tree and the second coding tree; and outputting streaming data according to the output decision tree and the frames.
Classes IPC ?
- H04N 19/96 - Codage au moyen d'une arborescence, p.ex. codage au moyen d'une arborescence quadratique
- H04N 19/147 - Débit ou quantité de données codées à la sortie du codeur selon des critères de débit-distorsion
- H04N 19/105 - Sélection de l’unité de référence pour la prédiction dans un mode de codage ou de prédiction choisi, p.ex. choix adaptatif de la position et du nombre de pixels utilisés pour la prédiction
- H04N 19/176 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c. à d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p.ex. un objet la zone étant un bloc, p.ex. un macrobloc
|
89.
|
PACKET FORWARDING SYSTEM AND ASSOCIATED PACKET FORWARDING METHOD
Numéro d'application |
18198839 |
Statut |
En instance |
Date de dépôt |
2023-05-17 |
Date de la première publication |
2023-11-30 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Liu, Heng-Xiu
- Kuo, Chen-Feng
- Yeh, Lun-Wu
|
Abrégé
The present invention provides a packet forwarding system including a packet, a packet analyzer and a DMA module. The packet buffer is configured to receive a packet and store the packet. The packet analyzer is configured to read the packet from the packet buffer, and analyze the packet to extract part of content of the packet to generate specific data. The DMA module is configured to write the specific data into a first buffer of a storage device, and write the packet into a second buffer of the storage device.
Classes IPC ?
- H04L 49/901 - Dispositions de mémoires tampon en utilisant un descripteur de stockage, p.ex. des pointeurs de lecture ou d'écriture
- H04L 49/00 - TRANSMISSION D'INFORMATION NUMÉRIQUE, p.ex. COMMUNICATION TÉLÉGRAPHIQUE Éléments de commutation de paquets
|
90.
|
METHOD FOR DATA ACCESS CONTROL AMONG MULTIPLE NODES AND DATA ACCESS SYSTEM
Numéro d'application |
18325124 |
Statut |
En instance |
Date de dépôt |
2023-05-30 |
Date de la première publication |
2023-11-30 |
Propriétaire |
REALTEK SEMICONDUCTOR CORP. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Hung, Yu-Hsuan
- Fang, Wei-Hao
- Shr, Kai-Ting
|
Abrégé
A method for data access control among multiple nodes and a data access system are provided. The data access system includes a data interconnect controller circuit that allocates resources of one or more slaves by one or more masters according to operating parameters of an interleaver, and includes an intelligent control module that collects use efficiency data of the one or more slaves and obtains a current setting of the data interconnect controller circuit via a monitor. The monitor calculates scores of use efficiency data. The scores and the setting are inputted to a neural network model. Parameters of the neural network model are adjusted according to the scores, and a new setting generated by the neural network model is applied to the interleaver of the data interconnect controller circuit, so that the data interconnect controller circuit performs access control among the multiple nodes with the new setting.
Classes IPC ?
- G06F 13/362 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès centralisée
- G06F 11/30 - Surveillance du fonctionnement
- G06N 3/08 - Méthodes d'apprentissage
|
91.
|
Solid-state drive controller and circuit controller
Numéro d'application |
18104679 |
Statut |
En instance |
Date de dépôt |
2023-02-01 |
Date de la première publication |
2023-11-30 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
Chen, Yen-Chung
|
Abrégé
A solid-state drive (SSD) controller is operable to determine whether M supply voltage(s) supplied to a NAND flash memory is correct. The SSD controller includes: a voltage detector configured to receive the M supply voltage(s) and thereby generate a detection result, wherein the M is a positive integer; a voltage inquiry module configured to output an inquiry signal to the NAND flash memory and thereby receive a response signal from the NAND flash memory, and configured to generate an inquiry result according to the response signal, wherein the inquiry result indicates M specified supply voltage(s) applicable to the NAND flash memory; and a voltage decision module configured to receive the detection result and the inquiry result, and configured to determine whether the M supply voltage(s) is/are equivalent to the M specified voltage(s) according to the detection result and the inquiry result and thereby generate a decision result.
Classes IPC ?
- G11C 16/30 - Circuits d'alimentation
- G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
|
92.
|
NAND flash memory controller
Numéro d'application |
18111911 |
Statut |
En instance |
Date de dépôt |
2023-02-21 |
Date de la première publication |
2023-11-30 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
Chen, Yen-Chung
|
Abrégé
A NAND flash memory controller can adjust its processing power according to a host speed and thereby save energy. The controller includes: a host speed estimation module estimating the host speed according to a first total data amount of the host's M first I/O command(s) received by the controller within a first period of time, the host speed correlating with the host's demand for access; a controller speed estimation module estimating a controller speed according to a second total data amount of the host's N second I/O command(s) completed by the controller within a second period of time, the controller speed correlating with the processing power of the controller; a speed decision module generating a decision result according to the relation between the host speed and the controller speed; and a speed adjustment module adjusting or maintaining the processing power of the controller according to the decision result.
Classes IPC ?
- G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
|
93.
|
Shielding circuits and semiconductor devices
Numéro d'application |
18143056 |
Statut |
En instance |
Date de dépôt |
2023-05-03 |
Date de la première publication |
2023-11-30 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
|
Inventeur(s) |
Chen, Yung-Chung
|
Abrégé
A shielding circuit applied to a semiconductor device includes a first shielding structure and a second shielding structure. The first shielding structure forms a first closed loop and is disposed adjacent to an inductor comprised in the semiconductor device. The second shielding structure forms a second closed loop and is disposed adjacent to an electronic component coupled to the inductor.
Classes IPC ?
- H01L 23/552 - Protection contre les radiations, p.ex. la lumière
|
94.
|
MEDIA PLAYBACK DEVICE AND RELATED MEDIA PLAYBACK METHOD
Numéro d'application |
18144242 |
Statut |
En instance |
Date de dépôt |
2023-05-07 |
Date de la première publication |
2023-11-30 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
|
Inventeur(s) |
- Chen, Chun-Yi
- Yang, Ching-Yao
|
Abrégé
A method for performing media playback on a media playback device includes: generating a quick launch area in a user interface according to a quick launch setting, wherein the quick launch area includes a plurality of windows, and the windows correspond to at least one audio-visual (AV) content and at least one application program respectively; according to the quick launch setting, retrieving data corresponding to the at least one AV content and buffering the data in a first buffering unit; according to the quick launch setting, retrieving data required by executing the at least one application program and buffering the data in a second buffering unit; and in response to a quick launch operation, decoding the data buffered in the first buffering unit to play the AV content, or utilizing the data buffered in the second buffering unit to execute the at least one application program.
Classes IPC ?
- H04N 21/44 - Traitement de flux élémentaires vidéo, p.ex. raccordement d'un clip vidéo récupéré d'un stockage local avec un flux vidéo en entrée ou rendu de scènes selon des graphes de scène MPEG-4
- H04N 21/482 - Interface pour utilisateurs finaux pour la sélection de programmes
- H04N 21/431 - Génération d'interfaces visuelles; Rendu de contenu ou données additionnelles
- H04N 21/433 - Opération de stockage de contenu, p.ex. opération de stockage en réponse à une requête de pause ou opérations de cache
- H04N 21/643 - Protocoles de communication
|
95.
|
SPEED DETECTION CIRCUIT AND ASSOCIATED CHIP
Numéro d'application |
18198301 |
Statut |
En instance |
Date de dépôt |
2023-05-17 |
Date de la première publication |
2023-11-30 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
|
Inventeur(s) |
Chang, Chih-Chiang
|
Abrégé
The present invention provides a speed detection circuit positioned in a chip, wherein the speed detection circuit includes a test signal generator, a launch flip-flop, a device under test (DUT), a capture flip-flop, a comparator and a control circuit. The test signal generator is configured to generate a test signal with a specific pattern. The launch flip-flop is configured to use a first clock signal to sample the test signal to generate a sampled test signal. The device under test is configured to receive the sampled test signal to generate a delayed test signal. The capture flip-flop is configured to use a second clock signal to sample the delayed test signal to generate an output signal. The comparator is configured to determine whether the output signal conforms to the specific pattern to generate a comparison result, for the control circuit to determine a speed of the chip.
Classes IPC ?
- G01R 31/28 - Test de circuits électroniques, p.ex. à l'aide d'un traceur de signaux
- H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p.ex. des signaux d'horloge
- H03K 3/037 - Circuits bistables
|
96.
|
HYBRID CLASS-D AMPLIFIER
Numéro d'application |
18200593 |
Statut |
En instance |
Date de dépôt |
2023-05-23 |
Date de la première publication |
2023-11-30 |
Propriétaire |
Realtek Semiconductor Corp. (Taïwan, Province de Chine)
|
Inventeur(s) |
Wang, Chih-Chiang
|
Abrégé
A hybrid class-D amplifier is provided. The hybrid class-D amplifier includes a digital-to-analog conversion (DAC) input stage circuit, a loop filter circuit electrically coupled to the DAC input stage circuit, a quantizer circuit electrically coupled to the loop filter circuit, an output stage circuit electrically coupled to the quantizer circuit, and a feedback circuit electrically coupled between the output stage circuit and the loop filter circuit. The DAC input stage circuit converts a digital signal into an analog signal. The loop filter circuit generates a filtered signal according to the analog signal and a feedback signal. The quantizer circuit performs a quantization operation on the filtered signal to generate a quantized signal. The output stage circuit performs power amplification on the quantized signal to generate an output signal. The feedback circuit generates the feedback signal according to the output signal.
Classes IPC ?
- H03F 3/217 - Amplificateurs de puissance de classe D; Amplificateurs à commutation
|
97.
|
LOW-DROPOUT REGULATOR CIRCUIT AND CONTROL METHOD THEREOF
Numéro d'application |
18315506 |
Statut |
En instance |
Date de dépôt |
2023-05-11 |
Date de la première publication |
2023-11-30 |
Propriétaire |
Realtek Semiconductor Corporation (Taïwan, Province de Chine)
|
Inventeur(s) |
- Lin, Sheng-Wei
- Tang, Wei-Cheng
|
Abrégé
A low-dropout regulator circuit includes a reference circuit, an amplifying circuit, a power switch circuit, a feedback circuit, and a control circuit. The reference circuit is configured to generate a reference voltage. The amplifying circuit is configured to generate an amplifying voltage according to the reference voltage and a feedback voltage. The power switch circuit is configured to receive the amplifying voltage and generate an output voltage at an output terminal according to an input voltage. The feedback circuit is configured to generate the feedback voltage according to the output voltage. The control circuit is configured to control the power switch circuit according to the input voltage and a signal from the reference circuit.
Classes IPC ?
- G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
- G05F 1/46 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu
- G05F 3/30 - Régulateurs utilisant la différence entre les tensions base-émetteur de deux transistors bipolaires fonctionnant à des densités de courant différentes
|
98.
|
Multi-core processing circuit and test method of the same having power-stabilizing test mechanism
Numéro d'application |
18196637 |
Statut |
En instance |
Date de dépôt |
2023-05-12 |
Date de la première publication |
2023-11-23 |
Propriétaire |
REALTEK SEMICONDUCTOR CORPORATION (Taïwan, Province de Chine)
|
Inventeur(s) |
- Huang, Ching-Feng
- Lo, Yu-Cheng
|
Abrégé
The present disclosure discloses a multi-core processing circuit having power-stabilizing test mechanism that includes a plurality of core-processing circuits arranged in an order and a self-test scheduling circuit. Each of the core-processing circuits includes a memory built-in self-test circuit. The self-test scheduling circuit receives a main activation signal to activate the memory built-in self-test circuit of one of the core-processing circuits every delay time in the order based on signal handshake to perform self-test, wherein one of the activated core-processing circuits has a largest average power draining amount in a predetermined range within the delay time.
Classes IPC ?
- G06F 11/27 - Tests intégrés
- G06F 11/273 - Matériel de test, c. à d. circuits de traitement de signaux de sortie
|
99.
|
LINEAR REGULATOR AND VOLTAGE REGULATION METHOD
Numéro d'application |
18302799 |
Statut |
En instance |
Date de dépôt |
2023-04-19 |
Date de la première publication |
2023-11-23 |
Propriétaire |
Realtek Semiconductor Corporation (Taïwan, Province de Chine)
|
Inventeur(s) |
Lei, Liang-Huan
|
Abrégé
A linear regulator includes a switching element, an error amplifier circuit, a feedback circuit and a triggering element. A first terminal of the switching element receives an input voltage, and outputs an output voltage to a load through a second terminal. A first input terminal of the error amplifier circuit receives a reference voltage, and an output terminal of the error amplifier circuit is electrically connected to a control terminal of the switching element. The feedback circuit is electrically connected between the second terminal and a second input terminal of the error amplifier circuit. The trigger element is electrically connected to the control terminal and the load to receive a trigger signal. The trigger element outputs a trigger voltage to the control terminal according to the trigger signal, and the switch element is configured to change the output voltage.
Classes IPC ?
- G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
- G05F 1/59 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de réglage final pour une charge unique
- G05F 1/565 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final sensible à une condition du système ou de sa charge en plus des moyens sensibles aux écarts de la sortie du système, p.ex. courant, tension, facteur de puissance
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100.
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METHOD FOR MOTION DETECTION AND CIRCUIT SYSTEM
Numéro d'application |
18319497 |
Statut |
En instance |
Date de dépôt |
2023-05-18 |
Date de la première publication |
2023-11-23 |
Propriétaire |
REALTEK SEMICONDUCTOR CORP. (Taïwan, Province de Chine)
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Inventeur(s) |
- Kuo, Jyun-Yi
- Wu, Chun-Hsien
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Abrégé
A method for motion detection and a circuit system are provided. In the method, when any moving object within a scene is sensed, continuous frame images are obtained. Each of the frame images is divided into multiple regions. Brightness and chromaticity of each region are calculated frame by frame, and are compared with a background model to obtain a difference. Accordingly, a movement event in each of the frame images can be identified. When any movement event is recognized, a region of interest (ROI) covering one or more of the regions where the movement event is detected is established. An intelligent model created by a neural network algorithm is used to calculate a trust score for a possibility of having the moving object in each of the frame images. The moving object can be detected by comparing the trust score with a determination threshold.
Classes IPC ?
- G06T 7/20 - Analyse du mouvement
- G06T 7/11 - Découpage basé sur les zones
- G06V 10/25 - Détermination d’une région d’intérêt [ROI] ou d’un volume d’intérêt [VOI]
- G06V 10/60 - Extraction de caractéristiques d’images ou de vidéos relative aux propriétés luminescentes, p.ex. utilisant un modèle de réflectance ou d’éclairage
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