A system and method of allowing a new device to join an existing network are disclosed. A configuration tool is used to communicate relevant information from the new network device to the gateway in the existing network using a secondary network protocol different from that used by the primary network. For example, in one embodiment, messages are exchanged between the configuration tool and the new device and between the configuration tool and the gateway using BLUETOOTH®. Once all of the pertinent information has been exchanged, the new device is able to securely join the primary network, which may be based on the IEEE802.15.4 standard.
An apparatus includes an integrated circuit, which includes a processor and a driver. The integrated circuit is fabricated by a process that establishes a nominal maximum voltage for components of the integrated circuit. The driver is adapted to selectively electrically couple a voltage that is higher than the nominal maximum voltage to an external terminal of the integrated circuit.
According to one embodiment, the present invention includes a system that has a mechanical tuning mechanism to enable a user to select a radio channel, a variable resistance coupled to the mechanical tuning mechanism, and a radio receiver implemented on a die of a semiconductor package. The variable resistance has a first terminal to couple to a supply voltage and a second terminal to couple to a ground voltage, and a connection to provide a variable analog voltage responsive to the user selection. In turn, the receiver is coupled to receive the variable analog voltage via a first pin of the package, receive the supply voltage via a second pin of the package, and receive the ground voltage via a third pin of the package, in a single pin tuning mode. The receiver can downconvert a radio frequency (RF) signal to a second frequency signal with a mixing signal having a frequency based on the variable analog voltage.
H01L 27/00 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun
H04H 40/18 - Dispositions caractérisées par des circuits ou composants spécialement adaptés à la réception
4.
RECEIVER AND METHODS FOR PROVIDING CHANNEL STABILITY
A receiver includes an analog-to-digital converter (ADC) including an input configurable to digitize a voltage from a potentiometer and including an output for providing an ADC output signal. The receiver further includes a controller coupled to the output of the ADC and adapted to determine a selected channel based on multiple consecutive samples of the ADC output signal.
A receiver includes a tuner input for receiving a radio frequency signal, a mixer, and a controller. The mixer includes a mixer input coupled to the tuner input, a control input for receiving an oscillating signal, and a mixer output for providing an output signal in response to the oscillating signal and the received radio frequency signal. The output signal corresponds to a selected frequency of the radio frequency signal. The controller controls a frequency of the oscillating signal to tune the mixer to produce the output signal at the selected frequency. The controller is configured to test for a valid signal at the selected frequency and to tune to the selected frequency in response to detecting the valid signal. The controller controls the frequency of the oscillating signal to frequency hop within a range of frequencies around the selected frequency to locate the valid signal when no signal is found at the selected frequency.
A receiver includes a tunable circuit and an input terminal which is used to receive Radio Frequency signal from antennas, wherein the tunable circuit includes an input end coupled to the input terminal, at least one control input end and an output terminal. The tunable circuit includes a varactor, wherein the varactor includes a first electrode coupled to the input terminal and a second electrode coupled to a power supply terminal. The receiver also includes a control circuit which is coupled to the output terminal and the at least one control input end. The control circuit receives a radio channel choice and, responding to the radio channel choice, determines the capacitance of the varactor based on a predefined inductance which relates to the tunable circuit.
H03J 7/08 - Commande automatique de fréquence dans lequel la commande de fréquence est réalisée en faisant varier les caractéristiques électriques d'un élément ajustable par des moyens non mécaniques ou bien dans lequel la nature de l'élément servant à commander la fréquence est sans importance en utilisant des varactors, c. à d. des diodes à capacité variable avec la tension
H03J 3/20 - Accord continu d'un seul circuit résonnant en faisant varier uniquement l'inductance ou uniquement la capacité
Systems and methods are disclosed for shared AM/FM air loop antennas that may be advantageously implemented to provide a AM/FM receiver system with a single common air loop antenna for receiving both AM and FM channels, thus eliminating the need for additional materials and electronics associated with provision of a separate FM pigtail antenna and FM antenna jack for connection of same. The shared AM/FM air loop antennas may be connected to a radio device having antenna connections.
An apparatus includes a processor, a clock recovery circuit and a frequency locked loop. The processor receives a system clock signal to clock operations of the processor; and the clock recovery circuit recovers a clock signal from data communication occurring over a bus. The frequency locked loop receives the clock signal from the clock recovery circuit as a reference clock signal, and the frequency locked loop is adapted to lock onto the clock signal provided by the clock recovery circuit to provide the system clock signal.
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p.ex. en utilisant une boucle verrouillée en phase
H04B 15/04 - Réduction des perturbations parasites dues aux appareils électriques avec des moyens disposés sur ou à proximité de la source de perturbation la perturbation étant causée par des ondes essentiellement sinusoïdales, p.ex. dans un récepteur ou un enregistreur à bande magnétique
H03L 7/00 - Commande automatique de fréquence ou de phase; Synchronisation
A method for interfacing with a capacitive touch screen is disclosed. The method includes charging an internal capacitor in the touch screen, which internal capacitor is disposed proximate a fixed location on the touch screen and is capable of changing in response to a touch at the specific location. After charging, the charge on the internal capacitor is transferred from the touch screen and the value of the charge on the internal capacitor then determined.
G09G 3/20 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p.ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice
G06F 3/044 - Numériseurs, p.ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction par des moyens capacitifs
An apparatus includes an integrated circuit (IC) configured to sense capacitance, and two or more capacitive elements coupled to the IC. The capacitive elements each have a first section, and one capacitive element has a second section. The first sections of the capacitive elements have the same or substantially the same lengths, shapes, and/or capacitance values.
G01R 27/26 - Mesure de l'inductance ou de la capacitance; Mesure du facteur de qualité, p.ex. en utilisant la méthode par résonance; Mesure de facteur de pertes; Mesure des constantes diélectriques
11.
SUBSCRIBER LINE INTERFACE CIRCUITRY WITH INTEGRATED SERIAL INTERFACES
Methods and apparatus for communicating PCM and SDI data on a common interface are described. Various embodiments of the common interface include two (580, 582, 1180, 1182) to three (880, 882) signal lines. The signal lines are unidirectional or bi-directional. A clock signal may be provided by dedicated signal line or recovered from frames carried by the signal lines. One embodiment includes a first device (522) coupled (710) to a second device (510) with a bi directional data line (574) and a clock line (572). Frames of data are serially communicated (720) between the first and second devices on the data line. Each frame is synchronized with a clock signal carried by the clock line. Each frame (602) has a portion allocated to data communicated from the first device to the second device and another portion allocated to data communicated from the second device to the first device.
H04M 3/00 - Centraux automatiques ou semi-automatiques
H04M 11/06 - Transmission simultanée téléphonique et de données, p.ex. transmission télégraphique sur les mêmes conducteurs
H04L 12/28 - Réseaux de données à commutation caractérisés par la configuration des liaisons, p.ex. réseaux locaux [LAN Local Area Networks] ou réseaux étendus [WAN Wide Area Networks]
H04J 3/16 - Systèmes multiplex à division de temps dans lesquels le temps attribué à chacun des canaux au cours d'un cycle de transmission est variable, p.ex. pour tenir compte de la complexité variable des signaux, pour adapter le nombre de canaux transmis
G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation
H04Q 11/04 - Dispositifs de sélection pour systèmes multiplex pour multiplex à division de temps
12.
CIRCUIT DEVICE AND METHOD OF CURRENT LIMIT-BASED DISCONNECT DETECTION
In a particular embodiment, a power sourcing equipment (PSE) device includes at least one network port (122) adapted to couple to a powered device to provide power and optionally data to the powered device via a network cable. The PSE device further includes a current limiter circuit (140) coupled to the at least one network port (122) and having an adjustable threshold. The PSE device also includes a logic circuit (134) coupled to the current limiter circuit (140) and adapted to reduce the adjustable threshold of the current limiter circuit (140) to have a threshold level that is below a nominal operating current level. After a period of time has elapsed during which the current limiter circuit (140) is not activated, the logic circuit (134) is adapted to determine that the powered device is disconnected (142) from the at least one network port (122).
In one embodiment, the present invention provide a method for detecting signal quality metrics of a constant modulo (CM) signal received in two different signal paths, and combining the signal from the two signal paths based at least in part on the detected first and second signal quality metrics. Such method may be implemented in a radio receiver such as an automobile receiver.
Methods and systems are disclosed for predictive feedback compensation (PFC) circuitry for suppressing distortions caused by supply voltage variations and output amplitude switching non-idealities in pulse width modulated (PWM) switching amplifiers by pre-compensating the PWM input based upon the supply voltage or output pulse amplitude. Output amplitude errors associated with previous PWM output signals are used to predict output amplitude errors expected for future PWM output signals. These predicted output amplitude errors are then used to adjust the pulse widths for the future PWM output signals. Closed loop width adjustment can also be applied by providing timing feedback signals associated with the pre-compensation of the PWM input signals. Traditional feedback techniques can also be used in conjunction with the predictive feedback compensation (PFC) circuitry.
A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.
A method performed by a receiver is provided. The method includes generating an RDS/RBDS candidate codeword from a set of RDS/RBDS symbols where the RDS/RBDS candidate codeword has a subset of RDS/RBDS values that differs from corresponding subsets of RDS/RBDS values in all other possible RDS/RBDS codewords and determining whether the RDS/RBDS candidate codeword meets an acceptance criterion by comparing a first subset of reliability values determined from the set of RDS/RBDS symbols and having signs that differ from corresponding signs in the subset of RDS/RBDS values with a second subset of reliability values determined from the set of RDS/RBDS symbols and mutually exclusive with the first subset of the reliability values. A first number of values in the first and the second subsets of reliability values is less than a second number of values in the RDS/RBDS candidate codeword.
A microcontroller includes a processing unit having a processing unit having normal power mode of operation and a low power mode of operation. The processing unit further having digital circuitry connected to the processing unit having a plurality of logic circuits associated therewith for processing digital values. A plurality of retention flip-flops are associated with the digital circuitry for storing a logical state of at least one or more of the logic circuits within the digital circuitry when the processing unit enters the low power mode of operation. The plurality of retention flip flops include a first type of transistors for operating in both the low and high power modes of operation and a second type of transistors for operation only in the normal mode of operation and wherein substantially the remainder of the digital circuitry in the processing unit comprises the second type of transistors.
A receiver including first circuitry configured to combine corresponding soft decision values from at least two groups of RDS/RBDS data transmitted as part of a broadcast channel to generate a set of combined values and second circuitry configured to identify a subset of the combined values that indicate a relatively constant subset of the received values from the at least two groups of the RDS/RBDS data is provided.
In one embodiment, the present invention includes a mixer circuit to receive and generate a mixed signal from a radio frequency (RF) signal and a master clock signal, a switch stage coupled to an output of the mixer circuit to rotatingly switch the mixed signal to multiple gain stages coupled to the switch stage, and a combiner to combine an output of the gain stages.
H03D 7/12 - Transfert de modulation d'une porteuse à une autre, p.ex. changement de fréquence au moyen de dispositifs à semi-conducteurs ayant plus de deux électrodes
In one embodiment, the present invention includes an accessory device for coupling to a portable system having an AM radio receiver. The accessory device includes a housing to house at least one accessory component and an AM antenna.
A receiver including a mixer configured to generate a mixed signal at a first intermediate frequency from an input signal and a mixing signal and processing circuitry configured to detect a power level for each of a plurality of possible images in the mixed signal and configured to cause the mixer to generate the mixed signal at a second intermediate frequency that differs from the first intermediate frequency and corresponds to an image frequency of one of the plurality of possible images with a lowest of the power level is provided.
A device is disclosed that includes an interface and an integrated circuit. The interface is communicatively coupled to a network connection to provide power and data to a power over Ethernet (PoE) powered device via the network connection. The integrated circuit is coupled to the interface. The integrated circuit includes a power over Ethernet (PoE) controller, a detection and classification circuit, and a voltage protection circuit. The detection and classification circuit is coupled to the interface to detect and classify a power level of the PoE powered device. The voltage protection circuit is coupled to the interface to detect a power event and to provide an alert to the PoE controller in response to the detected power event.
H02H 3/20 - Circuits de protection de sécurité pour déconnexion automatique due directement à un changement indésirable des conditions électriques normales de travail avec ou sans reconnexion sensibles à un excès de tension
An integrated system on a chip includes processing circuitry that performs predefined digital processing functions on the chip. The processing circuitry operates responsive to a regulated voltage. An on-chip boost converter generates the regulated voltage responsive to an off-chip voltage provided by an off chip voltage source. The regulated voltage source has a voltage level greater than the off-chip voltage.
G05F 1/253 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type alternatif utilisant des transformateurs montés en série ou en opposition comme dispositifs de réglage final les transformateurs comprenant plusieurs enroulements en série entre la source et la charge
The integrated system on a chip with LINBUS network communication capabilities includes processing circuitry for performing predefined digital processing functionalities on the chip. A free running clock circuit generates a temperature compensated clock that does not require a synch signal from external to the chip. A LINBUS network communications interface digitally communicates with off-chip LINBUS devices. Communication between said on-chip LINBUS communications interface and the off-chip LINBUS devices is affected without clock recovery. The LINBUS network communication interface has a time base derived from the temperature compensated clock which is independent of any timing information in the input data received during a receive operation. The temperature compensated clock further provides an on-chip time reference for both the processing circuitry and the LINBUS network communications interface.
In one aspect, the present invention includes a method for receiving an amplitude modulation (AM) signal in a receiver and performing a coordinate rotation digital computer (CORDIC) operation in obtaining a demodulated AM signal. The demodulated AM signal may be obtained from a magnitude output of the CORDIC operation or as a real output of a multiplication between a complex baseband signal and a demodulating carrier signal generated in a feedback loop.
Methods and systems for determining transmission channels for short range transmissions are disclosed. A transmitter provides short range transmission to a broadcast receiver configured to receive and tune channels within a signal spectrum. Channels within the broadcast signal spectrum are scanned, and an indication of received signal strength is obtained for each channel. The received signal strength indication (RSSI) can then be compared to a threshold power level that correlates to a signal level that the transmitter will be capable of overpowering based upon the transmission power of the transmitter. The scan results in an indication of one or more channels that have received signal strengths below the threshold power level of the transmitter.
A system includes a cellular radio and an FM transmitter that are fabricated in the same semiconductor. The FM transmitter includes at least one mixer, a filter and an antenna tuning network. The mixer(s) translate an intermediate carrier frequency of an input signal to generate a second signal that has an FM carrier frequency. The filter removes spectral energy from the second signal to generate a third signal. The antenna tuning network is separate from the filter and produces a fourth signal to drive an antenna in response to the third signal.
A technique includes providing a plurality of local oscillator signals such that each of the local oscillator signals has a different phase. The technique includes providing scaling units to scale the input signal pursuant to different scaling factors to generate scaled input signals. The scaling factors are selected on a periodic function of the phases. The technique also includes providing mixing circuits to mix the local oscillator signals with the scaled input signals to generate mixed signals and providing an adder to combine the mixed signals to generate an output signal.
A clock synthesis circuit includes a delta sigma modulator that receives a divide ratio and generates an integer portion and a digital quantization error (a fractional portion). A fractional-N divider divides a received signal according to a divide control value corresponding to the integer portion and generates a divided signal. A phase interpolator adjusts a phase of the divided signal according to the digital quantization error to thereby reduce noise associated with the fractional-N divider.
A powered device includes a voltage protection circuit, two outputs, a switch, and a snubber circuit. The two outputs of the integrated circuit maybe coupled to an external transformer. The snubber circuit of the integrated circuit is responsive to the switch and is coupled with respect to the two outputs to direct energy from at least one of the two outputs to the voltage protection circuit.
A transceiver includes a processor and an analog-to-digital converter. The processor is adapted to in a transmit mode of the transceiver, generate a modulated signal in response to a first digital signal. In a receive mode of the transceiver, the processor is adapted to generate a demodulated signal in response to a second digital signal. The analog-to-digital converter provides the first digital signal in the transmit mode and provides the second digital signal in the receive mode.
A technique includes digitally generating orthogonal modulated signals, each of which has spectral energy that is generally centered at an intermediate frequency. The orthogonal modulated signals are frequency translated to produce translated signals, each of which has spectral energy that is generally centered about a second frequency that is higher than the intermediate frequency. The translated signals are combined to generate a modulated signal.
H03C 3/40 - Modulation d'angle par conversion de modulation d'amplitude en modulation d'angle utilisant deux voies de signaux dont les sorties ont une différence de phase déterminée et l'une au moins des sorties étant modulée en amplitude
A programmable reference-less oscillator provides a wide range of programmable output frequencies. The programmable reference-less oscillator is implemented on an integrated circuit that includes a free running controllable oscillator circuit such as a voltage controlled oscillator (VCO), a programmable divider circuit coupled to divide an output of the controllable oscillator circuit according to a programmable divide value. A non-volatile storage stores the programmed divide value and a control word that controls the output of the controllable oscillator circuit. The control word provides a calibration capability to achieve a desired output frequency in conjunction with the programmable divider circuit. Open loop temperature compensation is achieved by adjusting the control word according to a temperature detected by a temperature sensor on the integrated circuit. Additional clock accuracy may be achieved by adjusting the control word for process as well as temperature.
A current sensor includes one or more inductors that generate a sensed output current responsive to a current in a conductor when the one or more inductors are inductively coupled to the conductor. The current sensor includes an integrated circuit die including an integrator circuit coupled to the one or more inductors for generating a sensed voltage responsive to the sensed current, the sensed voltage indicative of the first current in the conductor. The inductors may be formed in the integrated circuit and the conductor may incorporated into the package holding the die.
G01R 15/18 - Adaptations fournissant une isolation en tension ou en courant, p.ex. adaptations pour les réseaux à haute tension ou à courant fort utilisant des dispositifs inductifs, p.ex. des transformateurs
G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
In one embodiment, the present invention includes a method for receiving data corresponding to a portion of an incoming radio frequency (RF) spectrum, dete&pgr;nining a set of estimates including one or more pairs of a channel frequency estimate and a symbol rate estimate from the data via a linear spectrum analysis, and determining a refined set of estimates from the set of estimates via at least one non-linear spectrum analysis.
A technique includes receiving a signal spectrum that includes a plurality of channels within a first frequency range. The technique includes receiving a selection signal that identifies at least one desired channel to be tuned. The technique includes providing an oscillator that has a second frequency range that is substantially the same as the first frequency range and controlling the oscillators to generate one of a plurality of coarse-tune analog mixing signals. The signals substantially span across the second frequency range and each depends upon the location of the desired channel within the signal spectrum. The technique includes mixing the signal spectrum with the selected coarse-tune analog mixing signal to generate a coarsely tuned signal spectrum. The technique includes digitally processing the coarsely-tuned signal spectrum to fine tune the desired channel and to produce digital baseband signals for the desired channel.
H03D 3/00 - Démodulation d'oscillations modulées en angle
H03L 7/18 - Synthèse de fréquence indirecte, c. à d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle
A frequency synthesizer includes analog components and digital components. The frequency synthesizer includes at least one shunt regulator that is coupled to a supply rail to provide power to at least one of the digital components. The frequency synthesizer also includes at least one series regulator that is coupled to the supply rail to provide power to at least one of the analog components.
H03L 7/16 - Synthèse de fréquence indirecte, c. à d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase
38.
IN SYSTEM ANALYSIS AND COMPENSATION FOR A DIGITAL PWM CONTROLLER
A system for analyzing the operation of a switching power converter includes a digital controller for receiving an analog signal representing the output DC voltage of the power converter for comparison to a desired output voltage level and generating switching control signals to control the operation of the power supply to regulate the output DC voltage to said output voltage level. At least one portion of a control loop within the digital controller may he switched into the control loop in a first mode of operation and out of the control loop in a second mode of operation. A microcontroller emulates the operation of the at least one portion of the control loop during the second mode of operation.
An oscillator includes a plurality of varactor cells to receive a control signal to control a frequency of the oscillator. Each of the varactor cells includes a switch that includes a first terminal to receive the control signal and a second terminal such that the switch operates to control a capacitance of the varactor cell in response to a voltage between the first and second terminals. The oscillator includes a bias circuit to provide a different bias voltage to each second terminal and an amplifier that is coupled to the varactor cells to generate an oscillating signal.
H03J 3/18 - Accord sans déplacement d'élément réactif, p.ex. en faisant varier la perméabilité par tube à décharge ou dispositif à semi-conducteurs simulant une réactance variable
H03B 5/12 - Eléments déterminant la fréquence comportant des inductances ou des capacités localisées l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
H03L 7/099 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
40.
TELEVISION RECEIVER SUITABLE FOR MULTI-STANDARD OPERATION AND METHOD THEREFOR
A receiver (1100) includes a direct digital frequency synthesizer (130), a mixer (105), and a clock source (1110, 1130). The direct digital frequency synthesizer has an input terminal for receiving a first clock signal at a first frequency, and an output terminal for providing a digital local oscillator signal synchronously with the first clock signal. The mixer (105) has a first input terminal for receiving a radio frequency (RF) signal, a second input terminal coupled to the output terminal of the direct digital frequency synthesizer (130), and an output terminal for providing an IF signal having a spectrum centered about a selectable one of a plurality of center frequencies. The clock source (1110, 1130) has an output terminal for providing the first clock signal without using any harmonic frequency that overlaps the spectrum for any of the plurality of center frequencies.
H04B 15/06 - Réduction des perturbations parasites dues aux appareils électriques avec des moyens disposés sur ou à proximité de la source de perturbation la perturbation étant causée par des ondes essentiellement sinusoïdales, p.ex. dans un récepteur ou un enregistreur à bande magnétique par des oscillateurs locaux des récepteurs
H03J 1/00 - ACCORD DES CIRCUITS RÉSONNANTS; SÉLECTION DES CIRCUITS RÉSONNANTS - Détails des dispositions pour le réglage, l'entraînement, la signalisation ou la commande mécanique des circuits résonnants en général
41.
METHODS AND APPARATUS TO GENERATE SMALL FREQUENCY CHANGES
In one embodiment, the present invention includes an apparatus having a first capacitor coupled between a first node and a second node, a second capacitor coupled between the second node and a reference potential, and a third capacitor coupled between the second node and a switch, where the switch is controllable to couple the third capacitor to the second node. Using such an apparatus small changes in capacitance and correspondingly small changes in frequency may be effected. Other embodiments are directed to calibration of one or more capacitor banks.
H03J 1/00 - ACCORD DES CIRCUITS RÉSONNANTS; SÉLECTION DES CIRCUITS RÉSONNANTS - Détails des dispositions pour le réglage, l'entraînement, la signalisation ou la commande mécanique des circuits résonnants en général
In one embodiment, the present invention includes a delta-sigma modulator formed of a loop filter coupled to receive an incoming signal, and a quantizer coupled to the loop filter to receive an output of the loop filter and to generate a quantized output. The loop filter may have multiple integration stages and a transfer function constrained to maintain stability of the delta-sigma modulator regardless of an amplitude of the incoming signal. Methods directed to design of such a delta-sigma modulator are also described.
A low dropout voltage regulator (10) is provided, which outputs a regulated voltage (Vreg) in response to a reference signal (Vref ) ; the regulator (10) comprises a first reference circuit (12) to provide the reference signal (Vref) when the regulator (10) is in a stratup phase, and a second reference circuit (22) to supply the reference signal (Vref) after the stratup phase.
G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
G05F 1/46 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu
An apparatus includes a semiconductor package, a radio receiver and a processor. The radio receiver is located in the semiconductor package and includes at least one gain stage. The processor is located in the semiconductor package to execute stored instructions to control the gain stage(s).
A communication apparatus includes a radio frequency (RF) circuit configured to operate on an RF signal. The communication apparatus also includes a digital processing circuit and a buffer circuit having a first portion and a second portion. The digital processing circuit may operate in association with the RF circuit according to a time domain isolation technique. In addition, the digital processing circuit may perform a first task on received data and may alternately store a first set of results of the first task within the first buffer portion and a second set of results of the first task within the second buffer portion. The digital processing circuit may further perform a second task on the first set of results concurrently with storing the second set of results within the second buffer portion.
H04B 15/04 - Réduction des perturbations parasites dues aux appareils électriques avec des moyens disposés sur ou à proximité de la source de perturbation la perturbation étant causée par des ondes essentiellement sinusoïdales, p.ex. dans un récepteur ou un enregistreur à bande magnétique
In one embodiment, the present invention includes a method for receiving at a transceiver from a baseband processor digital control information that includes both event and schedule information, storing the digital control information in a storage of the transceiver, and operating the transceiver according to the event and schedule information.
The invention can utilize a switching power regulator and a non-switching power regulator in conjunction to provide regulated power to the digital logic. The digital logic and switching regulator may be deactivated during RF activity so that interference from both the digital circuitry and the switching regulator is significantly reduced. The state of the digital circuitry may be maintained during this standby period by using the non-switching power regulator to provide an as- required leakage current to the digital circuitry in order to maintain state. After the RF event (e.g. sending or receiving data) has concluded, the switching regulator may be activated and digital processing continued using the digital logic with no loss of continuity.
Embodiments of the present invention may provide for independent setting of jitter tolerance and jitter transfer levels, and reduced jitter generation of a data transmission device, such as a clock and data recovery (CDR) circuit or the like. An architecture may provide for reconfigurability of a circuit for use in various applications. The architecture may include a multi-loop structure, such as a tri-loop structure.
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p.ex. en utilisant une boucle verrouillée en phase
H03L 7/087 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie utilisant au moins deux détecteurs de phase ou un détecteur de fréquence et de phase dans la boucle
49.
TELEVISION RECEIVER WITH AUTOMATIC GAIN CONTROL (AGC)
A receiver (200) includes a processing path (240), a plurality of power detectors (251, 252), and an automatic gain control circuit (250). The processing path (240) has an input for receiving an input signal, and an output for providing an output signal. Each of the plurality of power detectors (251, 252) has an input coupled to a different node of the processing path (240), and an output. The automatic gain control circuit (250) has inputs coupled to respective outputs of each of the plurality of power detectors (251, 252), and a first output adapted to be coupled to a first controllable gain element (241) for controlling a gain thereof in response to the outputs of the plurality of power detectors (251, 252).
A method and apparatus is provided for use in an integrated circuit (60) or printed circuit board for reducing or minimizing interference. An inductance is formed using two or more inductors (10A, 10B) coupled together and configured such that current flows through the inductors (10A, 10B) in different directions, thus at least partially canceling magnetic fields. When designing a circuit, the configuration of the inductors(10A, 10B), as well as the relative positions of portions of the circuit, can be tweaked to provide optimal interference or noise control.
H01F 17/00 - Inductances fixes du type pour signaux
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01F 27/36 - Blindages ou écrans électriques ou magnétiques
H01F 27/34 - Moyens particuliers pour éviter ou réduire les effets électriques ou magnétiques indésirables, p.ex. pertes à vide, courants réactifs, harmoniques, oscillations, champs de fuite
51.
TECHNIQUES FOR PARTITIONING RADIOS IN WIRELESS COMMUNICATION SYSTEMS
A method and apparatus is provided for partitioning a radio (10, 20, 30, 40, 50, 60, 80) using a multi-chip module (12, 22, 32, 42, 52, 62, 82) to group some or all of the components of the radio in a single package. In one example, a radio uses a multi-chip module, including a chip carrier (14). Various components of the radio reside in integrated circuits that are mounted to the chip carrier (14). If desired, one or more antennas (22) can be integrated into the chip carrier (14).
H04B 1/38 - TRANSMISSION - Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission Émetteurs-récepteurs, c. à d. dispositifs dans lesquels l'émetteur et le récepteur forment un ensemble structural et dans lesquels au moins une partie est utilisée pour des fonctions d'émission et de réception
H01Q 1/24 - Supports; Moyens de montage par association structurale avec d'autres équipements ou objets avec appareil récepteur
An undervoltage detection circuit includes a first transistor and a second transistor coupled to a supply voltage node and arranged to form a current mirror. The undervoltage detection circuit also includes a first bipolar transistor and a second bipolar transistor. A collector of the first bipolar transistor is coupled to the first transistor, and an emitter of the first bipolar transistor is coupled to a reference voltage node. A collector of the second bipolar transistor is coupled to the second transistor and an emitter of the second bipolar transistor is coupled to the reference voltage node through a first resistor. The undervoltage detection circuit further includes a third transistor coupled through a second resistor to an input voltage node. An output signal indicative of an input voltage is derived from a voltage established at the collector of the second bipolar transistor.
G01R 31/36 - Dispositions pour le test, la mesure ou la surveillance de l’état électrique d’accumulateurs ou de batteries, p.ex. de la capacité ou de l’état de charge
G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
A system includes a digital circuit that may be clocked by a digital clock signal having an associated clock period. The system also includes a sample clock generation circuit coupled to a sampling circuit. The sample clock generation circuit may be configured to receive an input clock having a fixed phase relationship with respect to the digital clock signal. The sample clock generation circuit may also generate a sample clock having a first sampling edge corresponding to a first relative offset within the clock period and a subsequent sampling edge corresponding to a different relative offset within the clock period. The sampling circuit may be configured to sample a designated signal upon a first sampling instance corresponding to the first sampling edge and to sample the designated signal upon a subsequent sampling instance corresponding to the subsequent sampling edge.
In one embodiment, a power supply switching circuit may automatically provide power to a clock circuit from one of an auxiliary power supply and a main power supply, based on a voltage of the main power supply. To provide automatic switching, a switch circuit coupled between the power supplies and the clock circuit may be controlled by a voltage detector, in some embodiments.
Interchangeable high band low-noise-amplifiers (LNAs) and low band low-noise-amplifiers (LNAs) and related methods are disclosed that greatly enhance the efficiency of designing handsets for different combinations of frequency bands. The input signals to particular pins on a receiver or transceiver integrated circuit (IC) are swappable such that multiple frequency bands can be input to the same input pins thereby allowing for simplified system design. Efficient programmable techniques are also disclosed for controlling a swap mode within communication ICs. These interchangeable or band swappable input paths, for example, can be utilized to allow interchangeability between high band (PCS, DCS) and low band (GSM, E-GSM) inputs for cellular communications. In this way, for example, handset manufacturers can build a single printed circuit board (PCB) that can be utilized for cellular communications in the United States of America, where 850 MHz (GSM) and 1900 MHz (PCS) bands are utilized, and in Europe, wherein 900 MHz (E-GSM) and 1800 MHz (DCS) bands are utilized.
A communication apparatus including a radio frequency (RF) circuit coupled to a digital processing circuit and an interface circuit coupled to an authentication device. The RF circuit may be configured to operate on a radio frequency signal. A portion of the digital processing circuit may be disabled during an active mode of operation of the RF circuit. The interface circuit may be configured to buffer data communicated between the digital processing circuit and an authentication device during the active mode of operation of the RF circuit. In one embodiment, the interface circuit includes a memory and memory control logic to buffer data available for transmission to and/or received from the authentication device. In some embodiments, the digital processing circuit includes a processing unit configured to process authentication data received from the authentication device. In these and other embodiments, the authentication device may be a subscriber identity module (SIM).
A system includes a communication apparatus coupled to a test subsystem through a converter. The test subsystem may be configured to initiate an audio test of the communication apparatus and receive in response a set of audio test data at a predetermined constant data rate. The communication apparatus may be configured to enable output of audio test data during inactive periods of operation of an RF circuit of the communication apparatus and to disable output of audio test data during active periods of operation of the RF circuit. The converter may be configured to receive the set of audio test data from the communication apparatus and provide the set of audio test data to the test subsystem at the predetermined constant data rate during the active and the inactive periods of operation of the RF circuit.
An apparatus includes switches (126), a bank of capacitors (122) and an oscillator core (120). The oscillator core (120) is selectively coupled to the bank of capacitors (122) by the switches (126), and the oscillator core (120) provides a signal that has a frequency that is dependent on the selective coupling between the bank of capacitors (122) and the oscillator core (120). The apparatus also includes a circuit (300) that is adapted to change the coupling between the bank of capacitors (122) and the oscillator core (120) to change the frequency and impose a rate limit at which the frequency changes to avoid a significant glitch in the signal.
A method of operating a radio-frequency (RF) circuitry and a signal-processing circuitry in a mobile telephone apparatus includes at least partially disabling the signal-processing circuitry while transmitting or receiving signals. In one example, a processor is efficiently disabled by generating and servicing an interrupt of relatively high priority. One advantage of this example is that preexisting, legacy code can be maintained, while still achieving the desired objectives. The processor can be enabled by generating and servicing a second high priority interrupt.
In one embodiment, a local oscillator and mixer architecture may include a frequency divider (30) having I and Q channel master storage elements (32, 36) formed of devices of a first size, and I and Q channel slave storage elements (34, 38) formed of devices of a second size, where the second size is smaller than the first size. In such manner, power consumption may be reduced while reducing phase noise in signals provided from the frequency divider (30) to the corresponding mixer.
A method is disclosed for generating pulse width modulated pulse control signals for controlling switches in a switching power supply. First, a count value is determined of a master clock (5618) within a switching cycle of the power supply from beginning to end thereof. A separate state machine (3704) is provided for each edge in each of pulse control signals and each is operated to generate the associated edge as a function of the sum (5612) of a fixed reference count value from the beginning of the switching cycle and a determined count value when the sum is determined (5620) to equal the actual count value.
A digital controller (408, 412, 416) for controlling the operation of a DC-DC switching converter is disclosed. A digital feedback control system is provided for receiving an analog input voltage (406) representing the output of the switching converter and digitally processing the analog input voltage by comparing it to a reference voltage and then determining analog drive signals to control the operation of the switching converter (402) to provide a regulated output. The digital feedback control system (408, 412, 416) operates in accordance with predetermined operating parametrics. The digital feedback control system (408, 412, 416) also has monitoring inputs and control inputs. A microcontroller (442) monitors the operation of the digital feedback control system and is able to change the operating parametrics under certain predetermined conditions.
H02M 3/157 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation avec commande numérique
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
An output buffer circuit (100) drives multiple signal formats. The output buffer circuit reduces duplication of output bond pads on an integrated circuit die. The output buffer circuit reduces a need for including conversion buffers on system boards. A single integrated circuit including the output buffer circuit may meet a variety of applications. The output buffer achieves these results with a programmable output voltage swing and a programmable output common mode voltage. In some embodiments of the present invention, an integrated circuit includes at least one single-ended buffer (104) and at least one differential circuit (102) coupled to a pair of outputs (108, 110). One of the single-ended buffer and the differential circuit is selectively enabled to provide a signal to the outputs.
Mixing circuitry for quadrature processing in communication systems and related methods are disclosed. The weighted mixing circuitry allows for arbitrary dividers to be utilized in generating the mixing signals for quadrature processing and thereby provides a significant advantage over prior architectures where 90 degree offset I and Q mixing signals were needed for quadrature mixing.
H04L 27/36 - Circuits de modulation; Circuits émetteurs
H03C 3/40 - Modulation d'angle par conversion de modulation d'amplitude en modulation d'angle utilisant deux voies de signaux dont les sorties ont une différence de phase déterminée et l'une au moins des sorties étant modulée en amplitude
65.
RATIOMETRIC TRANSMIT PATH ARCHITECTURE FOR COMMUNICATION SYSTEMS
A ratiometric transmit path architecture for communication systems and related methods are disclosed. This ratiometric transmit path architecture utilizes a single local oscillator signal and dividers to provide mixing signals for intermediate frequency (IF) mixing circuitry and feedback mixing circuitry, thereby eliminating the need for separate IF and radio frequency (RF) voltage controlled oscillators (VCOs) in prior solutions.
A method of operating a radio-frequency (RF) circuitry and a signal-processing circuitry in a mobile telephone apparatus includes at least partially disabling the signal-processing circuitry while transmitting or receiving signals. In one example, a processor is efficiently disabled by generating and servicing an interrupt of relatively high priority. One advantage of this example is that preexisting, legacy code can be maintained, while still achieving the desired objectives. The processor can be enabled by generating and servicing a second high priority interrupt.
An integrated low-IF (low intermediate frequency) terrestrial broadcast receiver and associated method are disclosed that provide an advantageous and cost-efficient solution. The integrated receiver includes a mixer, local oscillator generation circuitry, low-IF conversion circuitry, and DSP circuitry. And the integrated receiver is particularly suited for small, portable devices and the reception of terrestrial audio broadcasts, such as FM and AM terrestrial audio broadcast, in such portable devices.
A ratiometric clock system for an integrated receiver and associated method are disclosed that provide an advantageous solution for combining digital signal processing (DSP) circuitry on the same integrated circuit as mixer and local oscillator (LO) generation circuitry. The generation circuitry generates an oscillation signal that is passed through a first divider to generate mixing signals for the mixer and that is passed through a second divider to generate a digital clock signal that is utilized by the DSP circuitry. This digital clock signal can be utilized by integrated analog-to-digital conversion circuitry, as well.
A noise cancellation signal is generated for a fractional-N phase-locked loop (200). A divide value is provided to a first delta sigma modulator circuit (203), which generates a divide control signal to control a divide value of a feedback divider (208) in the phase-locked loop. An error term (e) is generated that is indicative of a difference between the generated divide control signal and the divide value supplied to the first delta sigma modulator circuit. The error term is integrated in an integrator (320) to generate an integrated error term (x), where xk+1=xk+ek ; and a phase error correction circuit (209) utilizes the error term ek and the integrated error term xk to generate the phase error cancellation signal.
H03L 7/197 - Synthèse de fréquence indirecte, c. à d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle une différence de temps étant utilisée pour verrouiller la boucle, le compteur comptant entre des nombres variables dans le temps ou le diviseur de fréquence divisant par un facteur variable dans le temps, p.ex. pour obtenir une division de fréquence
70.
COMMUNICATION APPARATUS INCLUDING DUAL TIMER UNITS
A communication apparatus includes a radio frequency circuit that operates on a radio frequency signal and a digital processing circuit coupled to the radio frequency circuit. The digital processing circuit includes a first timing circuit that provides timed signals to control timing of system operations during an active mode of operation of the digital processing circuit, and a second timing circuit that provides timing signals to control timing of system operations during an active mode of operation of the radio frequency circuit. In one particular embodiment, at least a portion of the first timing circuit is disabled when the radio frequency circuit is active (receiving and/or transmitting).
H04B 15/04 - Réduction des perturbations parasites dues aux appareils électriques avec des moyens disposés sur ou à proximité de la source de perturbation la perturbation étant causée par des ondes essentiellement sinusoïdales, p.ex. dans un récepteur ou un enregistreur à bande magnétique
71.
ETHERNET CONTROLLER WITH EXCESS ON-BOARD FLASH FOR MICROCONTROLLER INTERFACE
A single chip network controller for interfacing (104) between a physical network (106) and a processing system on the media side of the network controller. The network controller includes a physical layer (106) for receiving data for transmission to the network and encoding the received data for transmission thereto and for receiving data from the network, and for receiving data from the network and coding the received data. A media layer is provided for interfacing with the processing system for receiving data from the processing system for interface with the physical layer (106) for encoding and transmission thereof and for receiving decoded data from the physical layer and providing access thereto by the processing system. An on-chip non-volatile memory is provided having a first portion associated with configuration information for configuring the operation of the physical layer (106) and the media layer, and a second portion thereof that is accessible by the processing system on the media side of the network controller (104). A memory interface allows the processing system to interface with the second portion of the memory, such that processing system has an expanded memory capability.
H04L 12/66 - Dispositions pour la connexion entre des réseaux ayant différents types de systèmes de commutation, p.ex. passerelles
H04J 3/16 - Systèmes multiplex à division de temps dans lesquels le temps attribué à chacun des canaux au cours d'un cycle de transmission est variable, p.ex. pour tenir compte de la complexité variable des signaux, pour adapter le nombre de canaux transmis
A microcontroller unit (MCU) is disclosed with a stand-alone Real Time Clock (RTC). The MCU includes a processing circuit for receiving digital information and processing said received digital information. A primary clock circuit provides the timing for the processing circuit. A power control circuit controls the power to the processing circuit and the primary clock circuit to control the operation thereof to operate in at least a full power mode drawing a full power level from a supply voltage input and a reduced power mode drawing less than the full power level from the supply voltage input. A stand-alone RTC circuit is also provided, the standalone RTC circuit including an RTC clock circuit operating independent of the primary clock circuit. A timer clocked by the RTC clock circuit is operable to increment a stored time value for output therefrom, the RTC clock circuit having a defined time base. An input/output (I/O) device provides access by the processing circuit to the results output by the timer. A power management circuitry manages the power to the stand-alone RTC circuit, such that the RTC clock circuit, the timer, and the I/O device operate regardless of the power mode of operation of the processing circuitry and the primary clock circuit.
A circuit package includes first and second units containing functional circuitry. At least one RF isolation link interconnects the first and second units and provides voltage isolation between the first and second units. The RF isolation link provides data between the first unit and the second unit using an RF carrier signal that sweeps between a first frequency and a second frequency.
A metal mesh structure for use in an integrated circuit is described. In one embodiment, a semiconductor integrated circuit includes a first region including, for example, a device layer having one or more active semiconductor devices. The circuit also includes a second region, which may include a metalization layer including circuit wires. The circuit further includes a layer of metal mesh interposed between the first and second regions, and which may be implemented on at least a portion of another metalization layer.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
brevets
