A technique for performing ray tracing operations is provided, The technique includes, in response to detecting that a threshold number of traversal stage work-items of a wavefront have terminated, increasing intersection test parallelization for non-terminated work-items..
A technique for performing ray tracing operations is provided. The technique includes, in response to detecting that a threshold number of traversal stage work-items of a wavefront have terminated, increasing intersection test parallelization for non-terminated work-items.
A first frame of a video stream is obtained. The first frame is defined by a plurality of pixels associated with a set of color data. A determination is made that a pixel of the plurality of pixels comprises high-frequency information. Responsive to the determination that the pixel comprises high-frequency information, a pixel lock is generated for the pixel such that color data associated with the pixel is maintained during a color accumulation process for at least one of the first frame or a second frame of the video stream that is subsequent to the first frame.
A first frame of a video stream rendered at a first resolution is obtained. A second frame of the video stream upscaled to a second higher resolution is also obtained. The first plurality of pixels is upscaled to the second resolution. The upsampling generates upsampled color data for the upsampled first plurality of pixels. The upsampled color data is accumulated with a second set of color data associated with a second plurality of pixels defining the second frame to generate final color data for the upsampled first plurality of pixels. Color data of the second set of color data associated with a pixel lock contributes more to the final color data than corresponding color data of the upsampled color data. The upsampled first plurality of pixels is stored with the final color data as an upscaled frame representing the first frame at the second resolution.
A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
G09G 5/00 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation
G09G 5/36 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation caractérisés par l'affichage de dessins graphiques individuels en utilisant une mémoire à mappage binaire
6.
VIDEO TIMING FOR DISPLAY SYSTEMS WITH VARIABLE REFRESH RATES
A display system supports variable refresh rates that include a plurality of refresh rates. A source such as a graphics processing unit (GPU) provides frames to the display system at a selected one of the refresh rates. The refresh rates are factored into a corresponding plurality of prime factors. A plurality of numbers of lines per frame in frames provided at the plurality of refresh rates is determined based on one or more ratios of the plurality of refresh rates, the plurality of prime factors, and a line rate for providing frames to the display system at the plurality of refresh rates. The source then selectively provides frames to the display system at one refresh rate of the plurality of refresh rates using the same line rate regardless of which refresh rate is chosen. Furthermore, the number of lines per frame is an integer for frames provided at the refresh rates.
G09G 5/00 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation
7.
TECHNIQUE FOR EXTENDED IDLE DURATION FOR DISPLAY TO IMPROVE POWER CONSUMPTION
A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.
G06F 1/3234 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise
G06F 1/3209 - Surveillance d’une activité à distance, p.ex. au travers de lignes téléphoniques ou de connexions réseau
A memory package includes first, second, third, and fourth channels arranged consecutively in a clockwise direction on the memory package, each of the first, second, third, and fourth channels having access circuitry and memory arrays. In a first mode, the first channel controls access to the memory arrays in the second channel and the fourth channel controls access to the memory arrays in the third channel.
A memory package includes first, second, third, and fourth channels arranged consecutively in a clockwise direction on the memory package, each of the first, second, third, and fourth channels having access circuitry and memory arrays. In a first mode, the first channel controls access to the memory arrays in the second channel and the fourth channel controls access to the memory arrays in the third channel.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
10.
QUANTIFYING THE HUMAN-LIKENESS OF ARTIFICIALLY INTELLIGENT AGENTS USING STATISTICAL METHODS AND TECHNIQUES
An apparatus includes a processor configured to determine a first distribution associated with an artificial agent based on behavior associated with the artificial agent and a second distribution based on behavior of a user. The processor is further configured to generate a human-likeness similarity measurement by comparing the first distribution to the second distribution and modify the behavior of the artificial agent in response to the similarity measurement failing to satisfy a similarity threshold.
An apparatus includes a processor configured to determine a first distribution associated with an artificial agent based on behavior associated with the artificial agent and a second distribution based on behavior of a user. The processor is further configured to generate a human-likeness similarity measurement by comparing the first distribution to the second distribution and modify the behavior of the artificial agent in response to the similarity measurement failing to satisfy a similarity threshold.
There are many instances where a standard dynamic range (“SDR”) overlay is displayed over high dynamic range (“HDR”) content on HDR displays. Because the overlay is SDR, the maximum brightness of the overlay is much lower than the maximum brightness of the HDR content, which can lead to the SDR elements being obscured if those elements have at least some transparency. The present disclosure provides techniques including modifying the luminance of either or both of the HDR and SDR content when an SDR layer with some transparency is displayed over HDR content. A variety of techniques are provided. In one example, a fixed adjustment is applied to pixels of one or both of the SDR layer and the HDR layer. The fixed adjustment comprises decreasing the luminance of the HDR layer and/or increasing the luminance of the SDR layer. In another example, a variable adjustment is applied.
H04N 23/741 - Circuits de compensation de la variation de luminosité dans la scène en augmentant la plage dynamique de l'image par rapport à la plage dynamique des capteurs d'image électroniques
13.
Arbitration Allocating Requests During Backpressure
An arbitration system receives requests to access a destination during an arbitration window that spans multiple processor clock cycles. During each clock cycle, the destination is monitored to determine whether the destination is suffering from backpressure by receiving more requests than the destination is able to accommodate during the clock cycle. In response to detecting backpressure, a masking index value assigned to a requesting source is incremented, which limits an amount of requests from the source that will be granted destination access during a subsequent arbitration window. Alternatively, in response to detecting an absence of backpressure during an arbitration window, the masking index value is decremented, which increases the amount of requests from the source that will be granted destination access during a subsequent arbitration window. This arbitration process continues for successive arbitration windows, oscillating between incrementing and decrementing the masking index value during the successive arbitration windows.
G06F 13/372 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès décentralisée utilisant une priorité dépendant du temps, p.ex. des compteurs de temps individuellement chargés ou des tranches de temps
G06F 13/364 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès centralisée utilisant des signaux indépendants de demande ou d'autorisation, p.ex. utilisant des lignes séparées de demande et d'autorisation
G06F 13/366 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès centralisée utilisant un arbitre d'interrogation centralisé
Restricting peripheral device protocols in confidential compute architectures, the method including: receiving a first address translation request from a peripheral device supporting a first protocol, wherein the first protocol supports cache coherency between the peripheral device and a processor cache; determining that a confidential compute architecture is enabled; and providing, in response to the first address translation request, a response including an indication to the peripheral device to not use the first protocol.
Systems, apparatuses, and methods for implementing a safety monitor framework for a safety-critical inference application are disclosed. A system includes a safety-critical inference application, a safety monitor, and an inference accelerator engine. The safety monitor receives an input image, test data, and a neural network specification from the safety-critical inference application. The safety monitor generates a modified image by adding additional objects outside of the input image. The safety monitor provides the modified image and neural network specification to the inference accelerator engine which processes the modified image and provides outputs to the safety monitor. The safety monitor determines the likelihood of erroneous processing of the original input image by comparing the outputs for the additional objects with a known good result. The safety monitor complements the overall fault coverage of the inference accelerator engine and covers faults only observable at the network level.
G06V 10/776 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant l’intégration et la réduction de données, p.ex. analyse en composantes principales [PCA] ou analyse en composantes indépendantes [ ICA] ou cartes auto-organisatrices [SOM]; Séparation aveugle de source Évaluation des performances
G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
G06V 10/764 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant la classification, p.ex. des objets vidéo
G06V 10/98 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos Évaluation de la qualité des motifs acquis
Cascading execution of atomic operations, including: receiving a request for each thread of a plurality of threads to perform an atomic operation, wherein the plurality of threads comprises a plurality of thread subsets each corresponding to a local memory, wherein the local memory for a thread subset is accessible by the thread subset and inaccessible to a remainder of threads in the plurality of threads; generating a plurality of intermediate results by performing, by each thread subset, the atomic operation in the local memory corresponding to the thread subset; and generating a result for the request by aggregating the plurality of intermediate results in a shared memory accessible to all threads in the plurality of threads.
Restricting peripheral device protocols in confidential compute architectures, the method including: receiving a first address translation request from a peripheral device supporting a first protocol, wherein the first protocol supports cache coherency between the peripheral device and a processor cache; determining that a confidential compute architecture is enabled; and providing, in response to the first address translation request, a response including an indication to the peripheral device to not use the first protocol.
A processing system [100] divides successive dispatches [135] of work items into portions [145]. The successive dispatches are separated from each other by barriers [202], [204], each barrier indicating that the work items of the previous dispatch must complete execution before work items of a subsequent dispatch can begin execution. In some embodiments, the processing system interleaves execution of portions of a first dispatch with portions of subsequent dispatches that consume data produced by the first dispatch. The processing system thereby reduces the amount of data written to the local cache [120] by a producer dispatch while preserving data locality for a subsequent consumer (or consumer/producer) dispatch and facilitating processing efficiency.
A multi-die integrated circuit [102] uses an on-chip test distribution module to distribute test data [105] to different dies, such as processor chiplets 104, 106,108, 110]. The test distribution module receives test input data [220] from an external source [115] via one or more integrated circuit pins [112] and distributes the test input data to the different dies, such that the different dies are able to concurrently apply the test data to one or more circuits. Based on application of the test input data the different dies concurrently generate corresponding test results [325] that are used to identify and address design or operation errors at the dies.
G01R 31/319 - Matériel de test, c. à d. circuits de traitement de signaux de sortie
G01R 31/3193 - Matériel de test, c. à d. circuits de traitement de signaux de sortie avec une comparaison entre la réponse effective et la réponse connue en l'absence d'erreur
20.
ALLOCATING PERIPHERAL COMPONENT INTERFACE EXPRESS (PCIE) STREAMS IN A CONFIGURABLE MULTIPORT PCIE CONTROLLER
Allocating peripheral component interface express (PCIe) streams in a configurable multiport PCIe controller, including: detecting, by a PCIe controller, a link by a first PCIe device; and allocating, for the link between the PCIe controller and the first PCIe device, a first one or more PCIe streams from a pool of PCIe streams.
Systems, apparatuses, and methods for implementing a discard engine in a graphics pipeline are disclosed. A system includes a graphics pipeline with a geometry engine launching shaders that generate attribute data for vertices of each primitive of a set of primitives. The attribute data is consumed by pixel shaders, with each pixel shader generating a deallocation message when the pixel shader no longer needs the attribute data. A discard engine gathers deallocations from multiple pixel shaders and determines when the attribute data is no longer needed. Once a block of attributes has been consumed by all potential pixel shader consumers, the discard engine deallocates the given block of attributes. The discard engine sends a discard command to the caches so that the attribute data can be invalidated and not written back to memory.
A virtual function (VF) [111] of a virtual machine [110] is enabled to directly reset a processing portion [106] of a processing unit [104]. The VF initiates the reset of the processing portion directly and a host driver [116] associated with the processing unit is bypassed during the reset process. By allowing for a direct reset of the processing portion, a processing system [100] reduces the overhead associated with the reset process, enhances system security, and improves overall VM and hardware isolation at the processing system.
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 1/24 - Moyens pour la remise à l'état initial
23.
ALLOCATING PERIPHERAL COMPONENT INTERFACE EXPRESS (PCIE) STREAMS IN A CONFIGURABLE MULTIPORT PCIE CONTROLLER
Allocating peripheral component interface express (PCIe) streams in a configurable multiport PCIe controller, including: detecting, by a PCIe controller, a link by a first PCIe device; and allocating, for the link between the PCIe controller and the first PCIe device, a first one or more PCIe streams from a pool of PCIe streams.
The present invention relates to a surgical method of treating a patient. The method involves cutting the patient’s skin and abdominal wall, dissecting an area of the patient’s intestine, cutting the patient’s intestine so as to form an intestinal wall of a reservoir, implanting at least a pump as part of a flow control device so as to permanently reside inside the patient’s body and to act on said intestinal wall so as to reduce the reservoir’s volume in order to empty intestinal contents from the reservoir to outside the patient’s body, and thereafter, permanently closing the abdominal wall and skin.
A61N 1/36 - Application de courants électriques par électrodes de contact courants alternatifs ou intermittents pour stimuler, p.ex. stimulateurs cardiaques
A61F 2/00 - Filtres implantables dans les vaisseaux sanguins; Prothèses, c.-à-d. éléments de substitution ou de remplacement pour des parties du corps; Appareils pour les assujettir au corps; Dispositifs maintenant le passage ou évitant l'affaissement de structures corporelles tubulaires, p.ex. stents
A61N 1/05 - Electrodes à implanter ou à introduire dans le corps, p.ex. électrode cardiaque
An approach is provided for a gaming overlay application to provide automatic in-game subtitles and/or closed captions for video game applications. The overlay application accesses an audio stream and a video stream generated by an executing game application. The overlay application processes the audio stream through a text conversion engine to generate at least one subtitle. The overlay application determines a display position to associate with the at least one subtitle. The overlay application generates a subtitle overlay comprising the at least one subtitle located at the associated display position. The overlay application causes a portion of the video stream to be displayed with the subtitle overlay.
A63F 13/53 - Commande des signaux de sortie en fonction de la progression du jeu incluant des informations visuelles supplémentaires fournies à la scène de jeu, p.ex. en surimpression pour simuler un affichage tête haute [HUD] ou pour afficher une visée laser dans un jeu de tir
A63F 13/87 - Communiquer avec d’autres joueurs, p.ex. par courrier électronique ou messagerie instantanée
G10L 17/06 - Techniques de prise de décision; Stratégies d’alignement de motifs
G10L 17/26 - Reconnaissance de caractéristiques spéciales de voix, p.ex. pour utilisation dans les détecteurs de mensonge; Reconnaissance des voix d’animaux
Systems, apparatuses, and methods for performing color channel correlation detection are disclosed. A compression engine performs a color channel transform on an original set of pixel data to generate a channel transformed set of pixel data. An analysis unit determines whether to compress the channel transformed set of pixel data or the original set of pixel data based on performing a comparison of the two sets of pixel data. In one scenario, the channel transformed set of pixel data is generated by calculating the difference between a first pixel component and a second pixel component for each pixel of the set of pixel data. The difference is then compared to the original first pixel component for each pixel. If the difference is less than or equal to the original for a threshold number of pixels, then the analysis unit decides to apply the color channel transform prior to compression.
A processor for optimizing partial writes to compressed blocks is configured to identify that a write request targets less than an entirety of a compressed block of pixel data, identify, based on a compression key, a compressed segment of the compressed block of pixel data that includes a target of the write request, and decompress, responsive to the write request, only the identified compressed segment of the compressed block of pixel data.
An electronic device includes a memory and a processor. The processor receives a platform management profile that includes information defining one or more platform management policies, a given platform management policy among the one or more platform management policies including a provided input from a specified hardware or software sensor and/or a provided output action. The processor uses the given platform management policy for controlling operating states of elements in the electronic device.
A system and method for efficiently processing security service requests are described. In various implementations, an integrated circuit includes at least one or more processors with a dedicated security processor and on-chip memory that has a higher security level than off-chip memory. During the processing of security service requests, the security processor receives multiple commands with each including a cryptographic function. The security processor identifies one or more issue groups of commands based at least upon data dependencies and shared source data. When the security processor determines an issued command is in a given issue group, the security processor issues a next command from remaining commands in the given issue group. Otherwise, the security processor issues an immediately next in-order command after the issued command.
G06F 21/72 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits de cryptographie
30.
ON-CHIP DISTRIBUTION OF TEST DATA FOR MULTIPLE DIES
A multi-die integrated circuit uses an on-chip test distribution module to distribute test data to different dies, such as processor chiplets. The test distribution module receives test input data from an external source via one or more integrated circuit pins and distributes the test input data to the different dies, such that the different dies are able to concurrently apply the test data to one or more circuits. Based on application of the test input data the different dies concurrently generate corresponding test results that are used to identify and address design or operation errors at the dies.
A virtual function (VF) of a virtual machine is enabled to directly reset a processing portion of a processing unit. The VF initiates the reset of the processing portion directly and a host driver associated with the processing unit is bypassed during the reset process. By allowing for a direct reset of the processing portion, a processing system reduces the overhead associated with the reset process, enhances system security, and improves overall VM and hardware isolation at the processing system.
G06F 1/24 - Moyens pour la remise à l'état initial
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p.ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
A system and method for efficiently performing a bootup operation are described. In various implementations, an integrated circuit includes at least one or more processors and on-chip memory. The on-chip memory has a higher security level than off-chip memory. One of the one or more processors is designated as a security processor. During the processing of the multiple boot steps of a bootup operation, the security processor receives one or more out of band (OOB) events that are not included in the bootup operation. The security processor initializes both an OOB queue and a main boot queue in the on-chip memory. The security processor stores boot steps of the bootup operation in the main boot queue and stores received OOB events in the OOB queue. The security processor executes at least one OOB event prior to completing the bootup operation.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 21/54 - Contrôle des usagers, programmes ou dispositifs de préservation de l’intégrité des plates-formes, p.ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p.ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par ajout de routines ou d’objets de sécurité aux programmes
G06F 11/36 - Prévention d'erreurs en effectuant des tests ou par débogage de logiciel
An approach is provided for a gaming overlay application to provide automatic in-game subtitles and/or closed captions for video game applications. The overlay application accesses an audio stream and a video stream generated by an executing game application. The overlay application processes the audio stream through a text conversion engine to generate at least one subtitle. The overlay application determines a display position to associate with the at least one subtitle. The overlay application generates a subtitle overlay comprising the at least one subtitle located at the associated display position. The overlay application causes a portion of the video stream to be displayed with the subtitle overlay.
A apparatus includes a reference signal generator, a droop detection circuit, a digital frequency-locked loop (DFLL), and a DFLL control circuit. The reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value. The droop detection circuit converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply voltage below a designated value relative to the analog signal, produces a droop detection signal. The DFLL provides a clock signal for synchronizing circuitry within a domain of the monitored supply voltage. The DFLL control circuit, responsive to receiving the droop detection signal, causes the DFLL to slow the clock signal.
H03L 7/081 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase avec un déphaseur commandé additionnel
H03L 7/24 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence directement appliqué au générateur
G01R 19/25 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant une méthode de mesure numérique
G01R 23/16 - Analyse de spectre; Analyse de Fourier
One or more components of a computing device are run by default in a boost mode state. The one or more components continue to run in the boost mode state until the boost mode state is no longer sustainable, e.g., due to power consumption of the one or more components or temperature of the one or more components. The one or more components are switched to a reduced power state (e.g., a non-boost mode state) in response to the boost mode state no longer being sustainable. When operating the one or more components in the boost mode state again becomes sustainable due to power consumption or temperature of the one or more components, the one or more components are returned to the default boost mode state.
G06F 1/3234 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise
G06F 9/50 - Allocation de ressources, p.ex. de l'unité centrale de traitement [UCT]
G06F 1/3206 - Surveillance d’événements, de dispositifs ou de paramètres initiant un changement de mode d’alimentation
Systems, apparatuses, and methods for updating and optimizing task scheduling policies are disclosed. A new policy is obtained and updated at runtime by a client based on a server analyzing a wide spectrum of telemetry data on a relatively long time scale. Instead of only looking at the telemetry data from the client's execution of tasks for the previous frame, the server analyzes the execution times of tasks for multiple previous frames so as to determine a more optimal policy for subsequent frames. This mechanism enables making a more informed task scheduling policy decision as well as customizing the policy per application, game, and user without requiring a driver update. Also, this mechanism facilitates improved load balancing across the various processing engines, each of which has their own task queues. The improved load balancing is achieved by analyzing the telemetry data including resource utilization statistics for the different processing engines.
Cascading execution of atomic operations, including: receiving a request for each thread of a plurality of threads to perform an atomic operation, wherein the plurality of threads comprises a plurality of thread subsets each corresponding to a local memory, wherein the local memory for a thread subset is accessible by the thread subset and inaccessible to a remainder of threads in the plurality of threads; generating a plurality of intermediate results by performing, by each thread subset, the atomic operation in the local memory corresponding to the thread subset; and generating a result for the request by aggregating the plurality of intermediate results in a shared memory accessible to all threads in the plurality of threads.
G06F 12/084 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec mémoire cache partagée
G06F 12/0895 - Mémoires cache caractérisées par leur organisation ou leur structure de parties de mémoires cache, p.ex. répertoire ou matrice d’étiquettes
G06F 12/0811 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec hiérarchies de mémoires cache multi-niveaux
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
Dynamic adjustment of power modes including: detecting an application identified in an application power policy; limiting an application power consumption of a computing component based on the application power policy; monitoring power consumption of a computing component; and selecting a power mode based on the monitored power consumption of the computing component and a power consumption threshold for each of a plurality of power modes.
G06F 1/3234 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise
G06F 1/3215 - Surveillance de dispositifs périphériques
A disclosed technique includes allocating a first set of resource slots for a first execution instance of a pipeline shader program; correlating the first set of resource slots with graphics pipeline passes; and on a second execution instance of the pipeline shader program, assigning resource slots, from the first set of resource slots, to the graphics pipeline passes, based on the correlating.
A semiconductor device includes a power delivery device die stack including a plurality of vertically arranged power delivery device dies. The plurality of power delivery device dies including at least a first power delivery device die and a second power delivery device die electrically connected to the first power delivery device die. The semiconductor device includes at least one external interconnect for providing a power input to the power delivery device die stack and at least one external interconnect for supplying a power output from the power delivery device die stack.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 25/10 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs ayant des conteneurs séparés
41.
THROUGH-SILICON VIA LAYOUT FOR MULTI-DIE INTEGRATED CIRCUITS
Integrated circuits and integrated circuit dies include TSVs laid out in symmetrical patterns. Because of the symmetrical arrangement of the TSVs and associated routing patterns, an integrated circuit is able to support operation of multiple similar dies that are placed in different positions in the integrated circuit. This in turn simplifies the design and production of the multiple similar dies, thus reducing development and manufacturing costs for the corresponding integrated circuits.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
A processing system divides successive dispatches of work items into portions. The successive dispatches are separated from each other by barriers, each barrier indicating that the work items of the previous dispatch must complete execution before work items of a subsequent dispatch can begin execution. In some embodiments, the processing system interleaves execution of portions of a first dispatch with portions of subsequent dispatches that consume data produced by the first dispatch. The processing system thereby reduces the amount of data written to the local cache by a producer dispatch while preserving data locality for a subsequent consumer (or consumer/producer) dispatch and facilitating processing efficiency.
An electronic device includes an accelerated processing unit (APU) and multiple elements. The APU performs operations for a platform boost and throttle (PBT) controller. For the operations, the APU receives a platform electrical power limit, the platform electrical power limit being a limit on a total electrical power allowed to be consumed by a group of the elements at a given time. The APU then determines a present platform electrical power consumption. The APU next adjusts one or more operating parameters for specified elements from among the group of elements to control electrical power consumption by the specified elements based on a relationship between the present platform electrical power consumption and the platform electrical power limit.
One or more components of a computing device are run by default in a boost mode state. The one or more components continue to run in the boost mode state until the boost mode state is no longer sustainable, e.g., due to power consumption of the one or more components or temperature of the one or more components. The one or more components are switched to a reduced power state (e.g., a non-boost mode state) in response to the boost mode state no longer being sustainable. When operating the one or more components in the boost mode state again becomes sustainable due to power consumption or temperature of the one or more components, the one or more components are returned to the default boost mode state.
G06F 1/3296 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par diminution de la tension d’alimentation ou de la tension de fonctionnement
Systems, apparatuses, and methods for implementing a discard engine in a graphics pipeline are disclosed. A system includes a graphics pipeline with a geometry engine launching shaders that generate attribute data for vertices of each primitive of a set of primitives. The attribute data is consumed by pixel shaders, with each pixel shader generating a deallocation message when the pixel shader no longer needs the attribute data. A discard engine gathers deallocations from multiple pixel shaders and determines when the attribute data is no longer needed. Once a block of attributes has been consumed by all potential pixel shader consumers, the discard engine deallocates the given block of attributes. The discard engine sends a discard command to the caches so that the attribute data can be invalidated and not written back to memory.
Systems, apparatuses, and methods for implementing gradient adaptive ringing control for image resampling are disclosed. A blending alpha calculation circuit generates a blending alpha value for a set of input pixels based on a normalized gradient calculated for the set of input pixels. The normalized gradient is a low-pass filtered gradient of the set of input pixels divided by a maximum gradient for the set of input pixels. The normalized gradient is passed through a mapping function so as to generate the blending alpha value. The mapping function is pre-tuned based on filter coefficients, video content type, pixel format, and so on. An interpolated pixel is generated for the set of input pixels by blending ringing free and ringing prone interpolation coefficients, or by blending results between ringing free and ringing prone interpolation filters, with the blending weight for each filter based on the blending alpha value.
G06V 10/60 - Extraction de caractéristiques d’images ou de vidéos relative aux propriétés luminescentes, p.ex. utilisant un modèle de réflectance ou d’éclairage
47.
PROCESSING UNIT RESET BASED ON GROUP CONFIGURATION
A processing system selects a reset sequence based on a sideband connected configuration of a plurality of processing units. The processing system identifies whether the plurality of processing units is in the sideband connected configuration, so that the plurality of processing units works together on assigned operations. Based on the identification, the processing system selects and executes one of a plurality of available reset sequences. The processing system is thus able to tailor the executed reset sequence for the configuration of the plurality of processing units, thereby reducing the number of overall system resets and improving processing efficiency.
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
A system and method for efficiently measuring on-die power supply voltage are described. In various implementations, an integrated circuit includes at least one or more processors and on-chip memory. The on-chip memory has a higher security level than off-chip memory. One of the one or more processors is designated as a security processor. During the processing of the multiple boot steps of a bootup operation, the security processor initializes a message queue in on-chip memory. The security processor also loads multiple modules from off-chip memory into the on-chip memory. The processor executes the multiple loaded modules in an order based on using the message queue to implement inter-module communication among the plurality of boot modules. The security processor transfers requested data between modules using messages from the modules and data storage of the message queue. The modules are completed without reloading any modules from off-chip memory.
Methods and devices are provided for encoding a video stream which comprise encoding a plurality of frames of video acquired from different points of view, generating statistical values for the frames of video determined from values of pixels of the frames, generating, for each of the plurality of frames, a perceptual hash value based on statistical values of the frame and encoding a current frame comprising video acquired from a corresponding one of the different points of view using a previously encoded reference frame based on a similarity of perceptual hashes of the current frame and the previously encoded reference frame.
H04N 19/136 - Caractéristiques ou propriétés du signal vidéo entrant
H04N 19/172 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c. à d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p.ex. un objet la zone étant une image, une trame ou un champ
H04N 19/105 - Sélection de l’unité de référence pour la prédiction dans un mode de codage ou de prédiction choisi, p.ex. choix adaptatif de la position et du nombre de pixels utilisés pour la prédiction
H04N 19/167 - Position dans une image vidéo, p.ex. région d'intérêt [ROI]
H04N 19/423 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques - caractérisés par les détails de mise en œuvre ou le matériel spécialement adapté à la compression ou à la décompression vidéo, p.ex. la mise en œuvre de logiciels spécialisés caractérisés par les dispositions des mémoires
H04N 19/142 - Détection de coupure ou de changement de scène
50.
VARIABLE DISPATCH WALK FOR SUCCESSIVE CACHE ACCESSES
A processing system [100] is configured to translate a first cache access pattern of a dispatch [135] of work items to a cache access pattern [145] that facilitates consumption of data stored at a cache [120] of a parallel processing unit [110] by a subsequent access before the data is evicted to a more remote level of a memory hierarchy. For consecutive cache accesses having read-after-read data locality, in some embodiments the processing system translates the first cache access pattern to a space-filling curve [506]. In some embodiments, for consecutive accesses having read-after-write data locality, the processing system translates a first typewriter cache access pattern that proceeds in ascending order for a first access [512] to a reverse typewriter cache access pattern that proceeds in descending order for a subsequent cache access [514]. By translating the cache access pattern based on data locality, the processing system increases the hit rate of the cache.
Techniques are described for adaptive device power management. The hardware computing unit detects a launch of an application by the operating system (OS) to be executed on the hardware computing unit. The hardware computing unit identifies the launched application and determines whether a hardware profile exists that is associated with the application. The hardware profile includes one or more hardware parameters that yield the optimal performance for power consumption by the hardware computing unit when executing the launched application. Based on determining that the hardware profile exists, the power policy of the OS is updated for the launched application and a driver updates the power state of the the hardware computing unit based on the new power policy.
A apparatus includes a reference signal generator, a droop detection circuit, a digital frequency-locked loop (DFLL), and a DFLL control circuit. The reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value. The droop detection circuit converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply voltage below a designated value relative to the analog signal, produces a droop detection signal. The DFLL provides a clock signal for synchronizing circuitry within a domain of the monitored supply voltage. The DFLL control circuit, responsive to receiving the droop detection signal, causes the DFLL to slow the clock signal.
H03L 7/08 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase
H03L 7/085 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie
A processing unit performs a dispatch walk of a set of thread groups based on a programmable access pattern. The access pattern is stored at a table that is programmed with the access pattern based upon a specified command. By using the command to program the table with different access patterns, the dispatch order of the set of thread groups is adapted to better suit the processing of different data sets, thereby reducing power consumption at the processing unit, and improving overall processing efficiency.
A processing system is configured to translate a first cache access pattern of a dispatch of work items to a cache access pattern that facilitates consumption of data stored at a cache of a parallel processing unit by a subsequent access before the data is evicted to a more remote level of the memory hierarchy. For consecutive cache accesses having read-after-read data locality, in some embodiments the processing system translates the first cache access pattern to a space-filling curve. In some embodiments, for consecutive accesses having read-after-write data locality, the processing system translates a first typewriter cache access pattern that proceeds in ascending order for a first access to a reverse typewriter cache access pattern that proceeds in descending order for a subsequent cache access. By translating the cache access pattern based on data locality, the processing system increases the hit rate of the cache.
A method for software management of DMA transfer commands includes receiving a DMA transfer command instructing a data transfer by a first processor device. Based at least in part on a determination of runtime system resource availability, a device different from the first processor device is assigned to assist in transfer of at least a first portion of the data transfer. In some embodiments, the DMA transfer command instructs the first processor device to write a copy of data to a third processor device. Software analyzes network bus congestion at a shared communications bus and initiates DMA transfer via a multi-hop communications path to bypass the congested network bus.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
A power supply monitor includes a droop detection circuit which receives a digital signal and converts the digital signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop below a designated value relative to the analog signal, produces a droop detection signal. The droop detection circuit includes a first comparator circuit with a series of inverters including at least a first complimentary-metal-oxide-semiconductor (CMOS) inverter with an input for receiving the analog signal and a second CMOS inverter, which are both supplied with a monitored supply voltage. The inverters operate in a crowbar mode when the monitored voltage supply is near a designated level, and each include four pull-up transistors connected in two parallel legs of two transistors, and four pull-down transistors connected in two parallel legs of two transistors.
G06F 1/28 - Surveillance, p.ex. détection des pannes d'alimentation par franchissement de seuils
H03K 19/20 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion caractérisés par la fonction logique, p.ex. circuits ET, OU, NI, NON
H03K 5/24 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p.ex. la pente, l'intégrale la caractéristique étant l'amplitude
An image generation apparatus includes at least a first configuration register that includes first configuration data for configuring parameters of an image processor, at least a second configuration register that includes second configuration data for configuring the parameters of a same image processing pipeline in the image processor, multiplexing logic coupled to the first configuration register and to the second configuration register, control logic that controls the multiplexing logic to in a non-demonstration mode select one of the first or second configuration registers to produce a first image frame and operative in a demonstration mode to provide both the first and second configuration data for the same image processing pipeline of the image processor to use for generating different regions of an image frame.
Techniques are described for adaptive device power management. The device interface application of a hardware computing unit detects a launch of an application by the operating system (OS) to be executed on the hardware computing unit, in an implementation. The device interface application identifies the launched application and determines whether a hardware profile exists that is associated with the application. The hardware profile includes one or more hardware parameters that yield the optimal performance for power consumption by the hardware computing unit when executing the launched application. Based on determining that the hardware profile exists, the power policy of the OS is updated for the launched application, and thereby, the driver updates the power state(s) of the hardware computing unit based on the new power policy.
G06F 1/3234 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise
59.
ELECTRONIC DEVICE INCLUDING A SUBSTRATE, A STRUCTURE, AND AN ADHESIVE AND A PROCESS OF FORMING THE SAME
An electronic device includes a substrate, an electronic component, a structure, and an adhesive. The substrate has a proximal surface. The electronic component includes at least one die, wherein the electronic component is attached to the substrate. The structure has a proximal surface adjacent to proximal surface of the substrate. A feature extends from the proximal surface of the structure or the substrate, and the adhesive contacts the feature and the proximal surfaces of the structure and the substrate. In another aspect, a process of forming the electronic device can include applying the adhesive, placing the substrate and structure adjacent to each other, wherein the adhesive contacts the feature and the proximal surfaces of the substrate and the substrate, and curing the adhesive.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
60.
Graphics Processing Architecture Employing a Unified Shader
A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
A read clock circuit selectively provides a read clock signal from a memory to a memory controller over a memory bus. A pulse-amplitude modulation (PAM) driver including an input and an output capable of driving at least three levels indicating respective digital values. A digital control circuit is coupled to the PAM driver and operable to cause the PAM driver to provide a preamble signal before the read clock signal, the preamble signal including an initial toggling state in which the PAM driver toggles between two selected levels at a first rate, and a final toggling state in which the PAM driver toggles between two selected levels at a second rate higher than the first rate, with a length of the initial toggling state and a length of the final toggling state are based on values in a mode register.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
A read clock circuit selectively provides a read clock signal from a memory to a memory controller over a memory bus. A pulse-amplitude modulation (PAM) driver including an input and an output capable of driving at least three levels indicating respective digital values. A digital control circuit is coupled to the PAM driver and operable to cause the PAM driver to provide a preamble signal before the read clock signal, the preamble signal including an initial toggling state in which the PAM driver toggles between two selected levels at a first rate, and a final toggling state in which the PAM driver toggles between two selected levels at a second rate higher than the first rate, with a length of the initial toggling state and a length of the final toggling state are based on values in a mode register.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
63.
PLATFORM RESOURCE SELCTION FOR UPSCALER OPERATIONS
Compound processing of an upscaler operation using platform resources includes: identifying a plurality of platform resources available to perform an upscaling operation, wherein the plurality of platform resources includes one or more graphics processor units (GPUs) and one or more accelerated processing units (APUs); and dynamically assigning workloads of the upscaling operation to one or more of the platform resources based on a modality of the upscaling operation; and processing the workloads of the upscaling operation by the platform resources to which the workloads are assigned.
Virtual Reality (VR) processing devices and methods are provided for transmitting user feedback information comprising at least one of user position information and user orientation information, receiving encoded audio-video (AN) data, which is generated based on the transmitted user feedback information, separating the A/V data into video data and audio data corresponding to a portion of a next frame of a sequence of frames of the video data to be displayed, decoding the portion of a next frame of the video data and the corresponding audio data, providing the audio data for aural presentation and controlling the portion of the next frame of the video data to be displayed in synchronization with the corresponding audio data.
H04N 21/2343 - Traitement de flux vidéo élémentaires, p.ex. raccordement de flux vidéo ou transformation de graphes de scènes MPEG-4 impliquant des opérations de reformatage de signaux vidéo pour la distribution ou la mise en conformité avec les requêtes des utilisateurs finaux ou les exigences des dispositifs des utilisateurs finaux
H04N 21/2368 - Multiplexage de flux audio et vidéo
H04N 21/236 - Assemblage d'un flux multiplexé, p.ex. flux de transport, en combinant un flux vidéo avec d'autres contenus ou données additionnelles, p.ex. insertion d'une adresse universelle [URL] dans un flux vidéo, multiplexage de données de logiciel dans un flu; Remultiplexage de flux multiplexés; Insertion de bits de remplissage dans le flux multiplexé, p.ex. pour obtenir un débit constant; Assemblage d'un flux élémentaire mis en paquets
H04N 21/414 - Plate-formes spécialisées de client, p.ex. récepteur au sein d'une voiture ou intégré dans un appareil mobile
H04N 21/422 - Périphériques d'entrée uniquement, p.ex. système de positionnement global [GPS]
H04N 21/434 - Désassemblage d'un flux multiplexé, p.ex. démultiplexage de flux audio et vidéo, extraction de données additionnelles d'un flux vidéo; Remultiplexage de flux multiplexés; Extraction ou traitement de SI; Désassemblage d'un flux élémentaire mis en paquets
H04N 21/437 - Interfaçage de la voie montante du réseau de transmission, p.ex. pour transmettre des requêtes de client à un serveur VOD
H04L 69/24 - Négociation des capacités de communication
H04N 21/43 - Traitement de contenu ou données additionnelles, p.ex. démultiplexage de données additionnelles d'un flux vidéo numérique; Opérations élémentaires de client, p.ex. surveillance du réseau domestique ou synchronisation de l'horloge du décodeur; Intergiciel de client
H04L 65/70 - Mise en paquets adaptés au réseau des données multimédias
H04L 65/75 - Gestion des paquets du réseau multimédia
H04L 67/131 - Protocoles pour jeux, simulations en réseau ou réalité virtuelle
65.
SEMICONDUCTOR CHIP HAVING STEPPED CONDUCTIVE PILLARS
In an implementation, a semiconductor chip includes a device layer, an interconnect layer fabricated on the device layer, the interconnect layer including a conductive pad, and a conductive pillar coupled to the conductive pad. The conductive pillar includes at least a first portion having a first width and a second portion having a second width, the first portion being disposed between the second portion and the conductive pad, wherein the first width of the first portion is greater than the second width of the second portion.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
66.
Decompression Engine for Decompressing Compressed Input Data that Includes Multiple Streams of Data
An electronic device that includes a decompression engine that includes N decoders and a decompressor decompresses compressed input data that includes N streams of data. Upon receiving a command to decompress compressed input data, the decompression engine causes each of the N decoders to decode a respective one of the N streams from the compressed input data separately and substantially in parallel with others of the N decoders. Each decoder outputs a stream of decoded data of a respective type for generating commands associated with a compression standard for decompressing the compressed input data. The decompressor next generates, from the streams of decoded data output by the N decoders, commands for decompressing the data using the compression standard to recreate the original data. The decompressor next executes the commands to recreate the original data and stores the original data in a memory or provides the original data to another entity.
A semiconductor package assembly includes a semiconductor package that includes a semiconductor chip bonded to a substrate. The assembly also includes a plurality of passive devices mounted on a bottom surface of the substrate opposite the semiconductor chip, the plurality of passive devices including a plurality of operable passive devices and a plurality of standoff passive devices, wherein a height of each of the plurality of standoff passive devices is greater than a height of any of the plurality of operable passive devices. The assembly also includes a plurality of solder structures attached to the bottom surface of the substrate. When mounted on a circuit board, the standoff passive devices prevent solder bridging.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des groupes principaux , ou dans une seule sous-classe de , , p.ex. circuit hybrides
A processing system includes a hardware translation lookaside buffer (TLB) retry loop that retries virtual memory address to physical memory address translation requests from a software client independent of a command from the software client. In response to a retry response notification at the TLB, a controller of the TLB waits for a programmable delay period and then retries the request without involvement from the software client. After a retry results in a hit at the TLB, the controller notifies the software client of the hit. Alternatively, if a retry results in an error at the TLB, the controller notifies the software client of the error and the software client initiates error handling.
G06F 12/1027 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p.ex. un répertoire de pages actives [TLB]
A system and method for texture decompression is described. The method comprises receiving a first compressed texture block including two or more disjoint subsets of data and decompressing the first compressed texture block. The decompressing includes decompressing the two or more disjoint subsets in the first compressed texture block to form texels. The two or more disjoint subsets include a first disjoint subset comprising a first set of color endpoints and a second disjoint subset comprising a second set of color endpoints.
H04N 19/426 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques - caractérisés par les détails de mise en œuvre ou le matériel spécialement adapté à la compression ou à la décompression vidéo, p.ex. la mise en œuvre de logiciels spécialisés caractérisés par les dispositions des mémoires utilisant des procédés de diminution de taille de mémoire
H04N 19/176 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c. à d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p.ex. un objet la zone étant un bloc, p.ex. un macrobloc
H04N 19/119 - Aspects de subdivision adaptative, p.ex. subdivision d’une image en blocs de codage rectangulaires ou non
H04N 19/46 - Inclusion d’information supplémentaire dans le signal vidéo pendant le processus de compression
H04N 19/60 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant un codage par transformée
H04N 19/96 - Codage au moyen d'une arborescence, p.ex. codage au moyen d'une arborescence quadratique
H04N 19/154 - Qualité visuelle après décodage mesurée ou estimée de façon subjective, p.ex. mesure de la distorsion
H04N 19/54 - Estimation de mouvement autre que basée sur les blocs utilisant des points ou des maillages caractéristiques
H04N 19/182 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c. à d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant un pixel
70.
DETECTING AND MITIGATING ARTIFACTS RELATED TO HIGH CHROMATIC COLORS
Systems, apparatuses, and methods for detecting and mitigating scaling artifacts caused by high chromatic colors in adjacent pixels are disclosed. A blend factor calculation circuit determines if high chromatic colors are in close proximity to each other in a set of pixel data of an image or frame. The blend factor calculation circuit generates a blend factor value to suppress artifacts which are introduced when filtering the set of pixel data when the set of pixel data has high chromatic colors in close proximity. In one scenario, the blend factor calculation circuit calculates pixel component difference values of adjacent pixels and uses a value calculated based on the difference values as an input to a transfer function. The output of the transfer function is a blend factor value which determines how filtering is blended between a plurality of filters.
A graphics processing unit (GPU) of a processing system transmits pixel data for a frame to a display in a compressed burst, so that the pixel data is communicated at a rate that is higher than the rate at which the display scans out the pixel data to refresh the frame at a display panel. By transmitting pixel data for the frame in a compressed burst, the GPU shortens the time spent transmitting the pixel data and extends the time before the next frame of pixel data is to be transmitted. During the extended time before the next frame of pixel data is to be transmitted, the GPU saves power by placing portions of the processing system in a reduced power mode.
G09G 5/00 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation
G06T 1/20 - Architectures de processeurs; Configuration de processeurs p.ex. configuration en pipeline
A method for hardware management of DMA transfer commands includes accessing, by a first DMA engine [314], a DMA transfer command and determining a first portion of a data transfer requested by the DMA transfer command. Transfer of a first portion of the data transfer by the first DMA engine is initiated based at least in part on the DMA transfer command. Similarly, a second portion of the data transfer by a second DMA engine is initiated based at least in part on the DMA transfer command. After transferring the first portion and the second portion of the data transfer, an indication is generated that signals completion of the data transfer requested by the DMA transfer command.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
A display system modifies display cycles of one or more displays to perform a system operation while avoiding visual perturbations at the one or more displays. The display system modifies, synchronizes, or both, blanking periods of the one or more displays such that blanking periods equal or exceed a blackout duration and overlap for at least the blackout duration. Then the system performs the system operation during an overlapping portion of the one or more blanking periods, where the system operation reduces availability of display data at the one or more displays.
Systems, apparatuses, and methods for implementing duplicated registers for access by initiators across multiple semiconductor dies are disclosed. A system includes multiple initiators on multiple semiconductor dies of a chiplet processor. One of the semiconductor dies is the master die, and this master die has copies of registers which can be accessed by the multiple initiators on the multiple semiconductor dies. When a given initiator on a given secondary die generates a register access, the register access is routed to the master die and a particular duplicate copy of the register maintained for the given secondary die. From the point of view of software, the multiple semiconductor dies appear as a single die, and the multiple initiators appear as a single initiator. Multiple types of registers can be maintained by the master die, with a flush register being one of the register types.
A system and method for efficiently capturing data by sequential circuits across multiple operating conditions are described. In various implementations, an integrated circuit includes multiple signal arrival adjusters both at its I/O boundaries and across its die. The signal arrival adjuster includes two internal timing paths, each with a respective latency. The signal arrival adjuster receives an input signal, and generates an output signal from the a selected one of the first timing path and the second timing path. The signal arrival adjuster sends the output signal to a sequential circuit. The sequential circuit uses the output signal as one of an input data signal and an input clock signal. The selection between the two timing paths within the signal arrival adjuster aids satisfying the setup and hold time requirements of the sequential circuit.
A computer vision processor in an image cluster defines a fenced memory region (FMR) that controls access to image data stored in a first portion of a trusted memory region (TMR). The computer vision processor receives FMR requests from an application implemented in a processing cluster. The FMR requests are to access the image data in the first portion of the TMR. The computer vision processor selectively allows the requesting application to access the image data. In some cases, the computer vision processor acquires the image data and stores the image data in the first portion of the TMR, such as buffers in the TMR. A data fabric selectively permits the image processing application to access the data stored in the TMR based on whether the image cluster has opened or closed the FMR for the portion of the TMR.
A system and method for efficiently capturing data by sequential circuits across multiple operating conditions are described. In various implementations, an integrated circuit includes multiple signal arrival adjusters both at its I/O boundaries and across its die. The signal arrival adjuster includes two internal timing paths, each with a respective latency. The signal arrival adjuster receives an input signal, and generates an output signal from the a selected one of the first timing path and the second timing path. The signal arrival adjuster sends the output signal to a sequential circuit. The sequential circuit uses the output signal as one of an input data signal and an input clock signal. The selection between the two timing paths within the signal arrival adjuster aids satisfying the setup and hold time requirements of the sequential circuit.
Systems, apparatuses, and methods for implementing duplicated registers for access by initiators across multiple semiconductor dies are disclosed. A system includes multiple initiators on multiple semiconductor dies of a chiplet processor. One of the semiconductor dies is the master die, and this master die has copies of registers which can be accessed by the multiple initiators on the multiple semiconductor dies. When a given initiator on a given secondary die generates a register access, the register access is routed to the master die and a particular duplicate copy of the register maintained for the given secondary die. From the point of view of software, the multiple semiconductor dies appear as a single die, and the multiple initiators appear as a single initiator. Multiple types of registers can be maintained by the master die, with a flush register being one of the register types.
A dynamic allocator for providing platform resource candidates is disclosed. In an implementation, a platform resource allocator receives a request from a workload initiator such as, an application, for a platform resource recommendation. The platform resource allocator analyzes performance capabilities and utilization metrics of a plurality of platform resources for each of a plurality of resource. The plurality of platform resources includes one or more graphics processor units (GPUs) and one or more accelerated processing units (APUs). The platform resource allocator dynamically provides the platform resource recommendation to the workload initiator to select one or more of the plurality of platform resources to execute a workload based on the performance capabilities and utilization metrics.
An optimized service-based pipeline includes a resource manager that receives a request that includes a description of a workload from a workload initiator such as an application. The resource manager identifies runtime utilization metrics of a plurality of processing resources, where the plurality of processing resources includes at least a first graphics processing unit (GPU) and a second GPU. The resource manager determines, based on the utilization metrics and one or more policies, a workload allocation recommendation for the workload. Thus, the workload initiator can determine whether placing a workload on a particular processing resource is preferable based on runtime behavior of the system and policies established of the workload.
Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.
A power supply circuit is provided for supplying power from multiple peripheral power supplies to a data processor. The power supply circuit includes a power bus, a plurality of load voltage converters each including an input coupled to the power bus and an output coupled to a respective one of multiple subsystems of the data processor, a plurality of input voltage converters each including an input for coupling to a respective one of multiple peripheral power supply voltages and an output coupled to the power bus, and a feedback control circuit having an input coupled to the power bus and a plurality of outputs coupled to respective ones of the input voltage converters for controlling a current draw of the respective input voltage converter.
G06F 1/26 - Alimentation en énergie électrique, p.ex. régulation à cet effet
G06F 1/18 - Installation ou distribution d'énergie
H02J 1/12 - Fonctionnement de générateurs à courant continu en parallèle avec des convertisseurs, p.ex. avec un redresseur à arc de mercure
H02M 1/00 - APPAREILS POUR LA TRANSFORMATION DE COURANT ALTERNATIF EN COURANT ALTERNATIF, DE COURANT ALTERNATIF EN COURANT CONTINU OU VICE VERSA OU DE COURANT CONTINU EN COURANT CONTINU ET EMPLOYÉS AVEC LES RÉSEAUX DE DISTRIBUTION D'ÉNERGIE OU DES SYSTÈMES D'ALI; TRANSFORMATION D'UNE PUISSANCE D'ENTRÉE EN COURANT CONTINU OU COURANT ALTERNATIF EN UNE PUISSANCE DE SORTIE DE CHOC; LEUR COMMANDE OU RÉGULATION - Détails d'appareils pour transformation
A carrier boat for die package flux cleaning, including: a body having at least one pair of substantially parallel sides, the body comprising one or more die package receptacles each oriented at a non-parallel angle relative to the substantially parallel sides of the body such that, when a die package is seated in a die package receptacle of the one or more die package receptacles, a first pair of opposing sides of a die of the die package are substantially perpendicular to the substantially parallel sides,
H01L 21/673 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants utilisant des supports spécialement adaptés
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
84.
HUE-ADAPTIVE SATURATION INCREASE FOR OLED DISPLAY POWER REDUCTION
A processing system adjusts a saturation component of a hue-saturation-value (HSV) color space pixel input for an organic light emitting diode (OLED) display panel as a function of the hue component. The processing system converts components of a pixel input from a non-HSV color space to HSV components of the pixel input in HSV color space and modifies the saturation component of the pixel input in HSV color space based on the hue component of the pixel input to generate modified HSV components of the pixel input. The processing system then converts the modified HSV components of the pixel input back into the original color space to produce modified components of the pixel input in the original color space and provides the modified components of the pixel input for receipt by the OLED display, allowing the pixel to be driven at a lower pixel value while maintaining perceptual quality.
G06F 1/3234 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise
H04N 9/64 - Circuits pour le traitement de signaux de couleur
G09G 3/3233 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p.ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p.ex. utilisant des diodes électroluminescentes [LED] organiques, p.ex. utilisant des diodes électroluminescentes organiques [OLED] utilisant une matrice active avec un circuit de pixel pour commander le courant à travers l'élément électroluminescent
85.
SCHEDULING AND CLOCK MANAGEMENT FOR REAL-TIME SYSTEM QUALITY OF SERVICE (QOS)
Scheduling and clock management for real-time system quality of service (QoS) is disclosed. In an implementations, a resource manager determines a target work rate based on respective job deadlines of a plurality of jobs on a processing platform. Determining the target work rate can include ordering the plurality of jobs based on the respective deadlines, determining an amount of work required to reach each of the respective deadlines, identifying one deadline among the respective deadlines as a most constraining deadline based on the amount of work required to reach that one deadline, and determining the target work rate based on the most constraining deadline. The resource manager adjusts a clock rate of the processing platform based on at least the target work rate.
A processing system includes a translation lookaside buffer (TLB). The TLB includes a plurality of TLB entries that are configured to store requested page size indications. The TLB is configured to be indexed via the requested page size indications such that a plurality of TLB requests that each indicate a same virtual address, but different respective requested page sizes are allocated respective TLB entries. As a result, in response to a TLB request that indicates a requested page size and has a virtual address that corresponds to multiple TLB entries, only a single TLB entry is identified as a TLB hit.
G06F 12/1027 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p.ex. un répertoire de pages actives [TLB]
Techniques described herein provide users with the ability to persistently adjust settings for boot-time features (BTF) of a computing device. A user requests a particular BTF configuration adjustment for a device via a device driver. The driver instructs trusted firmware of the device to store a boot override record in persistent storage accessible by a bootloader for the device. Upon implementation of the boot sequence for the device, the bootloader applies the changes reflected in the record to BTF configuration data. The boot override information is persistently available to the bootloader, which ensures that the configuration changes that the boot override record(s) represent are applied to the BTFs of the device until the boot override record(s) are cleared or invalidated. Further, to ensure the security of boot override record(s), the trusted firmware generates, for each record, an HMAC tag using an HMAC key derived from a Chip Endorsement Fused Secret from the hardware.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
An integrated circuit includes a TSV extending from a first surface of a semiconductor substrate to a second surface of the semiconductor substrate and having a first end and a second end, and a non-volatile repair circuit. The non-volatile repair circuit includes a one-time programmable (OTP) element having a programming terminal, wherein in response to an application of a fuse voltage to the programming terminal, the OTP element electrically couples the first end of the TSV to the second end of the TSV.
G11C 17/16 - Mémoires mortes programmables une seule fois; Mémoires semi-permanentes, p.ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p.ex. mémoires PROM utilisant des liaisons électriquement fusibles
G11C 17/18 - Circuits auxiliaires, p.ex. pour l'écriture dans la mémoire
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
G11C 29/44 - Indication ou identification d'erreurs, p.ex. pour la réparation
G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p.ex. compteurs de rafraîchissement défectueux
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H10B 20/20 - Dispositifs ROM programmable électriquement [PROM] comprenant des composants à effet de champ
A dynamic allocator for providing platform resource candidates is disclosed. In an implementation, a platform resource allocator receives a request from a workload initiator such as, an application, for a platform resource recommendation. The platform resource allocator analyzes performance capabilities and utilization metrics of a plurality of platform resources for each of a plurality of resource. The plurality of platform resources includes one or more graphics processor units (GPUs) and one or more accelerated processing units (APUs). The platform resource allocator dynamically provides the platform resource recommendation to the workload initiator to select one or more of the plurality of platform resources to execute a workload based on the performance capabilities and utilization metrics.
Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
An optimized service-based pipeline includes a resource manager that receives a request that includes a description of a workload from a workload initiator such as an application. The resource manager identifies runtime utilization metrics of a plurality of processing resources, where the plurality of processing resources includes at least a first graphics processing unit (GPU) and a second GPU. The resource manager determines, based on the utilization metrics and one or more policies, a workload allocation recommendation for the workload. Thus, the workload initiator can determine whether placing a workload on a particular processing resource is preferable based on runtime behavior of the system and policies established of the workload.
Chroma correction of inverse gamut mapping (IGM) for standard dynamic range (SDR) to high dynamic range (HDR) image conversion includes: converting R,G,B color components in the RGB color format of a pixel of an image to an intensity component (I) and chroma components (Ct and Cp) of an ICtCp color format, wherein the R,G,B color components represent red, green, and blue colors; applying an intensity transformation operation on the intensity component (I) of the pixel; executing a chroma correction operation on the transformed intensity component (I) and the chroma components (Ct and Cp) of the pixel; and converting the intensity component (I) and the chroma components (Ct and Cp) of the pixel back to the RGB color format.
Systems, apparatuses, and methods for performing machine learning content categorization leveraging video encoding pre-processing are disclosed. A system includes at least a motion vector unit and a machine learning (ML) engine. The motion vector unit pre-processes a frame to determine if there is temporal locality with previous frames. If the objects of the scene have not changed by a threshold amount, then the ML engine does not process the frame, saving computational resources that would typically be used. Otherwise, if there is a change of scene or other significant changes, then the ML engine is activated to process the frame. The ML engine can then generate a QP map and/or perform content categorization analysis on this frame and a subset of the other frames of the video sequence.
H04N 19/139 - Analyse des vecteurs de mouvement, p.ex. leur amplitude, leur direction, leur variance ou leur précision
H04N 19/126 - Quantification - Détails des fonctions de normalisation ou de pondération, p.ex. matrices de normalisation ou quantificateurs uniformes variables
G06K 9/00 - Méthodes ou dispositions pour la lecture ou la reconnaissance de caractères imprimés ou écrits ou pour la reconnaissance de formes, p.ex. d'empreintes digitales
H04N 19/142 - Détection de coupure ou de changement de scène
G06T 3/40 - Changement d'échelle d'une image entière ou d'une partie d'image
H04N 19/55 - Estimation de mouvement avec contraintes spatiales, p.ex. au niveau des contours de l’image ou des contours des régions
Systems, apparatuses, and methods for implementing content adaptive processing via ringing estimation and suppression are disclosed. A ring estimator estimates the amount of ringing when a wide filter kernel is used for image processing. The amount of ringing can be specified as an under-shoot or an over-shoot. A blend factor calculation unit determines if the estimated amount of ringing is likely to be visually objectionable. If the ringing is likely to be visually objectionable, then the blend factor calculation unit generates a blend factor value to suppress the objectionable ringing. The blend factor value is generated for each set of source pixels based on this determination. The blend factor value is then applied to how the blending is mixed between narrow and wide filters for the corresponding set of source pixels. The preferred blending between the narrow and wide filters is changeable on a pixel-by-pixel basis during image processing.
A power supply circuit is provided for supplying power from multiple peripheral power supplies to a data processor. The power supply circuit includes a power bus, a plurality of load voltage converters each including an input coupled to the power bus and an output coupled to a respective one of multiple subsystems of the data processor, a plurality of input voltage converters each including an input for coupling to a respective one of multiple peripheral power supply voltages and an output coupled to the power bus, and a feedback control circuit having an input coupled to the power bus and a plurality of outputs coupled to respective ones of the input voltage converters for controlling a current draw of the respective input voltage converter.
G06T 1/20 - Architectures de processeurs; Configuration de processeurs p.ex. configuration en pipeline
H02M 1/00 - APPAREILS POUR LA TRANSFORMATION DE COURANT ALTERNATIF EN COURANT ALTERNATIF, DE COURANT ALTERNATIF EN COURANT CONTINU OU VICE VERSA OU DE COURANT CONTINU EN COURANT CONTINU ET EMPLOYÉS AVEC LES RÉSEAUX DE DISTRIBUTION D'ÉNERGIE OU DES SYSTÈMES D'ALI; TRANSFORMATION D'UNE PUISSANCE D'ENTRÉE EN COURANT CONTINU OU COURANT ALTERNATIF EN UNE PUISSANCE DE SORTIE DE CHOC; LEUR COMMANDE OU RÉGULATION - Détails d'appareils pour transformation
96.
PLATFORM RESOURCE SELCTION FOR UPSCALER OPERATIONS
Compound processing of an upscaler operation using platform resources includes: identifying a plurality of platform resources available to perform an upscaling operation, wherein the plurality of platform resources includes one or more graphics processor units (GPUs) and one or more accelerated processing units (APUs); and dynamically assigning workloads of the upscaling operation to one or more of the platform resources based on a modality of the upscaling operation; and processing the workloads of the upscaling operation by the platform resources to which the workloads are assigned.
A processing system (100) adjusts a saturation component of a hue-saturation-value (HSV) color space pixel input (108) for an organic light emitting diode (OLED) display panel (122) as a function of the hue component. The processing system converts components of a pixel input from a non-HSV color space to HSV components of the pixel input in HSV color space and modifies the saturation component of the pixel input in HSV color space based on the hue component of the pixel input to generate modified HSV components of the pixel input. The processing system then converts the modified HSV components of the pixel input back into the original color space to produce modified components of the pixel input in the original color space and provides the modified components of the pixel input for receipt by the OLED display, allowing the pixel to be driven at a lower pixel value while maintaining perceptual quality.
G09G 3/3208 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p.ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p.ex. utilisant des diodes électroluminescentes [LED] organiques, p.ex. utilisant des diodes électroluminescentes organiques [OLED]
G09G 5/02 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation caractérisés par la manière dont la couleur est visualisée
98.
LOW POWER STATE SELECTION BASED ON IDLE DURATION HISTORY
An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.
G06F 1/3287 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par la mise hors tension d’une unité fonctionnelle individuelle dans un ordinateur
Devices, methods, and systems for secure communications on a computing device. A host operating system (OS) runs on a host processor in communication with a host memory. A secure OS runs on a coprocessor in communication with a secure memory. The coprocessor receives information from an external device over a secure peer-to-peer (P2P) connection. The secure P2P connection is managed by the secure OS and is not accessible by the host OS.
G06F 21/74 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information opérant en mode dual ou compartimenté, c. à d. avec au moins un mode sécurisé
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
Systems and methods are disclosed that automatically generating a gameplay recording from an application. Techniques are provided to extract data from a buffer, the extracted data are associated with the application; to detect, based on a signature associated with the extracted data, the occurrence of an event; and upon detection of the occurrence of the event, to generate the gameplay recording from an output of the application.
A63F 13/497 - Répétition partielle ou entière d'actions de jeu antérieures
G06K 9/00 - Méthodes ou dispositions pour la lecture ou la reconnaissance de caractères imprimés ou écrits ou pour la reconnaissance de formes, p.ex. d'empreintes digitales
A63F 13/53 - Commande des signaux de sortie en fonction de la progression du jeu incluant des informations visuelles supplémentaires fournies à la scène de jeu, p.ex. en surimpression pour simuler un affichage tête haute [HUD] ou pour afficher une visée laser dans un jeu de tir
A63F 13/54 - Commande des signaux de sortie en fonction de la progression du jeu incluant des signaux acoustiques, p. ex. pour simuler le bruit d’un moteur en fonction des tours par minute [RPM] dans un jeu de conduite ou la réverbération contre un mur virtuel
