A memory device includes a plurality of pages arrayed in a column direction in a plan view, each page being constituted by a plurality of memory cells arrayed in a row direction on a substrate. Each of the memory cells included in each of the pages includes a semiconductor base material, first and second impurity regions positioned at respective ends of the semiconductor base material, first, second, and third gate conductor layers. The first and second impurity regions, the first, second, and third gate conductor layers are connected to a source line, a bit line, a first select gate line, a plate line, and a second select gate line, respectively. Upon operation end of page write operation and page read operation, voltage of the plate line is set to negative voltage lower than 0 V through capacitive coupling of the plate line and each of the first and second select gate lines to improve data retention characteristics of a write memory cell.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A memory device including a semiconductor element includes two stacked memory cells including a first impurity region, first and second gate conductor layers, a second impurity region, third and fourth gate conductor layers, and a third impurity region on a P layer substrate in order from below in a vertical direction and configured to perform data write, read, and erase operation with voltage applied to each gate conductor layer. The first impurity region is connected to a first bit line. One of the first and second gate conductor layers and the other are connected to a word line and a plate line, respectively. The third and fourth gate conductor layers are each connected to the word line or plate line connected to the second or first gate conductor layer, respectively. The second and third impurity regions are connected to a source line and a second bit line, respectively.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4097 - Organisation de lignes de bits, p.ex. configuration de lignes de bits, lignes de bits repliées
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
A memory device in which, in a plan view, a plurality of pages are aligned in a column direction on a substrate and are formed by a plurality of memory cells aligned in a row direction, the memory device being characterized in that the memory cells included in each page have a semiconductor matrix, and at both ends of the semiconductor matrix, a first and second impurity layers, a first gate conductor layer, a second gate conductor layer, a third gate conductor layer, and a channel semiconductor layer, the first impurity layer of the memory cell is connected to a source line and the second impurity layer is connected to a bit line, the first gate conductor layer is connected to a first selection gate line, the second gate conductor layer is connected to a plate line, the third gate conductor layer is connected to a second selection gate line, and at the completion of a page write operation and a page read operation, the voltage of the plate line is brought to a negative voltage less than 0V by capacitive coupling of the first and second selection gate lines to the plate line, thereby improving the data retention property of a write memory cell.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10B 99/00 - Matière non prévue dans les autres groupes de la présente sous-classe
The present invention provides a memory device using a semiconductor element, the memory device comprising, in the vertical direction from the bottom, two layered memory cells including a first impurity layer, a first gate conductor layer, a second gate conductor layer, a second impurity layer, a third gate conductor layer, a fourth gate conductor layer, and a third impurity layer on a P-layer substrate, each of the memory cells performing a data write operation, a data read operation, and a data erase operation according to a voltage applied thereto. The memory device is characterized in that: the first impurity layer is connected to a first bit line; one of the first gate conductor layer and the second gate conductor layer is connected to a word line and the other one thereof is connected to a plate line; the third gate conductor layer is connected to the same word line or plate line as that connected to the second gate conductor layer; the fourth gate conductor layer is connected to the same word line or plate line as that connected to the first gate conductor layer; the second impurity layer is connected to a source line; and the third impurity layer is connected to a second bit line.
This memory device, in which in a plan view on a substrate, a page is formed by a plurality of memory cells arranged in the row direction and a plurality of the pages are arranged in the column direction, is characterized in that: the memory cells included in each page have a semiconductor matrix, a first impurity layer on both ends of the semiconductor matrix, a second impurity layer, a first gate conductor layer, a second gate conductor layer, and a channel semiconductor layer; the first impurity layer of the memory cell connects to a source line, the second impurity layer connects to a bit line, one among the first gate conductor layer and the second gate conductor layer connects to a word line, and the other connects to a plate line; a voltage applied across the source line, bit line, word line, and plate line is controlled to perform a page erase operation, a page write operation, and a page read operation; and a first operation in which data of a first page is output to an input/output circuit via a sense amplifier circuit, and a second operation in which data of a second page on the same bank as the first page is read out by the bit line, are performed in parallel.
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10B 99/00 - Matière non prévue dans les autres groupes de la présente sous-classe
6.
MEMORY DEVICE IN WHICH SEMICONDUCTOR ELEMENT IS USED
An N+layer 21a, a P layer 22a, an N+layer 21b, a P layer 22b, and an N+layer 21b are provided in sequence from below in the vertical direction on a P-layer substrate 19. There are provided a first gate insulation layer 26a surrounding the P layer 22b, a second gate insulation layer 26b surrounding the P layer 22b, a first gate conductor layer 27a and a second gate conductor layer 29a surrounding the first gate insulation layer 26a, and a third gate conductor layer 29b and a fourth gate conductor layer 27b surrounding the second gate insulation layer 26b. There are also provided a wiring layer 21a connected to an N+layer 20a, a wiring layer 30 connected to an N+layer 20b, and a wiring layer 21b connected to an N+ layer 20c. In plan view, the first gate conductor layer 27a, the second gate conductor layer 29a, the wiring layer 30, the third gate conductor layer 29b, and the fourth gate conductor layer 27b have the same shape and are orthogonal to the wiring layers 21a, 21b.
A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions, connected to a source line and a bit line, respectively, at both ends of the semiconductor base, and first and second gate conductor layers, one of which is connected to a word line and the other of which is connected to a plate line. Page erase, page write, and read operations are performed by controlling voltages applied to the source, bit, word, and plate lines. A first operation of outputting data of a first page to an input/output circuit via a sense amplifier circuit and a second operation of reading data of a second page of the same bank as the first page to the bit line are performed in parallel.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A first N+ layer, a first P layer, a second N+ layer, a second P layer, and a third N+ layer are formed on a P layer substrate in order from below vertically, a first gate insulating layer surrounds the first P layer, a second gate insulating layer surrounds the second P layer, first and second gate conductor layers surround the first gate insulating layer, and third and fourth gate conductor layers surround the second gate insulating layer. A first wiring layer is connected to the first N+ layer, a second wiring layer is connected to the second N+ layer, and a third wiring layer is connected to the third N+ layer. The first and second gate conductor layers, the second wiring layer, and the third and fourth gate conductor layers have identical shapes in a plan view and are orthogonal to the first and third wiring layers.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
This memory device having, on a substrate in a plan view, a plurality of pages which are each formed by a plurality of memory cells arrayed in the row direction and which are arrayed in the column direction is characterized in that: the memory cells included in each of the pages each have a semiconductor matrix, a first impurity layer and a second impurity layer at both ends of the semiconductor matrix, a first gate conductive layer, a second gate conductive layer, and a channel semiconductor layer; the first impurity layer in the memory cell is connected to a source line; the second impurity layer is connected to a bit line; either of the first gate conductive layer and the second gate conductive layer is connected to a word line; and the other is connected to a plate line. The memory device is also characterized by continuously performing, through the control of voltages applied to the source line, the bit line, the word line, and the plate line, a page erase operation and a page write operation without performing a reset operation to return the voltage applied to the plate line PL to the ground voltage Vss.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10B 99/00 - Matière non prévue dans les autres groupes de la présente sous-classe
The present invention provides a memory device in which a page is formed from a plurality of memory cells arranged in a row direction and a plurality of pages are arranged in a column direction on a substrate in a plan view. The memory cell included in each page has a semiconductor base body, a first impurity layer and a second impurity layer at both ends of the semiconductor base body, a first gate conductor layer, a second gate conductor layer, and a channel semiconductor layer. The first impurity layer of the memory cell is connected to a source line. The second impurity layer is connected to a bit line. One of the first gate conductor layer and the second gate conductor layer is connected to a word line and the other one thereof is connected to a plate line. The memory cell controls voltages applied to the source line, the bit line, the word line, and the plate line to perform a page erase operation, a page write operation, and a page read operation, stores logic "1" data in a first page group formed of at least one page, and is characterized in that a refresh operation is performed by increasing the number of holes in a hole group of the channel semiconductor layer by a current flowing from the bit line to the memory cell through the impact ionization phenomenon and, subsequently, the refresh operation is performed continuously up to an N-th page group in a state in which the applied voltage of the bit line is fixed.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10B 99/00 - Matière non prévue dans les autres groupes de la présente sous-classe
A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions, connected to a source line and a bit line, respectively, at both ends of the semiconductor base, and first and second gate conductor layers, one of which is connected to a word line and the other of which is connected to a plate line. A continuous operation of a page erase operation and a page write operation is performed by controlling voltages applied to the source line, the bit line, the word line, and the plate line without performing a reset operation for returning the voltage applied to the plate line to a ground voltage.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions at both ends of the semiconductor base, and first and second gate conductor layers. A page erase operation, a page write operation, and a page read operation are performed by controlling voltages applied to the first and second impurity regions and the first and second gate conductor layers. In a first page group including at least one page, a refresh operation of increasing positive holes is performed in a memory cell storing logical data “1”. The refresh operation is performed continuously to an N-th page group.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
Provided is a dynamic flash memory in which there are a semiconductor matrix p layer 1, an n+ layer 2 extends on one side thereof, and an n+ layer 3 is on the opposite side thereof in contact with the p layer 1, the p layer 1 is partially coated with a gate insulation layer 4, there is also a first gate conductor layer 5 in contact therewith, and, in contact with the gate insulation layer 4, the p layer 1 is partially coated with a gate insulation layer 6, and there is a second gate conductor layer 7 that is electrically separated from a gate electrode 5, and the n+ layer 2, the n+ layer 3, and the gate conductor layers 5, 7 are connected respectively to a source line, a bit line, a word line, and a plate line. During writing to the memory, after 1.0 V has been applied to the bit line, and after 1.5 V has been applied to the plate line, for example, 1.2 V is applied to the word line. The present invention is characterized in that during erasing of memory, after 2 V has been applied to the plate line, for example, the voltage applied to each terminal in the bit line is always a value such as 0.6 V that is no less than 0 V. In a memory read operation, after a voltage has been applied to the bit line, voltage is applied to the plate line and the word line in the stated order, and memory information is read.
A dynamic flash memory includes a p layer as a semiconductor base material, first and second n+ layers on opposite sides thereof, first and second gate insulating layers in contact with each other and partially covering the p layer, and first and second gate conductor layers electrically isolated from each other and respectively provided on the first and second gate insulating layers. The first and second n+ layers and first and second gate conductor layers are respectively connected to source, bit, word, and plate lines. During writing, 1.0 V, 1.5 V, and 1.2 V are sequentially applied to the bit, plate, and word lines, respectively. During erasing, 2 V is applied to the plate line, and then, a voltage applied to each terminal is always set 0 V or greater (e.g., 0.6 V for the bit line). Further, during reading, voltages are sequentially applied to the bit, plate, and word lines.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A memory device in which, on a substrate in a plan view, a page is configured from a plurality of memory cells arranged in a row direction, and a plurality of the pages are arranged in a column direction, the memory device being characterized in that: the memory cells included in each page each have a semiconductor matrix, a first impurity layer and a second impurity layer at respective ends of the semiconductor matrix, a first gate conductor layer, a second gate conductor layer, and a channel semiconductor layer; the first impurity layer of the memory cell is connected to a source line; the second impurity layer is connected to a bit line; one of the first gate conductor layer and the second gate conductor layer is connected to a word line, and the other is connected to a plate line; voltages applied to the source line, the bit line, the word line, and the plate line are controlled to perform a page erase operation and a page write operation; and a page read operation includes performing a first refresh operation in which the number of holes in a hole group in the channel semiconductor layer of a memory cell in which the page write operation has been performed is increased by impact ionization, a second refresh operation in which a part of the hole group in the channel semiconductor layer of memory cells in which the page write operation has not been performed is eliminated to reduce the number of holes, and a third refresh operation for a memory cell storing the logical "1" data within the page, using latch data of a sense amplifier circuit to which the bit line is connected via a switch circuit.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 7/06 - Amplificateurs de lecture; Circuits associés
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction in plan view on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, and in a page read operation, a first refresh operation of increasing by an impact ionization phenomenon, the number of positive holes in the semiconductor body of a memory cell for which page writing has been performed and a second refresh operation of decreasing the number of positive holes in the semiconductor body of a memory cell for which page writing has not been performed are performed and a third refresh operation for a memory cell, in a page, in which the logical “1” data is stored is performed by using latch data in a sense amplifier circuit.
G11C 11/403 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 11/4097 - Organisation de lignes de bits, p.ex. configuration de lignes de bits, lignes de bits repliées
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
A semiconductor memory device includes a semiconductor base body (Si pillar) erected or horizontally laid on a substrate; first and second impurity regions located on opposite ends of the semiconductor base body; and gate insulating layer and first and second gate conductor layers located between the impurity regions, surrounding the semiconductor base body. By applying voltages to the impurity regions and gate conductor layers, a current is passed between the impurity regions, thereby causing impact ionization phenomenon in a semiconductor base body to generate electron groups and positive hole groups. A memory write operation is performed to remove the electron groups from the semiconductor base body and hold part of the positive hole groups in the semiconductor base body. A memory erase operation is performed by removing positive hole groups held in the semiconductor base body from the first and/or second impurity region(s). Two semiconductor elements make up one memory cell.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, the first and second impurity regions and first and second gate conductor layers are connected to source, bit, word, and plate lines respectively, and a page read operation includes a first refresh operation of increasing by an impact ionization phenomenon, a group of positive holes in the semiconductor body of a memory cell for which page writing has been performed and a subsequent second refresh operation of making some of a group of positive holes in the semiconductor body of a memory cell for which page writing has not been performed disappear and decreasing the number of positive holes.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, the first and second impurity regions and first and second gate conductor layers are connected to source, bit, word, and plate lines respectively, and voltages applied to these lines are controlled to perform an erase operation of collecting a group of positive holes in the semiconductor body of a selected memory cell in a part adjacent to the first gate conductor layer and making some of the group of positive holes disappear and a page write operation of increasing by an impact ionization phenomenon, the number of positive holes in the semiconductor body of a selected memory cell in a page.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A memory device in which, in a plan view on a substrate, a page is configured from a plurality of memory cells arranged in a row direction, and a plurality of pages are arranged in a column direction, the memory device being characterized in that: the memory cells included in the pages each have a semiconductor matrix, a first impurity layer and a second impurity layer at respective ends of the semiconductor matrix, a first gate conductor layer, a second gate conductor layer, and a channel semiconductor layer; the first impurity layer of each memory cell is connected to a source line; the second impurity layer is connected to a bit line; one of the first gate conductor layer and the second gate conductor layer is connected to a word line, and the other is connected to a plate line; voltages applied to the source line, the bit line, the word line, and the plate line are controlled to perform a page erase operation and a page write operation; and a page read operation includes performing a first refresh operation in which the number of holes in a hole group in the channel semiconductor layer of memory cells where the page write operation was performed is increased via impact ionization, and a second refresh operation in which part of the hole group in the channel semiconductor layer of memory cells where the page write operation was not performed is terminated after the first refresh operation and the number of holes is reduced.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
A memory apparatus includes a page including a plurality of memory cells arranged in a column on a substrate. Each of voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell included in the page is controlled to perform a page write operation of retaining holes, which have been formed through an impact ionization phenomenon or using a gate induced drain leakage current, in a semiconductor base material, or each of voltages applied to the first and second gate conductor layers, third and fourth gate conductor layers, and the first and second impurity layers is controlled to perform a page erase operation of removing the holes from the semiconductor base material, and further lowering a voltage of the semiconductor base material through capacitive coupling with the first gate conductor layer and the second gate conductor layer.
This memory device having, on a substrate in a plan view, a plurality of pages which are each formed by a plurality of memory cells arrayed in the row direction and which are arrayed in the column direction is characterized in that: the memory cells included in each of the pages each have a semiconductor matrix, a first impurity layer and a second impurity layer disposed on opposite ends of the semiconductor matrix, a first gate conductive layer, a second gate conductive layer, and a channel semiconductor layer; the first impurity layer in the memory cell is connected to a source line; the second impurity layer is connected to a bit line; either one of the first gate conductive layer and the second gate conductive layer is connected to a word line; and the other one is connected to a plate line. The memory device is also characterized by performing, through control of voltage applying to the source line, the bit line, the word line, and the plate line: an erasing operation of reducing the number of holes by gathering a hole group in the channel semiconductor layer of a selected one of the memory cells to a portion of the channel semiconductor layer closer to the first gate conductive layer or to the second gate conductive layer and erasing a portion of the hole group; and a page writing operation in which the number of holes in the channel semiconductor layer of the selected memory cell of a page is increased by an impact ionization phenomenon.
H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
A semiconductor element memory device includes a first block including first memory cells arranged in a matrix, and/or a second block including second memory cells each formed of two memory cells. The memory device is configured to perform a data hold operation of controlling voltages to be applied to plate lines, word lines, a source line, odd-numbered bit lines, and even-numbered bit lines to hold, in a semiconductor base, a positive hole group generated by an impact ionization phenomenon or a gate-induced drain leakage current, and a data erase operation of controlling voltages to be applied to the plate lines, the word lines, the source line, the odd-numbered bit lines, and the even-numbered bit lines to discharge the positive hole group from the semiconductor base. The number of first blocks and the number of second blocks are variable in the memory device that is in operation.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
A memory device includes pages each constituted by a plurality of memory cells arranged in columns on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region in each memory cell included in each page are controlled to perform a page write operation of retaining a group of positive holes, generated by an impact ionization phenomenon or a gate-induced drain leakage current, inside a semiconductor body, the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region are controlled to perform a page erase operation of discharging the group of positive holes from inside the semiconductor body and further lowering a voltage of the semiconductor body with capacitive coupling with the first gate conductor layer and with the second gate conductor layer, and in the page erase operation, at least two or more pages are simultaneously selected from among the pages and the page erase operation is performed.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/4097 - Organisation de lignes de bits, p.ex. configuration de lignes de bits, lignes de bits repliées
This memory device includes a page composed of a plurality of memory cells arranged on a substrate in a columnar configuration as seen in a plan view, and hole groups generated by the impact ionization phenomenon are retained inside a channel semiconductor layer by controlling a voltage applied to a first gate conductor layer, a second gate conductor layer, a first impurity region and a second impurity region of each memory cell included in the page. The first impurity layer of the memory cell is connected to a source line, the second impurity layer is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to a word line, the other is connected to a plate line, and a page write operation, a page erase operation, and a page read operation are performed by applying a voltage to the source line, bit line, word line, and plate line. The hole groups formed by the impact ionization phenomenon are retained inside the channel semiconductor layer at a first timing during the page write operation, and a page post-write processing operation of annihilating a surplus hole group among the hole groups is performed at a second timing.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/10 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
A dynamic flash memory includes a p layer as a semiconductor base material; first and second n+ layers extending on opposite sides thereof; a first gate insulating layer partially covering the p layer; a first gate conductor layer provided thereon; a second gate insulating layer provided in contact with the first gate insulating layer and partially covering the p layer; and a second gate conductor layer provided on the second gate insulating layer and electrically isolated from the first gate conductor layer. The first and second n+ layers, and the first and second gate conductor layers are respectively connected to a source line, a bit line, a word line, and a plate line. A voltage applied to each terminal during memory erasing is always greater than or equal to 0 V such that 2 V and 0.6 V are respectively applied to the plate line and the bit line.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
The present invention is characterized in that, in a dynamic flash memory having a semiconductor parent p layer 1, an n+ layer 2 that is extended to one side, an n+ layer 3 that is adjacent to the p layer 1 on the opposite side, a first gate conductor layer 5 at which part of the p layer 1 is coated with a gate insulator layer 4 and which furthermore is adjacent thereto, and a second gate conductor layer 7 at which part of the p layer 1 is coated with a gate insulator layer 6 adjacent to the gate insulator layer 4 and which is electrically isolated from a gate electrode 5, the n+ layer 2, the n+ layer 3, and the gate conductor layers 5, 7 are connected to a source line, a bit line, a word line, and a plate line, and in that, during deletion in the memory, a voltage applied to terminals is normally 0 V or higher such that, e.g., 2 V is applied to the plate line and 0.6 V is applied to the bit line.
H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
A memory device includes pages each including memory cells arranged in columns in plan view on a substrate, and voltages applied to first and second gate conductor layers and first and second impurity regions in each memory cell are controlled to retain a group of positive holes, generated by an impact ionization phenomenon, inside a semiconductor body. The first and second impurity regions are connected to source and bit lines, the first and second gate conductor layers are connected to word and plate lines, and voltages applied to these lines are controlled to perform a page write operation, a page erase operation, and a page read operation. In the page write operation, the group of positive holes are retained inside the semiconductor body at a first time, and a page write post-processing operation of making a group of excess positive holes disappear is performed at a second time.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
29.
METHOD FOR PRODUCING MEMORY DEVICE USING PILLAR-SHAPED SEMICONDUCTOR ELEMENTS
Provided is dynamic flash memory for performing data write, read, and erase operations by controlling a voltage applied to each of a source line, a plate line, word lines, and bit lines. The memory is formed by forming on a substrate a first N+ layer, which connects to the source line, and second N+ layers, which connect to the bit lines, at opposite ends of Si pillars standing is the upright position along the vertical direction; and forming a SiO2 layer, which is located between a first TiN layer surrounding a first gate HfO2 layer surrounding the lower portion of the Si pillars, is continuous around the Si pillars, and connects to the plate line, and second TiN layers surrounding a second gate HfO2 layer surrounding the upper portion of the Si pillars and respectively connecting to the word lines, by oxidizing a doped semiconductor layer or conductor layer.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A first Si pillar and a second Si pillar are disposed above a substrate. The first Si pillar stands in a perpendicular direction. In plan view, the outer periphery line of the second Si pillar is located inside the outer periphery line of the first Si pillar. An N+ layer connected to a source line and an N+ layer connected to a bit line are disposed at both ends of the first and second Si pillars. A first gate insulating layer surrounds the first Si pillar. A first gate conductor layer surrounds the first gate insulating layer and is connected to a plate line. A second gate conductor layer surrounds a gate HfO2 layer surrounding the second Si pillar and is connected to a word line. Voltages applied to the source line, the plate line, the word line, and the bit line are controlled to perform a data hold operation of holding a group of holes generated by an impact ionization phenomenon or a gateinduced drain leakage current in a channel region of the Si pillar and a data erase operation of discharging the group of holes from the channel region.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A memory device according to the present invention includes memory cells each of which is formed of a semiconductor body that stands on a substrate in a vertical direction relative to the substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of the memory cell are controlled to perform a write operation of retaining a group of positive holes, generated by an impact ionization phenomenon or a gate-induced drain leakage current, inside a semiconductor body, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region are controlled to perform an erase operation of discharging the group of positive holes from inside the semiconductor body. The first impurity region of the memory cell is connected to a source line wiring layer, the second impurity region thereof is connected to a bit line wiring layer, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a word line wiring layer, and the other of the first gate conductor layer or the second gate conductor layer is connected to a first driving control line wiring layer, and in the vertical direction relative to the substrate, the source line wiring layer is connected to the first impurity region at a position lower than the first driving control line wiring layer and the word line wiring layer.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A semiconductor element memory device is configured to perform a data hold operation of controlling voltages to be applied to a plate line, a word line, a source line, and a bit line to hold, in a semiconductor base, a positive hole group formed by an impact ionization phenomenon or a gate-induced drain leakage current, and a data erase operation of controlling voltages to be applied to the plate line, the word line, the source line, and the bit line to discharge the positive hole group from the semiconductor base. The semiconductor element memory device includes a plurality of memory cells arranged in a matrix within a block, and constantly manages, using a controller circuit and a logical/physical conversion table, which physical block address of a dynamic flash memory corresponds to data stored in a logical block address.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G06F 12/02 - Adressage ou affectation; Réadressage
A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity region, and the second impurity region are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first impurity layer of the memory cell is connected to a source line, the second impurity layer thereof is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a word line, and the other of the first gate conductor layer or the second gate conductor layer thereof is connected to a first driving control line. In a page read operation, page data in a group of memory cells selected by the word line is read to sense amplifier circuits, and in at least one operation among the page write operation, the page erase operation, and the page read operation, a voltage applied to at least one of the source line, the bit line, the word line, or the first driving control line is controlled by a reference voltage generating circuit combined with a temperature-compensating circuit.
There is provided a columnar semiconductor memory device in which a data retention operation is performed in which voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region are controlled to retain a group of positive holes, generated by an impact ionization phenomenon or a gate-induced drain leakage current, inside a semiconductor body, and a data erase operation is performed in which the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region are controlled to discharge the group of positive holes from inside the semiconductor body and the voltage of the semiconductor body is lowered with capacitive coupling with the first gate conductor layer and capacitive coupling with the second gate conductor layer.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A data retention operation of holding positive hole groups generated by an impact ionization phenomenon or by a gate-induced drain leakage current in a semiconductor base body is performed by controlling voltages applied to plate lines, word lines, a source line, odd-numbered bit lines, and even-numbered bit lines; and a data erase operation is performed by removing positive hole groups from inside the semiconductor base body by controlling the voltages applied to plate lines, word lines, source line, odd-numbered bit lines, and even-numbered bit lines and lowering a voltage of The semiconductor base body by means of capacitive coupling between the plate lines and word lines. A block is made up of memory cells arrayed in a matrix, and storage data is read from the memory cells in the block alternately to the odd-numbered bit lines and even-numbered bit line.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A semiconductor-element-including semiconductor memory device includes a block in which a plurality of memory cells CL00 to CL13 are arranged in a matrix, in which a data retention operation is performed in which voltages applied to plate lines PL0 and PL1, word lines WL0 and WL1, a source line SL, and bit lines BL0 to BL3 are controlled to retain a group of positive holes, generated by an impact ionization phenomenon or a gate-induced drain leakage current, inside a semiconductor body, and a data erase operation is performed in which the voltages applied to the plate lines PL0 and PL1, the word lines WL0 and WL1, the source line SL, and the bit lines BL0 to BL3 are controlled to discharge the group of positive holes from inside the semiconductor body and the voltage of the semiconductor body is lowered with capacitive coupling with the plate lines PL0 and PL1 and capacitive coupling with the word lines WL0 and WL1. For the memory cells in the block, one or both of a memory re-write operation for the memory cells CL00, CL02, CL03, CL11, and CL13 that are in a state of the data retention operation and a memory re-erase operation for the memory cells CL01, CL10, and CL12 in a state of the data erase operation are performed for all of the memory cells in the block simultaneously.
G11C 16/16 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p.ex. des réseaux, des mots, des groupes
G11C 16/12 - Circuits de commutation de la tension de programmation
G11C 16/10 - Circuits de programmation ou d'entrée de données
A memory device uses semiconductor elements. By controlling voltages applied to plate lines, word lines, source lines, and bit lines, the memory device performs a data write operation of holding positive hole groups formed by an impact ionization phenomenon or by a gate-induced drain leakage current in a semiconductor base material, and a data erase operation of removing positive hole groups from inside the semiconductor base material. The memory device includes a block made up of memory cells, which are arrayed in a matrix. Storage data of memory cells connected with a first word line, i.e., a selected one of the word lines, in the block is read to the bit lines by applying a first voltage to the first word line, and a second voltage to a second word line adjacent to the first word line.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
38.
SEMICONDUCTOR ELEMENT MEMORY CELL AND SEMICONDUCTOR ELEMENT MEMORY DEVICE
By controlling voltages applied to plate lines, word lines, source lines, and bit lines, a memory device that uses semiconductor elements performs a data retention operation of holding positive hole groups formed by an impact ionization phenomenon or by a gate-induced drain leakage current in a semiconductor base material, and a memory erase operation of removing positive hole groups from inside the semiconductor base material. The memory device also performs a data erase operation during the memory erase operation to remove positive hole groups from inside the semiconductor base material of all the memory cells in a block made up of the memory cells, which are arrayed in a matrix.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
A memory apparatus includes a page including a plurality of memory cells arranged in a column on a substrate. Each of voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell included in the page is controlled to perform a page write operation of retaining holes, which have been formed through an impact ionization phenomenon or using a gate induced drain leakage current, in a semiconductor base material, or each of voltages applied to the first and second gate conductor layers, third and fourth gate conductor layers, and the first and second impurity layers is controlled to perform a page erase operation of removing the holes from the semiconductor base material, and to input page data for the page write operation to a sense amplifier circuit during the page erase operation.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A memory device includes pages including memory cells arranged on a substrate. Voltages applied to first and second gate conductor layers and first and second impurity regions in each memory cell are controlled to retain a group of positive holes. The first and second impurity regions and first and second gate conductor layers are connected to source, bit, plate, and word lines. In a page write operation, a channel semiconductor layer is at a first data retention voltage. In a page erase operation, the group of positive holes are discharged by controlling the voltages, the channel semiconductor layer is at a second data retention voltage, a positive voltage pulse is applied to at least one of the word and plate lines of a selected page, and a ground voltage is applied to the word and plate lines of a non-selected page and to all of the source and bit lines.
G11C 11/4097 - Organisation de lignes de bits, p.ex. configuration de lignes de bits, lignes de bits repliées
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
41.
PILLAR-SHAPED SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
A contact hole is formed on a boundary region between an N+ layer connected to a bottom part of a Si pillar forming a select transistor SGT and a P+ layer connected to a bottom part of a Si pillar forming a load transistor SGT on an X-X′ line and on a gate TiN layer surrounding a Si pillar forming a load transistor SGT on an XX-XX′ line in an SRAM cell. A conductor W layer is formed in a bottom part of the contact hole. A SiO2 layer including a hole is formed inside the contact hole on the W layer.
H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
This memory device comprises a page made of a plurality of memory cells arranged in columns, in plan view, on a substrate, wherein, during a page erase operation, voltages to be applied to a first impurity layer, a second impurity layer, a first gate conductor layer, and a second gate conductor layer are controlled to remove a hole group from one or both of the first impurity layer and the second impurity layer, and the voltage of a channel semiconductor layer is set to a second data retention voltage that is lower than a first data retention voltage. The first impurity layer is connected to a source line, the second impurity layer is connected to a bit line, the first gate conductor layer is connected to a plate line, and the second gate conductor layer is connected to a word line. During the page erase operation, a positive voltage pulse is applied to one or both of the word line and the plate line of the page that has been selected to be erased, a ground voltage is applied to the word line and the plate line of the page that has not been selected, and the ground voltage is applied to all the source line and the bit line.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/10 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
43.
MANUFACTURING METHOD OF PILLAR-SHAPED SEMICONDUCTOR DEVICE
P+ layers which entirely cover top parts of Si pillars and which surround the Si pillars at equal widths in a plan view are formed by self-alignment with the Si pillars, W layers are formed on the P+ layers, a band-shaped contact hole which is in contact with respective partial regions of the W layers and which extends in the Y direction is formed, and a supply wiring metal layer is formed by filling the band-shaped contact hole. The partial regions of the W layers are shaped so as to protrude to outside of the band-shaped contact hole in a plan view.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
H01L 29/66 - Types de dispositifs semi-conducteurs
44.
PILLAR-SHAPED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
In a method of forming a gate conductor layer which surrounds a semiconductor pillar, a first impurity region and a first mask material layer having oxidation resistance are respectively formed in a top part of a semiconductor pillar and on a side wall of the semiconductor pillar, thermal or chemical oxidation is performed on the entire stack, a first insulation layer is formed on the exposed surface of the first impurity region, the first mask material layer is removed, and a gate conductor layer is formed in an upper part of the first insulation layer.
H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/36 - Corps semi-conducteurs caractérisés par la concentration ou la distribution des impuretés
This semiconductor memory device comprises: a p layer 1 that is a semiconductor matrix; an n+ layer 2 that extends to one side; a second impurity layer n+ layer 3 that is in contact with the p layer 1 on the opposite side to the n+ layer 2; a first gate conductor layer 5 that covers a portion of the p layer 1 with a first gate insulating layer 4 and is in contact with the first gate insulating layer 4; and a second gate conductor layer 7 that is in contact with the gate insulating layer 4 and covers a portion of the p layer 1 with a second gate insulating layer 6 while being electrically isolated from the gate electrode 5, wherein voltages are applied to the n+ layer 2, the n+ layer 3, and the gate conductor layers 5 and 7 to perform memory operations. The semiconductor memory device is characterized in that a value obtained by dividing the impurity concentration of a region 1b by the gate capacitance of a MOS structure, which is formed by the gate conductor layer 7, the gate insulating layer 6, and the p layer 1, per unit area is larger than a value obtained by dividing the impurity concentration of a region 1a by the gate capacitance of a MOS structure, which is formed by the gate conductor layer 5, the gate insulating layer 4, and the p layer 1, per unit area at the time of the memory operations.
H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
A p layer extending in a direction horizontal to a substrate is provided separately from the substrate. An n+ layer and an n layer are provided on respective sides of the layer. A gate insulating layer partially covers the layers. A gate conductor layer partially covers the layer. A gate insulating layer partially covering the layer is provided separately from the layer. A gate conductor layer partially covers the layer. An n+ layer is provided at part of the p layer between the layers. The layers are connected to a bit line, a control line, a word line, a plate line, and a source line, respectively. Memory operation of a dynamic flash memory cell is performed by manipulating voltage of each line.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
The present invention comprises: a p layer 1 which extends in a horizontal direction with respect to a substrate 20, at a position away from the substrate 20; an n+ layer 2 which serves as a first impurity layer and is located on one side of the p layer 1; an n layer 8 which serves as a second impurity layer and is located on the other side of the p layer 1; a first gate insulating layer 4 which covers the p layer 1 and a part of the n+ layer 2; a first gate conductor layer 5 which covers a part of the gate insulating layer 4; a second gate insulating layer 6 which covers a part of the p layer 1, at a position away from the gate insulating layer 4; a second gate conductor layer 7 which covers a part of the gate insulating layer 6; an n+ layer 3 which serves as a third impurity layer and is located in a part of the p layer sandwiched between the gate conductor layer 5 and the gate conductor layer 7; and a dynamic flash memory cell which performs memory operation by connecting a bit line to the first impurity layer, a control line to the second impurity layer, a word line to the first gate conductor layer, a plate line to the second gate conductor layer, and a source line to the third impurity layer, and by controlling the respective voltages.
According to the present invention, on P layer stages 12a, 12b, which are connected in a belt shape in a first direction, N+ layers 2aa, 2bb, which are also connected in a belt shape in the first direction, and semiconductor columns 7a, 7b are formed when viewed in plan. In addition, a gate insulating layer 14 and gate conductor layers 15a, 15b are formed so as to surround the semiconductor columns 7a, 7b. A second conductor W layer 26a is formed in a second direction, which is perpendicular to the first direction, so as to be connected to the gate conductor layers 15a, 15b, while being separated from the P layer stages 12a, 12b when viewed vertically.
A p layer is a semiconductor base material. An n+ layer is disposed on one extension side. An n+ layer is disposed on the opposite side in contact with the p layer. A gate insulating layer partially covers the p layer. A first gate conductor layer contacts the insulating layer. A second gate conductor layer is electrically separated from the first gate conductor layer. Memory operation is performed by applying voltage to each of the layers. In the operation, the quotient of the impurity concentration of a region and the gate capacitance of a MOS structure constituted by the layers per unit area is larger than the quotient of the impurity concentration of a region and the gate capacitance of a MOS structure constituted by the layers per unit area.
This semiconductor memory device comprises: a plurality of bit line conductive layers that extend in a first direction in a horizontal plane on a surface of a semiconductor substrate; a plurality of semiconductor columns rising in a vertical direction on a bit line surface; an FET that has a source, a drain, and a base body in the semiconductor columns, and that has a gate that covers at least a part of the surface of the base body with an insulating film therebetween, the gate being composed of a conductor; and a plurality of word line conductive layers that are disposed over the surface of the semiconductor substrate and extend in a second direction in the horizontal plane different from the first direction. In the semiconductor memory device, at least one of the source and drain of the FET is connected to at least one of a plurality of bit lines, and the gate of the FET is connected to at least one of a plurality of word lines. In the plurality of word line conductive layers, at least one pair of adjacent word line conductive layers have different heights in the vertical direction on the semiconductor substrate. Because the adjacent word line conductive layers have different heights, it is possible to maintain a large distance between the word line conductive layers in the vertical direction even when the horizontal distance between memory cells is reduced, so that an increase in parasitic capacitance between the word line conductive layers can be suppressed.
H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
A p layer is a semiconductor base material. An n+ layer is disposed on one extension side of the layer. An n+ layer is disposed on the opposite side in contact with the layer. A gate insulating layer partially covers the layers. A gate conductor layer is disposed in contact with the layer. A gate insulating layer partially covers the layers. A gate conductor layer is disposed in electrical separation from the layer. Memory operation is performed by applying voltage to each of the layers. In this case, the gate capacitance of a MOS structure constituted by the layers per unit area is smaller than that of a MOS structure constituted by the layers.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
On a substrate Sub, a semiconductor base material (Si pillar) that stands on the substrate in a vertical direction or that extends along the substrate in a horizontal direction a first impurity layer and a second impurity layer that are disposed on respective ends of the semiconductor base material, a first gate conductor layer, and a second gate conductor layer that surround the semiconductor base material between the first impurity layer and the second impurity layer, and a channel semiconductor layer are disposed. Voltages are applied to perform a memory write operation of discharging a group of electrons from the channel semiconductor layer and retaining some of a group of positive holes in the channel semiconductor layer generated inside the channel semiconductor layer by a gate-induced drain leakage current, and a memory erase operation of discharging the group of positive holes retained in the channel semiconductor layer.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
According to the present invention, there is a p layer 1 that is a semiconductor matrix, there is an n+ layer 2 that extends to one side, there is a second impurity layer n+ layer 3 that is in contact with the p layer 1 on the side opposite from the n+ layer 2, there is a first gate conductor layer 5 that coats portions of the p layer 1 and the n+ layer 2 with a first gate insulating layer 4 and is in contact with the first gate insulating layer 4, there is a second gate conductor layer 7 that coats portions of the p layer 1 and the n+ layer 3 with a second gate insulating layer 6 and is electrically separated from the gate electrode 5, and voltages are respectively applied to the n+ layer 2, the n+ layer 3, and the gate conductor layers 5 and 7 to enable memory operations. The present invention is characterized in that the gate capacitance per unit area of a MOS structure formed at that time with the gate conductor layer 7, the gate insulating layer 6, and the p layer 1 is smaller than that of a MOS structure formed with the gate conductor layer 5, the gate insulating layer 4, and the p layer 1.
H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
The present invention comprises: a p layer 1 that extends in a direction horizontal to a substrate 20, at a position away from the substrate; an n+ layer 2 that serves as a first impurity layer and that is located on one side of the p layer; a first gate insulating layer 4 that covers the p layer 1 and a portion of the n+ layer 2; a first gate conductor layer 5 that covers a portion of the gate insulating layer 4; a second gate insulating layer 6 that covers a portion of the p layer 1, at a position away from the gate insulating layer 4; a second gate conductor layer 7 that covers a portion of the gate insulating layer 6; an n+ layer 3 that serves as a second impurity layer and that is located in a portion of the p layer sandwiched by the gate conductor layer 5 and the gate conductor layer 7; and a dynamic flush memory cell that performs memory operation by connecting a bit line to the first impurity layer, a source line to the second impurity layer, a word line to the first gate conductor layer, and a plate line to the second gate conductor layer, and by manipulating respective voltages therein.
H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
A p layer extending in a direction horizontal to a substrate is provided separately from the substrate. An n+ layer is provided on one side of the layer. A gate insulating layer partially covers the layers. A gate conductor layer partially covers the layer. A gate insulating layer partially covering the layer is provided separately from the layer. A gate conductor layer partially covers the layer. An n+ layer is provided at part of the p layer between the layers. The layers are connected to a bit line, a source line, a word line, and a plate line, respectively. Memory operation of a dynamic flash memory cell is performed by manipulating voltage of each line.
An N+ layer 11a connected to a source line SL, N+ layers 13a and 13c connected to a bit line BL1, and N+ layers 13b and 13d connected to a bit line BL2 are formed at both ends of Si pillars 12a to 12d standing on a substrate 10 in a perpendicular direction. Also formed are a TiN layer 18 surrounding a gate HfO2 layer surrounding the Si pillars 12a to 12d, the TiN layer 18 extending between the Si pillars 12a to 12d and connected to a plate line PL, and TiN layers 26a and 26b surrounding a gate HfO2 layer 17b surrounding the Si pillars 12a to 12d, the TiN layer 26a extending between the Si pillars 12a and 12b and connected to a word line WL1, the TiN layer 26b extending between the Si pillars 12c and 12d and connected to a word line WL2. The voltages applied to the source line SL, the plate line PL, the word lines WL1 and WL2, and the bit lines BL1 and BL2 are controlled to perform a data holding operation of holding a group of holes generated by an impact ionization phenomenon or a gate-induced drain leakage current in any or all of the Si pillars 12a to 12d and a data erase operation of removing the group of holes from the Si pillars 12a to 12d.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/51 - Matériaux isolants associés à ces électrodes
In the present invention, a first insulating layer 21 is provided on a substrate 20. Separate from the insulating layer are: a plurality of first impurity layers n+ layers 2 set apart in the horizontal direction and vertical direction with respect to the substrate; horizontally extending p layers 1 that contact the n+ layers 2; second impurity layer n+ layers 3 that contact the p layers 1; a second gate conductor layer 6 in which a portion of the p layers 1, n+ layers 2, and n+ layers 3 is covered by a gate insulating layer 4, said second gate conductor layer 6 being electrically isolated from a first gate conductor layer 5 that contacts gate insulating layer 4; a conductor layer 12 that contacts the plurality of n+ layers 2; a conductor layer 13 that contacts the plurality of n+ layers 3; a second insulating layer 22 that contacts the first gate conductive layer 5, the n+ layers 2, and the conductor layer 12; and a third insulating layer 23 that contacts the second gate conductive layer 6, the n+ layers 3, and the conductor layer 13.
H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
A first insulating layer 21 is disposed on a substrate 20. N+ layers 2 are separated from the insulating layer and in directions horizontal and vertical to the substrate. P layers 1 contact the n+ layers 2 and extend in the horizontal direction. N+ layers 3 contact the p layers 1. Gate insulating layers 4 cover the p layers 1 and part of the n+ layers 2 and 3. Second gate conductor layers 6 are electrically separated from a first gate conductor layer 5 contacting the gate insulating layers 4. A conductor layer 12 contacts the n+ layers 2. A conductor layer 13 contacts the n+ layers 3. A second insulating layer 22 contacts the first gate conductor layer 5, the n+ layers 2, and the conductor layer 12. A third insulating layer 23 contacts the second gate conductor layers 6, the n+ layers 3, and the conductor layer 13.
In the present invention, a memory device comprises a page composed of a plurality of memory cells arranged on a substrate in a columnar configuration as seen in plan view, said memory device controlling the voltage applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each of the memory cells included in the page, and a hole group generated by impact ionization being held inside a channel semiconductor layer. During a page writing operation, the voltage of the channel semiconductor layer is a first data retention voltage that is higher than the voltage of a first impurity layer and/or a second impurity layer. During a page erase operation: the voltages applied to the first impurity layer, the second impurity layer, a first gate conductor layer, and a second gate conductor layer are controlled; hole groups are extracted from the first impurity layer and/or the second impurity layer; and the voltage of the channel semiconductor layer is a second data retention voltage that is lower than the first data retention voltage. The first impurity layer is connected to a source line, the second impurity layer is connected to a bit line, the first gate conductor layer is connected to a plate line, and the second gate conductor layer is connected to a word line. The source line, the word line, and the plate line are arranged parallel to the page. The bit line is arranged perpendicularly with respect to the page. During the page erase operation, an erase voltage is applied to the page to be selectively erased, and a ground voltage is applied to the unselected pages.
H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
A memory device includes pages each including memory cells arranged on a substrate. Voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell are controlled to retain a group of positive holes. In a page write operation, a voltage of the channel semiconductor layer is made equal to a first data retention voltage. In a page erase operation, the group of positive holes are discharged by controlling the voltages, the voltage of the channel semiconductor layer is made equal to a second data retention voltage, and erase and ground voltages are applied to selected and non-selected pages respectively. The first and second impurity layers and first and second gate conductor layers are connected to source, bit, plate, and word lines. The source, word, and plate lines are disposed parallel to the pages. The bit line is disposed perpendicular to the pages.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
Si bodies 24aa to 24ad, 24ba to 24bd, and 45a to 45d are disposed parallel to a substrate 20 and are adjacent to each other in a horizontal direction at regular intervals. A HfO2 layer 27b surrounds the Si bodies 24aa to 45d. TiN layers 34a to 34d surround the HfO2 layer 27b, are isolated from each other, and are each formed of portions contiguous in the horizontal direction. The Si bodies 45a to 45d are formed stepwise in cross-sectional view in the terminating end in the horizontal direction. Metal wiring layers 52a to 52d are connected to the TiN layers 34a to 34d and extend up to above an insulating layer 50 through contact holes 51a to 51d extending in a vertical direction from the terminating ends of the TiN layers 34a to 34d. The metal wiring layers 52a to 52d are connected to word lines WL1 to WL4.
222 layers 27b are formed so as to be separated from each other, while being connected in the horizontal direction. The Si base materials 45a-45d, which are at an end in the horizontal direction, are formed in a stepped shape when viewed in cross section. Metal wiring layers 52a-52d, which are connected to gate TiN layers 34a-34d, are formed on an insulating layer 50 by the intermediary of contact holes 51a-51d that extend in the vertical direction on end parts of the gate TiN layers 34a-34d. The metal wiring layers 52a-52d are connected to word lines WL1-WL4 of a dynamic flash memory cell.
H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
A first insulating layer 1 is provided on a substrate 50. A first metal wiring layer 2 is embedded in the insulating layer. A second metal wiring layer 3 is in contact with the metal wiring layer 2 and extends in a direction perpendicular thereto. An n+ layer 5a that serves as a first impurity layer, is in contact with the metal wiring layer 3 and extends in the perpendicular direction, a semiconductor p layer 6 that is in contact with the n+ layer 5a and extends in the vertical direction, and an n+ layer 5b that serves as a second impurity layer are provided, and portions thereof are covered with a first gate insulating layer 7. A second gate conductor layer that is electrically isolated from a first gate conductor layer 8 and is in contact with the first gate insulating layer 7 is provided. A second insulating layer 10 covers portions of the n+ layer 5a, the n+ layer 5b, the first gate conductor layer 8, and the second gate conductor layer 9. Portions of the second impurity layer 5b and the second gate conductor layer are coated with a second insulating layer 11 that is in contact with the second insulating layer 10. A fourth metal wiring layer 13 is connected to the n+ layer 5b via a contact hole 12. A fifth metal wiring layer 14 is connected to the second gate conductor layer 9.
H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
64.
MEMORY DEVICE INCLUDING PILLAR-SHAPED SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING THE SAME
On P layer bases extending in a band shape in a first direction in plan view, N+ layers also extending in a band shape in the first direction and Si pillars are formed. Subsequently, a gate insulating layer and gate conductor layers are formed so as to surround the Si pillars. Subsequently, contact holes whose bottom portions are in contact with the N+ layers are formed in an insulating layer, and first conductor W layers are formed at the bottom portions of the contact holes. Subsequently, insulating layers each having a hole are formed in the contact holes. Subsequently, a second conductor W layer is formed in a second direction perpendicular to the first direction so as to be connected to the gate conductor layers.
According to the present invention, a dynamic flash memory cell and a fin transistor are formed on a P-layer substrate 10a. The dynamic flash memory cell comprises, on the P-layer substrate 10a: a first insulating layer 11a; a fin P-layer 25; N+layers 35ba, 35bb connected to both sides of the fin P-layer 25 in the longitudinal direction; a gate insulating layer 27b covering the fin P-layer 25; and gate conductor layers 30ba, 30bb covering the gate insulating layer 27b and separated from each other. The fin transistor comprises: a fin P-layer 22 composed of fin P-layers 15a, 15b the bottoms of which are present inside the P-layer substrate; N+ layers 35aa, 35ab connected to both sides of the fin P-layer 15a; a gate insulating layer 27a covering the fin P-layer 15a; and a gate conductor layer 30a covering the gate insulating layer 27a. In the vertical direction, the top position of the fin P-layer 25 is in the vicinity of or higher than the top position of the fin P-layer 15a, and the bottom positions of the gate insulating layers 27a, 27b are in the vicinity of each other, and the bottom position of the fin semiconductor layer 15b is in the P substrate 10a.
H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
66.
PILLAR-SHAPED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
On a semiconductor base that extends in a band shape in a direction (first direction) perpendicular to a line X-X′ direction (second direction) in plan view, an N+ layer, a P+ layer, and Si pillars that also extend in a band shape in the first direction are formed. Subsequently, a gate insulating layer and gate conductor layers are formed so as to surround the Si pillars. Subsequently, a contact hole whose bottom portion is in contact with the N+ layer and the P+ layer is formed in an insulating layer, and a first conductor W layer is formed at the bottom portion of the contact hole. Subsequently, an insulating layer that has a hole is formed in the contact hole. Subsequently, a second conductor W layer is formed in the line X-X′ direction so as to be connected to the gate conductor layers.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
In the present invention, a first insulating layer 1 is on a substrate 40, a first metal wiring layer 2 and a fourth metal wiring layer 3 are embedded in the insulating layer, a second metal wiring layer 4 abuts the metal wiring layer 2 and extends perpendicularly thereto, a first impurity layer (n+ layer) 5a abuts the second metal wiring layer 4 and extends perpendicularly thereto, a semiconductor p layer 6 and a second impurity layer (n+ layer) 5b abut the first impurity layer 5a and extend perpendicularly thereto, side surfaces of the first impurity layer 5a, the semiconductor p layer 6, and the second impurity layer 5b are partially covered by a first gate insulating layer 7, a first gate conductor layer 8 abuts the first gate insulating layer 7, the second impurity layer 5b is covered by a second insulating layer 9, and the n+ layer 5b is connected with a third metal wiring layer 10 via a contact hole 33. The fourth metal wiring layer 3 is connected to the gate conductor layer 8.
A dynamic flash memory cell and a fin transistor are formed on a P layer substrate 10a. The dynamic flash memory cell includes a first insulating layer 11a, a fin P layer 25, N+ layers 35ba and 35bb, a gate insulating layer 27b, and gate conductor layers 30ba and 30bb; the fin transistor includes a fin P layer 22 including fin P layers 15a and 15b, N+ layers 35aa and 35ab, a gate insulating layer 27a, and a gate conductor layer 30a; in a perpendicular direction, a top portion of the fin P layer 25 is positioned close to or higher than a top portion of the fin P layer 15a, bottom portions of the gate insulating layers 27a and 27b are positioned close to each other, and a bottom portion of the fin semiconductor layer 15b is positioned within the P layer substrate 10a.
Provided on a substrate are a first insulating layer; a first metal wire layer embedded therein; a second metal wire layer extending vertically on the first metal wire layer; a first n+ layer on the second metal wire layer, a semiconductor p layer on the first n+ layer, and a second n+ layer on the semiconductor p layer, each extending vertically; a gate insulating layer partially covering them; first and second electrically isolated gate conductor layers around the gate insulating layer; a second insulating layer partially covering the first and second n+ layers and the first and second gate conductor layers; a third insulating layer on the second insulating layer, partially covering the second n+ layer and the second gate conductor layer; and a fourth metal wire layer connecting to the second n+ layer via a contact hole. A fifth metal wire layer connects to the second gate conductor layer.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
70.
METHOD FOR MANUFACTURING MEMORY DEVICE INCLUDING PILLAR-SHAPED SEMICONDUCTOR ELEMENT
An N+ layer connected to a source line SL at both ends of individual Si pillars standing in a vertical direction; N+ layers connected to a bit line BL1; N+ layers connected to a bit line BL2; a TiN layer surrounding gate HfO2 layers surrounding the individual Si pillars, being continuous between the individual Si pillars, and connected to a plate line PL; a TiN layer surrounding gate HfO2 layers surrounding the four Si pillars, being continuous between the individual Si pillars, and connected to a word line WL1; and a TiN layer connected to a word line WL2 are formed on a substrate. Voltages to be applied to the source line SL, the plate line PL, the word lines WL1 and WL2, and the bit lines BL1 and BL2 are controlled to perform a data hold operation of holding, in any or all of the Si pillars, a positive hole group generated by an impact ionization phenomenon or a gate-induced drain-leakage current, and a data erase operation of discharging the positive hole group from the Si pillars.
An N+ layer and a P+ layer that are impurity regions at a bottom portion are formed using as etching masks top first mask material layers and SiN layers surrounding Si pillars and formed in a self-aligned manner with respect to the Si pillars and a SiO2 layer. Then, a SiO2 layer is formed that has an upper surface located at the level of the bottom portions of the N+ layer and the P+ layer. Then, a W layer is selectively formed on exposed side faces of the N+ layer and the P+ layer. Then, a contact hole for connection to a wire metal layer is formed above the W layer as seen in plan view.
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
A substrate has formed thereon a first semiconductor layer 1, a part of which has disposed thereon a first impurity layer 3 extending vertically, and a second semiconductor layer 4 is disposed on top of the first impurity layer. The side walls of the impurity layer and the second semiconductor layer, and the semiconductor layer 1 are covered with a first gate insulating layer 2, which has formed therein a groove in which a first gate conductor layer 22 and a second insulating layer 6 are formed. The second semiconductor layer 4 has disposed thereon: a third semiconductor layer 8 which has, on opposite sides thereof, an n+ layer 7a connected to a source line SL and an n+ layer 7b connected to a bit line BL, respectively; a second gate insulating layer 9 formed so as to cover the third semiconductor layer 8; and a second gate conductor layer 10 connected to a word line WL. The work function of the first gate conductor layer 22 at this case exhibits a numeral value higher than that of the second gate conductor layer 10. By controlling the voltages to be applied to the source line SL, a plate line PL that is connected to the first gate conductor layer 22, the word line WL, and the bit line BL, a data retention operation for retaining, in the vicinity of the gate insulating layers, a hole group generated in a channel region of the third semiconductor layer 8 by an impact ionization phenomenon or a gate-induced drain leakage current, and a data erasing operation for removing the hole group from the n layer 3, the n+ layer 7a, and the n+ layer 7b and removing some holes accumulated in a p layer 4 are carried out. It is characterized in that, during the data retention, the hole density of the second semiconductor layer 4 is higher than the hole density of the third semiconductor layer 8.
H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
On a substrate, a first semiconductor layer 1 is formed; from a portion of the layer 1, a first impurity layer 3 extends vertically, and a second semiconductor layer 4 is disposed on the layer 3; side walls of the layers 3 and 4 and the layer 1 are covered with a first gate insulating layer 2; in the resultant grooves, a first gate conductor layer 22 and a second insulating layer 6 are disposed; over the second semiconductor layer 4, layers are disposed that are a third semiconductor layer 8, an n+ layer 7a connecting to a source line SL and an n+ layer 7b connecting to a bit line BL that are disposed on both sides of the layer 8, a second gate insulating layer 9 formed so as to cover the layer 8, and a second gate conductor layer 10 connecting to a word line WL.
The present invention comprises: an N+layer 21 which is connected to a source line SL, N+layers 30a, 30b which are connected to a bit line BL1, and N+layers 30c, 30d which are connected to a bit line BL2, the layers being positioned at either end of Si columns 23a to 23d which vertically stand on a substrate 1 and are connected to the N+ layer 21; gate insulating layers 27a to 27d which surround the Si columns 23a to 23d; first gate conductor layers 28a, 28b which surround the gate insulating layers 27a to 27d and are connected to plate lines PL1, PL2; and second gate conductor layers 29a, 29b which are connected to word lines WL1, WL2. When perspectively viewed in cross sections along X1-X1' and X2-X2', the cross-sections of the Si columns 23a, 23c and the cross-sections of the Si columns 23b, 23d partially overlap with each other, respectively.
H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
An N+ layer 21 connected to a source line SL at both ends of Si pillars 23a to 23d standing in a vertical direction; N+ layers 30a and 30b connected to a bit line BL1; N+ layers 30c and 30d connected to a bit line BL2; the Si pillars 23a to 23d connected to the N+ layer 21; gate insulating layers 27a to 27d surrounding the Si pillars 23a to 23d; first gate conductor layers 28a and 28b surrounding the gate insulating layers 27a t 27d and connected to plate lines PL1 and PL2; and second gate conductor layers 29a and 29b connected to word lines WL1 and WL2 are disposed on a substrate 1. The Si pillars 23a and 23c have sections partially overlap each other in perspective view of the sections along line X1-X1′ and line X2-X2′, and the same applies to the Si pillars 23b and 23d.
This memory device is provided with a page comprising a plurality of memory cells arranged in columns on a substrate, and carries out: a page write operation for holding a hole group, which is formed by an impact-ionization phenomenon, inside a channel semiconductor layer by controlling voltages to be applied to a first gate conductor layer, a second gate conductor layer, a third gate conductor layer, a first impurity region and a second impurity region in each of the memory cells included in the page; and a page erase operation for deleting the hole group from the inside of the channel semiconductor layer by controlling the voltages to be applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the first impurity region and the second impurity region. The first impurity layer in the memory cells is connected to a source line, the second impurity layer is connected to a bit line, the first gate conductor layer is connected to a first selection gate line, the second gate conductor layer is connected to a drive control line, and the third gate conductor layer is connected to a second selection gate line. The bit line is connected to a sense amplifier circuit. The page data of a memory cell group selected in one or more pages is read out to the bit line during a page readout operation. A voltage of zero volts or less is applied during operation of the memory device to the drive control lines of the memory cells connected to an unselected page among the pages.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/10 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
This memory device comprises a page composed of a plurality of memory cells arranged in a column shape on a substrate, and controls voltages applied to a first gate conductive layer, a second gate conductive layer, a first impurity area, and a second impurity area of each of the memory cells included in the page, and performs a page writing operation that holds a hole group, which is formed by an impact ionization phenomenon, in a channel semiconductor layer. A first impurity layer in the memory cell is connected with a source line, a second impurity layer is connected with a bit line, the first gate conductive layer is connected with a word line, and the second gate conductive layer is connected with a driving control line. For the page writing operation and a page reading operation: the driving control line is turned into a zero-volt floating state by dropping the driving control line to 0 volts at a first reset time after the completion of both the operations and by separating the driving control line from a driving circuit at a second reset time after the first reset time; and the driving line is turned into a negative-volt floating state due to capacitive coupling between the word line and the driving control line by turning the word line into 0 volts at a third reset time after the second reset time.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/10 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
A memory device includes pages each composed of memory cells arrayed in columns on a substrate. A page write operation of retaining a hole group formed by impact ionization inside a channel semiconductor layer, and a page erase operation of discharging the hole group from the channel semiconductor layer are performed. A first impurity layer is connected to a source line, a second impurity layer to a bit line, a first gate conductor layer to a first selection gate line, a second gate conductor layer to a drive control line, a third gate conductor layer to a second selection gate line, and a bit line to a sense amplifier circuit. Page data of a memory cell group selected in at least one page is read to the bit line. Zero volts or less is applied to the drive control line of the memory cell connected to an unselected page.
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A memory device includes pages each constituted by memory cells, and a page write operation and a page erase operation are performed. First and second impurity layers and first and second gate conductor layers in each memory cell is connected to a source line, a bit line, a word line, and a driving control line. In a page read operation, page data is read. In the page write and read operations, a selected driving control line is lowered to zero volt at a first reset time, the driving control line is isolated from a driving circuit at a second reset time, thereby putting the driving control line in a zero-volt floating state, and a selected word line is set at zero volt at a third reset time, thereby putting the driving control line in a negative-voltage floating state by capacitive coupling between the word line and the driving control line.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
G11C 16/24 - Circuits de commande de lignes de bits
This memory device is provided with a page formed from multiple memory cells arranged in columns on a substrate, and carries out: a page write operation for holding a hole group, which is formed by an impact-ionization phenomenon, inside a channel semiconductor layer by controlling voltages to be applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each of the memory cells included in the page; and a page erase operation for removing the hole group from the inside of the channel semiconductor layer by controlling voltages to be applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region. The first impurity layer of each of the memory cells is connected to a source line, the second impurity layer is connected to a bit line, the first gate conductor layer is connected to a word line, and the second gate conductor layer is connected to a drive control line. The bit line is connected to a sense amplifier circuit. During a page read operation, page data of a memory cell group selected in at least one page is read to the bit line. A voltage of zero volts or less is applied to the drive control lines of the memory cells connected to the unselected pages among the pages during operation of the memory device.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/10 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
A memory device includes pages each constituted by memory cells, and a page write operation of retaining a group of positive holes, inside a channel semiconductor layer, generated by an impact ionization phenomenon by controlling voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell and a page erase operation of discharging the group of positive holes by controlling the voltages are performed. The first and second impurity layers and the first and second gate conductor layers of each memory cell is connected to a source line, a bit line connected to a sense amplifier circuit, a word line, and a driving control line respectively. In a page read operation, page data in a selected page is read to the bit lines. To the driving control line connected to a non-selected page, a voltage of zero volt or lower is applied.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
G11C 16/24 - Circuits de commande de lignes de bits
82.
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE
A Si pillar is formed in a memory region. A TiN layer to be connected to a plate line and a TiN layer to be connected to a word line are formed to extend in a horizontal direction, bend upward from the horizontal direction to a vertical direction in a memory region peripheral portion, and have upper surfaces on a same plane. The TiN layers are connected to metal wiring layers via contact holes formed on the upper surfaces thereof. A memory operation is performed by storing or not storing a group of holes generated by an impact ionization phenomenon in the Si pillar by controlling voltages to be applied to a source line, the plate line, the word line, and a bit line.
An Si column 33 is formed in a memory region. Around the Si column 33, a TiN layer 25A connecting to a horizontally extending plate PL and a TiN layer 27A connecting to a word line WL bend vertically upward in a peripheral portion of the memory region, and form upper surfaces in the same plane. The TiN layers 25A, 27A are connected to metal wiring layers 42, 49 via contact holes 41, 46 formed in the upper surfaces. A memory operation is performed by accumulating or not accumulating a group of holes formed by an impact ion phenomenon in the Si column 33 due to voltages applied to a development source line SL, a plate line PL, the word line WL, and a bit line BL.
A dynamic flash memory is formed by steps of laminating a first insulating layer, a first material layer, a second insulating layer, a second material layer, a third insulating layer, a third material layer, and a fourth material layer on a first impurity layer on a P-layer substrate 11, forming a first hole penetrating these layers on the P-layer substrate 11, filling the first hole with a semiconductor to form a semiconductor pillar 22, removing the first material layer, the second material layer, and the third material layer to form a second hole, a third hole, and a fourth hole, oxidizing a surface layer of the semiconductor pillar 22 exposed inside the second hole, the third hole, and the fourth hole to form first gate insulating layers 25a, 25b, and 25c, and filling the second hole, the third hole, and the fourth hole to form a first gate conductor layer 26aa, a second gate conductor layer 26ba and a third gate conductor layer 26ca.
A dynamic flash memory is formed by stacking, on a first impurity layer on a P-layer substrate, a first insulating layer, a first material layer, a second insulating layer, a second material layer, a third insulating layer, a third material layer, and a fourth material layer, forming a first hole penetrating these layers on the P-layer substrate, forming a semiconductor pillar by embedding the first hole with a semiconductor, removing the first, second, and third material layers to form second, third, and fourth holes, by oxidizing an outermost surface of the semiconductor pillar exposing in the second, third, and fourth holes to form first, second, and third gate insulating layers, and forming first, second, and third gate conductor layers embedded in the second, third, and fourth holes.
The present invention forms a dynamic flash memory, and has: a step for laminating a first insulating layer, a first material layer, a second insulating layer, a second material layer, a third insulating layer, and a third material layer on a first impurity layer on a P layer substrate 11; a step for forming a first hole penetrating through the stated layers on the P layer substrate 11; a step for filling the first hole and forming a semiconductor column 22; a step for removing the first and second material layers and forming second and third holes; a step for oxidizing the surface layer of the semiconductor column 22 exposed in the second and third holes and forming first gate insulating layers 25a, 25b; and a step for filling the second and third holes and forming first and second gate conductor layers 26aa, 26ba.
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 27/10 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A dynamic flash memory cell is formed by: stacking a first insulating layer, a first material layer, a second insulating layer, a second material layer, a third insulating layer, and a third material layer on a first impurity layer on a P-layer substrate; making a first hole that extends through the insulating layers and the material layers formed on the P-layer substrate; forming a semiconductor pillar by filling the first hole; making a second hole and a third hole by removing the first material layer and the second material layer; forming a first gate insulating layer and a second gate insulating layer by oxidizing a surface layer of the semiconductor pillar exposed inside the second hole and inside the third hole; and forming a first gate conductor layer and a second gate conductor layer by filling the second hole and the third hole.
The present invention provides a method for producing an SGT, the method comprising: a step for depositing a multilayer film, which comprises a dummy gate film for a replacement gate, on a semiconductor substrate; a step for forming a hole which penetrates the multilayer film and reaches the surface of the semiconductor substrate; a step for forming a dummy gate insulating film on the inner wall of the hole; a step for growing a semiconductor column within the hole; a step for forming a source/drain by implanting or diffusing an impurity of one conductivity type using the dummy gate insulating film and the dummy gate film as a mask; a step for forming an etching mask that covers the upper surface of the semiconductor column, a part of the lateral surface of the semiconductor column positioned above the upper surface of the dummy gate film, and a part of the lateral surface of the semiconductor column positioned below the lower surface of the dummy gate film; and a step for replacing the dummy gate film and the dummy gate insulating film with a gate insulating film and a gate metal film. The present invention enables the achievement of a self-aligned source/drain structure and a high dielectric constant film/metal gate (HKMG) structure at the same time.
This memory device is provided with a page formed from multiple memory cells arranged in columns on a substrate, and sets, during a page write operation, the voltage of a channel semiconductor layer to a first data retention voltage by controlling voltages to be applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each of the memory cells included in the page. During a page erase operation, the device sets the voltage of the channel semiconductor layer to a second data retention voltage which is lower than the first data retention voltage by controlling the voltages to be applied to the first impurity region, the second impurity region, the first gate conductor layer, and the second gate conductor layer. At a second time point when time has passed from the first time point, the device carries out a memory re-erase operation of a semiconductor matrix in the page where the voltage of the channel semiconductor layer was equal to the second data retention voltage at the first time point, and carries out a first refresh operation to return the voltage of the channel semiconductor layer substantially to the second data retention voltage. At a third time point when time has passed from the second time point, the device carries out a memory rewrite operation of a semiconductor matrix in the page where the voltage of the channel semiconductor layer was equal to the first data retention voltage at the first time point, and carries out a second refresh operation to return the voltage of the channel semiconductor layer substantially to the first data retention voltage.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/10 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
A memory device according to the present invention is provided with a page which is composed of a plurality of memory cells that are arranged in columns on a substrate. This memory device performs: a page write operation for holding a hole group, which is formed by an impact ionization phenomenon, inside a channel semiconductor layer by controlling voltages to be applied to a first gate conductor layer, a second gate conductor layer, a third gate conductor layer, a first impurity region and a second impurity region of each of the memory cells contained in the page; and a page erase operation for removing the hole group from the inside of the channel semiconductor layer by controlling the above-described voltages. The first impurity region is connected to a source line; the second impurity region is connected to a bit line; the first gate conductor layer is connected to a first plate line; the second gate conductor layer is connected to a second plate line; and the third gate conductor layer is connected to a word line. The page erase operation is performed without inputting a positive/negative bias pulse to the bit line and the source line.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/10 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
A memory device includes pages each constituted by memory cells on a substrate. Voltages applied to first and second gate conductor layers and impurity layers in each memory cell are controlled to retain positive holes inside a channel semiconductor layer. In a page write operation, the voltage of the channel semiconductor layer is set to a first data retention voltage. In a page erase operation, the applied voltages are controlled to discharge the positive holes, and the voltage of the channel semiconductor layer is set to a second data retention voltage. At a second time after a first time, a memory re-erase operation is performed for the channel semiconductor layers at the second data retention voltage at the first time. At a third time after the second time, a memory re-write operation is performed for the channel semiconductor layers at the first data retention voltage at the first time.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 16/24 - Circuits de commande de lignes de bits
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
A groove is formed in a first semiconductor layer 1, a sidewall of the groove is coated with a first insulating film 2, a first impurity layer 3 and a second impurity layer 4 thereon are disposed in the groove, a second semiconductor layer 7 is disposed on the second impurity layer, a first semiconductor is disposed at the other part, an n+ layer 6a and an n+ layer 6c are positioned at respective ends of the second semiconductor layer 7 and connected to a source line SL and a bit line BL, respectively, a first gate insulating layer 8 is formed on the second semiconductor layer 7, and a first gate conductor layer 9 is connected to a word line WL. Voltage applied to the source line SL, a plate line PL connected to the first semiconductor layer 1, the word line WL, and the bit line BL is controlled to perform data holding operation of holding, near the gate insulating layer, holes generated by an impact ionization phenomenon in a channel region 12 of the second semiconductor layer or by gate-induced drain leakage current, and data erase operation of removing the holes from the channel region 12.
This memory device is provided with a page formed from multiple memory cells arranged in columns on a substrate, and carries out: a page write operation for holding a hole group, which is formed by an impact-ionization phenomenon, inside a channel semiconductor layer by controlling voltages to be applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each of the memory cells included in the page; and a page erase operation for removing the hole group from the inside of the channel semiconductor layer by controlling voltages to be applied to the first gate conductor layer, the second gate conductor layer, a third gate conductor layer, a fourth gate conductor layer, the first impurity region, and the second impurity region. The first impurity region of each of the memory cells is connected to a source line; the second impurity region is connected to a bit line; and one of the first gate conductor layer and the second gate conductor layer is connected to a word line, and the other to a drive control line. At the time of a page read operation, a refresh operation is carried out at least once prior to the page read operation of a memory cell group which is selected by using any of the word lines.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/10 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
A memory device includes a page constituted by multiple memory cells arranged in a row form on a substrate, and performs a page write operation of controlling voltages to be applied to first and second gate conductor layers and first and second impurity layers of each memory cell included in the page to hold a positive hole group formed by an impact ionization phenomenon inside a channel semiconductor layer; During a page read operation, page data of a memory cell group selected with the word line is read to the sense amplifier circuit, and a refresh operation is performed at least once before the page read operation to hold a positive hole group formed by an impact ionization phenomenon inside a channel semiconductor layer.
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
In the present invention, a first semiconductor layer 1 is formed on a substrate; a vertically extending first impurity layer 3 and a second impurity layer 4 disposed on top of the first impurity layer are provided on a part of the first semiconductor layer; side walls of the impurity layers and the semiconductor layer 1 are covered with a third gate insulating layer 2; in a groove formed thereby, a first gate conductor layer 22a, a second gate conductor layer 22b, and a second insulating layer are disposed; and a second semiconductor layer 7, an n+layer 6a connected to a source line SL and an n+ layer 6b connected to a bit line BL which are arranged on both ends of the second semiconductor layer, a second gate insulating layer 8 formed to cover the second semiconductor layer 7, and a third gate conductor layer 9 connected to a word line WL are disposed on top of the second impurity layer. The memory device carries out a data hold operation for holding a hole group, which is generated in a channel region of the second semiconductor layer by an impact ionization phenomenon or by a gate-induced drain leakage current, in the vicinity of the gate insulating layers and a data erase operation for removing the hole group from the inside of the channel region 12 by controlling voltages to be applied to the source line SL, a plate line PL1 connected to the first gate conductor layer 22a, a plate line PL2 connected to the second gate conductor layer 22b, the word line WL, and the bit line BL.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 11/39 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des thyristors
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques
H01L 21/8242 - Structures de mémoires dynamiques à accès aléatoire (DRAM)
H01L 27/10 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
First and second impurity layers are formed on a first semiconductor layer on a substrate. A third gate insulating layer covers side walls of the impurity layers and the first semiconductor layer. First and second gate conductor layers and a second insulating layer are formed in a groove, and n+-layers connected to source and bit lines are formed at ends of a second semiconductor layer formed on the second impurity layer and covered with a second gate insulating layer, on which a third gate conductor layer connected to a word line is formed. An operation of maintaining holes generated in a channel region of the second semiconductor layer by impact ionization or a GIDL current near the gate insulating layer and an operation of discharging the holes from the channel region are performed by controlling voltages applied to the source, bit, and word lines and first and second plate lines.
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
G11C 11/404 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec une porte à transfert de charges, p.ex. un transistor MOS, par cellule
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
97.
METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT-INCLUDING MEMORY DEVICE
An N+ layer 11a and N+ layers 13a to 13d that are disposed on both ends of Si pillars 12a to 12d standing on a substrate 10 in a vertical direction, a TiN layer 18a that surrounds a gate HfO2 layer 17a surrounding the Si pillars 12a to 12d and that extends between the Si pillars 12a and 12b, a TiN layer 18b that surrounds the gate HfO2 layer 17a and that extends between the Si pillars 12c and 12d, a TiN layer 26a that surrounds a gate HfO2 layer 17b surrounding the Si pillars 12a to 12d and that extends between the Si pillars 12a and 12b, and a TiN layer 26b that surrounds the gate HfO2 layer 17b and that extends between the Si pillars 12c and 12d are formed. Voltages applied to the N+ layers 11a and 13a to 13d and the TiN layers 18a, 18b, 26a, and 26b are controlled to perform a data write operation of retaining, inside the Si pillars 12a to 12d, a group of positive holes generated by an impact ionization phenomenon and a data erase operation of discharging the group of positive holes from the inside of the Si pillars 12a to 12d.
This memory device comprises: a first impurity layer 3 and a second impurity layer 4 provided thereon in a trench which is formed in a first semiconductor layer 1 and the side walls of which are covered with a first insulating film 2; a second semiconductor layer 7 on the second impurity layer; a first semiconductor in other portions; an n+layer 6a connected to source lines SL present at both ends of the second semiconductor layer; an n+ layer 6c connected to a bit line BL; a first gate insulating layer 8 formed on the second semiconductor layer 7; and a first gate conductor layer 9 connected to a word line WL. By controlling a voltage applied to the source lines SL, a plate line PL connected to the first semiconductor layer 1, the word line WL, and the bit line BL, a data retention operation for retaining a hole group, which is generated by an impact ion phenomenon in a channel region 12 of the second semiconductor layer or a gate-induced drain leak current, in the vicinity of the gate insulating layer and a data erasing operation for removing the hole group from the channel region 12 are performed.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques
c positioned at respective ends of the layer 7 and connected to a source line SL and a bit line BL, respectively, a second gate insulating layer 8 formed to cover the second semiconductor layer 7, and a second gate conductor layer 9 connected to a word line WL are disposed on the second impurity layer. Voltage applied to the source line SL, a plate line PL connected to the first gate conductor layer 22, the word line WL, and the bit line BL is controlled to perform data holding operation of holding, near the gate insulating layer, holes generated by an impact ionization phenomenon in a channel region of the second semiconductor layer or by gate-induced drain leakage current, and data erase operation of removing the holes in the channel region 12.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
G11C 11/39 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des thyristors
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
The present invention proposes a columnar semiconductor manufacturing method that is applicable to both of a CSGT mainly used for a memory cell and an ESGT used for a peripheral circuit. In the case of a highly integrated CSGT, the CSGT is formed in a position where strip-shaped side walls overlap each other, the side walls being used twice in total for patterning in an X direction and a Y direction that are orthogonal to each other and being formed in each of the patterning in the X direction and the patterning in the Y direction. In the case of an ESGT, two rectangular-frame-shaped side walls are formed in desired positions, and the ESGT is formed in a position where the side walls overlap each other. This makes it possible to form both of a CSGT and an ESGT by using the same manufacturing process and the same manufacturing conditions.
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 21/8244 - Structures de mémoires statiques à accès aléatoire (SRAM)
H01L 27/11 - Structures de mémoires statiques à accès aléatoire
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
