The present disclosure provides a data processing apparatus and related products. The products include a control module including an instruction caching unit, an instruction processing unit, and a storage queue unit. The instruction caching unit is configured to store computation instructions associated with an artificial neural network operation; the instruction processing unit is configured to parse the computation instructions to obtain a plurality of operation instructions; and the storage queue unit is configured to store an instruction queue, where the instruction queue includes a plurality of operation instructions or computation instructions to be executed in the sequence of the queue. By adopting the above-mentioned method, the present disclosure can improve the operation efficiency of related products when performing operations of a neural network model.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
2.
DATA PROCESSING METHOD AND APPARATUS, AND RELATED PRODUCT FOR INCREASED EFFICIENCY OF TENSOR PROCESSING
A data processing method includes obtaining content of a descriptor when an operand of a first processing instruction includes the descriptor, where the descriptor is configured to indicate a shape of tensor data and to indicate data address of the tensor data, and executing the first processing instruction according to the content of the descriptor by determining the data address of the tensor data corresponding to the operand of the first processing instruction in a data storage space, according to the content of the descriptor, and according to the data address, executing data processing corresponding to the first processing instruction.
The present disclosure provides a data processing method and an apparatus and a related product. The products include a control module including an instruction caching unit, an instruction processing unit, and a storage queue unit. The instruction caching unit is configured to store computation instructions associated with an artificial neural network operation; the instruction processing unit is configured to parse the computation instructions to obtain a plurality of operation instructions; and the storage queue unit is configured to store an instruction queue, where the instruction queue includes a plurality of operation instructions or computation instructions to be executed in the sequence of the queue. By adopting the above-mentioned method, the present disclosure can improve the operation efficiency of related products when performing operations of a neural network model.
An integrated circuit apparatus may be included in a computing processing apparatus of a combined processing apparatus. The computing processing apparatus includes one or a plurality of integrated circuit apparatuses. The combined processing apparatus may further include an interface apparatus and other processing apparatus. The computing processing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus further includes a storage apparatus. The storage apparatus is connected to the apparatus and other processing apparatus, respectively. The storage apparatus is used to store data of the apparatus and other processing apparatus. The solution of the present disclosure may reduce the amount of data transferred between an internal device and an external storage apparatus, thus minimizing the I/O bottleneck caused by bandwidth limitations and then improving the overall performance of the integrated circuit apparatus.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
5.
DEVICE AND METHOD FOR NEURAL NETWORK COMPUTING, AND BOARD AND READABLE STORAGE MEDIUM
The present disclosure relates to an apparatus and a method for performing neural network computing, a board card, and a readable storage medium. The computing apparatus of the present disclosure is included in an integrated circuit apparatus. The integrated circuit apparatus includes a general interconnection interface and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The integrated circuit apparatus further includes a storage apparatus. The storage apparatus is connected to the computing apparatus and other processing apparatus, respectively. The storage apparatus is used for data storage of the computing apparatus and other processing apparatus.
The present disclosure relates to an apparatus and a method for forward fusing a neural network, a board card, and a readable storage medium. The computing apparatus of the present disclosure is included in an integrated circuit apparatus. The integrated circuit apparatus includes a general interconnection interface and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The integrated circuit apparatus further includes a storage apparatus. The storage apparatus is connected to the computing apparatus and other processing apparatus, respectively. The storage apparatus is used for data storage of the computing apparatus and other processing apparatus.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
The present disclosure discloses an integrated computing apparatus, a machine learning computing apparatus, a neural network chip, a board card, an electronic device, and a method. The integrated computing apparatus is included in a combined processing apparatus. The combined processing apparatus further includes an interface apparatus and other processing apparatus. The integrated computing apparatus interacts with other processing apparatus to jointly complete a user-specified computing operation. The combined processing apparatus further includes a storage apparatus. The storage apparatus is connected to the integrated computing apparatus and other processing apparatus, respectively. The storage apparatus is used to store data of the integrated computing apparatus and other processing apparatus. The solution of the present disclosure starts and/or shuts down circuits in accordance with a predetermined rule, thus avoiding excessive transient current caused by starting the circuits at the same time.
A method for video encoding, a method for video decoding, and a related product. The method may be comprised in a combined processing apparatus (800), and the combined processing apparatus (800) may further comprise a universal interconnection interface (804) and other processing apparatuses (806). A computing apparatus (802) interacts with the other processing apparatuses (806), so as to jointly complete a computing operation, which is specified by a user. The combined processing apparatus (800) may further comprise a storage apparatus (808), wherein the storage apparatus (808) is connected both to a device and the other processing apparatuses (806) and is used for storing data of the device and the other processing apparatuses (806). By means of the described technical solution, the compression efficiency of a video can be significantly improved.
A neural network processing method, comprising the following steps: obtaining a model dataset and model structure parameters of an original network (S100); obtaining an operational attribute of each compute node in the original network; operating the original network according to the model dataset and the model structure parameters of the original network and the operational attribute of each compute node, to obtain an instruction corresponding to each compute node in the original network (S200); and if the operational attribute of the current compute node is a first operational attribute, storing a network weight and the instruction corresponding to the current compute node into a first non-volatile memory, so as to obtain a first offline model corresponding to the original network (S300). Further provided are a computer system and a storage medium. The neural network processing method, the computer system, and the storage medium shorten the time for a processor to operate the same network, and improve the processing speed and efficiency of the processor.
The present invention relates to the field of artificial intelligence chips, and specifically relates to a neural network computation method and a related device. A computation device of the present application comprises a processor, a communication interface, and other processing devices. The processor and the communication interface are communicatively connected to each other by means of bus to jointly complete a computation operation specified by a user. The computation device can further comprise a storage device. The storage device is separately connected to the processor and other processing devices, and is used for data storage for the computation device and other processing devices. In the present application, pendulum type conversion is executed at most with respect to an input of an operator on the basis of an input pendulum type and a target pendulum type, such that unnecessary pendulum type conversions during a computation process can be reduced, thereby reducing memory overhead, and improving computation efficiency.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
A computation graph optimization method, a data processing method, a computing apparatus, a computer-readable storage medium and a computer program product. The computing apparatus for executing a computation graph optimization method may be comprised in a combined processing apparatus, and the combined processing apparatus may further comprise an interface apparatus and other processing apparatuses. The computing apparatus interacts with the other processing apparatuses, so as to jointly complete a computing operation specified by a user. The combined processing apparatus may further comprise a storage apparatus, and the storage apparatus is connected to the computing apparatus and the other processing apparatuses and is used for storing data of the computing apparatus and the other processing apparatuses. According to the present solution, constructing a view-type operator subgraph can optimize the data memory access. Furthermore, optimizing the view-type operator subgraph can reduce the carrying of a device-end memory and the calling of an operator. Furthermore, backward deduction is performed to obtain a view-type operator which causes tensor data to change into in a memory non-continuous state, such that a suitable computing library operator can be called, so as to convert the tensor data into a memory continuous state, thereby reducing the data carrying of the device-end memory.
An integrated circuit chip apparatus and a processing method performed by an integrated circuit chip apparatus are disclosed. The disclosed integrated circuit chip apparatus and processing method are used for executing a multiplication operation, a convolution operation, or a training operation of a neural network. The present technical solution has the advantages of a reduced computational cost and low power consumption.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p.ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G06N 3/06 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
Provided are an integrated circuit chip apparatus and a related product, the integrated circuit chip apparatus being used for executing a multiplication operation, a convolution operation or a training operation of a neural network. The present technical solution has the advantages of a small amount of calculation and low power consumption.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p.ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G06N 3/06 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
An integrated circuit chip device and related products are provided. The integrated circuit chip device is used for performing a multiplication operation, a convolution operation, or a training operation of a neural network. The device has the advantages of small calculation amount and low power consumption.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
Disclosed in the present disclosure are a computing device for performing a binary operation of multi-dimensional data, a method for performing a binary operation by using the computing device, and a related product. The computing device may be comprised in a combined processing device. The combined processing device further comprises an interface device and another processing device. The computing device interacts with the another processing device to jointly complete a computing operation that is designated by a user. The combined processing device may further comprise a storage device. The storage device is respectively connected to the computing device and the another processing device, and is used for storing data of the computing device and the another processing device. According to the solution of the present disclosure, by reasonably allocating the loading frequency of operation data, the number of times of data exchange and loading can be reduced, the throughput pressure is relieved, and the processing efficiency of a machine is improved. Fig. 2
Provided in the embodiments of the present application are a graph task scheduling method, an execution-end device, a storage medium, and a program product. By means of the technical means of determining a task execution state of the previous task which has a dependency relationship with the current task, determining, according to the task execution state of the previous task and a task execution state of the current task, whether to execute the current task, and if so, updating the task execution state of the current task after the execution of the current task is finished, an execution-end device can directly acquire the task execution state of the previous task of the current task before executing the current task; and graph task scheduling processing of the execution-end device is implemented, such that there is no need for a host-end device to perform task scheduling for the task execution of the execution-end device, thereby reducing communication overheads, and improving the task running efficiency.
The present disclosure relates to a data quantization processing method and apparatus, an electronic device, and a storage medium. The apparatus includes a control unit having an instruction caching unit, an instruction processing unit, and a storage queue unit. The instruction caching unit is configured to store a calculation instruction associated with an artificial neural network operation, the instruction processing unit is configured to parse the calculation instruction to obtain a plurality of operation instructions, and the storage queue unit is configured to store an instruction queue. The instruction queue includes a plurality of operation instructions or calculation instructions to be executed in an order of the queue. The above-mentioned method improves the operation precision of related products during a neural network model operation.
An embodiment of the present disclosure provides an operation apparatus which includes a storage unit, a control unit and a compute unit. The technical solution provided in this disclosure can reduce resource consumption of convolution operation, improve the speed of convolution operation and reduce operation time.
The present disclosure provides a winograd convolution operation method, a winograd convolution operation apparatus, a device, and a storage medium. The apparatus includes: processors and a memory, where the memory is configured to store a program code, and the processors are configured to call the program code stored in the memory and execute the operation method. Through the operation method, a system, the device and the storage medium of the present disclosure, performance loss of a computer system may be reduced, and operation speed may be improved. Through the present disclosure, processing efficiency may be improved.
Provided in the present disclosure are a method and system for sorting data in single-core and multi-core processors. The system and method may be involved in a combined processing apparatus, and the combined processing apparatus may further comprise a universal interconnection interface and another processing apparatus. A computing apparatus interacts with the other processing apparatus to jointly complete a computing operation designated by a user. The combined processing apparatus may further comprise a storage apparatus, which is respectively connected to a device and the other processing apparatus, and is used for storing data of the device and the other processing apparatus. By means of the solution of the present disclosure, the running efficiency of operations can be improved in various fields of data processing including, for example, the field of artificial intelligence, thereby reducing the overall overheads and costs for operations.
This disclosure relates to a data processing method, a data processing apparatus, and related products. The products include a control unit. The control unit includes: an instruction caching unit, an instruction processing unit, and a storage queue unit. The instruction caching unit is used for storing a calculation instruction associated with an artificial neural network computation; the instruction processing unit is used for parsing the calculation instruction to obtain a plurality of computation instructions; and the storage queue unit is used for storing an instruction queue, where the instruction queue includes the plurality of computation instructions or calculation instructions to be executed according to a front-back sequence of a queue. Through the above method of this disclosure, computation efficiency of the related products during a neural network model computation may be improved.
The present invention relates to a device for optimizing parameters of a deep neural network. The device of the present invention is comprised in an integrated circuit apparatus, the integrated circuit apparatus comprising a universal interconnection interface and other processing apparatuses. A computing apparatus interacts with the other processing apparatuses to jointly complete a computing operation specified by a user. The integrated circuit apparatus may further comprise a storage apparatus. The storage apparatus is separately connected to the computing apparatus and the other processing apparatuses for storing data of the device apparatus and the other processing apparatuses.
Provided are a method and system for fusing operators of a neural network. The system and method may be comprised in a combined processing apparatus. The combined processing apparatus may further comprise a universal interconnection interface and another processing apparatus; a computing apparatus interacts with the another processing apparatus to jointly complete a computing operation designated by a user; the combined processing apparatus may further comprise a storage apparatus, and the storage apparatus is respectively connected to a device and the another processing apparatus, and is configured to store data of the device and the another processing apparatus.
The present disclosure provides a data processing apparatus and related products. The products include a control module including an instruction caching unit, an instruction processing unit, and a storage queue unit. The instruction caching unit is configured to store computation instructions associated with an artificial neural network operation; the instruction processing unit is configured to parse the computation instructions to obtain a plurality of operation instructions; and the storage queue unit is configured to store an instruction queue, where the instruction queue includes a plurality of operation instructions or computation instructions to be executed in the sequence of the queue. By adopting the above-mentioned method, the present disclosure can improve the operation efficiency of related products when performing operations of a neural network model.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
Disclosed are a method for optimizing a convolution operation of a system on chip and a related product. The system on chip can be comprised in a computing processing device of a combined processing device, and the computing processing device can comprise one or more integrated circuit devices. The combined processing device can further comprise an interface device and another processing device. The computing processing device interacts with the another processing device to together complete a computing operation specified by a user. The combined processing device can further comprise a storage device, and the storage device is separately connected to an apparatus and the another processing device for storing data of the apparatus and the another processing device. By means of the solution of the present disclosure, the data transmission amount between an internal apparatus and an external storage device can be decreased, such that the problem of an I/O bottleneck caused due to a bandwidth limit is reduced to the maximum extent, and the overall performance of an integrated circuit device can be improved.
A method for optimizing a matrix multiplication operation on a system on chip, and a related product, the method comprising: receiving matrix information of a first matrix and a second matrix, which are to be split so as to execute a matrix multiplication operation, wherein the first matrix is in the form of M rows × K columns, and the second matrix is in the form of K rows × N columns; and by minimizing a cost function, determining a splitting coefficient for splitting the first matrix and the second matrix, wherein the splitting coefficient comprises the numbers of rows and columns of a matrix block obtained after the first matrix is split, and the numbers of rows and columns of a matrix block obtained after the second matrix is split, and the cost function is used to determine the cost caused by transferring matrix data between a system on chip and a system off chip on executing a matrix multiplication operation on the system on chip.
Disclosed are a data processing device and method, and a related product. The data processing device can be comprised as a computing device in a combined processing device; the combined processing device can further comprise an interface device and another processing device. The computing device interacts with the another processing device to jointly complete a computing operation specified by a user. The combined processing device can further comprise a storing device, and the storing device is separately connected to the computing device and the another processing device and is used for storing data of the computing device and the another processing device. According to the solution of the present disclosure, by means of partitioning and partial rearrangement, the IO time during operation is reduced, and the memory requirement is also lowered.
Aspects for neural network operations with fixed-point number of short bit length are described herein. The aspects may include a fixed-point number converter configured to convert one or more first floating-point numbers to one or more first fixed-point numbers in accordance with at least one format. Further, the aspects may include a neural network processor configured to process the first fixed-point numbers to generate one or more process results.
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p.ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
30.
FRACTAL CALCULATING DEVICE AND METHOD, INTEGRATED CIRCUIT AND BOARD CARD
A fractal calculating device according to an embodiment of the present application is included in an integrated circuit device. The integrated circuit device includes a universal interconnect interface and other processing devices. The calculating device interacts with other processing devices to jointly complete a user specified calculation operation. The integrated circuit device may also comprise a storage device. The storage device is respectively connected with the calculating device and other processing devices and is used for data storage of the computing device and other processing devices
Provided are an integrated circuit chip apparatus and a related product, the integrated circuit chip apparatus being used for executing a multiplication operation, a convolution operation or a training operation of a neural network. The present technical solution has the advantages of a small amount of calculation and low power consumption.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p.ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G06N 3/06 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
Provided are an integrated circuit chip apparatus and a related product, the integrated circuit chip apparatus being used for executing a multiplication operation, a convolution operation or a training operation of a neural network. The present technical solution has the advantages of a small amount of calculation and low power consumption.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p.ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G06N 3/06 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
33.
Model conversion method, device, computer equipment, and storage medium
A model conversion method is disclosed. The model conversion method includes obtaining model attribute information of an initial offline model and hardware attribute information of a computer equipment, determining whether the model attribute information of the initial offline model matches the hardware attribute information of the computer equipment according to the initial offline model and the hardware attribute information of the computer equipment and in the case when the model attribute information of the initial offline model does not match the hardware attribute information of the computer equipment, converting the initial offline model to a target offline model that matches the hardware attribute information of the computer equipment according to the hardware attribute information of the computer equipment and a preset model conversion rule.
An integrated circuit apparatus, an electronic device, a board card, and a method for performing matrix multiplication using the integrated circuit apparatus. The integrated circuit apparatus can be comprised in a computing processing apparatus of a combination processing apparatus. The computing processing apparatus can comprise one or more integrated circuit apparatuses. The combination processing apparatus can also comprise an interface apparatus and the other processing apparatus, and the computing processing apparatus interacts with the other processing apparatus to jointly complete a computing operation specified by a user. The combination processing apparatus can also comprise a storage apparatus, and the storage apparatus is respectively connected to the computing apparatus and the other processing apparatus, and is used for storing data of the computing apparatus and the other processing apparatus. The present scheme can reduce the amount of data transmission between an internal device and an external storage apparatus, reducing the problem of I/O bottleneck caused by bandwidth limitation to the maximum extent, thereby improving the overall performance of the integrated circuit apparatus.
A data processing apparatus and method for executing a neural network model, and related products. The data processing apparatus can, as a computing apparatus, be comprised in a combination processing apparatus. The combination processing apparatus can also comprise an interface apparatus and other processing apparatuses. The computing apparatus interacts with other processing apparatuses to jointly complete a computing operation specified by a user. The combination processing apparatus can further comprise a storage apparatus, wherein the storage apparatus is connected to the computing apparatus and other processing apparatuses and is used for storing data of the computing apparatus and other processing apparatuses. According to the present solution, a convolution operation of a multi-dimensional array is optimized, thereby improving the operation processing efficiency.
An inter-chip communication circuit, method and system. The circuit comprises a first scheduling unit, a first computation unit and a sending unit. The first scheduling unit is configured to receive first task description information. The first computation unit is configured to receive the first task description information from the first scheduling unit and process first data according to the first task description information so as to obtain the first processed data. The first computing unit is further configured to transmit the first processed data to the sending unit. The sending unit is configured to send the first processed data off chip.
A data processing circuit, a data processing method, and related products. The data processing circuit can be implemented as a computing apparatus (201) and is comprised in a combination processing apparatus (20). The combination processing apparatus (20) can also comprise an interface apparatus (202) and the other processing apparatus (203). The computing apparatus (201) interacts with the other processing apparatus (203) to jointly complete a computing operation specified by a user. The combination processing apparatus (20) can also comprise a storage apparatus (204), the storage apparatus (204) being respectively connected to the computing apparatus (201) and the other processing apparatus (203), and being used for storing data of the computing apparatus (201) and the other processing apparatus (203). Provided are hardware implementations for structured sparse correlation operations, which can simplify processing and improve the processing efficiency of a machine.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
38.
DATA PROCESSING DEVICE, DATA PROCESSING METHOD, AND RELATED PRODUCT
A data processing device, a data processing method, and a related product. The data processing device can be implemented as a computation device comprised in a combined processing device, and the combined processing device can further comprise an interface device and another processing device. The computation device interacts with the another processing device to jointly complete a computation operation specified by a user. The combined processing device can further comprise a storage device, and the storage device is respectively connected to the computation device and the another processing device and is used for storing data of the computation device and the another processing device. The solution provides a dedicated instruction for a structured sparsification related operation, can simplify processing, and improves the processing efficiency of a machine.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
39.
DATA PROCESSING APPARATUS, DATA PROCESSING METHOD AND RELATED PRODUCT
A data processing apparatus, a data processing method and a related product. The data processing apparatus can be implemented as a computation apparatus comprised in a combined processing apparatus. The combined processing apparatus may also comprise an interface apparatus and other processing apparatuses. The computation apparatus interacts with the other processing apparatuses to jointly complete a computation operation specified by a user. The combined processing apparatus may also comprise a storage apparatus, which is respectively connected to the computation apparatus and the other processing apparatuses, and is used for storing data of the computation apparatus and the other processing apparatuses. Provided is a special instruction for a structured sparse convolution operation, and the special instruction can simplify processing, thereby improving the processing efficiency of a machine.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
40.
DEVICE, BOARD AND METHOD FOR MERGING BRANCH STRUCTURES, AND READABLE STORAGE MEDIUM
A device, board and method for dynamically merging branch structures of a neural network according to a merging strategy, and a readable storage medium. A computing device is comprised in an integrated circuit device, and the integrated circuit device comprises a general-purpose interconnection interface and other processing devices. The computing device interacts with the other processing devices to together complete a computing operation specified by a user. The integrated circuit device can further comprise a storage device. The storage device is separately connected to the computing device and the other processing devices, and is used for the data storage of the computing device and the other processing devices.
The present invention relates to a computational neural network apparatus, a card, a method, and a readable storage medium, wherein a computational apparatus of the present invention is contained within an integrated circuit apparatus, and the integrated circuit apparatus comprises a general interconnection interface and an other processing apparatus. The computational apparatus and the other processing apparatus interact and jointly complete a computation operation specified by a user. The integrated circuit apparatus may further comprise a storage apparatus, the storage apparatus being separately connected to the computational apparatus and the other processing apparatus, and said storage apparatus being used for data storage for the computational apparatus and the other processing apparatus.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
42.
FRACTAL CALCULATING DEVICE AND METHOD, INTEGRATED CIRCUIT AND BOARD CARD
A fractal computing device according to an embodiment of the present application may be included in an integrated circuit device. The integrated circuit device includes a universal interconnect interface and other processing devices. The calculating device interacts with other processing devices to jointly complete a user specified calculation operation. The integrated circuit device may also include a storage device. The storage device is respectively connected with the calculating device and other processing devices and is used for data storage of the computing device and other processing devices.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
An apparatus (200) and method for training a neural network, and an integrated circuit board. The apparatus (200) is embodied by a computing device (610) in a combined processing device (600). The combined processing device (600) can further comprise a universal interconnect interface and other processing devices (606). The computing device (610) interacts with the other processing devices (606) to jointly complete a user-specified computing operation. The combined processing device (600) can further comprise a storage device (608). The storage device (608) is separately connected to the computing device (610) and the other processing devices (606) and is used for data of the computing device (610) and the other processing devices (606). The present invention can speed by the training of a neural network.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
44.
ACCUMULATION DEVICE AND METHOD, AND READABLE STORAGE MEDIUM
An accumulation device and method, and a readable storage medium, for use in accumulating multiple floating-point numbers. Firstly, a reference exponent is identified, then an accumulation cluster is screened according to the reference exponent, and floating-point numbers of the accumulation cluster are accumulated.
A method, device and system for acquiring hardware performance data. The device may be included in a calculation processing apparatus of a combined processing apparatus. The calculation processing apparatus may comprise one or more data processing apparatuses. The described combined processing apparatus may further comprise an interface apparatus and another processing apparatus. The calculation processing apparatus interacts with the other processing apparatus to complete together a calculation operation specified by a user. The combined processing apparatus may further comprise a storage apparatus. The storage apparatus is respectively connected to the device and the other processing apparatus, and is used for storing data of the device and the other processing apparatus. The present method may effectively acquire hardware performance data related to the execution of an object code.
A processing method, a processing apparatus, and a related product. The processing apparatus can be implemented as a computing apparatus (510) included in a combined processing apparatus (500); the combined processing apparatus (500) further can comprise an interface apparatus (504) and other processing apparatuses (506); the computing apparatus (510) interacts with other processing apparatuses (506) so as to jointly complete a computing operation specified by a user; the combined processing apparatus (500) further can comprise a storage apparatus (508); and the storage apparatus (508) is separately connected to the computing apparatus (510) and other processing apparatuses (506) and used for storing the data of the computing apparatus (510) and other processing apparatuses (506). The method provides an instruction parallel solution that can improve instruction parallelism, thereby improving the processing efficiency of a machine.
The invention provides an artificial intelligence computing device and a related product. The artificial intelligence computing device is used for executing machine learning computation. According to the device of the invention, for the instructions in the more than two instruction sets forming the loop body, the same operation code in the operation code storage area is used for the repeated instructions, so that the storage space of the operation code is saved, the code amount of each instruction in the instruction set in the second time slice can be reduced, the instruction storage space can also be saved, and the operation efficiency is improved.
G06F 9/32 - Formation de l'adresse de l'instruction suivante, p.ex. par incrémentation du compteur ordinal
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
48.
DATA PROCESSING APPARATUS, DATA PROCESSING METHOD, AND RELATED PRODUCT
A data processing apparatus (300), a data processing method (400), and a related product, relating to an instruction system for tensor data. The data processing apparatus (300) can serve as a computing apparatus (510) and is thus comprised in a combination processing apparatus (500). The combination processing apparatus (500) can also comprise an interface apparatus (504) and another processing apparatus (506). The computing apparatus (510) and the other processing apparatus (506) interact with each other, and jointly complete a computing operation designated by a user. The combination processing apparatus (500) can also comprise a storage apparatus (508), the storage apparatus (508) being respectively connected to the computing apparatus (510) and the other processing apparatus (506) and being used for storing data of the computing apparatus (510) and the other processing apparatus (506). By means of the data processing apparatus (300), the data processing method (400), and the related product, the time taken to access data can be shortened, thereby improving the processing efficiency of a machine.
An integrated computing apparatus, a machine learning operation apparatus, a neural network chip, a board card, an electronic device and a method. The integrated computing apparatus is comprised in a combined processing apparatus, the combined processing apparatus comprises an interface apparatus and other processing apparatuses, the integrated computing apparatus interacts with the other processing apparatuses, so as to jointly complete a computing operation designated by a user, the combined processing apparatus comprises a storage apparatus, and the storage apparatus is respectively connected to the integrated computing apparatus and the other processing apparatuses, so as to store the data of the integrated computing apparatus and the other processing apparatuses.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
A device and method for processing multi-dimensional data, and an electronic device and a compilation apparatus (1802). The compilation apparatus (1802) may be comprised in a combined processing apparatus (1800). The combined processing apparatus (1800) may also comprise a universal interconnection interface (1804) and other processing apparatuses (1806). The compilation apparatus (1802) interacts with the other processing apparatuses (1806), so as to jointly complete a user-specified computing operation. The combined processing apparatus (1800) may further comprise a storage apparatus (1808). The storage apparatus (1808) is respectively connected to the compilation apparatus (1802) and the other processing apparatuses (1806), and is used for storing data of the compilation apparatus (1802) and the other processing apparatuses (1806).
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
51.
Fractal calculating device and method, integrated circuit and board card
A fractal computing device according to an embodiment of the present application may be included in an integrated circuit device. The integrated circuit device includes a universal interconnect interface and other processing devices. The calculating device interacts with other processing devices to jointly complete a user specified calculation operation. The integrated circuit device may also include a storage device. The storage device is respectively connected with the calculating device and other processing devices and is used for data storage of the computing device and other processing devices.
An encapsulation structure, an integrated circuit apparatus, a board card, and a method for laying out an integrated circuit on a wafer of an encapsulation structure. The method comprises: attaching a system-on-chip (501) to a system area on a wafer (51); attaching a memory (502) to a storage area (52) on the wafer; and attaching a plurality of capacitors (503) to a capacitor area (53) on the wafer, wherein the capacitor area (53) is a leftover area outside of the system area (51) and the storage area (52).
A device and method for neural network computing, and a board and a readable storage medium. A computing device (201) is comprised in an integrated circuit device. The integrated circuit device comprises a universal interconnection interface and another processing device (203). The computing device (201) interacts with the other processing device (203) to jointly complete computing operations specified by a user. The integrated circuit device can further comprise a storage device. The storage device is respectively connected to the computing device (201) and the other processing device (203) for storing data of the computing device (201) and the other processing device (203).
The present disclosure relates to a device and method for implementing live migration, wherein the system on chip of the present disclosure is comprised in an integrated circuit device, and the integrated circuit device comprises a universal interconnect interface and other processing devices. A computing device interacts with the other processing devices to jointly complete a computing operation specified by a user. The integrated circuit device may further comprise a storage device. The storage device is respectively connected to the computing device and the other processing devices for use in storing data of the computing device and the other processing devices.
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
55.
DATA PROCESSING DEVICE, INTEGRATED CIRCUIT CHIP, DEVICE, AND IMPLEMENTATION METHOD THEREFOR
A data processing device, a method, an integrated circuit chip, an electronic device, and a card. The data processing device is comprised in a computing device. The computing device may be comprised in a combined processing device. The combined processing device may also comprise a universal interconnect interface and other processing devices. The computing device interacts with the other processing devices to jointly complete a computing operation specified by a user. The combined processing device may also comprise a storage device. The storage device is connected respectively to the computing device and the other processing devices and is used for storing data of the computing device and of the other processing devices. This is broadly applicable in various conversions of multidimensional data and increases the efficiency of data conversion.
A device for forward fusion of a neural network, a board, a method, and a readable storage medium. A computing device (201) is comprised in an integrated circuit device (20), and the integrated circuit device (20) comprises an interface device (202) and a processing device (203). The computing device (201) and the processing device (203) interact with each other to jointly complete a computing operation specified by a user. The integrated circuit device (20) may further comprise a memory device DRAM (204), and the memory device DRAM (204) is separately connected to the computing device (201) and the processing device (203) and used for storing data of the computing device (201) and the processing device (203).
The present disclosure provides a data processing apparatus and related products. The products include a control module including an instruction caching unit, an instruction processing unit, and a storage queue unit. The instruction caching unit is configured to store computation instructions associated with an artificial neural network operation; the instruction processing unit is configured to parse the computation instructions to obtain a plurality of operation instructions; and the storage queue unit is configured to store an instruction queue, where the instruction queue includes a plurality of operation instructions or computation instructions to be executed in the sequence of the queue. By adopting the above-mentioned method, the present disclosure can improve the operation efficiency of related products when performing operations of a neural network model.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
Disclosed are a computing apparatus, an integrated circuit chip, a board card, a device and a method. The computing apparatus may be comprised in a combined processing apparatus, and the combined processing apparatus may further comprise an interface apparatus and other processing apparatuses. The computing apparatus and the other processing apparatuses interact with each other, so as to jointly complete a computing operation specified by a user. The combined processing apparatus may further comprise a storage apparatus, and the storage apparatus is respectively connected to the computing apparatus and the other processing apparatuses and is used for storing data of the computing apparatus and the other processing apparatuses. By means of the solution of the present disclosure, operation processing can be executed by using at least two pieces of small-bit-width data that represent large-bit-width data, such that the processing capacity of a processor is not affected by bit width. Fig. 7
Provided are an address deduction method employing a control flow graph, a device, and a readable storage medium. A computing device is included in an integrated circuit device. The integrated circuit device comprises a universal interconnect interface and other processing devices. The computing device interacts with said other processing devices to jointly complete a computing operation specified by a user. The integrated circuit device may further comprise a storage device. The storage device is respectively connected to the computing device and said other processing devices for storing data of the computing device and said other processing devices.
A method for computing a data dependence relationship in a program, and a computer readable storage medium, applied in a computing device (902). The computing device (902) is comprised in an integrated circuit device, and the integrated circuit device comprises a universal interconnect interface (904) and other processing device (906). The computing device (902) interacts with the other processing device (906) to jointly complete a user-specified computing operation. The integrated circuit device may further comprise a storage device (908), and the storage device (908) is separately connected to the computing device (902) and the other processing device (906) and is used for data storage of the computing device (902) and the other processing device (906).
The present disclosure relates to a method and device for allocating storage addresses for data in a memory, and a computing apparatus, wherein the computing apparatus may be comprised in a combined processing apparatus, and the combined processing apparatus may also comprise a universal interconnection interface and other processing apparatuses. The computing apparatus interacts with other processing apparatuses to jointly complete a computing operation specified by a user. The combined processing apparatus may also comprise a storage apparatus, which is separately connected to the computing apparatus and other processing apparatuses, and which is used for data of the computing apparatus and the other processing apparatuses. The technical solution of the present disclosure may improve the storage space utilization rate of the memory.
Provided are a method for realizing live migration, a computing device, and a readable storage medium. The computing device is comprised in an integrated circuit device, and the integrated circuit device comprises a universal interconnect interface and other processing devices. The computing device interacts with other processing devices to jointly complete a computing operation specified by a user. The integrated circuit device may also comprise a storage device, and the storage device is respectively connected to the computing device and other processing devices and is used for data storage of the computing device and other processing devices.
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
64.
Data pre-processing method and device, and related computer device and storage medium
The present disclosure provides a data pre-processing method and device and related computer device and storage medium. By storing the target output data corresponding to the target operation into the first memory close to the processor and reducing the time of reading the target output data, the occupation time of I/O read operations during the operation process can be reduced, and the speed and efficiency of the processor can be improved.
The present invention relates to an inter-node communication method and device based on multiple processing nodes, and a communication configuration apparatus. The communication configuration apparatus may be comprised in a combined processing apparatus, and the combined processing apparatus may further comprise an interconnection interface and other processing apparatus. The communication configuration apparatus interacts with the other processing apparatus to jointly complete a calculation operation specified by a user. The combined processing apparatus may further comprise a storage apparatus, and the storage apparatus is connected to the communication configuration apparatus and the other processing apparatus, respectively, and is used for storing data of the communication configuration apparatus and of the other processing apparatus. The technical solution of the present invention can improve the efficiency of inter-node communication.
The present disclosure relates to a method and device for constructing a communication topology structure on the basis of multiple processing nodes, and a communication configuration apparatus. The communication configuration apparatus can be comprised in a combined processing apparatus. The combined processing apparatus can further comprise an interconnection interface and other processing apparatuses. The communication configuration apparatus interacts with the other processing apparatuses to jointly complete a computing operation specified by a user. The combined processing apparatus can further comprise a storage apparatus. The storage apparatus is respectively connected to the communication configuration apparatus and the other processing apparatuses, and is used for storing data of the communication configuration apparatus and the other processing apparatuses. By means of the technical solution of the present disclosure, the efficiency of inter-chip communication can be improved.
The present disclosure discloses a data processing method and related products, in which the data processing method includes: generating, by a general-purpose processor, a binary instruction according to device information of an AI processor, and generating an AI learning task according to the binary instruction; transmitting, by the general-purpose processor, the AI learning task to the cloud AI processor for running; receiving, by the general-purpose processor, a running result corresponding to the AI learning task; and determining, by the general-purpose processor, an offline running file according to the running result, where the offline running file is generated according to the device information of the AI processor and the binary instruction when the running result satisfies a preset requirement. By implementing the present disclosure, the debugging between the AI algorithm model and the AI processor can be achieved in advance.
The present disclosure provides a data processing method and an apparatus and a related product. The products include a control module including an instruction caching unit, an instruction processing unit, and a storage queue unit. The instruction caching unit is configured to store computation instructions associated with an artificial neural network operation; the instruction processing unit is configured to parse the computation instructions to obtain a plurality of operation instructions; and the storage queue unit is configured to store an instruction queue, where the instruction queue includes a plurality of operation instructions or computation instructions to be executed in the sequence of the queue. By utilizing the above-mentioned method, the present disclosure can improve the operation efficiency of related products when performing operations of a neural network model.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p.ex. plusieurs processeurs de données à instruction unique
G06F 15/173 - Communication entre processeurs utilisant un réseau d'interconnexion, p.ex. matriciel, de réarrangement, pyramidal, en étoile ou ramifié
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
An operation method, a processor, and a related product. The product comprises a storage device (390), an interface apparatus (391), a control device (392), and an artificial intelligence chip (389); the artificial intelligence chip (389) is connected to the storage device (390), the control device (392), and the interface apparatus (391) respectively; the storage device (390) is used for storing data; the interface apparatus (391) is used for implementing data transmission between the artificial intelligence chip (389) and an external device; and the control device (392) is used for monitoring the state of the artificial intelligence chip (389). The operation method or related product can increase the operation efficiency of the related product when performing matrix multiplication.
The present disclosure relates to a data quantification processing method and apparatus, an electronic device and a storage medium. The apparatus comprises a control module, and the control module comprises an instruction cache unit, an instruction processing unit, and a storage queue unit. The instruction cache unit is used to store computing instructions correlated to artificial neural network operations, the instruction processing unit is used to parse the computing instructions so as to obtain a plurality of operation instructions, the storage queue unit is used to store an instruction queue, and the instruction queue comprises a plurality of operation instructions or computing instructions to be executed according to the sequential order of the queue. By means of the above method, the present disclosure may improve the operation efficiency of a related product when neural network model operations are performed.
The present disclosure provides a data processing method and an apparatus and a related product. The products include a control module including an instruction caching unit, an instruction processing unit, and a storage queue unit. The instruction caching unit is configured to store computation instructions associated with an artificial neural network operation; the instruction processing unit is configured to parse the computation instructions to obtain a plurality of operation instructions; and the storage queue unit is configured to store an instruction queue, where the instruction queue includes a plurality of operation instructions or computation instructions to be executed in the sequence of the queue. By adopting the above-mentioned method, the present disclosure can improve the operation efficiency of related products when performing operations of a neural network model.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Central processing units (CPU); Computer hardware; Data processing apparatus; Electronic downloadable publications, namely, books, magazines and journals in the field of data processing and artificial intelligence; Integrated circuit cards; Recorded computer operating software; Encoded smart cards containing programming used for data processing in the field of artificial intelligence; Mobile telephones; Wafers for integrated circuits; Silicon chips; Electronic chips for the manufacture of integrated circuits; Integrated circuits; Heat sink for central processing unit; Digital signal processor; Raster image processor; Computer central processing units; Central processing units for processing information, data, sound or images; Digital voice signal processors; Digital sound processor; Signal processors for audio speakers; Secure digital (SD) memory card; Blank electronic chip cards; Microchip card; Chip card reader; DNA chips; Bio-chips for research or scientific purposes; Computer chip; Microchip; Multiprocessor chip; High definition integrated graphics computer chips; Biochip sensors for measuring pressure, acceleration, force and flow, not for medical use; Blank smart card; Smart card reader; Blank integrated circuit cards Technological research in the field of computer hardware systems; Research and development of new products for others; Scientific research; Computer technology consultancy; Computer programming; Computer software design; Computer software consultancy; Consultancy in the design and development of computer hardware; Computer system design
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Computer server; Network server; Central processing units (CPU); Computer hardware; Data processing apparatus; Integrated circuit cards; Recorded computer operating software; Mobile telephones; Wafers for integrated circuits; Silicon chips; Electronic chips for the manufacture of integrated circuits; Integrated circuits; Heat sink for central processing unit; Digital signal processor; Raster image processor; Computer central processing units; Central processing units for processing information, data, sound or images; Digital voice signal processors; Digital sound processor; Signal processors for audio speakers; Secure digital (SD) memory card; Blank electronic chip cards; Microchip card; Chip card reader; DNA chips; Bio-chips for research or scientific purposes; Computer chip; Microchip; Multiprocessor chip; High definition integrated graphics computer chips; Biochip sensors for measuring pressure, acceleration, force and flow, not for medical use; Blank smart card; Smart card reader; Blank integrated circuit cards; Encoded smart cards containing programming used for data processing in the field of artificial intelligence Technological research in the field of computer hardware systems; Research and development of new products for others; Scientific research; Computer programming; Computer software design; Computer software consultancy; Computer technology consultancy; Consultancy in the design and development of computer hardware; Computer system design
75.
TASK MIGRATION METHOD AND APPARATUS, AND COMPUTER DEVICE AND READABLE STORAGE MEDIUM
The present application relates to a task migration method and apparatus, and a computer device and a readable storage medium. The method comprises: when it is detected that a migratable task satisfies a preset migration condition, determining a target node matching the migratable task from various nodes according to a task attribute of the migratable task, the task attribute comprising a target number of operation units required for executing the migratable task; and migrating the migratable task to the target node, so that the target node executes the migratable task. According to the present application, the waiting duration of the migratable task can be reduced, and the execution efficiency of the migratable task is improved. The present application relates to an operation processing method and apparatus, and a computer device and a readable storage medium.
A memory allocation method and device, and a computer readable storage medium. The device comprises a combined processing means, and the combined processing means comprises a universal interconnection interface (1204) and another processing means. A master device (1202) of the device interacts with another processing means to jointly complete a designated computing operation. The combined processing means also comprises a storage means (1208). The storage means (1208) is connected to the master device (1202) and another processing means, separately, and used for data storage of the master device (1202) and another processing means.
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
A data processing method and apparatus, a computer device, and a storage medium. The method comprises: splitting first data according to a preset splitting mode to obtain a plurality of pieces of second data (S21); for any of the second data, performing a winograd convolution operation on the second data and a weight to obtain a plurality of first convolution results (S22); and merging the plurality of first convolution results according to a preset merging mode to obtain a dilated convolution result of the first data and the weight, wherein the preset merging mode is an inverse process of the preset splitting mode. By means of the method, operation efficiency of related products during operation of a neural network model can be improved.
The present disclosure relates to a system, a computing apparatus, a board card, and an electronic device for data accelerated processing. The computing apparatus may be included in a combined processing apparatus. The combined processing apparatus may also include a universal interconnection interface and other processing apparatuses. The computing apparatus interacts with other processing apparatuses to jointly complete computing operations specified by the user. The combined processing apparatus may also include a storage apparatus which is respectively connected to the computing apparatus and other processing apparatuses and is used for storing data of the computing apparatus and other processing apparatuses. The solution of the present disclosure can be applied to various electronic devices.
The present disclosure relates to a learning task compiling method of artificial intelligence processors and related products. The learning task compiling method of artificial intelligence processors includes fusing a redundant neural network layer to a convolution layer, optimizing a structure of a convolution neural network, and compiling a learning task of an artificial intelligence processor based on the optimized convolution neural network. The method may achieve high efficiency for learning task compiling of artificial intelligence processors, and may reduce data exchange during processing when being executed on a device.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06N 5/04 - Modèles d’inférence ou de raisonnement
A data processing method and apparatus, a computer device and a storage medium. The computer device comprises a control module, and the control module comprises: an instruction caching unit, an instruction processing unit and a queue storage unit, wherein the instruction caching unit is used for storing a calculation instruction associated with the computation of an artificial neural network; the instruction processing unit is used for parsing the calculation instruction to obtain a plurality of computation instructions; and the queue storage unit is used for storing an instruction queue, and the instruction queue comprises: a plurality of computation instructions or calculation instructions to be executed in the sequential order of the queue. By means of the data processing method and apparatus, the computer device and the storage medium, the computation efficiency of a related product during the computation of a neural network model is improved.
An integrated circuit chip device and related products are provided. The integrated circuit chip device is used for performing a multiplication operation, a convolution operation or a training operation of a neural network. The device has the advantages of small calculation amount and low power consumption.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
The present disclosure provides a data processing method and an apparatus and related products. The products include a control module including an instruction caching unit, an instruction processing unit, and a storage queue unit. The instruction caching unit is configured to store computation instructions associated with an artificial neural network operation; the instruction processing unit is configured to parse the computation instructions to obtain a plurality of operation instructions; and the storage queue unit is configured to store an instruction queue, where the instruction queue includes a plurality of operation instructions or computation instructions to be executed in the sequence of the queue. By adopting the above-mentioned method, the present disclosure can improve the operation efficiency of related products when performing operations of a neural network model.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
The invention relates to a shared storage space access method, device and system and a storage medium. The product comprises a control module. The control module comprises an instruction cache unit, an instruction processing unit and a storage queue unit. The instruction caching unit is used for storing a calculation instruction associated with the artificial neural network operation; the instruction processing unit is used for analyzing the calculation instruction to obtain a plurality of operation instructions; the storage queue unit is used for storing an instruction queue, and the instruction queue comprises a plurality of operation instructions or calculation instructions to be executed according to the front-back sequence of the queue. Through the method or the product, the access efficiency of the storage space can be improved.
The present disclosure relates to a video retrieval method, a method, system and device for generating a video retrieval mapping relationship, and a storage medium. The video retrieval method comprises: acquiring a retrieval instruction, wherein the retrieval instruction carries retrieval information for retrieving a target frame picture; and obtaining the target frame picture according to the retrieval information and a preset mapping relationship. The method for generating a video retrieval mapping relationship comprises: performing a feature extraction operation on each frame picture in a video stream by using a feature extraction model so as to obtain a key feature sequence corresponding to each frame picture; inputting the key feature sequence corresponding to each frame picture into a text sequence extraction model for processing so as to obtain a text description sequence corresponding to each frame picture; and constructing a mapping relationship according to the text description sequence corresponding to each frame picture. By means of the video retrieval method and the method for generating a video retrieval mapping relationship provided in the present application, the efficiency of video retrieval can be improved, and human-machine interaction is made more intelligent.
G06F 16/783 - Recherche de données caractérisée par l’utilisation de métadonnées, p.ex. de métadonnées ne provenant pas du contenu ou de métadonnées générées manuellement utilisant des métadonnées provenant automatiquement du contenu
G06F 16/901 - Indexation; Structures de données à cet effet; Structures de stockage
G06N 3/084 - Rétropropagation, p.ex. suivant l’algorithme du gradient
G06V 10/764 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant la classification, p.ex. des objets vidéo
G06V 10/774 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant l’intégration et la réduction de données, p.ex. analyse en composantes principales [PCA] ou analyse en composantes indépendantes [ ICA] ou cartes auto-organisatrices [SOM]; Séparation aveugle de source méthodes de Bootstrap, p.ex. "bagging” ou “boosting”
G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
G06V 20/40 - RECONNAISSANCE OU COMPRÉHENSION D’IMAGES OU DE VIDÉOS Éléments spécifiques à la scène dans le contenu vidéo
Aspects for neural network operations with floating-point number of short bit length are described herein. The aspects may include a neural network processor configured to process one or more floating-point numbers to generate one or more process results. Further, the aspects may include a floating-point number converter configured to convert the one or more process results in accordance with at least one format of shortened floating-point numbers. The floating-point number converter may include a pruning processor configured to adjust a length of a mantissa field of the process results and an exponent modifier configured to adjust a length of an exponent field of the process results in accordance with the at least one format.
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p.ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
G06F 9/44 - Dispositions pour exécuter des programmes spécifiques
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06N 3/082 - Méthodes d'apprentissage modifiant l’architecture, p.ex. par ajout, suppression ou mise sous silence de nœuds ou de connexions
G06N 3/084 - Rétropropagation, p.ex. suivant l’algorithme du gradient
88.
DATA PROCESSING METHOD AND APPARATUS, COMPUTER DEVICE AND STORAGE MEDIUM
The present application relates to a data processing method and apparatus, a computer device and a storage medium. Disclosed is a board card, the board card comprising: a storage device, an interface apparatus, a control device, and an artificial intelligence chip comprising a data processing apparatus, wherein the artificial intelligence chip is respectively connected to the storage device, the control device and the interface apparatus; the storage device is used for storing data; the interface apparatus is used for realizing data transmission between the artificial intelligence chip and an external device; and the control device is used for monitoring the state of the artificial intelligence chip. According to the data processing method and apparatus, the computer device and the storage medium provided in the embodiments of the present application, the precision of quantization can be improved, and the operation time for Winograd convolution and the energy consumption are also reduced.
A winograd convolution operation method, apparatus, and device, and a storage medium. The device comprises a processor (61) and a memory (62), wherein the memory (62) is used for storing a program code, and the processor (61) is used for invoking the program code stored in the memory (62) to implement an operation method. The present invention can reduce the performance loss of a computer system, improve an operation speed, and improve processing efficiency.
An operation apparatus (10), comprising a storage unit (12), a control unit (11), and an operation unit (13). The operation apparatus (10) can reduce resource consumption of a convolution operation, improve a convolution operation speed, and reduce operation time.
A Winograd convolution operation method and a related product. The method comprises: in a process of training a neural network on the basis of a preconfigured Winograd convolution algorithm, respectively decomposing forward transformation operation of a reverse input gradient of a jth layer in the neural network and forward transformation operation of forward input feature data of the jth layer into summation, so as to obtain a transformation result of the forward transformation operation of the reverse input gradient of the jth layer, and a transformation result of the forward transformation operation of the forward input feature data of the jth layer on the basis of the summation (201); performing element-wise multiplication on the transformation result of the forward transformation operation of the reverse input gradient of the jth layer and the transformation result of the forward transformation operation of the forward input feature data of the jth layer, and obtaining a first multiplication result (202); decomposing inverse transformation operation of the first multiplication result into summation, and using a result obtained by summation as a weight difference of the jth layer (203); and completing training of the neural network according to the weight difference of the jth layer (204).
An operational apparatus and a related product. The product comprises a control module; the control module comprises: an instruction cache unit, an instruction processing unit and a storage queue unit; the instruction cache unit is used for storing a calculation instruction associated with an artificial neural network operation; the instruction processing unit is used for parsing the calculation instruction to obtain multiple operation instructions; and the storage queue unit is used for storing an instruction queue, the instruction queue comprising multiple operation instructions or calculation instructions to be executed according to the sequence of the queue. The present application can improve the operation efficiency of a related product when carrying out an operation of a neural network model.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
93.
DATA PROCESSING METHOD AND DEVICE, COMPUTER EQUIPMENT AND STORAGE MEDIUM
A data processing method and device, a computer equipment and a storage medium. The data processing method comprises: according to the mean value of the absolute value of quantized data obtained by using a plurality of pairs of truncation thresholds to quantize a set of data to be quantized, determining a pair of truncation thresholds from the plurality of pairs of truncation thresholds, wherein the set of data to be quantized is a set of data during a winograd convolution processing, and each pair of truncation thresholds of the plurality of pairs of truncation thresholds comprise a positive truncation value and a negative truncation value that are symmetrical (101); according to the determined one pair of truncation thresholds, quantizing the set of data to be quantized to obtain first quantized data (102); according to the first quantized data, continuing executing the winograd convolution processing to obtain a quantized winograd convolution result (103); and inversely quantizing the quantized winograd convolution result to obtain a winograd convolution result (104). The described method can improve quantization precision and calculating performances.
The present invention relates to a data processing method and apparatus, and a computer device and a storage medium. A board disclosed comprises: a storage device, an interface apparatus and a control device, and an artificial intelligence chip comprising the data processing apparatus. The artificial intelligence chip is separately connected to the storage device, the control device, and the interface apparatus. The storage device is used for storing data. The interface apparatus is used for implementing data transmission between the artificial intelligence chip and an external device. The control device is used for monitoring the state of the artificial intelligence chip. The data processing method and apparatus, and the computer device and the storage medium provided by embodiments of the present invention can improve the precision of quantization, save the operation time of winograd convolution, and reduce energy consumption.
A computing device and method, and a related product. The device comprises a master control unit, a slave control unit, a storage unit, a master computing unit, and a slave computing unit. The invention effectively improves the energy efficiency ratio and computing speed of deep learning networks in terms of hardware architecture, thus improving the performance of the deep learning networks.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
An operation method and a related product, the method comprising: acquiring feature data outputted by an upper layer convolutional network and a feature transformation matrix used for performing forward transformation on the feature data (201); on the basis of the feature transformation matrix, transforming the feature data to obtain a feature transformation result, wherein the transformation operation of the feature data is disassembled into a summation operation, and the feature transformation result is determined on the basis of the summation operation (202); acquiring the weight transformation result of the present layer convolutional network after forward transformation and performing a bitwise multiplication operation on the feature transformation result and the weight transformation result to obtain a multiplication operation result (203); acquiring an inverse transformation matrix used for performing inverse transformation on the multiplication operation result and, on the basis of the inverse transformation matrix, performing transformation on the multiplication operation result to obtain an operation result, wherein the transformation operation of the multiplication operation result is disassembled into a summation operation, and the operation result is determined on the basis of the summation operation (204); and outputting the operation result to a lower layer convolutional network (205).
An operation apparatus and a related product. The product comprises a control module, with the control module comprising an instruction cache unit, an instruction processing unit and a storage queue unit, wherein the instruction cache unit is used for storing a computing instruction associated with artificial neural network operation; the instruction processing unit is used for parsing the computing instruction to obtain a plurality of operation instructions; and the storage queue unit is used for storing an instruction queue, with the instruction queue comprising a plurality of operation instructions or computing instructions to be executed according to the sequence of the queue. The operation efficiency of the related product during the operation of a neural network model can thus be improved.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
98.
DATA PROCESSING METHOD AND APPARATUS, AND COMPUTER DEVICE AND STORAGE MEDIUM
A data processing method and apparatus, and a computer device and a storage medium. The method comprises: splitting a first convolution kernel according to a step length N to obtain a plurality of second convolution kernels (S11); splitting first input data according to the step length N to obtain a plurality of second input data corresponding to the plurality of first convolution kernels (S12); for any second input data, executing a Winograd convolution operation on the second input data and the corresponding second convolution kernel to obtain a convolution result corresponding to the second input data (S13); and determining that a sum of the convolution results corresponding to the plurality of second input data is a convolution result of the first convolution kernel and the first input data (S14). By means of the above method, the reusability of data can be improved.
A data processing method and apparatus capable of reducing calculation amount, saving calculation time, and saving energy, and a related product. The data processing method comprises: splitting a convolution kernel having a size of greater than 3*3 into a plurality of sub-convolution kernels having a size of smaller than or equal to 3*3 (S201); according to position distribution of the plurality of sub-convolution kernels in the convolution kernel, splitting input data into a plurality of pieces of target sub-input data having a size of smaller than or equal to 4*4, each of the sub-convolution kernels corresponding to one or more pieces of target sub-input data (S202); for any sub-convolution kernel, performing a winograd convolution operation on the sub-convolution kernel and the corresponding target sub-input data, so as to obtain a convolution result corresponding to the sub-convolution kernel (S203); and performing a summation operation on convolution results corresponding to the plurality of sub-convolution kernels, so as to obtain a convolution result of the convolution kernel and the input data (S204).
An integrated circuit chip device and related products are provided. The integrated circuit chip device is used for performing a multiplication operation, a convolution operation or a training operation of a neural network. The device has the advantages of small calculation amount and low power consumption.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
