A first communication device generates a first physical layer (PHY) data unit that includes information indicating a capability to use a channel bandwidth greater than a maximum channel bandwidth of the first communication device, and transmits the first PHY data unit to a second communication device during an association process with the second communication device. The first communication device generates a second PHY data unit that includes information indicating a capability to use at most the maximum channel bandwidth of the first communication device, and transmits the second PHY data unit to the second communication device when the first communication device is associated with the second communication device.
H04W 72/21 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens ascendant de la liaison sans fil, c. à d. en direction du réseau
H04W 8/22 - Traitement ou transfert des données du terminal, p.ex. statut ou capacités physiques
A first communication device generates an Operation, Administration, and Maintenance (OAM) frame that includes i) OAM message content and ii) an OAM frame header outside of the OAM message content, wherein generating the OAM frame comprises generating the OAM frame header to include information that signals one of i) a low power sleep (LPS) request, and ii) a wake-up request (WUR). The first communication device transmits the OAM frame to a second communication device via a communication medium to signal to the second communication device the one of i) the LPS request, and ii) the WUR.
H04L 12/12 - Dispositions pour la connexion ou la déconnexion à distance de sous-stations ou de leur équipement
G06F 1/3296 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par diminution de la tension d’alimentation ou de la tension de fonctionnement
3.
System and method for large memory transaction (LMT) stores
A system and corresponding method perform large memory transaction (LMT) stores. The system comprises a processor associated with a data-processing width and a processor accelerator. The processor accelerator performs a LMT store of a data set to a coprocessor in response to an instruction from the processor targeting the coprocessor. The data set corresponds to the instruction. The LMT store includes storing data from the data set, atomically, to the coprocessor based on a LMT line (LMTLINE). The LMTLINE is wider than the data-processing width. The processor accelerator sends, to the processor, a response to the instruction. The response is based on completion of the LMT store of the data set in its entirety. The processor accelerator enables the processor to perform useful work in parallel with the LMT store, thereby improving processing performance of the processor.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/1045 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p.ex. un répertoire de pages actives [TLB] associée à une mémoire cache de données
4.
Structures and methods for deriving stable physical unclonable functions from semiconductor devices
A semiconductor device includes circuitry configured to derive a physical unclonable function. The circuitry includes a plurality of bitcells, each bitcell being readable as one of a ‘0’ value and a ‘1’ value, and sense amplifier circuitry configurable to read values from the plurality of bitcells. The sense amplifier circuitry includes margin circuitry configurable (i) to selectably bias reading of the plurality of bitcells toward one of ‘0’ values and ‘1’ values, (ii) to identify addresses of bitcells having a stable ‘1’ value when the margin circuitry is configured to bias reading of the plurality of bitcells toward ‘0’ values, and (iii) to identify addresses of bitcells having a stable ‘0’ value when the margin circuitry is configured to bias reading of the plurality of bitcells toward ‘1’ values. Each bitcell in the plurality of bitcells may include a differential transistor pair.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
G06F 21/44 - Authentification de programme ou de dispositif
A first communication device is configured to process packets that conform to a first physical layer (PHY) protocol for wireless vehicular communications and packets that conform to a second PHY protocol for wireless vehicular communications. The first communication device determines that one or more second communication devices neighboring the first communication device are not capable of processing packets that conform to the second PHY protocol. The first communication device transmits a first packet to a third communication device that is configured to process packets that conform to the first PHY protocol and packets that conform to the second PHY protocol. The first packet indicates that the one or more second communication devices neighboring the first communication device are not capable of processing packets that conform to the second PHY protocol to inform the third communication device of the one or more second communication devices.
H04L 69/323 - Protocoles de communication intra-couche entre entités paires ou définitions d'unité de données de protocole [PDU] dans la couche physique [couche OSI 1]
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
H04W 28/02 - Gestion du trafic, p.ex. régulation de flux ou d'encombrement
H04W 72/044 - Affectation de ressources sans fil sur la base du type de ressources affectées
6.
MEMORY ALLOCATION AND REALLOCATION FOR PROGRAM INSTRUCTIONS AND DATA USING INTERMEDIATE PROCESSOR
Memory blocks are allocated for a microcontroller having one memory subsystem storing instruction information, and a separate memory subsystem storing data information. At design time, an address map is created implementing configurations of different ways of allocating instruction information and data information between memory blocks. At runtime, a configuration signal is received, and a particular memory block configuration for storing instruction information and data information is determined. An incoming instruction signal received from a dedicated microcontroller port, is communicated according to the configuration signal and the address map to a connection point (e.g., pin, fuse, register). Via that connection point, the instruction signal is routed to a memory block designated exclusively for instructions. Similarly, based upon the configuration signal and the address map, an incoming data signal (received from another dedicated microcontroller port), is routed via a connection point to a different memory block designated to store exclusively data information.
A decoder for a receiver in a communication system includes an interface configured to receive encoded input data via a communication channel. The encoded input data includes forward error correction (FEC) codewords. A processor is configured to decode the FEC codewords using low density parity check (LDPC) codes defined by a parity check matrix. The parity check matrix is defined by both regular column partition (RCP) constraints and quasi-cyclic (QC) constraints. An output circuit is configured to output a decoded codeword based on the FEC codewords decoded by the processor.
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
8.
System and Method for Neural Network-Based Autonomous Driving
A system and corresponding method for autonomous driving of a vehicle are provided. The system comprises at least one neural network (NN) that generates at least one output for controlling the autonomous driving. The system further comprises a main data path that routes bulk sensor data to the at least one NN and a low-latency data path with reduced latency relative to the main data path. The low-latency data path routes limited sensor data to the at least one NN which, in turn, employs the limited sensor data to improve performance of the at least one NN's processing of the bulk sensor data for generating the at least one output. Improving performance of the at least one NN's processing of the bulk sensor data enables the system to, for example, identify a safety hazard sooner, enabling the autonomous driving to divert the vehicle and avoid contact with the safety hazard.
B60W 50/04 - COMMANDE CONJUGUÉE DE PLUSIEURS SOUS-ENSEMBLES D'UN VÉHICULE, DE FONCTION OU DE TYPE DIFFÉRENTS; SYSTÈMES DE COMMANDE SPÉCIALEMENT ADAPTÉS AUX VÉHICULES HYBRIDES; SYSTÈMES D'AIDE À LA CONDUITE DE VÉHICULES ROUTIERS, NON LIÉS À LA COMMANDE D'UN SOUS-ENSEMBLE PARTICULIER - Détails des systèmes d'aide à la conduite des véhicules routiers qui ne sont pas liés à la commande d'un sous-ensemble particulier pour surveiller le fonctionnement du système d'aide à la conduite
The present disclosure describes apparatuses and methods for contextual search of a storage system. In some aspects, a metadata manager of a storage system receives a query to search the data stored on the storage media of the apparatus. The metadata manager identifies an entry in a relational database of the metadata manager that includes a label that is relevant to the query and determines, based on the entry in the relational database, a reference address of a target node in a navigational database of the metadata manager that corresponds to the label. As results for the query to search, the metadata manager returns an object of the target node at the reference address in the navigational database and corresponding objects of relative nodes connected to the target node via respective links. By so doing, the metadata database may enable contextual or implicit search of data in the storage system.
Methods, PHYs, and computer-readable media are provided for reliably receiving data at a physical layer transceiver of an automobile in the presence of noise or interference. A non-equalized signal is received at a physical layer transceiver via a communication channel in a high noise or interference automotive environment. The non-equalized signal is prepared for extraction of data by performing one or more of the following: improving a signal-to-noise ratio of the non-equalized signal by using two or more parallel matching filters to correlate the non-equalized signal with two or more signal templates to detect the presence of logic low signal patterns and logic high signal patterns in the non-equalized signal; reducing jitter in the non-equalized signal by tracking a phase of the non-equalized signal using a digital timing loop; compensating for noise or interference distortion in the non-equalized signal by selecting a decision sample defined by a plurality of peaks, the selecting performed based on tracking peaks in the non-equalized signal; searching the non-equalized signal for a preamble before initiating a process of receiving payload data, to reduce false data reception caused by noise or interference; and extracting data from the prepared non-equalized signal.
H04L 25/497 - Circuits d'émission; Circuits de réception à au moins trois niveaux d'amplitude par codage corrélatif, p.ex. par codage à réponse partielle ou par codage par modulation à échos
H04L 25/49 - Circuits d'émission; Circuits de réception à au moins trois niveaux d'amplitude
An apparatus for performing cryptographic primitives includes a processor that is configured to receive an instruction to perform a cryptographic primitive, where the instruction includes one or more operands, at least one of the operands indicates one or more data structures that include values for the cryptographic primitive, and where the values include a first value indicating a mode of encryption that indicates an order of performing an encryption operation and an authentication operation and a second value indicating a cipher type; and perform the cryptographic primitive and store an output of the cryptographic primitive in an output data structure.
H04L 29/06 - Commande de la communication; Traitement de la communication caractérisés par un protocole
H04L 9/06 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p.ex. système DES
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
12.
EXPLICIT BEAMFORMING IN A HIGH EFFICIENCY WIRELESS LOCAL AREA NETWORK
A first communication device receives a sounding packet from a second communication device and develops beamforming information based on the sounding packet. The first communication device transmits beamforming feedback to the second communication device, the beamforming feedback including beamforming information for use by the second communication device to beamsteer a data packet to the first communication device, the data packet having a data portion that includes a second number of OFDM tones greater than a first number of OFDM tones in the sounding packet. After transmitting the beamforming feedback, the first communication device receives the data packet from the second communication device, the data packet including one or more data OFDM symbols, each of the one or more data OFDM symbols having the second number of OFDM tones.
H04B 7/0456 - Sélection de matrices de pré-codage ou de livres de codes, p.ex. utilisant des matrices pour pondérer des antennes
H04B 7/06 - Systèmes de diversité; Systèmes à plusieurs antennes, c. à d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
H04W 16/28 - Structures des cellules utilisant l'orientation du faisceau
In an embodiment, a method includes programming a control signal that specifies a target resistance and a target voltage in a circuit. The method further includes sending the control signal to at least one transistor configured to control a current flow in the circuit. The method further includes providing, as an output, a signal with the target voltage and target resistance.
H03K 19/00 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion
H03K 19/20 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion caractérisés par la fonction logique, p.ex. circuits ET, OU, NI, NON
14.
WIRELINE TRANSCEIVER WITH INTERNAL AND EXTERNAL CLOCK GENERATION
An integrated circuit device having functional circuitry driven by a clock signal includes onboard clock generation circuitry. The clock generation circuitry includes an input configured to accept a frequency reference signal, at least one variable loading capacitor coupled to the input for converting the crystal resonator signal into a calibrated clock signal, and calibration circuitry configured to calibrate the at least one variable loading capacitor based on a reference voltage. The input configured to accept a frequency reference signal may be configured to accept a crystal resonator signal.
A network device accesses, from a queue corresponding to a port of the device, a packet for processing. The device identifies a present operating region (ORE) of one or more OREs specified for the device, an ORE being associated with at least one of (i) one or more device attributes, or (ii) one or more environmental factors associated with an environment in which the device is operational. The device determines a number of power credits available for processing one or more packets. In response to determining that the number of power credits available is non-negative, the device completes processing of the packet. The device computes, based at least on the present ORE, a power credit reduction for the packet, which corresponds to an amount of power for processing the packet, and reduces the number of power credits available by the power credit reduction for the packet.
G06F 1/3296 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par diminution de la tension d’alimentation ou de la tension de fonctionnement
A method of reading servo wedge data from a rotating constant-density magnetic storage medium having a plurality of tracks, where each track is written at a track pattern frequency, the respective track pattern frequencies varying from a lowest frequency at an innermost one of the tracks to a highest frequency at an outermost one of the tracks, includes, for each respective track, determining, based on the pattern frequency of the respective track, a desired sampling position, sampling actual samples of servo wedge data based on a sampling clock used for all tracks, having a sampling frequency at least equal to the track pattern frequency of the outermost track, determining a phase relationship of the desired sampling position to the sampling clock, and, depending on the phase relationship between the sampling position and the sampling clock, interpolating a sample, or omitting interpolation of a sample and squelching the interpolation clock.
A method for writing repeatable run-out (RRO) data, to surfaces of a rotating magnetic storage medium in a storage device having two read channels, includes detecting, with a first head, using a first read channel, a servo sync mark (SSM) on a first track on a first surface, establishing a recurring servo-gating signal at a successive fixed interval from the SSM, detecting, with the first head, servo signals from the first track on occurrence of the recurring servo-gating signal, processing the servo signals from the first track, to generate first positioning signals for positioning the first head relative to the first track, following a similar procedure with a second read channel having a second head to generate second positioning signals for the second read head, and writing first and second RRO data to servo wedges of the first and second tracks according to the respective positioning signals.
G11B 5/596 - Disposition ou montage des têtes par rapport aux supports d'enregistrement comportant des dispositions pour déplacer la tête dans le but de maintenir l'alignement relatif de la tête et du support d'enregistrement pendant l'opération de transduction, p.ex. pour compenser les irrégularités de surface ou pour suivre les pistes pour suivre les pistes d'un disque
18.
Reduction of four-wave mixing crosstalk in optical links
A transmitter includes at least three tunable laser sources, an optical multiplexer, and a processor. The at least three tunable laser sources are configured to receive respective data streams, and to output respective Tx light beams at different respective carrier frequencies, modulated with the respective data streams. The optical multiplexer is configured to combine the multiple Tx light beams to produce a combined beam formed of the modulated Tx light beams at the different carrier frequencies, and to transmit the combined beam over an optical fiber. The processor is configured to receive a notification indicative of an interference occurring due to Four-Wave Mixing (FWM) in the optical fiber, and to modify at least one of the carrier frequencies responsively to the notification in order to mitigate the interference due to FWM.
H04B 10/50 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs
G02B 6/293 - Moyens de couplage optique ayant des bus de données, c. à d. plusieurs guides d'ondes interconnectés et assurant un système bidirectionnel par nature en mélangeant et divisant les signaux avec des moyens de sélection de la longueur d'onde
An integrated circuit includes a silicon photonics substrate having a silicon-based material, silicon photonics components formed in the silicon photonics substrate to receive and transmit optical signals, and electrical connections; a transimpedance amplifier chip arranged on the silicon photonics substrate, having a silicon-germanium material that is different than the silicon-based material, connected via the electrical connections to at least one of the silicon photonics components configured to receive an optical signal, and configured to process a received optical signal and output a processed signal to a digital signal processor; and a driver chip arranged on the silicon photonics substrate, having CMOS material that is different than the silicon-germanium material and the silicon-based material, connected via the electrical connections to drive at least one of the silicon photonics components configured to generate an optical signal for transmission.
H04B 10/40 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs-récepteurs
G02B 6/12 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES - Détails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p.ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/126 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES - Détails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p.ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré utilisant des effets de polarisation
G02B 6/42 - Couplage de guides de lumière avec des éléments opto-électroniques
H01S 3/13 - Stabilisation de paramètres de sortie de laser, p.ex. fréquence ou amplitude
A multi-chip package includes first and second groups of integrated circuit (IC) chips and a transfer IC chip disposed in the multi-chip package. The transfer IC chip is communicatively interposed between the first and second groups of IC chips and is configured to transfer signals from at least a first IC chip of the first group of IC chips to at least a second IC chip of the second group of IC chips or an output interface. The output interface is configured to output first data from the multi-chip package. A first set of ultra-short reach (USR) signaling links connects the first group of IC chips to the transfer IC chip. A second set of USR signaling links connects the second group of IC chips to the transfer IC chip. Each of the USR signaling links comprises a trace length of less than one inch.
Forming a metal gate transistor includes forming a semiconductor channel in a substrate, and depositing a source electrode and a drain electrode on the semiconductor channel. The source and drain electrodes are spaced apart. Dielectric spacers are provided above the source and drain electrodes to define a gate void spanning the source and drain electrodes. A dielectric layer is deposited on a bottom wall and sidewalls of the gate void. A work-function metal layer is deposited on the dielectric layer. The work-function metal layer is etched away from the sidewalls leaving the work-function metal layer on the bottom wall to control work function between the semiconductor channel and a conductive metal gate material to be deposited. The gate void above the work-function metal layer on the bottom wall, and between the dielectric layers on the sidewalls, is filled with the conductive metal gate material.
H01L 21/3213 - Gravure physique ou chimique des couches, p.ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/66 - Types de dispositifs semi-conducteurs
22.
Semiconductor device with mechanism to prevent reverse engineering
A semiconductor device is configured to implement a security protocol. The semiconductor device includes an entropy source that includes a plurality of bitcells. The entropy source is configured to output a sequence of physical unclonable function bit values based on intrinsic properties of the plurality of bitcells to generate a unique device secret for the security protocol, and selectively damage at least a portion of the plurality of bitcells to prevent reverse engineering the sequence of physical unclonable function bit values.
G06F 21/71 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information
G06F 21/14 - Protection des logiciels exécutables contre l’analyse de logiciel ou l'ingénierie inverse, p.ex. par masquage
A circuit and corresponding method perform resource arbitration. The circuit comprises a pending arbiter (PA) that outputs a PA selection for accessing a resource. The PA is selection based on PA input. The PA input represents respective pending-state of requesters of the resource. The circuit further comprises a valid arbiter (VA) that outputs a VA selection for accessing the resource. The VA selection is based on VA input. The VA input represents respective valid-state of the requesters. The circuit performs a validity check on the PA selection output. The circuit outputs a final selection for accessing the resource by selecting, based on the validity check performed, the PA selection output or VA selection output. The circuit addresses arbitration fairness issues that may result when multiple requesters are arbitrating to be selected for access to a shared resource and such requesters require a credit (token) to be eligible for arbitration.
A circuit detects a voltage droop exhibited by a power supply. A first signal delay line outputs a first delayed signal, and is comprised of delay elements having a first threshold voltage. A second delay line outputs a second delayed signal, and is comprised of delay elements having a second threshold voltage that is higher than the first threshold voltage. A phase detector compares the first and second delayed signals and outputs a comparison signal indicating which of the first and second signal delay lines exhibits a shorter delay. A reset circuit resets the first and second signal delay lines in response to the comparison signal, and a clock controller outputs a command to adjust a clock frequency or engage in other mitigation measures based on the comparison signal.
G01R 25/00 - Dispositions pour procéder aux mesures de l'angle de phase entre une tension et un courant ou entre des tensions ou des courants
H03K 5/14 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de lignes à retard
H03L 7/00 - Commande automatique de fréquence ou de phase; Synchronisation
25.
System and method for schedule-based I/O multiplexing for integrated circuit (IC) scan test
An approach is proposed to support schedule-based I/O multiplexing for scan testing of an IC. A plurality of I/Os are assigned to a plurality of blocks in the IC for scan testing based on a set of slots under a set of schedules. Each of the set of slots includes a fixed number of scan input pins/pads and scan output pins/pads of the IC. Each slot is then assigned to a specific block on the IC for the scan test until all of the slots available are utilized. The group of assigned blocks is referred to as a schedule, and all of these blocks belonging to this schedule are scan tested in parallel at the same time. The remaining blocks on the IC are also assigned to the slots until all blocks on the IC are assigned to a schedule to be scan tested.
G01R 31/3185 - Reconfiguration pour les essais, p.ex. LSSD, découpage
G01R 31/319 - Matériel de test, c. à d. circuits de traitement de signaux de sortie
G06F 30/34 - Conception de circuits pour circuits reconfigurables, p.ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 11/4093 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. mémoires tampon de données
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
26.
OUT-OF-BAND BASED INDEPENDENT LINK TRAINING OF IN-BAND LINKS BETWEEN HOST DEVICES AND OPTICAL MODULES
A first optical module includes an optical transceiver and a chip. The optical transceiver, subsequent to completion of link training of an in-band transmission link between the first optical module and a host device, waits for a second optical module to come up including transmitting a first awake signal from the first optical module to the second optical module, and receives a second awake signal from the second optical module when the second optical module is up. The chip i) based on a first out-of-band signal transmitted via an out-of-band link, performs the link training of the in-band transmission link independently of an in-band reception link between the first optical module and the host device, and ii) based on the second awake signal and a second out-of-band signal transmitted via the out-of-band link, performs link training of the in-band reception link independent of the in-band transmission link.
H04B 10/079 - Dispositions pour la surveillance ou le test de systèmes de transmission; Dispositions pour la mesure des défauts de systèmes de transmission utilisant un signal en service utilisant des mesures du signal de données
H04B 10/077 - Dispositions pour la surveillance ou le test de systèmes de transmission; Dispositions pour la mesure des défauts de systèmes de transmission utilisant un signal en service utilisant un signal de surveillance ou un signal supplémentaire
H04B 10/80 - Aspects optiques concernant l’utilisation de la transmission optique pour des applications spécifiques non prévues dans les groupes , p.ex. alimentation par faisceau optique ou transmission optique dans l’eau
27.
OUT-OF-BAND BASED INDEPENDENT LINK TRAINING OF IN-BAND LINKS BETWEEN HOST DEVICES AND OPTICAL MODULES
A first optical module includes an optical transceiver and a chip. The optical transceiver, subsequent to completion of link training of an in-band transmission link between the first optical module and a host device, waits for a second optical module to come up including transmitting a first awake signal from the first optical module to the second optical module, and receives a second awake signal from the second optical module when the second optical module is up. The chip i) based on a first out-of-band signal transmitted via an out-of-band link, performs the link training of the in-band transmission link independently of an in-band reception link between the first optical module and the host device, and ii) based on the second awake signal and a second out-of-band signal transmitted via the out-of-band link, performs link training of the in-band reception link independent of the in-band transmission link.
H04J 14/02 - Systèmes multiplex à division de longueur d'onde
H04B 10/40 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs-récepteurs
28.
GATE ALL-AROUND (GAA) FIELD EFFECT TRANSISTORS (FETS) FORMED ON BOTH SIDES OF A SUBSTRATE
An electronic device (11) includes a substrate (55), first and second semiconductor devices (22, 33), and a power supply structure (88b). The first semiconductor device (22) includes a first plurality of gate all-around (GAA) field effect transistors (FETs) (44) formed over a first side (25) of substrate (55). The second semiconductor device (33) includes a second plurality of GAA FETs (44) formed over a second side (35) of substrate (55), opposite first side (25). The power supply structure (88b) is (a) disposed at the first side (25), and (b) configured to supply power to one or more of: (i) the first plurality of GAA FETs (44) through first electrical couplings (77) disposed at the first side (25), and (ii) the second plurality of GAA FETs (44) through second electrical couplings (77) including inter-side vias (ISVs) (66) traversing the substrate (55) from the second side (35) to the first side (35).
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
29.
System and methods for firmware security mechanism
A new approach is proposed to support a hardware-based lock mechanism having a hardware-based lock unit associated with a resource, wherein the lock is utilized by an arbitrator to arbitrate between multiple agents requesting access to the resource. When a first agent requests access to resource in unlocked state, the arbitrator creates a lock ID and set a locked state indicating that the resource is locked. The lock ID is provided to the first agent, which now has exclusive control over the resource. The arbitrator ensures that any agent with the same ID may access the resource. When a second agent requests access to the resource with a lock ID to the arbitrator, it is granted access to the resource if the lock ID provided matches the one stored on the lock unit. If there is a mismatch between the lock IDs, access to the resource is denied.
G06F 21/71 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information
A multi-port transceiver comprises a plurality of first ports, a first communication interface, and a second communication interface. Multi-rate interleaver circuitry interleaves i) a plurality of first data streams, each received via a respective first port at a first data rate, and ii) a second data stream received via the first communication interface at a second data rate, to generate a third data stream to be transmitted via the second communication interface at a third data rate. Multi-rate deinterleaver circuitry deinterleaves a fourth data stream that was received via the second communication interface at the third data rate into i) a plurality of fifth data streams, each fifth data stream to be transmitted via a respective first port at the first data rate, and ii) a sixth data stream to be transmitted via the first communication interface at the second data rate.
In a storage area network operating in accordance with a transport-level protocol to interconnect host and target devices, where the transport-level protocol issues congestion notifications when any of the host or target devices becomes congested, a method for reducing congestion includes, on receipt of a request to (a) write data to one of the target devices or (b) read data from one of the target devices for return to one of the host devices, (A) determining whether congestion already exists at (a) the target device to which the write request is directed, or (b) the host device to which data from the read request is to be returned, and (B) when a congestion state already exists, comparing current depth of a queue of write or read requests to a maximum permissible queue depth. When the current depth of the queue exceeds a maximum permissible queue depth, the request is rejected.
The present disclosure describes apparatuses and methods for implementing an adaptive low-density parity check (LDPC) decoder. In various aspects, an adaptive LDPC decoder processes a first portion of data using first parameters effective to change a status of the LDPC decoder. The LDPC decoder selects second parameters of the LDPC decoder based on the status of the LDPC decoder. The LDPC decoder then processes a second portion of the data with the LDPC decoder using the second parameters and provides decoded data of the channel based on at least the processing the first portion of the data using the first parameters and the processing of the second portion of the data using the second parameters. By adaptively altering the decoding parameters based the status of the decoder, the adaptive LDPC decoder may decode channel data in fewer decoding iterations or with a higher success rate, thereby improving LDPC decoding performance.
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
33.
Gate All-Around (GAA) Field Effect Transistors (FETS) Formed on Both Sides of a Substrate
An electronic device includes a substrate, first and second semiconductor devices, and a power supply structure. The first semiconductor device includes a first plurality of gate all-around (GAA) field effect transistors (FETs) formed over a first side of the substrate. The second semiconductor device includes a second plurality of GAA FETs formed over a second side of the substrate, opposite the first side. The power supply structure is (a) disposed at the first side, and (b) configured to supply power to one or more of: (i) the first plurality of GAA FETs through first electrical couplings disposed at the first side, and (ii) the second plurality of GAA FETs through second electrical couplings including one or more inter-side vias (ISVs) traversing the substrate from the second side to the first side.
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 21/84 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant autre chose qu'un corps semi-conducteur, p.ex. étant un corps isolant
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p.ex. structures d'interconnexions enterrées
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
A first communication device performs a handshaking procedure with a second communication device, the handshaking procedure associated with transitioning from an active mode to a low power mode. The first communication device transmits data and/or idle symbols to the second communication device i) after completion of the handshake procedure, and ii) at least until the earlier of a) a time period expiring, and b) determining that the second communication device quieted a transmitter of the second communication device. The first communication device transitions to the low power mode in connection with the handshaking procedure.
The present disclosure describes apparatuses and methods for implementing an adaptive low-density parity check (LDPC) decoder performing iterations on bit-flipping or symbol-flipping operations. In various aspects, an adaptive LDPC decoder (130) processes (704) a first portion of data using first parameters, e.g. flipping thresholds, effective to change a status of the LDPC decoder, e.g. syndrome weight. The LDPC decoder selects (706) second parameters, e.g. adaptively changes flipping thresholds, of the LDPC decoder based on the status of the LDPC decoder. The LDPC decoder then processes (708) a second portion of the data with the LDPC decoder using the second parameters and provides (712) decoded data of the channel based on at least the processing the first portion of the data using the first parameters and the processing of the second portion of the data using the second parameters. By adaptively altering the decoding parameters based the status of the decoder, the adaptive LDPC decoder may decode channel data in fewer decoding iterations or with a higher success rate, thereby improving LDPC decoding performance.
H03M 13/37 - Méthodes ou techniques de décodage non spécifiques à un type particulier de codage prévu dans les groupes
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
36.
Disk writing mode with timing control of main pole relaxation
When writing data to a magnetic data storage medium, it is detected whether duration, before occurrence of a data transition, of data to be written exceeds a predetermined threshold. When the duration, before the transition, of the data to be written exceeds the predetermined threshold, the data is written by applying an initial pulse and then maintaining, until a shut-off pulse, a steady-state write current having an amplitude less than the initial pulse. A shut-off adjustment is determined based on a predetermined delay. The shut-off pulse is initiated at a time based on one bit period prior to the transition, adjusted by the shut-off adjustment. When the duration, before the transition, of the data to be written is at most equal to the predetermined threshold, the data is written by applying the initial pulse without applying a steady-state write current before the transition.
G11B 20/10 - Enregistrement ou reproduction numériques
G11B 11/105 - Enregistrement sur, ou reproduction depuis le même support d'enregistrement, dans lesquels, pour ces deux opérations, les procédés ou les moyens sont couverts par différents groupes principaux des groupes ou par différents sous-groupes du groupe ; Supports d'enregistrement correspondants utilisant l'enregistrement par magnétisation ou démagnétisation utilisant un faisceau de lumière ou un champ magnétique pour l'enregistrement et un faisceau de lumière pour la reproduction, p.ex. enregistrement thermomagnétique induit par la lumière ou reproduction par l'effet Kerr
A receiver includes an optical front-end and digital circuitry. The optical front-end is configured to receive an optical signal including first and second optical signal components having first and second polarizations and modulated with symbols at a symbol rate. The digital circuitry is configured to derive first and second digital signals representing the first and second optical signal components having the first and second polarizations. The digital circuitry includes a clock detector configured to calculate correlation terms, the correlation terms being calculated in a frequency-domain with a frequency offset commensurate with the symbol rate. The clock detector is configured to recover a clock signal of the symbols by (i) summing selected pairs of the correlation terms, and (ii) calculating or estimating a sum-of-squares of the summed pairs.
Methods and apparatus for providing soft and blind combining for PUSCH acknowledgement (ACK) processing. In an exemplary embodiment, a method includes soft-combining acknowledgement (ACK) bits received from a UE that are contained in a received sub-frame of symbols. The ACK bits are soft-combined using a plurality of scrambling sequences to generate a plurality of hypothetical soft-combined ACK bit streams. The method also includes receiving a parameter that identifies a selected scrambling sequence to be used. The method also includes decoding a selected hypothetical soft-combined ACK bit stream to generate a decoded ACK value, wherein the selected hypothetical soft-combined ACK bit stream is selected from the plurality of hypothetical soft-combined ACK bit streams based on the parameter.
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
H04L 25/06 - Moyens pour rétablir le niveau à courant continu; Correction de distorsion de polarisation
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H04L 1/1607 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue en utilisant un canal de retour dans lesquelles le canal de retour transporte des signaux de contrôle, p.ex. répétition de signaux de demande - Détails du signal de contrôle
H04W 72/121 - Planification du trafic sans fil pour les groupes de terminaux ou d’utilisateurs
H04W 72/1268 - Jumelage du trafic à la planification, p.ex. affectation planifiée ou multiplexage de flux de flux de données en liaison ascendante
A laser device based on silicon photonics with in-cavity power monitor includes a gain chip, a reflector, and a photodiode. The gain chip is mounted on a silicon photonics substrate and is configured to emit light from an active region bounded between a frontend facet and a backend facet. The reflector is configured to reflect the light in a cavity formed between the reflector and the frontend facet through which a laser light is output. The photodiode is coupled to one or more waveguides in the cavity by a splitter disposed directly in an optical path between the reflector and a component positioned in the cavity. The photodiode is configured to measure power of light propagating through the cavity between the reflector and the component.
H01S 5/026 - Composants intégrés monolithiques, p.ex. guides d'ondes, photodétecteurs de surveillance ou dispositifs d'attaque
H01S 5/02 - Lasers à semi-conducteurs - Détails ou composants structurels non essentiels au fonctionnement laser
H01S 5/343 - Structure ou forme de la région active; Matériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p.ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p.ex. laser AlGaAs
A method for data transmission includes receiving a data stream from a host device, the data stream as received from the host device including encoded data, separating the encoded data in the data stream into first data blocks and second data blocks, and generating a first forward error correction (FEC) block. The first FEC block includes a first parity section and a first data section, the first parity section includes a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section includes the first data blocks and the second data blocks. The method further includes transmitting the first FEC block.
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H03M 13/15 - Codes cycliques, c. à d. décalages cycliques de mots de code produisant d'autres mots de code, p.ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]
H03M 13/29 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes combinant plusieurs codes ou structures de codes, p.ex. codes de produits, codes de produits généralisés, codes concaténés, codes interne et externe
H04B 14/02 - Systèmes de transmission non caractérisés par le milieu utilisé pour la transmission caractérisés par l'utilisation de la modulation par impulsions
41.
HIERARCHICAL STATISICALLY MULTIPLEXED COUNTERS AND A METHOD THEREOF
Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.
H03K 23/64 - Compteurs d'impulsions comportant des chaînes de comptage; Diviseurs de fréquence comportant des chaînes de comptage avec une base ou racine différente d'une puissance de deux
H04L 47/62 - Ordonnancement des files d’attente caractérisé par des critères d’ordonnancement
09 - Appareils et instruments scientifiques et électriques
Produits et services
Computer hardware; computer chips; semiconductors; semiconductor chips and chip sets; microprocessors; central processing units; integrated circuits; integrated circuit chips; software and firmware for controlling and using integrated circuits; integrated circuits in the nature of application specific standard products (ASSPs), application specific integrated circuits (ASICs), and system-on-chips (SoCs), and related downloadable software for use in automotive applications, namely, downloadable software for providing high-performance computing and secure Ethernet connectivity in a vehicle; data communication circuits; computer network bridges; Ethernet switches; Ethernet adapters; Ethernet transceivers; Ethernet controllers; Ethernet repeaters; data processors for packet processing, encryption, Ethernet connectivity, digital signal processing, telematic control, advanced driver assistance, in-vehicle cameras and sensors, and artificial intelligence for use in automotive applications; processors, namely, artificial intelligence data processors, server data processors, general purpose computer data processors, high-performance computing data processors, digital signal data processors, data processors, programmable data processors, audio or video data processors; computer hardware and downloadable software and firmware for setting up, configuring, managing, operating, and securing local and wide-area computer networks and network products; In-Vehicle Networking (INV) systems comprised of computer hardware and recorded software for facilitating electronic data communication transmission used to connect electronic control units in automobiles; computer hardware and downloadable software and firmware for use in enabling autonomous driving vehicles, connected vehicles, and components of autonomous driving vehicles and connected vehicles; lidar apparatus; computer hardware and software for lidar apparatus.
43.
Traffic characteristics for target wake time (TWT) negotiation
A first communication device generates a beacon frame that includes i) parameters of a broadcast target wake time (TWT) schedule and ii) information regarding a quantity of client stations that have currently joined the broadcast TWT schedule. The first communication device transmits the beacon frame to inform one or more second communication devices of i) the parameters of the broadcast TWT schedule and ii) the quantity of client stations that have currently joined the broadcast TWT schedule.
H04L 69/324 - Protocoles de communication intra-couche entre entités paires ou définitions d'unité de données de protocole [PDU] dans la couche liaison de données [couche OSI 2], p.ex. HDLC
H04W 28/18 - Négociation des paramètres de télécommunication sans fil
An interface in a communications system includes a physical layer transceiver (PHY) for coupling to a wireline channel medium, and for coupling to a functional device via a single-ended cable. The PHY is an integrated circuit (IC) device having first and second differential input/output (I/O) conductors for coupling to the functional device, an impedance element configured to terminate a first one of the differential I/O conductors to a system ground, a second one of the differential I/O conductors being coupled to the single-ended cable, and a common-mode filter coupled to both of the differential I/O conductors. The PHY may further include a printed circuit board (PCB), with the IC device being mounted on the PCB, the first and second differential I/O conductors being signal traces on the PCB. The single-ended cable may be a coaxial cable.
A circuit and corresponding method employ mixed-dimension order routing. The circuit comprises an interconnect, associated with a two-dimensional (2D) coordinate system, and a switch coupled to the interconnect. The switch determines a route path for a flit based on a mixed-dimension order routing method. The flit originates at an origin. The mixed-dimension order routing method employs, based on the origin of the flit, vertical-to-horizontal dimension routing or horizontal-to-vertical dimension routing. The switch routes the flit via the interconnect of the circuit based on the route path determined. The vertical-to-horizontal dimension routing and horizontal-to-vertical dimension routing are relative to the 2D coordinate system. The mixed-dimension order routing method prevents deadlock and congestion that otherwise degrade performance of the circuit.
H04L 49/109 - TRANSMISSION D'INFORMATION NUMÉRIQUE, p.ex. COMMUNICATION TÉLÉGRAPHIQUE Éléments de commutation de paquets caractérisés par la construction de la matrice de commutation intégrés sur micropuce, p.ex. interrupteurs sur puce
H04L 47/122 - Prévention de la congestion; Récupération de la congestion en détournant le trafic des entités congestionnées
A circuit and corresponding method generate a filtered timestamp. The circuit comprises recursive filter logic. The circuit generates the filtered timestamp from a received timestamp by filtering the received timestamp via the recursive filter logic. The recursive filter logic reduces jitter in the filtered timestamp relative to jitter of the received timestamp. The jitter represents a deviation of the received timestamp from a target (ideal) timestamp. The circuit outputs the filtered timestamp generated. The filtered timestamp is a more accurate representation of the target timestamp, relative to the received timestamp, due to the jitter reduced.
H04L 43/106 - Surveillance active, p.ex. battement de cœur, utilitaire Ping ou trace-route en utilisant des informations liées au temps dans des paquets, p.ex. en ajoutant des horodatages
A silicon photonics integration circuit includes a silicon substrate member; a RX sub-circuit formed in the silicon substrate member including multiple RX-input ports each having a mode size converter configured to receive an incoming light signal into one of multiple waveguides and multiple RX photo detectors coupled respectively to the multiple waveguides; and a TX sub-circuit formed in the silicon substrate member including one or more TX-input ports each having a mode size converter coupled to a first TX photo detector into one input waveguide, one or more 1×2 directional couplers each coupled between the input waveguide and two mod-input waveguides, multiple modulators coupled between respective multiple mod-input waveguides and multiple mod-output waveguides each being coupled to a second TX photo detector into one of multiple output waveguides, and multiple TX-output ports each having a mode size converter coupled to respective one of the multiple output waveguides.
G02B 6/12 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES - Détails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p.ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
H04B 10/50 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs
A packet to be forwarded over a computer network to a destination is received. A group of multiple network paths is available to forward to the packet to the destination. One or more path selection factors are determined to be used to identify a specific network load balancing algorithm to select a specific network path from the group of multiple network paths. The one or more path selection factors include at least one path selection factor determined based at least in part on a dynamic state of the computer network or a network node in the computer network. In response to selecting, by the specific network load balancing algorithm, the specific network path from among the group of multiple network paths, the packet is forwarded over the specific network path.
A method for writing data to a magnetic data storage medium includes detecting whether the duration, before occurrence of a data transition, of data to be written exceeds a predetermined threshold, and, when the duration, before the occurrence of the data transition, of the data to be written exceeds the predetermined threshold, writing the data by applying an initial pulse and then maintaining a steady-state write current for a defined interval, and when the duration, before the occurrence of the data transition, of the data to be written is at most equal to the predetermined threshold, writing the data by applying the initial pulse without applying a steady-state write current before the data transition. The predetermined threshold may be determined by size of a magnetic bubble formed when writing a single bit to the magnetic data storage medium. A subsequent pulse may be applied following the defined interval.
G11B 11/105 - Enregistrement sur, ou reproduction depuis le même support d'enregistrement, dans lesquels, pour ces deux opérations, les procédés ou les moyens sont couverts par différents groupes principaux des groupes ou par différents sous-groupes du groupe ; Supports d'enregistrement correspondants utilisant l'enregistrement par magnétisation ou démagnétisation utilisant un faisceau de lumière ou un champ magnétique pour l'enregistrement et un faisceau de lumière pour la reproduction, p.ex. enregistrement thermomagnétique induit par la lumière ou reproduction par l'effet Kerr
G11B 7/00 - Enregistrement ou reproduction par des moyens optiques, p.ex. enregistrement utilisant un faisceau thermique de rayonnement optique, reproduction utilisant un faisceau optique à puissance réduite; Supports d'enregistrement correspondants
G11B 5/012 - Enregistrement, reproduction ou effacement sur des disques magnétiques
A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.
H04L 49/109 - TRANSMISSION D'INFORMATION NUMÉRIQUE, p.ex. COMMUNICATION TÉLÉGRAPHIQUE Éléments de commutation de paquets caractérisés par la construction de la matrice de commutation intégrés sur micropuce, p.ex. interrupteurs sur puce
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
H04L 45/64 - Routage ou recherche de routes de paquets dans les réseaux de commutation de données à l'aide d'une couche de routage superposée
H04L 45/745 - Recherche de table d'adresses; Filtrage d'adresses
H04L 49/1546 - Multi-étages non bloquants, p.ex. Clos en utilisant un fonctionnement en pipeline
H04L 69/22 - Analyse syntaxique ou évaluation d’en-têtes
H04L 49/00 - TRANSMISSION D'INFORMATION NUMÉRIQUE, p.ex. COMMUNICATION TÉLÉGRAPHIQUE Éléments de commutation de paquets
G06F 16/00 - Recherche d’informations; Structures de bases de données à cet effet; Structures de systèmes de fichiers à cet effet
H04L 67/63 - Ordonnancement ou organisation du service des demandes d'application, p.ex. demandes de transmission de données d'application en utilisant l'analyse et l'optimisation des ressources réseau requises en acheminant une demande de service en fonction du contenu ou du contexte de la demande
51.
Circuit and Method for Timestamp Filtering with Input/Output Format Conversion
A circuit and corresponding method perform timestamp filtering. The circuit comprises input format-conversion logic that converts a received timestamp from an original format to an intermediate format. The circuit further comprises recursive filter logic coupled to the input format-conversion logic. The recursive filter logic generates a filtered timestamp in the intermediate format by filtering the received timestamp in the intermediate format. The circuit further comprises output format-conversion logic coupled to the recursive filter logic. The output format-conversion logic converts the filtered timestamp from the intermediate timestamp format to the original timestamp format and outputs the filtered timestamp in the original timestamp format. Converting the received timestamp into a different format avoids use of complex logic to handle rollover of input values, thereby reducing area and power consumption of the circuit.
A circuit and corresponding method perform timestamp filtering. The circuit comprises recursive filter logic that implements a recursive least-squares (RLS) filter. The circuit (i) generates a filtered timestamp from a received timestamp by filtering the received timestamp via the recursive filter logic. The recursive filter logic applies the RLS filter to a portion of the received timestamp. A number of bits of the portion is less relative to a total number of bits of the received timestamp. The circuit outputs the filtered timestamp generated. Applying the RLS filter to the portion enables the circuit to be more efficient (e.g., smaller adders, fewer flipflops, etc.), thereby reducing area and power consumption of the circuit.
H04L 43/106 - Surveillance active, p.ex. battement de cœur, utilitaire Ping ou trace-route en utilisant des informations liées au temps dans des paquets, p.ex. en ajoutant des horodatages
A first communication device determines that a trigger frame and another frame are to be transmitted to at least a second communication device. The first communication device determines whether the second communication device announced support of aggregation of buffer status report (BSRP) trigger frames with additional frames. In response to the first communication device determining that the second communication device announced support of aggregation of BSRP trigger frames with additional frames, the first communication device generates an aggregate media access control protocol data unit (A-MPDU) to include the BSRP trigger frame and the other frame, and transmits the A-MPDU within a packet. In response to the first communication device determining that the second communication device did not announce support of aggregation of BSRP trigger frames with additional frames, the first communication device transmits a packet having only the BSRP trigger frame.
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
H04W 72/0453 - Ressources du domaine fréquentiel, p.ex. porteuses dans des AMDF [FDMA]
H04W 84/12 - Réseaux locaux sans fil [WLAN Wireless Local Area Network]
54.
METHOD, SYSTEM AND DEVICE OF SERIALIZING AND DE-SERIALIZING THE DELIVERY OF SCAN TEST DATA THROUGH CHIP I/O TO REDUCE THE SCAN TEST DURATION OF AN INTEGRATED CIRCUIT
An integrated circuit verification system including automatic test equipment (ATE) and a device under test (DUT) having an internal test data de-serializer and test response data serializer. Specifically, the de-serializer of the DUT is able to de-serialize a test pattern or scan test data generated and received from an ATE at a general-purpose I/O pin (or functional pin) of the DUT for testing a circuit under test (CUT) of the DUT and then serialize the response to the test data with the serializer for output back to the ATE via the same or a different general-purpose I/O pin (or functional pin) of the DUT.
G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation
55.
A METHOD OF USING BIT VECTORS TO ALLOW EXPANSION AND COLLAPSE OF HEADER LAYERS WITHIN PACKETS FOR ENABLING FLEXIBLE MODIFICATIONS AND AN APPARATUS THEREOF
Embodiments of the apparatus for modifying packet headers relate to a use of bit vectors to allow expansion and collapse of protocol headers within packets for enabling flexible modification. A rewrite engine expands each protocol header into a generic format and applies various commands to modify the generalized protocol header. The rewrite engine maintains a bit vector for the generalized protocol header with each bit in the bit vector representing a byte of the generalized protocol header. A bit marked as 0 in the bit vector corresponds to an invalid byte, while a bit marked as 1 in the bit vector corresponds to a valid byte. The rewrite engine uses the bit vector to remove all the invalid bytes after all commands have been operated on the generalized protocol header to thereby form a new protocol header.
An optical transceiver includes optical circuitry disposed on a substrate and comprising a transmitter and a receiver. The circuitry includes least one multi-mode interferometer (MMI), including a multi-mode waveguide comprising an input face and an output face, the input and output faces being bisected by a longitudinal axis, the multi-mode waveguide having a predefined width transverse to the longitudinal axis. Ports are coupled to respective waveguides and are configured to launch one or more input beams through the input face and receive one or more output beams from the output face. The ports include, on at least one of the faces, two or more ports at respective locations that are offset transversely from the longitudinal axis by at least λ0/300 from respective base transverse displacements that are equal to integer fractions of the width.
H04B 10/40 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs-récepteurs
H04B 10/11 - Dispositions spécifiques à la transmission en espace libre, c. à d. dans l’air ou le vide
G02B 6/293 - Moyens de couplage optique ayant des bus de données, c. à d. plusieurs guides d'ondes interconnectés et assurant un système bidirectionnel par nature en mélangeant et divisant les signaux avec des moyens de sélection de la longueur d'onde
57.
Method and apparatus for determining bit-error rate in a data channel
A method for determining a bit-error rate in data received on high-speed data channel that uses a forward-error-correcting decoder includes receiving at receiver circuitry on the high-speed data channel a received predetermined data pattern, comparing, bit-wise, the received predetermined data pattern to a locally generated copy of the predetermined data pattern to derive output bits representing whether there was an error in a corresponding bit of the received predetermined data pattern, to determine error bits in the received predetermined data pattern, grouping output bits from the comparing into symbols and codewords, and for each codeword for which a count of symbols containing errors exceeds a number of symbols correctable by the forward-error-correcting decoder, counting a total number of bit errors contained in the symbols containing errors, for use in adjusting the receiver circuitry in response to the total number of bit errors.
H03M 13/01 - Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
H03M 13/15 - Codes cycliques, c. à d. décalages cycliques de mots de code produisant d'autres mots de code, p.ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]
58.
Bandwidth indication, negotiation and TXOP protection with multiple channel segments
A communication device generates a first packet to include a first indication of one or more first frequency subchannels in a first frequency segment that will be utilized to transmit the first packet. The communication device also generates a second packet to include a second indication of one or more second frequency subchannels in a second frequency segment that will be utilized to transmit the second packet. The communication device simultaneously transmits the first packet via the first frequency segment and the second packet via the second frequency segment.
H04W 72/0453 - Ressources du domaine fréquentiel, p.ex. porteuses dans des AMDF [FDMA]
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
H04W 72/23 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c. à d. en direction du terminal
H04W 74/08 - Accès non planifié, p.ex. accès aléatoire, ALOHA ou accès multiple par détection de porteuse [CSMA Carrier Sense Multiple Access]
H04W 84/12 - Réseaux locaux sans fil [WLAN Wireless Local Area Network]
H04L 1/1607 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue en utilisant un canal de retour dans lesquelles le canal de retour transporte des signaux de contrôle, p.ex. répétition de signaux de demande - Détails du signal de contrôle
H04L 69/22 - Analyse syntaxique ou évaluation d’en-têtes
H04L 101/622 - Adresses de couche 2, p.ex. adresses de contrôle d'accès au support [MAC]
59.
INTEGRATED CIRCUIT DEVICE EXPOSED DIE PACKAGE STRUCTURE WITH ADHESIVE
An integrated circuit (IC) device package includes a structure having a base and walls extending from the base, at least one IC die mounted to the base within the walls, each die having a top surface parallel to the base and having a thickness extending along an axis, perpendicular to the top surface, at most equal to a height of the walls, a thermally conductive heat spreader extending parallel to the base above the die and the walls, and an interface layer including an adhesive layer portion disposed between the walls and the heat spreader to adhere the heat spreader to the walls, and a thermal interface material (TIM) layer portion coplanar with, and laterally displaced from, the adhesive layer portion, the TIM layer portion being disposed in thermally conductive relationship between the heat spreader and each respective die, to dissipate heat from each respective die to the heat spreader.
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 23/42 - Choix ou disposition de matériaux de remplissage ou de pièces auxiliaires dans le conteneur pour faciliter le chauffage ou le refroidissement
A first communication device transmits first bitmap length capability information for the first communication device regarding block acknowledgment procedures, and receives second bitmap length capability information for a second communication device regarding block acknowledgment procedures. The first communication device performs a block acknowledgment procedure, including setting a block acknowledgment transmission window size for the block acknowledgment procedure based on the second bitmap length capability information for the second communication device, and a determination of whether a block acknowledgement frame used in the block acknowledgment procedure is a compressed block acknowledgement (C-BA) frame or a multi-station (multi-STA) block acknowledgement frame.
H04L 1/1607 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue en utilisant un canal de retour dans lesquelles le canal de retour transporte des signaux de contrôle, p.ex. répétition de signaux de demande - Détails du signal de contrôle
H04L 1/1829 - Dispositions spécialement adaptées au point de réception
H04L 1/1867 - Dispositions spécialement adaptées au point d’émission
H04B 7/26 - Systèmes de transmission radio, c. à d. utilisant un champ de rayonnement pour communication entre plusieurs postes dont au moins un est mobile
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
61.
INTEGRATED CIRCUIT DEVICE EXPOSED DIE PACKAGE STRUCTURE WITH ADHESIVE
An integrated circuit (IC) device package includes a structure having a base and walls extending from the base, at least one IC die mounted to the base within the walls, each die having a top surface parallel to the base and having a thickness extending along an axis, perpendicular to the top surface, at most equal to a height of the walls, a thermally conductive heat spreader extending parallel to the base above the die and the walls, and an interface layer including an adhesive layer portion disposed between the walls and the heat spreader to adhere the heat spreader to the walls, and a thermal interface material (TIM) layer portion coplanar with, and laterally displaced from, the adhesive layer portion, the TIM layer portion being disposed in thermally conductive relationship between the heat spreader and each respective die, to dissipate heat from each respective die to the heat spreader.
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/367 - Refroidissement facilité par la forme du dispositif
62.
System and methods for latency reduction for fuse reload post reset
A new approach is proposed that contemplates systems and methods to support post reset fuse reload for latency reduction. First, values of fuses are read once and stored into one or more load registers on an electronic device, wherein the load registers are protected. Once the values of the fuse are loaded into the load registers, a valid indicator of the load registers is set indicating that the values have been successfully loaded into the load registers. When other components of the electronic device need to access these values, the other components will check the load registers first. If it is determined that the valid indicator of the load registers is set, the stored values are read from the load registers instead of from the fuses. If the valid indicator of the load registers is not set, the values are loaded again from the fuses into the load registers.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
A wireless network interface of a first client station negotiates with an access point a first component channel of an operating channel via which the first client station is to receive wakeup frames from the access point. A wakeup radio of the first client station receives a wakeup packet from the access point. The wakeup packet spans the operating channel, which comprises at least four component channels, and one or more of the component channels within the operating channel are punctured so that the access point does not transmit the wakeup packet in the one or more component channels that are punctured. The wakeup packet includes a first wakeup frame for the first client station in the first component channel and one or more respective second wakeup frames for one or more second client stations in one or more respective second component channels.
A network controller for coupling a host device to a data network, in accordance with network command blocks initiated in a request queue in the host device, includes a channel interface configured to couple to the data network, where the channel interface includes memory configured to store the network command blocks and processing circuitry configured to execute the network command blocks to move data between the host device and the data network, and a host interface configured to couple the network controller to the host device, and to move the network command blocks from the request queue in the host device to the memory using cache operations, including fetching one of the network command blocks from the request queue upon receipt from the host device of a message advising that a request queue location has changed.
Systems and methods are provided for introducing time diversity in a transmitter. The systems and methods may include receiving, at the transmitter, a request from a receiver to retransmit data. The systems and methods may further include receiving an input of data corresponding to the data requested for retransmission at a first transmitter block. The systems and methods may further include operating on the signals using the first transmitter block in at least one of a first mode and a second mode, such that an output of signals from the first transmitter block is dependent on a time-varying function and corresponds to the data requested by the receiver for retransmission.
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H04L 1/1867 - Dispositions spécialement adaptées au point d’émission
H04L 1/1825 - Adaptation de paramètres spécifiques de protocoles ARQ en fonction des conditions de transmission
H04L 1/08 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue par émission répétée, p.ex. système Verdan
H04B 7/06 - Systèmes de diversité; Systèmes à plusieurs antennes, c. à d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
A preamble of physical layer (PHY) data unit includes a first legacy portion and a first non-legacy portion that follows the first legacy portion. The first non-legacy portion includes i) a first orthogonal frequency division multiplexing (OFDM) symbol that immediately follows the first legacy portion and that is modulated using binary phase shift keying (BPSK), and ii) a second OFDM symbol that immediately follows the first OFDM symbol and that is modulated using BPSK modulation rotated by 90 degrees (Q-BPSK). The modulation of the first and second OFDM symbols indicates to a receiver device that conforms to a first communication protocol that the data unit conforms to the first communication protocol. The first OFDM symbol being modulated using BPSK modulation causes a receiver device that conforms to a second communication protocol to determine that the PHY data unit conforms to a third communication protocol.
A communication device includes a convolutional interleaver and an encoder. The convolutional interleaver is configured to receive blocks of data defining symbol blocks that are encoded using a block code to correct an error in a block of data and to interleave the symbol blocks into a stream of interleaved symbol blocks. The encoder is configured to encode a set of symbol blocks among the interleaved symbol blocks with an error-correcting code to correct single bit errors in the set of symbol blocks. The error-correcting code is configured to generate an error-correcting block and to add the error-correcting block to the set of interleaved symbol blocks.
H03M 13/27 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes utilisant des techniques d'entrelaçage
H03M 13/15 - Codes cycliques, c. à d. décalages cycliques de mots de code produisant d'autres mots de code, p.ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]
Decompressing a compressed image to obtain a decompressed image includes receiving, in a compressed stream, compressed pixel values of the compressed image; decompressing, from the compressed stream, a first compressed pixel value of the compressed pixel values using a lossy floating-point decompression scheme to obtain a floating-point pixel value; rounding the floating-point pixel value to a nearest integer to obtain a pixel value of the decompressed image; and displaying or storing the decompressed image.
In a method for adapting an orthogonal frequency division multiplexing (OFDM) numerology configuration for use in a communication network one or more OFDM numerology configurations are adaptively selected at a first communication device to be used in communication with one or more second communication devices. Adaptively one or more OFDM numerology configurations includes selecting at least one combination of two or more of (i) a guard interval duration, (ii) a tone spacing, (iii) a starting location of the selected guard interval duration, and (iv) a starting location of the selected tone spacing. A physical layer (PHY) data unit to be transmitted to a second communication device is generated at the first communication device. The PHY data unit is generated using one of the one or more adaptively selected OFDM numerology configurations to generate OFDM symbols of at least a portion of the PHY data unit.
An Ethernet Physical Layer (PHY) device includes a link interface and a transceiver. The link interface is configured to connect to a full-duplex wired Ethernet link. The transceiver is configured to receive first Ethernet signals carrying first data at a first data rate over the Ethernet link in a first direction, the first Ethernet signals occupying a first frequency band, and to transmit second Ethernet signals carrying second data at a second data rate different from the first data rate, over the Ethernet link in a second direction that is opposite the first direction, the second Ethernet signals occupying a second frequency band that is different from the first frequency band.
H04L 5/14 - Fonctionnement à double voie utilisant le même type de signal, c. à d. duplex
H04B 3/23 - Systèmes à ligne de transmission - Détails ouverture ou fermeture de la voie d'émission; Commande de la transmission dans une direction ou l'autre utilisant une reproduction du signal transmis décalée dans le temps, p.ex. par dispositif d'annulation
H04L 7/04 - Commande de vitesse ou de phase au moyen de signaux de synchronisation
An integrated circuit device includes functional circuitry, and serializer/deserializer circuitry for serial communication with the functional circuitry. The serializer/deserializer circuitry includes phase interpolator circuitry for interpolating phases of a clock signal of the integrated circuit device. The phase interpolator circuitry includes a phase shift register having storage locations configured to represent the phases of the clock signal, and phase rotation control circuitry configured to decode a phase code signal to determine a shifting direction for phase selections in storage locations of the phase shift register. The phase rotation control circuitry may be configured to determine the shifting direction based on only the most significant bit and the second most significant bit of the phase code signal. The phase interpolator circuitry may further include weight decoder circuitry configured to derive, from the phase code signal, interpolation weights to control combination of selected phases of the clock signal.
An analog front-end (AFE) device and method for a high baud-rate receiver. The device can include an input matching network coupled to a first buffer device, which is coupled to a sampler array. The input matching network can include a first T-coil configured to receive a first input and a second T-coil configured to receive a second input. The first buffer device can include one or more buffers each having a bias circuit coupled to a first class-AB source follower and a second class-AB source follower. The sampling array can include a plurality of sampler devices configured to receive a multi-phase clocking signal. Additional optimization techniques can be used, such as having a multi-tiered sampler array and having the first buffer device configured with separate buffers for odd and even sampling phases. Benefits of this AFE configuration can include increased bandwidth, sampling rate, and power efficiency.
An optical signal transceiver includes a circuit board substrate, a silicon photonics-based interposer mounted on the circuit board substrate, the silicon photonics-based interposer including at least one of a waveguide configured to transmit optical communication signals and a photo detector configured to detect optical communication signals, and a planar lightwave circuit disposed on the circuit board substrate. The planar lightwave circuit is configured to perform at least a portion of propagation of light signals in an optical communication network, and the planar lightwave circuit is aligned with a side surface of the silicon photonics-based interposer to transmit optical communication signals between the silicon photonics-based interposer and the planar lightwave circuit. The optical signal transceiver includes at least one spacer component disposed between the planar lightwave circuit and the circuit board substrate, and epoxy material in contact with the spacer component.
An assembled electro-optical switch module includes a package substrate. Four optical socket members are disposed respectively to the package substrate. Each optical socket member includes four sockets closely packed in a row. Each socket has a recessed flat region with topside land grid array (LGA) interposer connected to bottom side solder bumps and a side notch opening aligned to an edge of the package substrate at the corresponding edge region. Sixteen optical modules in four sets are co-packaged in the package substrate. Each set has four optical modules respectively seated in the four sockets of each optical socket member with top side LGA interposer. Four clamp latch members are applied to clamp each of the four sets of optical modules in respective optical socket members. A data processor device with 51.2 Tbps data interface is disposed to the package substrate and electrically coupled to each of the sixteen optical module.
A storage device controller includes drive controller circuitry configured to control writing and fetching of data from a storage medium, read data channel circuitry for interfacing between the drive controller circuitry and the storage medium, test controller circuitry configured to test the read data channel circuitry by issuing test commands simulating the writing and fetching of data from the storage medium, and selector circuitry configured to switchably couple the read data channel circuitry to the drive controller circuitry in an operating mode and to the test controller circuitry in a testing mode. The storage device controller may include a pattern generator configured to output the test commands. Processor circuitry may be configured to store test results in memory, to compute performance metrics from the stored test results, and communicate the performance metrics to a host device.
Retiring instructions out-of-order includes: receiving processor instructions comprising two or more and fewer than all processor instructions generated based on a program, where the processor instructions include a first instruction and a second instruction such that the first instruction precedes the second instruction in a program order of the program; receiving a start instruction that immediately precedes the processor instructions and indicates that the processor instructions are to be retired out-of-order; receiving a stop instruction immediately that succeeds the processor instructions and indicates a stop to out-of-order instruction retirement; and, in response to completing execution of the second instruction before completing execution of the first instruction, retiring the second instruction before retiring the first instruction.
Controlling a vehicle comprises: providing, from an activation port, an activation signal for activating control of at least one of one or more electronically controllable devices during a high-speed activation time interval; and managing power consumed by an integrated circuit that includes two or more processor cores during the high-speed activation time interval. The managing includes: receiving the activation signal from the activation port, in response to the activation signal, executing at least a portion of stored code by a first subset of fewer than all of the processor cores at a first power level, and after the high-speed activation time interval, executing at least a portion of the stored code by a second subset of one or more of the processor cores at a second power level lower than the first power level.
B60R 16/03 - Circuits électriques ou circuits de fluides spécialement adaptés aux véhicules et non prévus ailleurs; Agencement des éléments des circuits électriques ou des circuits de fluides spécialement adapté aux véhicules et non prévu ailleurs électriques pour l'alimentation des sous-systèmes du véhicule en énergie électrique
G06F 1/324 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par réduction de la fréquence d’horloge
G06F 1/3293 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par transfert vers un processeur plus économe en énergie, p.ex. vers un sous-processeur
79.
System and methods for hardware-based PCIe link up based on post silicon characterization
A new approach is proposed to support hardware-based PCIe link up based on post silicon characterization of an electronic device. A non-volatile storage medium of a bootup unit on the electronic device maintains an initialization sequence for the physical layer of a PCIe link, and a non-volatile storage medium allows flexible programming. During operation, the bootup unit reads from the non-volatile storage medium instructions to program/override one or more PCIe physical layer settings and controller registers for the PCIe link based on the post silicon characterization of the electronic device. The bootup unit is limited to access and override only to the one or more physical layer settings and controller registers of the PCIe link. The entire process of reading the initialization sequence and programming the one or more PCIe physical layer settings and the controller registers happens within time limit constraints of the PCIe specification for latency reduction.
A method of packaging the silicon photonics wafer for fabricating custom optical-electrical modules includes fabricating a wafer with multiple dies of silicon photonics circuits based on custom design and conducting electrical and optical tests of the silicon photonics circuits in wafer level. The method further includes preparing the wafer for next point of use. Additionally, the method includes performing post-wafer processing on the wafer received at the next point of use. The method further includes conducting post-process electrical tests of the silicon photonics circuits in wafer level. Furthermore, the method includes preparing the wafer with known-good-dies or a known-good-wafer identified for custom use. Moreover, the method includes performing custom process on the know good dies.
H01L 31/02 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails - Détails
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
G02B 6/13 - Circuits optiques intégrés caractérisés par le procédé de fabrication
G01M 11/00 - Test des appareils optiques; Test des structures ou des ouvrages par des méthodes optiques, non prévu ailleurs
H01L 31/0232 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails - Détails Éléments ou dispositions optiques associés au dispositif
H01L 31/18 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives
A network device includes a memory, a memory access circuit, and a processor. The memory is configured to store a hash table for accessing a database of network addresses, the hash table including multiple buckets, each bucket dimensioned to store entries for up to a maximal permitted number of the network addresses. The memory access circuit is configured to receive a network address, to calculate a hash value over at least the network address by applying a hashing scheme selected from among a plurality of hashing schemes, to choose a bucket of the hash table based on the hash value, and to access information in the database pertaining to the network address by accessing the selected bucket. The processor is configured to select the hashing scheme to ensure that none of the buckets will be mapped to more than the maximal permitted number of the network addresses.
G06F 12/1018 - Traduction d'adresses avec tables de pages, p.ex. structures de table de page impliquant des techniques de hachage, p.ex. tables de page inversée
G06F 12/0864 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant des moyens pseudo-associatifs, p.ex. associatifs d’ensemble ou de hachage
H04L 61/5046 - Résolution des conflits d'allocation d'adresses; Test des adresses
H04L 9/06 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p.ex. système DES
A network interface device operates in a normal transmit operating mode in which the network interface device continually receives transmission symbols from a link partner via the communication link. The network interface device determines that receive circuitry of the network interface device is to transition to a low power mode in response to receiving a sleep signal from the link partner. The network interface device then operates according to a quiet/refresh cycle of the low power mode to conserve power. The quiet/refresh cycle corresponds to a time schedule that includes a refresh time window in which receive circuitry of the network interface device is to be powered to receive a refresh signal from the link partner. Immediately after transmission of the sleep signal, the network interface device transitions to a quiet time window of the time schedule in which the network interface device ignores transmissions from the link partner.
Some embodiments of the present disclosure provide an associatively indexed circular buffer (ACB). The ACB may be viewed as a dynamically allocatable memory structure that offers in-order data access (say, first-in-first-out, or “FIFO”) or random order data access at a fixed, relatively low latency. The ACB includes a data store of non-contiguous storage. To manage the pushing of data to, and popping data from, the data store, the ACB includes a contiguous pointer generator, a content addressable memory (CAM) and a free pool.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
G06F 5/10 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour modifier la vitesse de débit des données, c. à d. régularisation de la vitesse ayant une séquence d'emplacements d'emmagasinage, chacun étant individuellement accessible à la fois pour des opérations de mise en file d'attente et pour des opérations de retrait de file d'attente, p.ex. utilisant une mémoire à accès aléatoire
G06F 12/02 - Adressage ou affectation; Réadressage
84.
System and method for hardware-based register protection mechanism
A new approach is proposed to support hardware-based protection for registers of an electronic device. Sources requesting access to the registers are categorized into a set of internal sources that can be trusted and a set of external sources that are untrusted. The registers are classified into a set of internal registers allowed to be accessed by the internal resources only, a set of read-only external registers that can be read by the external resources in addition to accessed by the internal resources, and a set of read/write external registers that can be read and written by both the internal and the external resources. Each access request by a source to the registers includes the source type, wherein access request is granted or denied based on the matching between the source bits in the access request and the register classification bits of the one or more registers to be accessed.
Link data is stored in a distributed link descriptor memory (“DLDM”) including memory instances storing protocol data unit (“PDU”) link descriptors (“PLDs”) or cell link descriptors (“CLDs”). Responsive to receiving a request for buffering a current transfer data unit (“TDU”) in a current PDU, a current PLD is accessed in a first memory instance in the DLDM. It is determined whether any data field designated to store address information in connection with a TDU is currently unoccupied within the current PLD. If no data field designated to store address information in connection with a TDU is currently unoccupied within the current PLD, a current CLD is accessed in a second memory instance in the plurality of memory instances of the same DLDM. Current address information in connection with the current TDU is stored in an address data field within the current CLD.
A communication device performs a first backoff operation to determine when the communication device can begin a first simultaneous transmission via multiple channel segments. The first backoff operation includes counting down a first backoff timer in connection with a first channel segment. In response to the first backoff timer expiring, the communication device performs the first simultaneous transmission via the multiple channel segments. After performing the first simultaneous transmission via the multiple channel segments, the communication device performs a second backoff operation to determine when the communication device can begin a second simultaneous transmission via the multiple channel segments. The second backoff operation includes counting down a second backoff timer in connection with a second channel segment. In response to the second backoff timer expiring, the communication device performs the second simultaneous transmission via the multiple channel segments.
A first client station receives a multi-user physical layer (PHY) data unit from an access point. The multi-user PHY data unit includes i) a PHY preamble, and ii) a multi-user multiple input, multiple output (MU-MIMO) transmission. The PHY preamble includes a subfield that indicates respective numbers of spatial streams allocated to respective client stations among a plurality of client station that includes the first client station. The subfield has been encoded according to an encoding that supports allocating up to sixteen spatial streams to up to eight intended receivers, and the subfield consists of six or fewer bits. The first client station decodes the subfield to determine a number of spatial streams allocated to the first client station and processes the determined number of spatial streams in the MU-MIMO transmission.
Methods and apparatus for successive interference cancellation (SIC). In an embodiment, a method includes receiving symbols from a plurality of user equipment (UE), identify a target UE and non-target UEs, decoding code blocks from the symbols received from the non-target UEs to generate decoded bits for each code block. The method also includes performing a CRC check on each code block to generate a tag (0) when the CRC check passes and a tag (1) when the CRC check fails, and re-encoding the decoded bits to generate re-encoded code blocks having the associated tags attached. The method also includes reconstructing symbols from the re-encoded code blocks where symbols reconstructed from re-encoded code blocks having tag (0) are reconstructed with data and symbols reconstructed from re-encoded code blocks having tag (1) are reconstructed as zero value symbols, and utilizing the reconstructed symbols to cancel interference on symbols from the target UE.
Described herein are systems and methods for prime and probe attack mitigation. For example, some methods include, responsive to a cache miss caused by a process, checking whether a priority level of the process satisfies a first priority requirement of a first cache block of a cache with multiple ways including cache blocks associated with respective priority requirements; responsive to the priority level satisfying the first priority requirement, loading the first cache block; and, responsive to the priority level satisfying the first priority requirement, updating the first priority requirement to be equal to the priority level of the process.
A communication device generates a legacy portion of a physical layer (PHY) preamble of a PHY data unit. The legacy portion includes a plurality of legacy training fields and a legacy signal field that indicates a duration of the PHY data unit. The communication device generates a non-legacy portion of the PHY preamble to include a multi-bit signal field header to indicate at least one of i) a particular wireless communication protocol from among the multiple wireless communication protocols, and ii) a particular version of the particular wireless communication protocol. The communication device generates the non-legacy portion of the PHY preamble to also include a non-legacy signal field having a field format that conforms to the at least one of the i) particular wireless communication protocol and ii) the particular version of the particular wireless communication protocol.
A first communication device selects respective sets of medium access control (MAC) layer data units for transmission via respective channel segments of a communication channel, where the first channel segment and the second channel segment are non-overlapping frequency segments of the communication channel. The first communication device generates respective aggregate MAC layer data units to include the respective sets of MAC layer data units, generates respective physical (PHY) layer data units to include the respective aggregate MAC layer data units, and transmits the respective PHY layer data units in the respective channel segments to one or more second communication devices, where transmissions of the respective aggregate MAC layer data units in the respective channel segment overlap in time.
H04W 80/02 - Protocoles de couche liaison de données
H04W 74/08 - Accès non planifié, p.ex. accès aléatoire, ALOHA ou accès multiple par détection de porteuse [CSMA Carrier Sense Multiple Access]
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
H04L 1/1607 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue en utilisant un canal de retour dans lesquelles le canal de retour transporte des signaux de contrôle, p.ex. répétition de signaux de demande - Détails du signal de contrôle
H04W 84/12 - Réseaux locaux sans fil [WLAN Wireless Local Area Network]
An optical modulator includes a photonic substrate a first modulator arm disposed on the photonic substrate. The first modulator arm is configured to modulate a first optical signal portion of an input optical signal at a first signal level. The optical modulator further includes a second modulator arm disposed on the photonic substrate. The second modulator arm is configured to modulate a second optical signal portion of the input optical signal at a second signal level that is different from the first signal level. The optical modulator further includes an optical combiner configured combine the first optical signal portion at the first signal level and the second optical signal portion at the second signal level to impart a target chirp onto the recombined optical signal. The target chirp is based on a signal level difference between the first signal level and the second signal level.
G02B 6/12 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES - Détails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p.ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/122 - Elements optiques de base, p.ex. voies de guidage de la lumière
G02B 6/293 - Moyens de couplage optique ayant des bus de données, c. à d. plusieurs guides d'ondes interconnectés et assurant un système bidirectionnel par nature en mélangeant et divisant les signaux avec des moyens de sélection de la longueur d'onde
93.
IMPROVING INTEROPERABILITY OF COMMUNICATION DEVICES
In a communication network operating according to a communication protocol that defines a link establishment procedure having i) a negotiating procedure and ii) a training procedure, a first communication device performs the link establishment procedure with a second communication device. During the negotiating procedure, the first communication device negotiates one or more new parameter values for the link establishment procedure that are different than one or more mandated parameter values specified by the communication protocol. During the link establishment procedure, the first communication device uses the one or more new parameter values instead of using the one or more mandated parameter values specified by the communication protocol.
H04L 12/413 - Réseaux à ligne bus avec commande décentralisée avec accès aléatoire, p.ex. accès multiple avec détection de porteuse et détection de collision (CSMA-CD)
H04L 5/14 - Fonctionnement à double voie utilisant le même type de signal, c. à d. duplex
H04L 49/00 - TRANSMISSION D'INFORMATION NUMÉRIQUE, p.ex. COMMUNICATION TÉLÉGRAPHIQUE Éléments de commutation de paquets
The present invention is directed to electrical circuits. More specifically, an embodiment of the present invention provides a variable impedance module with a first capacitor coupled to a first input terminal and the second capacitor coupled to a second input terminal. A diode bridge is connected between the input capacitors. The anodes of the top diodes are connected to a supply through a resistor, and the cathodes of the lower diodes are connected to a high-impedance current source. A third capacitor is connected between these two nodes.
In a communication network operating according to a communication protocol that defines a link establishment procedure having i) a negotiating procedure and ii) a training procedure, a first communication device performs the link establishment procedure with a second communication device. During the negotiating procedure, the first communication device negotiates one or more new parameter values for the link establishment procedure that are different than one or more mandated parameter values specified by the communication protocol. During the link establishment procedure, the first communication device uses the one or more new parameter values instead of using the one or more mandated parameter values specified by the communication protocol.
A wireless communication device generates physical layer (PHY) protocol service data units (PSDUs), and, in response to determining that the PHY data unit is to be transmitted according to a HARQ process, generates HARQ coding units of a common length, each of the HARQ coding units including a respective set of one or more PSDUs, and individually encodes the HARQ coding units. The wireless communication device also generates a HARQ signal field to the included in a PHY preamble of the PHY data unit. The HARQ signal field includes i) a common information subfield to indicate one or more parameters that commonly apply to each of at least some of the one or more HARQ coding units and ii) a respective HARQ coding unit information subfield for each of the HARQ coding units to indicate one or more parameters that apply to only the corresponding HARQ coding unit.
A network interface device operates in a normal transmit operating mode in which the network interface device continually receives transmission symbols from a link partner via the communication link. The network interface device determines that receive circuitry of the network interface device is to transition to a low power mode in response to receiving a sleep signal from the link partner. The network interface device then operates according to a quiet/refresh cycle of the low power mode to conserve power. The quiet/refresh cycle corresponds to a time schedule that includes a refresh time window in which receive circuitry of the network interface device is to be powered to receive a refresh signal from the link partner Immediately after transmission of the sleep signal, the network interface device transitions to a quiet time window of the time schedule in which the network interface device ignores transmissions from the link partner.
An access point manages a first wireless local area network (WLAN) in a 6 GHz radio frequency (RF) band and ii) a second WLAN operating in another RF band. The access point generates a physical layer (PHY) data unit to include a management frame having i) first information indicating first network parameters of the first WLAN, and ii) second information indicating second network parameters of the second WLAN. The AP transmits the PHY data unit in the other RF band to provide, to any client stations that are operating in the other RF band and that are also capable of operating in the 6 GHz band: the first information indicating the first network parameters of the first WLAN operating in the 6 GHz RF band to assist the any client stations that are operating in the other RF band with joining the first WLAN operating in the 6 GHz RF band.
An optical module includes a plurality of lasers, each of at least some of the lasers configured to be selectively turned on and turned off depending on a type of modulation to be used. Each laser corresponds to a respective wavelength. The optical module also includes an optical modulation system having a plurality of optical modulators. A reconfigurable optical network of the optical module is configured to selectively direct light from the plurality of lasers to the optical modulation system differently depending on the type of modulation to be used.
H04B 10/50 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs
H04B 10/516 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs - Détails du codage ou de la modulation
H04B 10/40 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs-récepteurs
100.
RECONFIGURABLE OPTICAL TRANSCEIVER FOR USE WITH MULTIPLE MODULATION TECHNIQUES
An optical module includes a plurality of lasers, each of at least some of the lasers configured to be selectively turned on and turned off depending on a type of modulation to be used. Each laser corresponds to a respective wavelength. The optical module also includes an optical modulation system having a plurality of optical modulators. A reconfigurable optical network of the optical module is configured to selectively direct light from the plurality of lasers to the optical modulation system differently depending on the type of modulation to be used.
H04B 10/516 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs - Détails du codage ou de la modulation
H04B 10/50 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs
