A communication apparatus includes a receiver disposed in proximity to a transmitter, and a crosstalk cancellation circuit. The receiver includes an input buffer, a front end, and an adaptive resampling circuit. The input buffer receives from the transmitter aggressor data, the aggressor data being timed by a transmitter clock clocking the transmitter. The front end receives data over a communication link, the data being serialized according to a receiver clock clocking the receiver, the receiver clock operating independently of the transmitter clock. The front end further generates a stream of data samples corresponding to the received data. The adaptive resampling circuit resamples the aggressor data, and generates resampled data timed by the receiver clock. The crosstalk cancellation circuit estimates, based on the resampled data, a crosstalk error signal related to the aggressor data, and subtracts the estimated crosstalk error signal from the stream of data samples.
A physical layer transceiver assembly includes physical layer transceiver circuitry having an input/output terminal configured for coupling to data channel medium, and an electrostatic discharge protection circuit coupled between the terminal and a ground of the assembly. The electrostatic discharge protection circuit includes a reactive filter network coupled to the terminal and configured to selectively limit current flow through the electrostatic discharge protection circuit, and an electrostatic discharge protection device coupled between the reactive filter network and the ground of the assembly. Where the electrostatic discharge protection device is a snapback device, the reactive filter network is configured to limit current at frequencies that adversely affect the snapback device. One implementation of the reactive filter network is a band-stop filter that limits current in a frequency band including the frequencies that adversely affect the snapback device, and passes current at frequencies above and below the frequency band.
H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
H04B 1/3827 - TRANSMISSION - Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission Émetteurs-récepteurs, c. à d. dispositifs dans lesquels l'émetteur et le récepteur forment un ensemble structural et dans lesquels au moins une partie est utilisée pour des fonctions d'émission et de réception Émetteurs-récepteurs portatifs
H04B 1/3888 - Dispositions pour le transport ou la protection d’émetteurs-récepteurs
3.
MULTI-CHIP MODULE INCLUDING INTEGRATED CIRCUIT WITH RECEIVER CIRCUITRY IMPLEMENTING TRANSMIT SIGNAL CANCELLATION
A multi-chip module (MCM includes a substrate and first and second integrated circuit chips disposed on the substrate. The second IC chip includes transceiver circuitry configured to communicate with the first IC chip. The transceiver circuitry includes transmit circuitry having an inverter circuit to generate a first signal for transmission to the first IC chip along a signaling link. The signaling link includes a line termination impedance. Receiver circuitry includes a receiver circuit to receive a second signal from the first IC chip along the signaling link concurrently with transmission of the first signal along the signaling link. Hybrid circuitry is coupled to the transmit circuitry and to the receiver circuitry. The hybrid circuitry is configured to cancel a received component of the first signal. The hybrid circuitry includes a replica termination impedance that is configured in an open state.
A new approach is proposed to support device under test (DUT) validation reuse across a plurality of platforms, e.g., hardware simulation, hardware emulation, and post-silicon validation. First, an inference profile used for an inference operation of an application, e.g., a machine learning (ML) application, is generated based on a set of profile configurations, a set of test parameters, and a set of randomized constraints. A plurality of math functions specified by, e.g., an architecture team, for the ML application are also statically and/or dynamically verified via block simulation and/or formal verification. An inference model for the DUT is then built based on the inference profile and the plurality of verified math functions. Finally, an inference database including one or more of stimulus, DUT configurations, input data and predicted output results is generated based on the inference model, wherein the inference database for the DUT is reusable across the plurality of platforms.
A method and structure for probabilistic shaping and compensation techniques in coherent optical receivers. According to an example, the present invention provides a method and structure for an implementation of distribution matcher encoders and decoders for probabilistic shaping applications. The techniques involved avoid the traditional implementations based on arithmetic coding, which requires intensive multiplication functions. Furthermore, these probabilistic shaping techniques can be used in combination with LDPC codes through reverse concatenation techniques.
H04B 10/00 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques
H04B 10/40 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs-récepteurs
A communication device determines that a communication channel to be used for a multi-user (MU) transmission spans a frequency bandwidth greater than 160 MHz. The communication device allocates one or more frequency resource units (RUs) for the MU transmission, including: in response to determining that the communication channel spans the frequency bandwidth greater than 160 MHz, selecting one or more frequency RUs from a second set of frequency RUs. The second set of frequency RUs omits at least some RUs of a smallest bandwidth that are included in a first set of RUs that is used for allocating frequency RUs for communication channels having bandwidths of at most 160 MHz. The communication device generates allocation information that indicates the allocation of the one or more frequency RUs for the MU transmission, and transmits the allocation information to one or more other communication devices in connection with the MU transmission.
H04L 12/28 - Réseaux de données à commutation caractérisés par la configuration des liaisons, p.ex. réseaux locaux [LAN Local Area Networks] ou réseaux étendus [WAN Wide Area Networks]
H04W 72/0453 - Ressources du domaine fréquentiel, p.ex. porteuses dans des AMDF [FDMA]
A first component of a network device determines that the first component is to provide packet data to a second component of the network device for processing by the second component. In connection with determining that the first component is to provide packet data to the second component of the network device, the first component prompts the second component to activate a clock network of the second component. In connection with prompting the second component to activate the clock network, the first component sends the packet data to the second component to be processed by the second component. The first component determines when the second component has completed processing of the packet data, and prompts the second component to deactivate the clock network in response to determining that the second component has completed processing of the packet data.
Clock data recovery circuitry, for a deserializer of a data transceiver, includes a clock recovery loop with a first feed-forward equalizer having a smaller number of taps and operating on received signals to recover a clock signal, and a data recovery loop including a second feed-forward equalizer having a larger number of taps, operating on received signals to recover a data signal. Output of the second feed-forward equalizer is coupled to output of the first feed-forward equalizer to improve recovery of the clock signal. The clock recovery loop may include adaptation circuitry configured to operate on output of the first feed-forward equalizer to counteract effects, on the clock signal, of adaptation of the second feed-forward equalizer by signals output by a decision feedback equalizer in the data recovery loop.
In a vehicular communication network, a communication device generates a physical layer (PHY) preamble of a PHY protocol data unit (PPDU) for transmission in the vehicular communication network. The communication device generates a plurality of PHY data segments of the PPDU, and one or more PHY midambles, each PHY midamble to be transmitted between a respective pair of adjacent PHY data segments, and each PHY midamble including one or more training signal fields. Generating the one or more PHY midambles includes, when the PPDU is to be transmitted according to an extended range (ER) mode, generating each training signal field to include i) a first portion based on a very high throughput long training field (VHT-LTF) defined by the IEEE 802.11ac Standard and ii) a second portion based on the VHT-LTF defined by the IEEE 802.11ac Standard; and transmitting, by the communication device, the PPDU in the vehicular communication network.
H04W 4/40 - Services spécialement adaptés à des environnements, à des situations ou à des fins spécifiques pour les véhicules, p.ex. communication véhicule-piétons
H04L 27/26 - Systèmes utilisant des codes à fréquences multiples
H04W 80/02 - Protocoles de couche liaison de données
H04W 84/12 - Réseaux locaux sans fil [WLAN Wireless Local Area Network]
10.
Methods and apparatus for combining received uplink transmissions
Methods and apparatus for combining received uplink transmissions. In an embodiment, a method is provided that includes receiving a descrambled resource element associated with selected second channel state information (CSI2) and receiving a descrambling sequence used to generate the descrambled RE. The method also includes rescrambling the descrambled RE using the descrambling sequence to generate a rescrambled RE and modifying the descrambling sequence to generate a modified descrambling sequence. The method also includes descrambling the rescrambled RE with the modified descrambling sequence to generate a modified descrambled RE and accumulating the modified descrambled RE to form a combined CSI2 value.
A coordinator communication device operates in a communication network according to a communication protocol that defines repeating time cycles and specifies that each of multiple communication devices is provided a respective transmit opportunity in each time cycle. The coordinator communication device determines a number of follower communication devices in a communication network while the follower communication devices are selecting transmit opportunities using respective initial device identifiers. The coordinator communication device determines a quantity of transmit opportunities to be provided in each of multiple time cycles during which the follower communication devices are selecting transmit opportunities using respective new device identifiers. The coordinator communication device determines the quantity of transmit opportunities at least by using the number of follower communication devices. While the follower communication devices are selecting transmit opportunities using the respective new device identifiers, the coordinator communication device provides the quantity of transmit opportunity periods in each time cycle.
A coordinator communication device operates in a communication network according to a communication protocol that defines repeating time cycles and specifies that each of multiple communication devices is provided a respective transmit opportunity in each time cycle. The coordinator communication device determines a number of follower communication devices in a communication network while the follower communication devices are selecting transmit opportunities using respective initial device identifiers. The coordinator communication device determines a quantity of transmit opportunities to be provided in each of multiple time cycles during which the follower communication devices are selecting transmit opportunities using respective new device identifiers. The coordinator communication device determines the quantity of transmit opportunities at least by using the number of follower communication devices. While the follower communication devices are selecting transmit opportunities using the respective new device identifiers, the coordinator communication device provides the quantity of transmit opportunity periods in each time cycle.
A pre-scaled accumulated byte count of a port of a network node over a sampling period is scaled with a scaling factor to generate a scaled accumulated byte count. The pre-scaled accumulated byte count represents a total number of bytes in packets transferred by the port. The scaling factor represents a first port-specific attribute of the port and scales a port-specific maximum throughput of the port to a specific maximum port throughput of the network node. An iterative vector encoding method is applied to the scaled accumulated byte count to generate an encoded bit vector comprising bits respectively ordered bit positions. Each set bit of the encoded bit vector represents a respective weighted value of port utilization of the port. The encoded bit vector is stored, at a map location, in an operational statistics map.
An optoelectronic device includes a gain medium configured to amplify laser radiation within a given gain band. A resonant optical cavity contains the gain medium and includes first and second reflectors disposed on first and second sides of the gain medium. A comb filter between the first and second reflectors and configured to pass a set of distinct wavelength sub-bands within the gain band, the set of distinct wavelength sub-bands defining a comb. A plurality of optical ring resonators between the first and second reflectors in series with the comb filter have tunable resonant wavelengths in proximity to different, respective wavelength sub-bands of the comb. A control circuit applies respective control voltages to the optical ring resonators so as to tune the respective resonant wavelengths relative to the respective wavelength sub-bands, thereby modulating the sub-bands in the laser radiation that is output from the device.
H01S 3/107 - Commande de l'intensité, de la fréquence, de la phase, de la polarisation ou de la direction du rayonnement, p.ex. commutation, ouverture de porte, modulation ou démodulation par commande de dispositifs placés dans la cavité utilisant des dispositifs électro-optiques, p.ex. produisant un effet Pockels ou Kerr
H01S 3/082 - Structure ou forme des résonateurs optiques ou de leurs composants comprenant trois réflecteurs ou plus définissant une pluralité de résonateurs, p.ex. pour la sélection ou la suppression de modes
An integrated circuit device includes a main integrated circuit die having functional circuitry configured to communicate over a network through one or more high-speed communications interfaces, and at least one secondary integrated circuit die including serial interface circuitry. Each integrated circuit die among the at least one secondary integrated circuit die is mounted on a first surface of the main integrated circuit die, and first metallization connections extend along one or more first through-silicon vias between the functional circuitry and the serial interface circuitry of the at least one secondary integrated circuit die. The first metallization connections may be configured to provide data from the main die to the secondary die, and the secondary die may be configured to communicate data between the integrated circuit device and a remote integrated circuit device. Second metallization connections extend between the serial interface circuitry of and terminals of the main integrated circuit die.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
16.
OPERATIONAL STATISTICS ENCODING AND MAPPING IN NETWORK NODES
A pre-scaled accumulated byte count of a port of a network node over a sampling period is scaled with a scaling factor to generate a scaled accumulated byte count. The pre-scaled accumulated byte count represents a total number of bytes in packets transferred by the port. The scaling factor represents a first port-specific attribute of the port and scales a port-specific maximum throughput of the port to a specific maximum port throughput of the network node. An iterative vector encoding method is applied to the scaled accumulated byte count to generate an encoded bit vector comprising bits respectively ordered bit positions. Each set bit of the encoded bit vector represents a respective weighted value of port utilization of the port. The encoded bit vector is stored, at a map location, in an operational statistics map.
An integrated circuit device package includes a substrate, at least two integrated circuit dies mounted to the substrate, and a thermally conductive stiffener attached to the substrate to counteract warping of the substrate. The stiffener has a first portion in a thermally conductive relationship with a surface of a first integrated circuit die to provide a first heat dissipation mode for the first integrated circuit die, and has a second portion, different from the first portion, the second portion being configured to provide a second heat dissipation mode, different from the first heat dissipation mode, for a second integrated circuit die. The stiffener may be configured to expose a surface of the second integrated circuit die through an opening in the stiffener. A heat sink may be disposed in a thermally conductive relationship with the second integrated circuit die through the opening in the stiffener.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/552 - Protection contre les radiations, p.ex. la lumière
09 - Appareils et instruments scientifiques et électriques
Produits et services
Electronic circuits; semiconductors; semiconductor chips; semiconductor computer chips; integrated circuits; computer hardware; microprocessors; micro controllers, data storage devices, components, or circuits, namely, computer hardware in the nature of memory expander controllers, compute express link, active memory expanders; computer hardware and downloadable computer software and firmware for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems; integrated circuits for controlling hard disk drives; integrated circuits for processing data read from, and written to, hard disk drives; integrated circuits for controlling solid state drives; integrated circuits for processing data read from, and written to, solid state drives; integrated circuits for controlling the storage of data on a peripheral storage device connected to a host computer; integrated circuits for connecting multiple devices to a host computer over a compute express link (CXL) compliant connection; compute express link (CXL) switches and bridges; semiconductor memory subsystems, namely, memory storage subsystems, and computer hardware and downloadable software for supporting, controlling and operating semiconductor memory subsystems; memory circuit designs, namely, integrated circuit memory and memory controller layouts recorded on computer media; downloadable computer software and firmware for managing the storage of data on a peripheral storage device; downloadable computer software and firmware for managing the storage of data on a hard disk drive; downloadable computer software and firmware for managing the storage of data on a solid state drive; flash memory controllers; nonvolatile memory accelerators; computer memories; computer memory devices; computer memories, namely, memory devices and controllers for use with computers.
A method for recovering a clock from input data, in a deserializer that couples a transmission medium to receive circuitry of a data transceiver, includes operating, in a first clock recovery loop, on equalized input data from a data recovery loop to provide a first timing error signal, operating, in a second clock recovery loop, on unequalized input data to provide a second timing error signal, combining the first and second timing error signals, and deriving a recovered clock signal from the combined first and second timing error signals using an oscillator circuit. Combining the first and second timing error signals may include operating on the first and second timing error signals in a manner that filters the first timing error signal to remove low-frequency components including adaptation errors introduced by the data recovery loop, and that filters the second timing error signal to remove high frequency components including jitter.
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p.ex. en utilisant une boucle verrouillée en phase
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
The present disclosure describes apparatuses and methods for scalable packet processing. In some aspects, match logic of a scalable packet processor extracts and compares bits from a packet header to determine if the packet matches a context. The match logic may also determine a context index value based on other bits extracted from the header. In response to the match and based on a virtual function associated with the packet, context generation logic of the packet processor obtains a base context value and a context range value from a lookup table. The context generation logic then determines a context identifier for the packet based on the context index value, base context value, and context range value through modular arithmetic. Accordingly, the packet processor can generate context identifiers for packet distribution across contexts without maintaining a table of every context, enabling efficient scaling of the packet processor with less silicon area.
An Integrated Circuit (IC) includes one or more functional circuits of a given type, a test circuit including a selected one of the functional circuits or a replica circuit of the same type as the functional circuits, and an Adaptive Voltage Scaling (AVS) circuit. The AVS circuit is configured to determine a delay of the test circuit, and to adjust a supply voltage of the functional circuits in response to the determined delay of the test circuit.
A system and corresponding method isolate work within a virtualized scheduler using tag-spaces. The system comprises a tag-space resource configured to store at least one respective assignment of at least one scheduling group to a given tag-space. The given tag-space defines a given ordering-atomicity domain that isolates, within the virtualized scheduler, (i) work belonging to the at least one scheduling group from (ii) work belonging to at least one other scheduling group, assigned, in the tag-space resource, to a respective tag-space different from the given tag-space. The system further comprises a work scheduler that schedules, for processing, work belonging to the at least one scheduling group and work belonging to the at least one other scheduling group. Such scheduling may have independent ordering and atomicity effectuated therebetween by the given ordering-atomicity domain. Such independency of ordering and atomicity improves quality-of-service of the virtualized scheduler.
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
09 - Appareils et instruments scientifiques et électriques
Produits et services
Electronic circuits; semiconductors; semiconductor chips; semiconductor computer chips; integrated circuits; computer hardware; microprocessors; micro controllers, data storage devices, components, or circuits, namely, computer hardware in the nature of memory expander controllers, compute express link, active memory expanders; computer hardware and downloadable computer software and firmware for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems; integrated circuits for controlling hard disk drives; integrated circuits for processing data read from, and written to, hard disk drives; integrated circuits for controlling solid state drives; integrated circuits for processing data read from, and written to, solid state drives; integrated circuits for controlling the storage of data on a peripheral storage device connected to a host computer; integrated circuits for connecting multiple devices to a host computer over a compute express link (CXL) compliant connection; compute express link (CXL) switches and bridges; semiconductor memory subsystems, namely, memory storage subsystems, and computer hardware and downloadable software for supporting, controlling and operating semiconductor memory subsystems; memory circuit designs, namely, integrated circuit memory and memory controller layouts recorded on computer media; downloadable computer software and firmware for managing the storage of data on a peripheral storage device; downloadable computer software and firmware for managing the storage of data on a hard disk drive; downloadable computer software and firmware for managing the storage of data on a solid state drive; flash memory controllers; nonvolatile memory accelerators; computer memories; computer memory devices; computer memories, namely, memory devices and controllers for use with computers
24.
METHOD AND APPARATUS FOR SHARING KEYS FOR ENCRYPTION AND/OR DECRYPTION
A vehicle subsystem assembly transmits an identifier of the vehicle subsystem assembly to an electronic control unit (ECU) via an Ethernet link as part of a procedure for obtaining a first key for secure communications with the ECU via the Ethernet link from a backend system. Then, the vehicle subsystem assembly receives an encrypted message from the ECU via the Ethernet link and decrypts the encrypted message using a second key stored at the vehicle subsystem assembly to generate a first decrypted message. The vehicle subsystem assembly determines whether the first decrypted message includes a second identifier that matches the first identifier, and extracts the first key from the decrypted message. In response to determining that the decrypted message includes the second identifier that matches the first identifier, the vehicle subsystem assembly uses the first key in connection with secure communications between the vehicle subsystem assembly and the ECU.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
25.
NETWORK USING ASYMMETRIC UPLINK AND DOWNLINK BAUD RATES TO REDUCE CROSSTALK
A transmitter transmits a first signal via a first cable at a first baud rate. A receiver receives a second signal via the first cable concurrently with transmitting the first signal via the first cable. The second signal is transmitted by another device at a second baud rate that is lower than both i) the first baud rate and ii) a third baud rate at which a third signal is being transmitted in a second cable that causes crosstalk in the second signal being received via the first cable. Reception of the second signal at the second baud rate that is lower than the third baud rate facilitates mitigation of the crosstalk in the second signal caused by transmission of the third signal in the second cable at the third baud rate.
H04B 3/32 - Réduction de la diaphonie, p.ex. par compensation
H04B 3/21 - Systèmes à ligne de transmission - Détails ouverture ou fermeture de la voie d'émission; Commande de la transmission dans une direction ou l'autre utilisant un ensemble de filtres passe-bandes
An optoelectronic device includes a reflective semiconductor optical amplifier (RSOA), which includes a gain medium to amplify laser radiation within a given gain band, a first reflector at a first end of the gain medium, and a waveguide coupled to convey the laser radiation into and out of a second end of the gain medium. An external laser cavity, disposed on an optical substrate, is optically coupled to the waveguide. The external laser cavity includes a second reflector, a comb filter, disposed between the second reflector and the RSOA and configured to pass a set of distinct wavelength sub-bands within the gain band, the set of distinct wavelength sub-bands defining a comb, and a bandpass filter between the second reflector and the RSOA in series with the comb filter, having a passband encompassing a subset of the wavelength sub-bands in the comb.
H01S 3/10 - Commande de l'intensité, de la fréquence, de la phase, de la polarisation ou de la direction du rayonnement, p.ex. commutation, ouverture de porte, modulation ou démodulation
H01S 5/30 - Structure ou forme de la région active; Matériaux pour la région active
H01S 5/50 - Structures amplificatrices non prévues dans les groupes
27.
METHOD AND APPARATUS FOR DETERMINING TIME OF FLIGHT
A first communication device receives an analog receive signal via a communication medium. An ADC of the first communication device converts the analog receive signal to a digital receive signal. Logic circuitry of the first communication device detects a plurality of timing signals from a second communication device based on analyzing the digital receive signal. The logic circuitry adjusts a sampling phase of the ADC in connection with at least some of the timing signals so that the ADC is using different sampling phases when different ones of the timing signals are detected. The logic circuitry determines timing information based on the detection of the plurality of timing signals when the ADC is using different sampling phases when different ones of the timing signals are detected. The first communication device determines a time of flight between the first communication device and the second communication device based on the timing information.
H04L 43/106 - Surveillance active, p.ex. battement de cœur, utilitaire Ping ou trace-route en utilisant des informations liées au temps dans des paquets, p.ex. en ajoutant des horodatages
H04L 41/12 - Découverte ou gestion des topologies de réseau
28.
Circuit and method for translation lookaside buffer (TLB) implementation
A circuit and corresponding method provide a translation lookaside buffer (TLB) implementation. The circuit comprises a plurality of TLB banks and TLB logic. The TLB logic computes a plurality of hash values of a tag included in a memory request. The TLB logic locates, based on hash values of the plurality of hash values computed, a contiguous translation entry (TE) and a non-contiguous TE in different TLB banks of the plurality of TLB banks. The TLB logic determines a result by comparing the tag with the contiguous TE located and by comparing the tag with the non-contiguous TE located. The TLB logic outputs the result determined toward servicing the memory request. The TLB logic advantageously enables the TLB implementation to support contiguous pages using standard random-access memories for the plurality of TLB banks.
G06F 12/1027 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p.ex. un répertoire de pages actives [TLB]
G06F 12/0864 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant des moyens pseudo-associatifs, p.ex. associatifs d’ensemble ou de hachage
G06F 12/1009 - Traduction d'adresses avec tables de pages, p.ex. structures de table de page
29.
Network identifiers for WLAN using multiple communication links
A communication device assigns a first basic service set (BSS) color identifier (ID) to a first communication link among multiple communication links corresponding to multiple frequency segments, and assigns a second BSS color ID to a second communication link among the multiple communication links. The communication device uses the first BSS color ID when communicating via the first communication link, and uses the second BSS color ID when communicating via the second communication link.
A transmitter includes a shift register, a lookup table, and a digital to analog converter. The shift register is configured to receive an input signal and to output delayed copies of the input signal. The lookup table is configured to store compensation values estimated based on the input signal and the delayed copies of the input signal. The digital to analog converter is configured to output a transmit signal based on the input signal and the compensation values. The compensation values are designed to mitigate distortion of the transmit signal from conversion of the input signal to a digital signal.
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p.ex. réseaux de mise en forme adaptatifs
G01R 13/34 - Circuits pour représenter une seule forme d'onde par échantillonnage, p.ex. pour de très hautes fréquences
G01R 19/25 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant une méthode de mesure numérique
H03F 1/32 - Modifications des amplificateurs pour réduire la distorsion non linéaire
A method and system for flexibly assigning hardware resources to physical and virtual functions in a processor system supporting hardware virtualization is disclosed. The processor system includes a resource virtualization unit which is used to flexibly assign hardware resources to physical functions and also flexibly assign local functions to virtual functions associated with one or more of the physical functions. Thereby, standard PCI software is compatible with the physical functions and any associated virtualized hardware resources that have been flexibly assigned to the virtual and local functions.
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 13/24 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant l'interruption
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation
A communication device includes a plurality of communication pipelines configured to receive respective input data streams and a multiplexer coupled to the plurality of communication pipelines. The multiplexer is configured to generate an output data stream by combining the input data streams and to insert one or more special characters into the output data stream in response to a fault with one of the communication pipelines.
H04Q 11/00 - Dispositifs de sélection pour systèmes multiplex
H04B 10/516 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs - Détails du codage ou de la modulation
H04J 14/02 - Systèmes multiplex à division de longueur d'onde
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
A system and corresponding method employ an object-oriented memory device. The object-oriented memory device includes at least one physical memory and a hardware controller. The hardware controller is coupled intra the object-oriented memory device to the at least one physical memory. The hardware controller (i) decodes an object-oriented message received from a hardware client of the object-oriented memory device and (ii) performs an action for the hardware client based on the object-oriented message received and decoded. The object-oriented message is associated with an object instantiated or to-be-instantiated in the at least one physical memory. The action is associated with the object. The object-oriented memory device alleviates the hardware client(s) from having to manage structure of respective data stored in the at least one physical memory, obviating duplication of code among the hardware clients for managing same and efforts for design and verification thereof.
G06F 9/50 - Allocation de ressources, p.ex. de l'unité centrale de traitement [UCT]
G06F 5/06 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour modifier la vitesse de débit des données, c. à d. régularisation de la vitesse
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G06F 12/02 - Adressage ou affectation; Réadressage
G06F 12/0893 - Mémoires cache caractérisées par leur organisation ou leur structure
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
A method of scan-chain testing of an integrated circuit device having a plurality of respective scan-chain paths, at least some of the respective scan-chain paths being designated as having resource constraints, includes propagating a respective scan-chain data pattern through each of the respective scan-chain paths, and gating each respective scan-chain path designated as having resource constraints, to reduce a rate of scan-chain data propagation through the respective scan-chain path, without gating any scan-chain path not designated as having resource constraints. Scan-chain paths may be designated as having resource constraints because of high power consumption or data congestion.
A controller of a solid state drive (SSD) device, in response to determining that the SSD device is to transition to a power saving mode: transfers information from at least some of a volatile memory of an SSD device controller of the SSD device to a host memory of a host computer via a communication interface; and transitions the at least some of the volatile memory to an OFF state to reduce power consumption of the SSD device. In response to determining that the SSD device is to transition from the power saving mode to a normal operating mode, the controller also: transitions the at least some of the volatile memory to an ON state in which the at least some of the volatile memory is configured to retain data; and transfers the information from the host memory to the volatile memory of the SSD device controller via the communication interface.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G06F 12/0804 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec mise à jour de la mémoire principale
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
A hardware client and corresponding method employ an object-oriented memory device. The hardware client generates an object-oriented message associated with an object of an object class. The object class includes at least one data member and at least one method. The hardware client transmits the object-oriented message generated to the object-oriented memory device via a hardware communications interface. The hardware communications interface couples the hardware client to the object-oriented memory device. The object is instantiated or to-be instantiated in at least one physical memory of the object-oriented memory device according to the object class. The at least one method enables the object-oriented memory device to access the at least one data member for the hardware client.
G06F 9/50 - Allocation de ressources, p.ex. de l'unité centrale de traitement [UCT]
G06F 5/06 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour modifier la vitesse de débit des données, c. à d. régularisation de la vitesse
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G06F 12/02 - Adressage ou affectation; Réadressage
G06F 12/0893 - Mémoires cache caractérisées par leur organisation ou leur structure
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
37.
PADDING AND BACKOFF OPERATIONS WHEN TRANSMITTING VIA MULTIPLE FREQUENCY SEGMENTS IN A WLAN
A communication device performs a first backoff operation with a first backoff counter to determine when to transmit a first packet in a first frequency, and performs a second backoff operation with a second backoff counter to determine when to transmit a second packet in a second frequency segment. In connection with the first backoff counter expiring, the communication device transmits the first packet in the first frequency segment. In connection with the second backoff counter expiring, the communication device transmits the second packet in the second frequency segment simultaneously with transmitting the first packet in the first frequency segment. In response to determining that transmission of the first packet in the first frequency segment failed, the communication device increases a first contention window for a retransmission of the first packet, and does not adjust the second contention window for a next transmission in the second frequency segment.
An access point (AP) device that serves a wireless local area network (WLAN) determines that a coverage area of the AP device is partitioned into a plurality of sectors, the coverage area corresponding to the WLAN. The AP device determines that a first transmission is occurring within a first sector among the plurality of sectors, and determines that a client station is located in a second sector among the plurality of sectors, the second sector different than the first sector. In response to determining that the first transmission is occurring within the first sector, the AP device selects the client station for a directional second transmission in a direction i) within the second sector and ii) outside of the first sector, and transmits the directional second transmission to the client station in the second sector while the first transmission in the first sector is occurring.
H04W 72/542 - Critères d’affectation ou de planification des ressources sans fil sur la base de critères de qualité en utilisant la qualité mesurée ou perçue
H04W 72/541 - Critères d’affectation ou de planification des ressources sans fil sur la base de critères de qualité en utilisant le niveau d’interférence
H04W 84/12 - Réseaux locaux sans fil [WLAN Wireless Local Area Network]
39.
Methods and network device for uncoded bit protection in 10GBASE-T Ethernet
A network interface device decodes a first set of encoded bits in a fixed-length frame according to a first error correction encoding scheme to generate a first set of bits among decoded bits. The network interface device decodes a second set of encoded bits in the fixed-length frame according to a second error correction encoding scheme to generate a second set of bits among the decoded bits. The network interface device generates a first set of bit blocks and a second set of bit blocks from the decoded bits at least by de-aggregating the decoded bits. A decoder of the network interface device decodes the first set of bit blocks and the second set of bit blocks to generate a plurality of uncoded bits.
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
H04L 27/26 - Systèmes utilisant des codes à fréquences multiples
H04L 69/22 - Analyse syntaxique ou évaluation d’en-têtes
H04W 84/12 - Réseaux locaux sans fil [WLAN Wireless Local Area Network]
40.
Methods and apparatus for combining received uplink transmissions
Methods and apparatus for combining received uplink transmissions. In an embodiment, a method is provided that includes receiving a descrambled resource element associated with selected second channel state information (CSI2) and receiving a descrambling sequence used to generate the descrambled RE. The method also includes rescrambling the descrambled RE using the descrambling sequence to generate a rescrambled RE and modifying the descrambling sequence to generate a modified descrambling sequence. The method also includes descrambling the rescrambled RE with the modified descrambling sequence to generate a modified descrambled RE and accumulating the modified descrambled RE to form a combined CSI2 value.
The present invention is directed to data communication systems and techniques thereof. In a specific embodiment, the present invention provides a network connector that includes an interface for connecting to a host. The interface includes a circuit for utilizing two data paths for the host. The circuit is configured to transform the host address to different addresses based on the data path being used. There are other embodiments as well.
A communication device generates a first packet and a second packet. The first packet includes a first physical layer (PHY) preamble having: a first legacy signal field (L-SIG) having first duration information that indicates a first duration of the first packet; and first non-legacy signal field information having first modulation information that indicates a first modulation used in the first packet. The second packet includes a second PHY preamble having: a second L-SIG having second duration information that indicates a second duration of the second packet, wherein the second duration is different than the first duration; and second non-legacy signal field information having second modulation information that indicates a second modulation used in the second packet, wherein the second modulation is different than the first modulation. The communication device simultaneously transmits the first packet in a first frequency segment and the second packet in a second frequency segment.
A system and corresponding method queue work within a virtualized scheduler based on in-unit accounting (IUA) of in-unit entries (IUEs). The system comprises an IUA resource and arbiter. The IUA resource stores, in association with an IUA identifier, an IUA count and threshold. The IUA count represents a global count of work-queue entries (WQEs) that are associated with the IUA identifier and occupy respective IUEs of an IUE resource. The IUA threshold limits the global count. The arbiter retrieves the IUA count and threshold from the IUA resource based on the IUA identifier and controls, as a function of the IUA count and threshold, whether a given WQE from a given scheduling group, assigned to the IUA identifier, is moved into the IUE resource to be queued for scheduling. The IUA count and threshold prevent group(s) assigned to the IUA identifier from using more than an allocated amount of IUEs.
A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.
H03L 7/16 - Synthèse de fréquence indirecte, c. à d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase
H03K 5/13 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés
H03L 5/00 - Commande automatique de la tension, du courant ou de la puissance
H03L 7/099 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
45.
Method and apparatus for establishing timing to perform link training in ethernet communication based on link quality and/or channel conditions
Systems and methods are described for dynamically updating a duration of link training time for a first stage of link training implemented to set up a first characteristic of a link connection between a physical layer transceiver (PHY) and a link partner. A first stage of link training preconfigured to last for a first duration of time is initiated and a metric of link quality that measures a link connection quality is initiated. Based on the determined metric of link quality, updating the first duration of time for the first stage of link training.
H04B 3/20 - Systèmes à ligne de transmission - Détails ouverture ou fermeture de la voie d'émission; Commande de la transmission dans une direction ou l'autre
46.
Method and apparatus for performing machine learning operations in parallel on machine learning hardware
A method includes receiving a first set of data. The method also includes receiving an instruction to determine a largest value within the first set of data. The first set of data is divided into a first plurality of data portions based on a hardware architecture of a first plurality of processing elements. The first plurality of data portions is mapped to the first plurality of processing elements. Each data portion of the first plurality of data portions is mapped exclusively to a processing element of the first plurality of processing elements. Each data portion of the first plurality of data portions is processed by its respective processing element to identify a largest value from each data portion of the first plurality of data portions, wherein the processing forms a first output data comprising the largest value from the each data portion of the first plurality of data portions.
G06N 20/10 - Apprentissage automatique utilisant des méthodes à noyaux, p.ex. séparateurs à vaste marge [SVM]
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p.ex. plusieurs processeurs de données à instruction unique
G06N 5/04 - Modèles d’inférence ou de raisonnement
G06N 20/20 - Techniques d’ensemble en apprentissage automatique
An optical transmitter includes a first encoder, a first interleaver, a second encoder, a mapper, a second interleaver, and a frame generator. The first encoder is configured to encode data using a staircase code to generate first codewords. The first interleaver is configured to interleave the first codewords using convolutional interleaving to spread a transmission order of the first codewords. The second encoder is configured to encode the interleaved first codewords using a second code to generate second codewords. The mapper is configured to map the second codewords to transmit symbols. The second interleaver is configured to interleave the transmit symbols to distribute the transmit symbols between pilot symbols. The frame generator is configured to generate a transmit frame including the interleaved transmit symbols and the pilot symbols.
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H03M 13/19 - Correction d'une seule erreur sans utiliser les propriétés particulières des codes cycliques, p.ex. codes de Hamming, codes de Hamming étendus ou généralisés
H03M 13/25 - Détection d'erreurs ou correction d'erreurs transmises par codage spatial du signal, c. à d. en ajoutant une redondance dans la constellation du signal, p.ex. modulation codée en treillis [TMC]
H03M 13/29 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes combinant plusieurs codes ou structures de codes, p.ex. codes de produits, codes de produits généralisés, codes concaténés, codes interne et externe
48.
METHOD AND APPARATUS FOR COMMUNICATING INFORMATION VIA PILOT SIGNALS
A first communication device receives control data that are to be communicated to a transceiver of a second communication device, the control data for use by the transceiver to adjust one or more operating parameters of the transceiver. The first communication device encodes the control data on multiple pilot symbols so that each pilot symbol of the multiple pilot symbols encodes less than all of the multiple bits of control data. The first communication device receives information bits that are to be communicated to the second communication device via data symbols, and generates a plurality of data symbols using the information bits. The first communication device transmits the plurality of data symbols and the multiple pilot symbols to the second communication device via a communication medium. When transmitted, the multiple pilot symbols and encoded portions of the multiple bits of control data are interspersed among the plurality of data symbols.
Transceiver circuitry in an integrated circuit device includes a receive path including an analog front end for receiving analog signals from an analog transmission path and conditioning the analog signals, and an analog-to-digital converter configured to convert the conditioned analog signals into received digital signals for delivery to functional circuitry, and a transmit path including a digital front end configured to accept digital signals from the functional circuitry and to condition the accepted digital signals, and a digital-to-analog converter configured to convert the conditioned digital signals into analog signals for transmission onto the analog transmission path. At least one of the analog front end and the digital front end introduces distortion and outputs a distorted conditioned signal. The transceiver circuitry further includes distortion correction circuitry at the one of the analog front end and the digital front end, to determine and apply a distortion cancellation function to the distorted signal.
A first communication device receives control data that are to be communicated to a transceiver of a second communication device, the control data for use by the transceiver to adjust one or more operating parameters of the transceiver. The first communication device encodes the control data on multiple pilot symbols so that each pilot symbol of the multiple pilot symbols encodes less than all of the multiple bits of control data. The first communication device receives information bits that are to be communicated to the second communication device via data symbols, and generates a plurality of data symbols using the information bits. The first communication device transmits the plurality of data symbols and the multiple pilot symbols to the second communication device via a communication medium. When transmitted, the multiple pilot symbols and encoded portions of the multiple bits of control data are interspersed among the plurality of data symbols.
The present disclosure describes apparatuses and methods for implementing a reinforcement learning-enabled low-density parity check (LDPC) decoder. In aspects, an RL-enabled LDPC decoder processes, as part of a first decoding iteration, data of a channel to generate LDPC state information and provides the LDPC state information to a machine learning (ML) algorithm of an RL agent. The RL-enabled LDPC decoder is then configured with LDPC decoding parameters obtained from the ML algorithm and processes, as part of a second decoding operation, the data using the decoding parameters to generate subsequent LDPC state information. The RL-enabled LDPC decoder provides decoded data of the channel based on the subsequent LDPC state information. By using the LDPC decoding parameters provided by the ML algorithm of the RL agent, the RL-enabled LDPC decoder may decode channel data in fewer decoding iterations or with a higher success rate, thereby improving LDPC decoding performance.
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
An optical transceiver includes a silicon photonics substrate, transmitter circuitry, and receiver circuitry that are heterogeneously integrated. The transmitter circuitry includes a plurality of laser devices formed on the silicon photonics substrate, each of the plurality of laser devices configured to generate a respective laser light, a plurality of modulators formed on the silicon photonics substrate, each of the plurality of modulators configured to modulate the laser lights based on driver signals and output, from the silicon photonics substrate, the modulated laser lights, and a driver formed on the silicon photonics substrate and configured to generate the driver signals. The receiver circuitry includes a photodetector configured to receive a plurality of optical signals and convert the plurality of optical signals to respective electrical signals and a transimpedance amplifier device configured to receive the electrical signals and output the electrical signals from the silicon photonics substrate as electrical outputs.
B60G 21/05 - Systèmes d'interconnexion à plusieurs roues conjuguées suspendues élastiquement, p.ex. pour stabiliser la caisse du véhicule eu égard aux forces d'accélération, de décélération ou aux forces centrifuges conjuguées en permanence mécaniquement entre roues appartenant au même essieu, mais n'étant pas disposées du même côté du véhicule, c. à d. la suspension de la roue gauche étant reliée à celle de la roue droite
B60G 15/02 - Suspensions élastiques caractérisées par la disposition, l'emplacement ou le type de combinaison de ressorts et d'amortisseurs de vibrations, p.ex. du type télescopique ayant un ressort mécanique
An Ethernet Physical layer (PHY) device includes a PHY interface and PHY circuitry. The PHY interface is configured to connect to a physical link. The PHY circuitry is configured to generate layer-1 frames that carry data for transmission to a peer Ethernet PHY device, to insert among the layer-1 frames one or more management frames that are separate from the layer-1 frames and that are configured to control a General-Purpose Input-Output (GPIO) port associated with the peer Ethernet PHY device, to transmit the layer-1 frames and the inserted management frames, via the PHY interface, to the peer Ethernet PHY device over the physical link, for controlling one or more operations of the GPIO port associated with the peer Ethernet PHY device, and to receive, via the PHY interface, one or more verifications acknowledging that the one or more management frames were received successfully at the peer Ethernet PHY device.
H04L 12/413 - Réseaux à ligne bus avec commande décentralisée avec accès aléatoire, p.ex. accès multiple avec détection de porteuse et détection de collision (CSMA-CD)
H04L 69/323 - Protocoles de communication intra-couche entre entités paires ou définitions d'unité de données de protocole [PDU] dans la couche physique [couche OSI 1]
Passage of data packets on a data pipeline is arbitrated in a distributed manner along the pipeline. Multiple data arbiters each operate to merge data from a respective data source to the data pipeline at a distinct point in the pipeline. At each stage, a multiplexer selectively passes, to the data pipeline, an upstream data packet or a local data packet from the respective data source. A register stores an indication of data packets passed by the multiplexer based on the respective data source originating the data packet. A controller controls the multiplexer to select the upstream data packet or the local data packet based on the indication of data packets passed by the multiplexer.
A system to support validation and debugging of compiled low-level instructions for a machine learning (ML) network model on an ML-specific hardware. A compiler identifies well-defined boundaries in the ML network model based on primitives used to generate low-level instructions for the hardware. The ML network model is partitioned into units/layers/sub-graphs based on the plurality of well-defined boundaries. The compiler then generates an internal representation for each of the units wherein the internal representation is mapped to components in the hardware. Each of the units is compiled into a first set to be executed on the ML-specific hardware and a second set to be executed on a second computing device. The output results from executing the two sets of low-level instructions are compared to validate the first set of low-level instructions. If the outputs do not match fully, the first set of low-level instructions is debugged and recompiled.
A circuit and corresponding method enable mining for digital currency in a blockchain network. The circuit comprises a controller and at least one partial hash engine that (i) implements a hash function, partially, to compute a partial hash digest of a final hash digest for a block header of a block candidate and (ii) generates a notification based on determining that the partial hash digest satisfies a criterion. The controller includes a complete hash engine that implements the hash function, completely. In response to the notification generated, the controller activates the complete hash engine to compute, in its entirety, the final hash digest for the block header, effectuating a decision for submission of the block candidate with the block header to the blockchain network for mining the digital currency. Power savings and reduction in area are achieved relative to multiple hash engines that compute the entire final hash digest.
H04L 29/06 - Commande de la communication; Traitement de la communication caractérisés par un protocole
G06Q 20/06 - Circuits privés de paiement, p.ex. impliquant de la monnaie électronique utilisée uniquement entre les participants à un programme commun de paiement
G06Q 20/38 - Architectures, schémas ou protocoles de paiement - leurs détails
G06Q 20/40 - Autorisation, p.ex. identification du payeur ou du bénéficiaire, vérification des références du client ou du magasin; Examen et approbation des payeurs, p.ex. contrôle des lignes de crédit ou des listes négatives
H04L 9/06 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p.ex. système DES
H04L 9/00 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité
A first communication device generates and transmits a frame that is configured to cause one or more second communication devices in a wireless local area network (WLAN) to refrain from transmitting during a set of repeating time segments, and the frame is generated to include an indication of a time period of the time segments in the set of repeating time segments, the time period being less than a duration of a beacon interval of the WLAN such that multiple ones of the time segments occur within one beacon interval. Alternatively, the frame is configured to cause one or more second communication devices in the WLAN to refrain from transmitting during a time segment that begins in conjunction with an end of transmission of i) the frame or ii) a packet that includes the frame, and the frame is generated to include an indication of a time duration of the time segment.
A communication device selects a frequency bandwidth via which a physical layer (PHY) protocol data unit (PPDU) will be transmitted in a vehicular communication network, and generates, the PPDU i) according to a downclocking ratio of 1/2, and ii) based on an orthogonal frequency division multiplexing (OFDM) numerology defined by an IEEE 802.11ac Standard. In response to the selected frequency bandwidth being 10 MHz, the PPDU is generated according to the downclocking ratio of 1/2 and based on the OFDM numerology defined by the IEEE 802.11ac Standard for 20 MHz PPDUs. In response to the selected frequency bandwidth being 20 MHz, the PPDU is generated according to the downclocking ratio of 1/2 and based on the OFDM numerology defined by the IEEE 802.11ac Standard for 40 MHz PPDUs.
A first communication device receives an analog receive signal via a communication medium. An ADC of the first communication device converts the analog receive signal to a digital receive signal. Logic circuitry of the first communication device detects a plurality of timing signals from a second communication device based on analyzing the digital receive signal. The logic circuitry adjusts a sampling phase of the ADC in connection with at least some of the timing signals so that the ADC is using different sampling phases when different ones of the timing signals are detected. The logic circuitry determines timing information based on the detection of the plurality of timing signals when the ADC is using different sampling phases when different ones of the timing signals are detected. The first communication device determines a time of flight between the first communication device and the second communication device based on the timing information.
G01S 7/00 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , ,
G01S 13/34 - Systèmes pour mesurer la distance uniquement utilisant la transmission d'ondes continues, soit modulées en amplitude, en fréquence ou en phase, soit non modulées utilisant la transmission d'ondes continues modulées en fréquence, tout en faisant un hétérodynage du signal reçu, ou d’un signal dérivé, avec un signal généré localement, associé au signal transmis simultanément
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p.ex. en utilisant une boucle verrouillée en phase
60.
CIRCUIT FOR MULTI-PATH INTERFERENCE MITIGATION IN AN OPTICAL COMMUNICATION SYSTEM
An optical receiver includes an error generator, a multipath interference estimator, and a combiner. The error generator is configured to receive an input comprising a received optical signal, to estimate a modulation level of samples of the received optical signal, and to generate an error signal based on the estimated modulation level of the samples, the error signal representing a difference between an actual level of the received optical signal and the estimated modulation level. The multipath interference estimator is configured to generate estimates of multipath interference (MPI) associated with the samples of the received optical signal based on the error signal. The combiner is configured to generate an MPI-mitigated signal based on a combination of the samples and the estimates of MPI.
H04B 10/58 - Compensation pour sortie d’émetteur non linéaire
H04B 10/00 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques
H04B 10/2507 - Dispositions spécifiques à la transmission par fibres pour réduire ou éliminer la distorsion ou la dispersion
H04B 10/516 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs - Détails du codage ou de la modulation
Methods and apparatus for receiving a user message in a communication network are disclosed. In an exemplary embodiment, a method includes receiving data samples in an uplink transmission from user equipment, performing preamble detection on the data samples, generating a trigger signal that indicates when a preamble is detected, and decoding a user message in response to the trigger signal, wherein the user message follows the detected preamble.
A method for cancelling, from servo signals read in a read channel while a write channel is active, interference caused by write signals in the write channel, includes generating a predicted channel response signal from the write signals in a data clock domain, resampling the generated predicted channel response signal using a clock in the data clock domain having a rate corresponding to a servo clock from a servo clock domain, transferring the resampled predicted channel response signal from the data clock domain to the servo clock domain and aligning phase of the transferred resampled predicted channel response signal with phase of the servo clock, determining a domain-boundary-crossing delay incurred in the transferring, based on the domain-boundary-crossing delay, synchronizing the phase-aligned transferred resampled predicted channel response signal with the servo signals, and subtracting the synchronized phase-aligned transferred resampled predicted channel response signal from the servo signals.
G11B 5/00 - Enregistrement par magnétisation ou démagnétisation d'un support d'enregistrement; Reproduction par des moyens magnétiques; Supports d'enregistrement correspondants
G11B 5/012 - Enregistrement, reproduction ou effacement sur des disques magnétiques
G11B 20/10 - Enregistrement ou reproduction numériques
63.
REPORTING BANDWIDTH CAPABILITY OF A BANDWIDTH-LIMITED COMMUNICATION DEVICE
A first communication device generates a first physical layer (PHY) data unit that includes information indicating a capability to use a channel bandwidth greater than a maximum channel bandwidth of the first communication device, and transmits the first PHY data unit to a second communication device during an association process with the second communication device. The first communication device generates a second PHY data unit that includes information indicating a capability to use at most the maximum channel bandwidth of the first communication device, and transmits the second PHY data unit to the second communication device when the first communication device is associated with the second communication device.
H04W 72/21 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens ascendant de la liaison sans fil, c. à d. en direction du réseau
H04W 8/22 - Traitement ou transfert des données du terminal, p.ex. statut ou capacités physiques
A first communication device generates an Operation, Administration, and Maintenance (OAM) frame that includes i) OAM message content and ii) an OAM frame header outside of the OAM message content, wherein generating the OAM frame comprises generating the OAM frame header to include information that signals one of i) a low power sleep (LPS) request, and ii) a wake-up request (WUR). The first communication device transmits the OAM frame to a second communication device via a communication medium to signal to the second communication device the one of i) the LPS request, and ii) the WUR.
H04L 12/12 - Dispositions pour la connexion ou la déconnexion à distance de sous-stations ou de leur équipement
G06F 1/3296 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par diminution de la tension d’alimentation ou de la tension de fonctionnement
65.
System and method for large memory transaction (LMT) stores
A system and corresponding method perform large memory transaction (LMT) stores. The system comprises a processor associated with a data-processing width and a processor accelerator. The processor accelerator performs a LMT store of a data set to a coprocessor in response to an instruction from the processor targeting the coprocessor. The data set corresponds to the instruction. The LMT store includes storing data from the data set, atomically, to the coprocessor based on a LMT line (LMTLINE). The LMTLINE is wider than the data-processing width. The processor accelerator sends, to the processor, a response to the instruction. The response is based on completion of the LMT store of the data set in its entirety. The processor accelerator enables the processor to perform useful work in parallel with the LMT store, thereby improving processing performance of the processor.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/1045 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p.ex. un répertoire de pages actives [TLB] associée à une mémoire cache de données
66.
Structures and methods for deriving stable physical unclonable functions from semiconductor devices
A semiconductor device includes circuitry configured to derive a physical unclonable function. The circuitry includes a plurality of bitcells, each bitcell being readable as one of a ‘0’ value and a ‘1’ value, and sense amplifier circuitry configurable to read values from the plurality of bitcells. The sense amplifier circuitry includes margin circuitry configurable (i) to selectably bias reading of the plurality of bitcells toward one of ‘0’ values and ‘1’ values, (ii) to identify addresses of bitcells having a stable ‘1’ value when the margin circuitry is configured to bias reading of the plurality of bitcells toward ‘0’ values, and (iii) to identify addresses of bitcells having a stable ‘0’ value when the margin circuitry is configured to bias reading of the plurality of bitcells toward ‘1’ values. Each bitcell in the plurality of bitcells may include a differential transistor pair.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
G06F 21/44 - Authentification de programme ou de dispositif
A first communication device is configured to process packets that conform to a first physical layer (PHY) protocol for wireless vehicular communications and packets that conform to a second PHY protocol for wireless vehicular communications. The first communication device determines that one or more second communication devices neighboring the first communication device are not capable of processing packets that conform to the second PHY protocol. The first communication device transmits a first packet to a third communication device that is configured to process packets that conform to the first PHY protocol and packets that conform to the second PHY protocol. The first packet indicates that the one or more second communication devices neighboring the first communication device are not capable of processing packets that conform to the second PHY protocol to inform the third communication device of the one or more second communication devices.
H04L 69/323 - Protocoles de communication intra-couche entre entités paires ou définitions d'unité de données de protocole [PDU] dans la couche physique [couche OSI 1]
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
H04W 28/02 - Gestion du trafic, p.ex. régulation de flux ou d'encombrement
H04W 72/044 - Affectation de ressources sans fil sur la base du type de ressources affectées
68.
MEMORY ALLOCATION AND REALLOCATION FOR PROGRAM INSTRUCTIONS AND DATA USING INTERMEDIATE PROCESSOR
Memory blocks are allocated for a microcontroller having one memory subsystem storing instruction information, and a separate memory subsystem storing data information. At design time, an address map is created implementing configurations of different ways of allocating instruction information and data information between memory blocks. At runtime, a configuration signal is received, and a particular memory block configuration for storing instruction information and data information is determined. An incoming instruction signal received from a dedicated microcontroller port, is communicated according to the configuration signal and the address map to a connection point (e.g., pin, fuse, register). Via that connection point, the instruction signal is routed to a memory block designated exclusively for instructions. Similarly, based upon the configuration signal and the address map, an incoming data signal (received from another dedicated microcontroller port), is routed via a connection point to a different memory block designated to store exclusively data information.
A decoder for a receiver in a communication system includes an interface configured to receive encoded input data via a communication channel. The encoded input data includes forward error correction (FEC) codewords. A processor is configured to decode the FEC codewords using low density parity check (LDPC) codes defined by a parity check matrix. The parity check matrix is defined by both regular column partition (RCP) constraints and quasi-cyclic (QC) constraints. An output circuit is configured to output a decoded codeword based on the FEC codewords decoded by the processor.
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
70.
System and Method for Neural Network-Based Autonomous Driving
A system and corresponding method for autonomous driving of a vehicle are provided. The system comprises at least one neural network (NN) that generates at least one output for controlling the autonomous driving. The system further comprises a main data path that routes bulk sensor data to the at least one NN and a low-latency data path with reduced latency relative to the main data path. The low-latency data path routes limited sensor data to the at least one NN which, in turn, employs the limited sensor data to improve performance of the at least one NN's processing of the bulk sensor data for generating the at least one output. Improving performance of the at least one NN's processing of the bulk sensor data enables the system to, for example, identify a safety hazard sooner, enabling the autonomous driving to divert the vehicle and avoid contact with the safety hazard.
B60W 50/04 - COMMANDE CONJUGUÉE DE PLUSIEURS SOUS-ENSEMBLES D'UN VÉHICULE, DE FONCTION OU DE TYPE DIFFÉRENTS; SYSTÈMES DE COMMANDE SPÉCIALEMENT ADAPTÉS AUX VÉHICULES HYBRIDES; SYSTÈMES D'AIDE À LA CONDUITE DE VÉHICULES ROUTIERS, NON LIÉS À LA COMMANDE D'UN SOUS-ENSEMBLE PARTICULIER - Détails des systèmes d'aide à la conduite des véhicules routiers qui ne sont pas liés à la commande d'un sous-ensemble particulier pour surveiller le fonctionnement du système d'aide à la conduite
The present disclosure describes apparatuses and methods for contextual search of a storage system. In some aspects, a metadata manager of a storage system receives a query to search the data stored on the storage media of the apparatus. The metadata manager identifies an entry in a relational database of the metadata manager that includes a label that is relevant to the query and determines, based on the entry in the relational database, a reference address of a target node in a navigational database of the metadata manager that corresponds to the label. As results for the query to search, the metadata manager returns an object of the target node at the reference address in the navigational database and corresponding objects of relative nodes connected to the target node via respective links. By so doing, the metadata database may enable contextual or implicit search of data in the storage system.
Methods, PHYs, and computer-readable media are provided for reliably receiving data at a physical layer transceiver of an automobile in the presence of noise or interference. A non-equalized signal is received at a physical layer transceiver via a communication channel in a high noise or interference automotive environment. The non-equalized signal is prepared for extraction of data by performing one or more of the following: improving a signal-to-noise ratio of the non-equalized signal by using two or more parallel matching filters to correlate the non-equalized signal with two or more signal templates to detect the presence of logic low signal patterns and logic high signal patterns in the non-equalized signal; reducing jitter in the non-equalized signal by tracking a phase of the non-equalized signal using a digital timing loop; compensating for noise or interference distortion in the non-equalized signal by selecting a decision sample defined by a plurality of peaks, the selecting performed based on tracking peaks in the non-equalized signal; searching the non-equalized signal for a preamble before initiating a process of receiving payload data, to reduce false data reception caused by noise or interference; and extracting data from the prepared non-equalized signal.
H04L 25/497 - Circuits d'émission; Circuits de réception à au moins trois niveaux d'amplitude par codage corrélatif, p.ex. par codage à réponse partielle ou par codage par modulation à échos
H04L 25/49 - Circuits d'émission; Circuits de réception à au moins trois niveaux d'amplitude
An apparatus for performing cryptographic primitives includes a processor that is configured to receive an instruction to perform a cryptographic primitive, where the instruction includes one or more operands, at least one of the operands indicates one or more data structures that include values for the cryptographic primitive, and where the values include a first value indicating a mode of encryption that indicates an order of performing an encryption operation and an authentication operation and a second value indicating a cipher type; and perform the cryptographic primitive and store an output of the cryptographic primitive in an output data structure.
H04L 29/06 - Commande de la communication; Traitement de la communication caractérisés par un protocole
H04L 9/06 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p.ex. système DES
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
74.
EXPLICIT BEAMFORMING IN A HIGH EFFICIENCY WIRELESS LOCAL AREA NETWORK
A first communication device receives a sounding packet from a second communication device and develops beamforming information based on the sounding packet. The first communication device transmits beamforming feedback to the second communication device, the beamforming feedback including beamforming information for use by the second communication device to beamsteer a data packet to the first communication device, the data packet having a data portion that includes a second number of OFDM tones greater than a first number of OFDM tones in the sounding packet. After transmitting the beamforming feedback, the first communication device receives the data packet from the second communication device, the data packet including one or more data OFDM symbols, each of the one or more data OFDM symbols having the second number of OFDM tones.
H04B 7/0456 - Sélection de matrices de pré-codage ou de livres de codes, p.ex. utilisant des matrices pour pondérer des antennes
H04B 7/06 - Systèmes de diversité; Systèmes à plusieurs antennes, c. à d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
H04W 16/28 - Structures des cellules utilisant l'orientation du faisceau
In an embodiment, a method includes programming a control signal that specifies a target resistance and a target voltage in a circuit. The method further includes sending the control signal to at least one transistor configured to control a current flow in the circuit. The method further includes providing, as an output, a signal with the target voltage and target resistance.
H03K 19/00 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion
H03K 19/20 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion caractérisés par la fonction logique, p.ex. circuits ET, OU, NI, NON
76.
WIRELINE TRANSCEIVER WITH INTERNAL AND EXTERNAL CLOCK GENERATION
An integrated circuit device having functional circuitry driven by a clock signal includes onboard clock generation circuitry. The clock generation circuitry includes an input configured to accept a frequency reference signal, at least one variable loading capacitor coupled to the input for converting the crystal resonator signal into a calibrated clock signal, and calibration circuitry configured to calibrate the at least one variable loading capacitor based on a reference voltage. The input configured to accept a frequency reference signal may be configured to accept a crystal resonator signal.
A network device accesses, from a queue corresponding to a port of the device, a packet for processing. The device identifies a present operating region (ORE) of one or more OREs specified for the device, an ORE being associated with at least one of (i) one or more device attributes, or (ii) one or more environmental factors associated with an environment in which the device is operational. The device determines a number of power credits available for processing one or more packets. In response to determining that the number of power credits available is non-negative, the device completes processing of the packet. The device computes, based at least on the present ORE, a power credit reduction for the packet, which corresponds to an amount of power for processing the packet, and reduces the number of power credits available by the power credit reduction for the packet.
G06F 1/3296 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par diminution de la tension d’alimentation ou de la tension de fonctionnement
A method of reading servo wedge data from a rotating constant-density magnetic storage medium having a plurality of tracks, where each track is written at a track pattern frequency, the respective track pattern frequencies varying from a lowest frequency at an innermost one of the tracks to a highest frequency at an outermost one of the tracks, includes, for each respective track, determining, based on the pattern frequency of the respective track, a desired sampling position, sampling actual samples of servo wedge data based on a sampling clock used for all tracks, having a sampling frequency at least equal to the track pattern frequency of the outermost track, determining a phase relationship of the desired sampling position to the sampling clock, and, depending on the phase relationship between the sampling position and the sampling clock, interpolating a sample, or omitting interpolation of a sample and squelching the interpolation clock.
A method for writing repeatable run-out (RRO) data, to surfaces of a rotating magnetic storage medium in a storage device having two read channels, includes detecting, with a first head, using a first read channel, a servo sync mark (SSM) on a first track on a first surface, establishing a recurring servo-gating signal at a successive fixed interval from the SSM, detecting, with the first head, servo signals from the first track on occurrence of the recurring servo-gating signal, processing the servo signals from the first track, to generate first positioning signals for positioning the first head relative to the first track, following a similar procedure with a second read channel having a second head to generate second positioning signals for the second read head, and writing first and second RRO data to servo wedges of the first and second tracks according to the respective positioning signals.
G11B 5/596 - Disposition ou montage des têtes par rapport aux supports d'enregistrement comportant des dispositions pour déplacer la tête dans le but de maintenir l'alignement relatif de la tête et du support d'enregistrement pendant l'opération de transduction, p.ex. pour compenser les irrégularités de surface ou pour suivre les pistes pour suivre les pistes d'un disque
80.
Reduction of four-wave mixing crosstalk in optical links
A transmitter includes at least three tunable laser sources, an optical multiplexer, and a processor. The at least three tunable laser sources are configured to receive respective data streams, and to output respective Tx light beams at different respective carrier frequencies, modulated with the respective data streams. The optical multiplexer is configured to combine the multiple Tx light beams to produce a combined beam formed of the modulated Tx light beams at the different carrier frequencies, and to transmit the combined beam over an optical fiber. The processor is configured to receive a notification indicative of an interference occurring due to Four-Wave Mixing (FWM) in the optical fiber, and to modify at least one of the carrier frequencies responsively to the notification in order to mitigate the interference due to FWM.
H04B 10/50 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs
G02B 6/293 - Moyens de couplage optique ayant des bus de données, c. à d. plusieurs guides d'ondes interconnectés et assurant un système bidirectionnel par nature en mélangeant et divisant les signaux avec des moyens de sélection de la longueur d'onde
An integrated circuit includes a silicon photonics substrate having a silicon-based material, silicon photonics components formed in the silicon photonics substrate to receive and transmit optical signals, and electrical connections; a transimpedance amplifier chip arranged on the silicon photonics substrate, having a silicon-germanium material that is different than the silicon-based material, connected via the electrical connections to at least one of the silicon photonics components configured to receive an optical signal, and configured to process a received optical signal and output a processed signal to a digital signal processor; and a driver chip arranged on the silicon photonics substrate, having CMOS material that is different than the silicon-germanium material and the silicon-based material, connected via the electrical connections to drive at least one of the silicon photonics components configured to generate an optical signal for transmission.
H04B 10/40 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs-récepteurs
G02B 6/12 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES - Détails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p.ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/126 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES - Détails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p.ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré utilisant des effets de polarisation
G02B 6/42 - Couplage de guides de lumière avec des éléments opto-électroniques
H01S 3/13 - Stabilisation de paramètres de sortie de laser, p.ex. fréquence ou amplitude
A multi-chip package includes first and second groups of integrated circuit (IC) chips and a transfer IC chip disposed in the multi-chip package. The transfer IC chip is communicatively interposed between the first and second groups of IC chips and is configured to transfer signals from at least a first IC chip of the first group of IC chips to at least a second IC chip of the second group of IC chips or an output interface. The output interface is configured to output first data from the multi-chip package. A first set of ultra-short reach (USR) signaling links connects the first group of IC chips to the transfer IC chip. A second set of USR signaling links connects the second group of IC chips to the transfer IC chip. Each of the USR signaling links comprises a trace length of less than one inch.
Forming a metal gate transistor includes forming a semiconductor channel in a substrate, and depositing a source electrode and a drain electrode on the semiconductor channel. The source and drain electrodes are spaced apart. Dielectric spacers are provided above the source and drain electrodes to define a gate void spanning the source and drain electrodes. A dielectric layer is deposited on a bottom wall and sidewalls of the gate void. A work-function metal layer is deposited on the dielectric layer. The work-function metal layer is etched away from the sidewalls leaving the work-function metal layer on the bottom wall to control work function between the semiconductor channel and a conductive metal gate material to be deposited. The gate void above the work-function metal layer on the bottom wall, and between the dielectric layers on the sidewalls, is filled with the conductive metal gate material.
H01L 21/3213 - Gravure physique ou chimique des couches, p.ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/66 - Types de dispositifs semi-conducteurs
84.
Semiconductor device with mechanism to prevent reverse engineering
A semiconductor device is configured to implement a security protocol. The semiconductor device includes an entropy source that includes a plurality of bitcells. The entropy source is configured to output a sequence of physical unclonable function bit values based on intrinsic properties of the plurality of bitcells to generate a unique device secret for the security protocol, and selectively damage at least a portion of the plurality of bitcells to prevent reverse engineering the sequence of physical unclonable function bit values.
G06F 21/71 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information
G06F 21/14 - Protection des logiciels exécutables contre l’analyse de logiciel ou l'ingénierie inverse, p.ex. par masquage
A circuit and corresponding method perform resource arbitration. The circuit comprises a pending arbiter (PA) that outputs a PA selection for accessing a resource. The PA is selection based on PA input. The PA input represents respective pending-state of requesters of the resource. The circuit further comprises a valid arbiter (VA) that outputs a VA selection for accessing the resource. The VA selection is based on VA input. The VA input represents respective valid-state of the requesters. The circuit performs a validity check on the PA selection output. The circuit outputs a final selection for accessing the resource by selecting, based on the validity check performed, the PA selection output or VA selection output. The circuit addresses arbitration fairness issues that may result when multiple requesters are arbitrating to be selected for access to a shared resource and such requesters require a credit (token) to be eligible for arbitration.
A circuit detects a voltage droop exhibited by a power supply. A first signal delay line outputs a first delayed signal, and is comprised of delay elements having a first threshold voltage. A second delay line outputs a second delayed signal, and is comprised of delay elements having a second threshold voltage that is higher than the first threshold voltage. A phase detector compares the first and second delayed signals and outputs a comparison signal indicating which of the first and second signal delay lines exhibits a shorter delay. A reset circuit resets the first and second signal delay lines in response to the comparison signal, and a clock controller outputs a command to adjust a clock frequency or engage in other mitigation measures based on the comparison signal.
G01R 25/00 - Dispositions pour procéder aux mesures de l'angle de phase entre une tension et un courant ou entre des tensions ou des courants
H03K 5/14 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de lignes à retard
H03L 7/00 - Commande automatique de fréquence ou de phase; Synchronisation
87.
System and method for schedule-based I/O multiplexing for integrated circuit (IC) scan test
An approach is proposed to support schedule-based I/O multiplexing for scan testing of an IC. A plurality of I/Os are assigned to a plurality of blocks in the IC for scan testing based on a set of slots under a set of schedules. Each of the set of slots includes a fixed number of scan input pins/pads and scan output pins/pads of the IC. Each slot is then assigned to a specific block on the IC for the scan test until all of the slots available are utilized. The group of assigned blocks is referred to as a schedule, and all of these blocks belonging to this schedule are scan tested in parallel at the same time. The remaining blocks on the IC are also assigned to the slots until all blocks on the IC are assigned to a schedule to be scan tested.
G01R 31/3185 - Reconfiguration pour les essais, p.ex. LSSD, découpage
G01R 31/319 - Matériel de test, c. à d. circuits de traitement de signaux de sortie
G06F 30/34 - Conception de circuits pour circuits reconfigurables, p.ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 11/4093 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. mémoires tampon de données
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
88.
OUT-OF-BAND BASED INDEPENDENT LINK TRAINING OF IN-BAND LINKS BETWEEN HOST DEVICES AND OPTICAL MODULES
A first optical module includes an optical transceiver and a chip. The optical transceiver, subsequent to completion of link training of an in-band transmission link between the first optical module and a host device, waits for a second optical module to come up including transmitting a first awake signal from the first optical module to the second optical module, and receives a second awake signal from the second optical module when the second optical module is up. The chip i) based on a first out-of-band signal transmitted via an out-of-band link, performs the link training of the in-band transmission link independently of an in-band reception link between the first optical module and the host device, and ii) based on the second awake signal and a second out-of-band signal transmitted via the out-of-band link, performs link training of the in-band reception link independent of the in-band transmission link.
H04B 10/079 - Dispositions pour la surveillance ou le test de systèmes de transmission; Dispositions pour la mesure des défauts de systèmes de transmission utilisant un signal en service utilisant des mesures du signal de données
H04B 10/077 - Dispositions pour la surveillance ou le test de systèmes de transmission; Dispositions pour la mesure des défauts de systèmes de transmission utilisant un signal en service utilisant un signal de surveillance ou un signal supplémentaire
H04B 10/80 - Aspects optiques concernant l’utilisation de la transmission optique pour des applications spécifiques non prévues dans les groupes , p.ex. alimentation par faisceau optique ou transmission optique dans l’eau
89.
OUT-OF-BAND BASED INDEPENDENT LINK TRAINING OF IN-BAND LINKS BETWEEN HOST DEVICES AND OPTICAL MODULES
A first optical module includes an optical transceiver and a chip. The optical transceiver, subsequent to completion of link training of an in-band transmission link between the first optical module and a host device, waits for a second optical module to come up including transmitting a first awake signal from the first optical module to the second optical module, and receives a second awake signal from the second optical module when the second optical module is up. The chip i) based on a first out-of-band signal transmitted via an out-of-band link, performs the link training of the in-band transmission link independently of an in-band reception link between the first optical module and the host device, and ii) based on the second awake signal and a second out-of-band signal transmitted via the out-of-band link, performs link training of the in-band reception link independent of the in-band transmission link.
H04J 14/02 - Systèmes multiplex à division de longueur d'onde
H04B 10/40 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs-récepteurs
90.
GATE ALL-AROUND (GAA) FIELD EFFECT TRANSISTORS (FETS) FORMED ON BOTH SIDES OF A SUBSTRATE
An electronic device (11) includes a substrate (55), first and second semiconductor devices (22, 33), and a power supply structure (88b). The first semiconductor device (22) includes a first plurality of gate all-around (GAA) field effect transistors (FETs) (44) formed over a first side (25) of substrate (55). The second semiconductor device (33) includes a second plurality of GAA FETs (44) formed over a second side (35) of substrate (55), opposite first side (25). The power supply structure (88b) is (a) disposed at the first side (25), and (b) configured to supply power to one or more of: (i) the first plurality of GAA FETs (44) through first electrical couplings (77) disposed at the first side (25), and (ii) the second plurality of GAA FETs (44) through second electrical couplings (77) including inter-side vias (ISVs) (66) traversing the substrate (55) from the second side (35) to the first side (35).
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
91.
System and methods for firmware security mechanism
A new approach is proposed to support a hardware-based lock mechanism having a hardware-based lock unit associated with a resource, wherein the lock is utilized by an arbitrator to arbitrate between multiple agents requesting access to the resource. When a first agent requests access to resource in unlocked state, the arbitrator creates a lock ID and set a locked state indicating that the resource is locked. The lock ID is provided to the first agent, which now has exclusive control over the resource. The arbitrator ensures that any agent with the same ID may access the resource. When a second agent requests access to the resource with a lock ID to the arbitrator, it is granted access to the resource if the lock ID provided matches the one stored on the lock unit. If there is a mismatch between the lock IDs, access to the resource is denied.
G06F 21/71 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information
A multi-port transceiver comprises a plurality of first ports, a first communication interface, and a second communication interface. Multi-rate interleaver circuitry interleaves i) a plurality of first data streams, each received via a respective first port at a first data rate, and ii) a second data stream received via the first communication interface at a second data rate, to generate a third data stream to be transmitted via the second communication interface at a third data rate. Multi-rate deinterleaver circuitry deinterleaves a fourth data stream that was received via the second communication interface at the third data rate into i) a plurality of fifth data streams, each fifth data stream to be transmitted via a respective first port at the first data rate, and ii) a sixth data stream to be transmitted via the first communication interface at the second data rate.
In a storage area network operating in accordance with a transport-level protocol to interconnect host and target devices, where the transport-level protocol issues congestion notifications when any of the host or target devices becomes congested, a method for reducing congestion includes, on receipt of a request to (a) write data to one of the target devices or (b) read data from one of the target devices for return to one of the host devices, (A) determining whether congestion already exists at (a) the target device to which the write request is directed, or (b) the host device to which data from the read request is to be returned, and (B) when a congestion state already exists, comparing current depth of a queue of write or read requests to a maximum permissible queue depth. When the current depth of the queue exceeds a maximum permissible queue depth, the request is rejected.
The present disclosure describes apparatuses and methods for implementing an adaptive low-density parity check (LDPC) decoder. In various aspects, an adaptive LDPC decoder processes a first portion of data using first parameters effective to change a status of the LDPC decoder. The LDPC decoder selects second parameters of the LDPC decoder based on the status of the LDPC decoder. The LDPC decoder then processes a second portion of the data with the LDPC decoder using the second parameters and provides decoded data of the channel based on at least the processing the first portion of the data using the first parameters and the processing of the second portion of the data using the second parameters. By adaptively altering the decoding parameters based the status of the decoder, the adaptive LDPC decoder may decode channel data in fewer decoding iterations or with a higher success rate, thereby improving LDPC decoding performance.
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
95.
Gate All-Around (GAA) Field Effect Transistors (FETS) Formed on Both Sides of a Substrate
An electronic device includes a substrate, first and second semiconductor devices, and a power supply structure. The first semiconductor device includes a first plurality of gate all-around (GAA) field effect transistors (FETs) formed over a first side of the substrate. The second semiconductor device includes a second plurality of GAA FETs formed over a second side of the substrate, opposite the first side. The power supply structure is (a) disposed at the first side, and (b) configured to supply power to one or more of: (i) the first plurality of GAA FETs through first electrical couplings disposed at the first side, and (ii) the second plurality of GAA FETs through second electrical couplings including one or more inter-side vias (ISVs) traversing the substrate from the second side to the first side.
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 21/84 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant autre chose qu'un corps semi-conducteur, p.ex. étant un corps isolant
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p.ex. structures d'interconnexions enterrées
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
A first communication device performs a handshaking procedure with a second communication device, the handshaking procedure associated with transitioning from an active mode to a low power mode. The first communication device transmits data and/or idle symbols to the second communication device i) after completion of the handshake procedure, and ii) at least until the earlier of a) a time period expiring, and b) determining that the second communication device quieted a transmitter of the second communication device. The first communication device transitions to the low power mode in connection with the handshaking procedure.
The present disclosure describes apparatuses and methods for implementing an adaptive low-density parity check (LDPC) decoder performing iterations on bit-flipping or symbol-flipping operations. In various aspects, an adaptive LDPC decoder (130) processes (704) a first portion of data using first parameters, e.g. flipping thresholds, effective to change a status of the LDPC decoder, e.g. syndrome weight. The LDPC decoder selects (706) second parameters, e.g. adaptively changes flipping thresholds, of the LDPC decoder based on the status of the LDPC decoder. The LDPC decoder then processes (708) a second portion of the data with the LDPC decoder using the second parameters and provides (712) decoded data of the channel based on at least the processing the first portion of the data using the first parameters and the processing of the second portion of the data using the second parameters. By adaptively altering the decoding parameters based the status of the decoder, the adaptive LDPC decoder may decode channel data in fewer decoding iterations or with a higher success rate, thereby improving LDPC decoding performance.
H03M 13/37 - Méthodes ou techniques de décodage non spécifiques à un type particulier de codage prévu dans les groupes
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
98.
Disk writing mode with timing control of main pole relaxation
When writing data to a magnetic data storage medium, it is detected whether duration, before occurrence of a data transition, of data to be written exceeds a predetermined threshold. When the duration, before the transition, of the data to be written exceeds the predetermined threshold, the data is written by applying an initial pulse and then maintaining, until a shut-off pulse, a steady-state write current having an amplitude less than the initial pulse. A shut-off adjustment is determined based on a predetermined delay. The shut-off pulse is initiated at a time based on one bit period prior to the transition, adjusted by the shut-off adjustment. When the duration, before the transition, of the data to be written is at most equal to the predetermined threshold, the data is written by applying the initial pulse without applying a steady-state write current before the transition.
G11B 20/10 - Enregistrement ou reproduction numériques
G11B 11/105 - Enregistrement sur, ou reproduction depuis le même support d'enregistrement, dans lesquels, pour ces deux opérations, les procédés ou les moyens sont couverts par différents groupes principaux des groupes ou par différents sous-groupes du groupe ; Supports d'enregistrement correspondants utilisant l'enregistrement par magnétisation ou démagnétisation utilisant un faisceau de lumière ou un champ magnétique pour l'enregistrement et un faisceau de lumière pour la reproduction, p.ex. enregistrement thermomagnétique induit par la lumière ou reproduction par l'effet Kerr
A receiver includes an optical front-end and digital circuitry. The optical front-end is configured to receive an optical signal including first and second optical signal components having first and second polarizations and modulated with symbols at a symbol rate. The digital circuitry is configured to derive first and second digital signals representing the first and second optical signal components having the first and second polarizations. The digital circuitry includes a clock detector configured to calculate correlation terms, the correlation terms being calculated in a frequency-domain with a frequency offset commensurate with the symbol rate. The clock detector is configured to recover a clock signal of the symbols by (i) summing selected pairs of the correlation terms, and (ii) calculating or estimating a sum-of-squares of the summed pairs.
Methods and apparatus for providing soft and blind combining for PUSCH acknowledgement (ACK) processing. In an exemplary embodiment, a method includes soft-combining acknowledgement (ACK) bits received from a UE that are contained in a received sub-frame of symbols. The ACK bits are soft-combined using a plurality of scrambling sequences to generate a plurality of hypothetical soft-combined ACK bit streams. The method also includes receiving a parameter that identifies a selected scrambling sequence to be used. The method also includes decoding a selected hypothetical soft-combined ACK bit stream to generate a decoded ACK value, wherein the selected hypothetical soft-combined ACK bit stream is selected from the plurality of hypothetical soft-combined ACK bit streams based on the parameter.
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
H04L 25/06 - Moyens pour rétablir le niveau à courant continu; Correction de distorsion de polarisation
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H04L 1/1607 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue en utilisant un canal de retour dans lesquelles le canal de retour transporte des signaux de contrôle, p.ex. répétition de signaux de demande - Détails du signal de contrôle
H04W 72/121 - Planification du trafic sans fil pour les groupes de terminaux ou d’utilisateurs
H04W 72/1268 - Jumelage du trafic à la planification, p.ex. affectation planifiée ou multiplexage de flux de flux de données en liaison ascendante
