Abrégé

Methods and systems for cross-protocol time synchronization may comprise, for example, in a premises-based network, receiving a signal that conforms to a data over cable service interface specification (DOCSIS) communications protocol. A global time of day (GTOD) clock may be extracted from the received signal. Communication on the premises-based network in accordance with a multimedia over cable alliance (MoCA) communications protocol may be synchronized based at least in part on the extracted GTOD clock. Communication in a third communications protocol may be synchronized, wherein the third communications protocol may include a home phoneline networking alliance (HPNA) standard, an IEEE 802.11x standard, and a non-public wireless network protocol. The extracted GTOD clock may comprise a GPS clock, GLONASS clock, and a Galileo clock. A second signal for extracting a GTOD may be received, such as a satellite signal, and may conform to a low Earth orbit satellite signal protocol.

Classes IPC  ?

• G01S 19/05 - Systèmes de positionnement par satellite à radiophares émettant des messages horodatés, p.ex. GPS [Système de positionnement global], GLONASS [Système global de navigation par satellite] ou GALILEO Éléments coopérants; Interaction ou communication entre les différents éléments coopérants ou entre les éléments coopérants et les récepteurs fournissant des données d'assistance
• G01S 19/24 - Acquisition ou poursuite des signaux émis par le système
• G01S 19/23 - Test, contrôle, correction ou étalonnage d'un élément récepteur
• H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
• H04B 1/707 - Techniques d'étalement de spectre utilisant une modulation par séquence directe

Abrégé

A digital-to-analog conversion circuit (DAC) is operable to convert an input digital signal to an output analog signal. The DAC includes a digital signal processing circuit operable to process the input digital signal according to a first transfer function to generate a first processed digital signal and process the digital input signal according to a second transfer function to generate a second processed digital signal. The DAC includes a first unit DAC operable to convert the first processed digital signal to a first intermediate analog signal, and a second unit DAC operable to convert the second processed digital signal to a second intermediate analog signal. The DAC includes switching circuits and a combiner circuit to generate the output analog signal from the intermediate analog signals.

Classes IPC  ?

• H03M 1/66 - Convertisseurs numériques/analogiques
• H03H 17/02 - Réseaux sélecteurs de fréquence

Abrégé

An analog-to-digital converter circuit comprises code-shuffling circuitry, a plurality of digital-to-analog converter circuits, a plurality of difference circuits, and a plurality of latch circuits. The code-shuffling circuitry is operable to shuffle a plurality of digital codes among a plurality of its outputs. The plurality of digital-to-analog converter circuits are operable to convert a digital code on the respective one of the outputs to a corresponding one of a plurality of analog reference voltages. The plurality of difference circuits is operable to generate a respective one of a plurality of difference signals corresponding to a difference between an input voltage and a respective one of the plurality of reference voltages. The plurality of latch circuits is operable to latch a respective one of the plurality of difference signals to a corresponding one of a plurality of digital values.

Classes IPC  ?

• H03M 1/36 - Valeur analogique comparée à des valeurs de référence uniquement simultanément, c. à d. du type parallèle
• H03M 3/00 - Conversion de valeurs analogiques en, ou à partir d'une modulation différentielle
• H03M 1/06 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques

Abrégé

A transconductance circuit comprises a first transistor, a second transistor, a first source-degeneration device, a second source-degeneration device, a first feedback device, and a second feedback device. The gate node of the first transistor is coupled to a source node of the second transistor via the first feedback device. The gate node of the second transistor is coupled to a source node of the second transistor via the second feedback device. The source node of the first transistor is coupled to a reference voltage via the first source-degeneration device. The source node of the second transistor is coupled to the reference voltage via the second source-degeneration device.

Classes IPC  ?

• H03F 1/34 - Circuits à contre-réaction avec ou sans réaction
• H03F 3/45 - Amplificateurs différentiels
• H03F 1/22 - Modifications des amplificateurs pour réduire l'influence défavorable de l'impédance interne des éléments amplificateurs par utilisation de couplage dit "cascode", c. à d. étage avec cathode ou émetteur à la masse suivi d'un étage avec grille ou base à la masse respectivement
• H03F 1/32 - Modifications des amplificateurs pour réduire la distorsion non linéaire

Abrégé

A digital signal processing circuit comprises a first equalizer circuit and a second equalizer circuit. An output of the second equalizer is used as feedback to generate an equalized signal. The output of the second equalizer circuit is based on a plurality of postcursor values and a plurality of precursor values, where the precursor values are generated based on an output of the first DFE circuit, and the postcursor values are generated independently of the output of the first DFE.

Classes IPC  ?

• H03K 5/159 - Applications des lignes à retard non couvertes par les sous-groupes précédents
• H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p.ex. réseaux de mise en forme adaptatifs

Abrégé

A cable modem comprises transceiver circuitry and echo cancellation training circuitry. The transceiver circuitry may be operable to transmit and receive signals on a full-duplex Data Over Cable System Interface Specification (DOCSIS®) network. The echo cancellation training circuitry may be operable to: determine an echo cancellation training group to which the electronic communication device belongs; determine one or more training periods during which the echo cancellation training group is permitted to transmit training signals; and transmit an echo cancellation training signal during the determined training one or more periods and use the transmitted training signal to train echo cancellation circuitry of the cable modem.

Classes IPC  ?

• H04B 3/23 - Systèmes à ligne de transmission - Détails ouverture ou fermeture de la voie d'émission; Commande de la transmission dans une direction ou l'autre utilisant une reproduction du signal transmis décalée dans le temps, p.ex. par dispositif d'annulation
• H04L 5/18 - Changement automatique de la direction du trafic
• H04L 12/64 - Systèmes de commutation hybrides
• H04L 12/28 - Réseaux de données à commutation caractérisés par la configuration des liaisons, p.ex. réseaux locaux [LAN Local Area Networks] ou réseaux étendus [WAN Wide Area Networks]

Abrégé

A signal receiver chip may be configured to receive a satellite signal, and when the satellite signal is partially-processed off-chip, to bypass at least a portion of processing functions applied in the signal receiver chip during processing of satellite signals. The bypassed processing functions may comprise or correspond to signal band conversions. The satellite signal chip may generate an output signal, corresponding to the satellite signal, with the output signal being configured for communication to a peer device (e.g., satellite STB). The output signal may be generated and/or configured such that to enable distributing content carried in the output signal to a plurality of client devices in a local network serviced by the peer device. The signal receiver chip may combine a plurality of portions, corresponding to a plurality of satellite signals, into the output signal.

Classes IPC  ?

• H04N 21/61 - Structure physique de réseau; Traitement de signal
• H04H 40/90 - Dispositions caractérisées par des circuits ou composants spécialement adaptés à la réception spécialement adaptés aux systèmes de radiodiffusion couverts par les groupes spécialement adaptés à la réception de la radiodiffusion par satellite
• H04N 17/04 - Diagnostic, test ou mesure, ou leurs détails, pour les systèmes de télévision pour les récepteurs
• H04N 21/436 - Interfaçage d'un réseau de distribution local, p.ex. communication avec un autre STB ou à l'intérieur de la maison

Abrégé

Methods and systems are provided for adaptive guard interval (GI) combining. A signal carrying a symbol that is preceded by a guard interval (GI) that includes a portion of the symbol may be received, and a portion of the GI that is free from inter-symbol interference (ISI) may be determined. Only a part of the ISI-free portion of the GI may be selected. The selected part of the ISI-free portion of the GI may be less than a whole of the ISI-free portion. The selection may be configured based on a parameter that is applied to a function used in extracting the symbol. The parameter may be a timing adjustment, relative to a start of the symbol, applied to the function when extracting the symbol. Only the part of the ISI-free portion of the GI may then be extracted and combined with a corresponding portion of the symbol.

Classes IPC  ?

• H04L 27/26 - Systèmes utilisant des codes à fréquences multiples
• H04L 25/02 - Systèmes à bande de base - Détails

Abrégé

Systems and methods are provided for receiver nonlinearity estimation and cancellation. Narrowband (NB) estimation may be performed in a receiver during handling of received radio frequency (RF) signals. The narrowband (NB) may include generating estimation channelization information relating to received RF signals; generating reference nonlinearity information relating to one or more other signals, which may cause or contribute to nonlinearity that affects the processing of the received RF signals; and generating, based on the estimation channelization information relating to the received RF signals and the reference nonlinearity information relating to the other signals, control data for configuring nonlinearity cancellation functions. The received RF signals may be channelized, and the estimation channelization information may be generated based on the channelization of the received RF signals. The other signals may be channelized, and the reference nonlinearity information may be generated based on the channelization of the other signals.

Classes IPC  ?

• H04B 1/12 - Montages de neutralisation, d'équilibrage ou de compensation
• H04B 1/04 - Circuits

Abrégé

Systems and methods are provided for utilizing low gain low noise signal amplification and ideal taps in coaxial networks. An ideal tap configured for use in coaxial networks may have a plurality of ports, one or more processing circuits configured for handling reception and transmission of signals communicated via the tap, and one or more echo cancellation circuits configured for providing echo cancellation during operations of the tap. The processing circuits are configured based on particular predefined tap performance criteria. The tap performance criteria may relate to one or more of port-to-port isolation, return loss, port-to-port gain, and up-tilt. The echo cancellation circuits may be configurable for providing the echo cancellation based on the tap performance criteria. The echo cancellation circuits may include an echo cancellation control circuit for controlling echo cancellation functions and/or operations. The echo cancellation circuits may include dedicated per-port echo cancellation circuits.

Classes IPC  ?

• H04L 25/00 - Systèmes à bande de base
• H04B 3/23 - Systèmes à ligne de transmission - Détails ouverture ou fermeture de la voie d'émission; Commande de la transmission dans une direction ou l'autre utilisant une reproduction du signal transmis décalée dans le temps, p.ex. par dispositif d'annulation
• H04L 5/14 - Fonctionnement à double voie utilisant le même type de signal, c. à d. duplex
• H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p.ex. réseaux de mise en forme adaptatifs

Abrégé

A system supporting enhanced programmable signal adjustments may include a plurality of circuits configured to generate a corresponding plurality of input signals; a signal conditioner configured to condition the plurality of signals; and a controller configured to control the signal conditioner. The controller may generate one or more control signals for the controlling of the signal conditioner. The signal conditioner may select one or more input signals from the plurality of input signals, based on a first control signal generated by the controller; may generate an adjustment signal based on a second control signal generated by the controller; and may adjust at least one of the selected one or more input signals based on the adjustment signal and a third control signal generated by the controller.

Classes IPC  ?

• G01D 18/00 - Test ou étalonnage des appareils ou des dispositions prévus dans les groupes
• G05B 19/042 - Commande à programme autre que la commande numérique, c.à d. dans des automatismes à séquence ou dans des automates à logique utilisant des processeurs numériques
• G01D 5/16 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensible; Moyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminé; Transducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension en faisant varier la résistance

Abrégé

Systems and methods are provided for peak to average power ratio (PAPR) reduction in multichannel transmissions. A plurality of frequency-domain symbols may be generated and assigned to a plurality of subcarriers associated with a multichannel transmission. The subcarriers may be assigned to a plurality of channels used for the multichannel transmission, with a number of the channels being different than a number of the subcarriers. A plurality of time-domain signals corresponding to the plurality of channels may be generated, and an adjustment may be applied to at least one time-domain signal, to generate a corresponding adjusted time-domain signal. The adjustment may be configured based on one or more characteristic associated with at least two of the frequency-domain symbols. Handling related information may be communicated form the transmit-side to the receive-side, such as using spare carriers, to enable handling an output corresponding to the plurality of time-domain signals.

Classes IPC  ?

• H03D 1/06 - Modifications de démodulateurs pour réduire la distorsion, p.ex. par réaction négative
• H04B 15/00 - Suppression ou limitation du bruit ou des interférences
• H04L 27/26 - Systèmes utilisant des codes à fréquences multiples
• H04B 1/10 - Dispositifs associés au récepteur pour limiter ou supprimer le bruit et les interférences
• H03D 3/00 - Démodulation d'oscillations modulées en angle

Abrégé

As a non-limiting example, various aspects of this disclosure provide embodiments of AC direct drives for light emitting diodes for a wide variety of drive stages.

Classes IPC  ?

• H05B 33/08 - Circuits pour faire fonctionner des sources lumineuses électroluminescentes

Abrégé

Systems and methods are provided for handling jitter improvement in transmitters. During processing of input data for serial transmission, it may be determined if jitter may occur, and when jitter occurs one or more adjustments may be determined, based on dummy data, to reduce jitter in an output corresponding to the input data. The one or more adjustments may then be applied during processing of the input data, to reduce jitter in a serial output corresponding to the input data. The dummy data may be generated based on the input data. The dummy data may be configured such that it may generate corresponding dummy current pulses which may be used in controlling supply variations during generation of the serial output. The use of the dummy data may be selectively turned on or off.

Classes IPC  ?

• H04L 1/20 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue en utilisant un détecteur de la qualité du signal
• H04B 1/04 - Circuits
• H04B 15/02 - Réduction des perturbations parasites dues aux appareils électriques avec des moyens disposés sur ou à proximité de la source de perturbation
• H03K 3/01 - Circuits pour produire des impulsions électriques; Circuits monostables, bistables ou multistables - Détails
• H03M 9/00 - Conversion parallèle/série ou vice versa
• H04B 1/717 - Aspects liés aux impulsions
• H04L 12/841 - Actions liées à la commande de flux utilisant des données temporelles, p.ex. temps d'aller retour [RTT]
• H04L 12/26 - Dispositions de surveillance; Dispositions de test

Abrégé

Aspects of methods and systems for PAPR reduction in a microwave backhaul outdoor unit are provided.

Classes IPC  ?

• H04B 1/00 - TRANSMISSION - Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission
• H04B 1/04 - Circuits
• H04B 3/36 - Circuits de répéteur
• H04B 3/56 - Circuits de couplage, blocage ou dérivation des signaux
• H04L 27/26 - Systèmes utilisant des codes à fréquences multiples

Abrégé

The present invention provides a system and method for protecting data stored in the control registers of an integrated circuit, such as a television chip. The system and method use one or more selectively activated read protection modules to prevent the control registers from being read unless a predetermined key or password is entered. The password or key may be stored in password registers within the chip. A key access generator will enable read access of the control registers if correct values are written to the appropriate password registers. The key access generator may enable read access for a predetermined period of time or until it receives another input.

Classes IPC  ?

• G06F 1/26 - Alimentation en énergie électrique, p.ex. régulation à cet effet
• G06F 21/10 - Protection de programmes ou contenus distribués, p.ex. vente ou concession de licence de matériel soumis à droit de reproduction

Abrégé

Systems and methods are provided for full duplex DOCSIS cable modem echo cancellation with training. During reception of downstream signals, echo effects on downstream signals may be determined, with at least some of the echo effects corresponding to concurrently transmitted upstream signals. Echo cancellation corrections may be determined based on the determined echo effects, and the echo cancellation corrections may be applied during processing of the downstream signals. The echo cancellation corrections may include one or both of ACI (adjacent channel interference) cancellation corrections and ALI (adjacent leakage interference) cancellation correction. The echo cancellation may include or be based on preforming echo cancellation training, during active communication and based on one or both of the downstream signals and the upstream signals.

Classes IPC  ?

• H04B 3/20 - Systèmes à ligne de transmission - Détails ouverture ou fermeture de la voie d'émission; Commande de la transmission dans une direction ou l'autre
• H04B 3/23 - Systèmes à ligne de transmission - Détails ouverture ou fermeture de la voie d'émission; Commande de la transmission dans une direction ou l'autre utilisant une reproduction du signal transmis décalée dans le temps, p.ex. par dispositif d'annulation
• H04L 12/28 - Réseaux de données à commutation caractérisés par la configuration des liaisons, p.ex. réseaux locaux [LAN Local Area Networks] ou réseaux étendus [WAN Wide Area Networks]
• H04L 5/14 - Fonctionnement à double voie utilisant le même type de signal, c. à d. duplex
• H04J 3/06 - Dispositions de synchronisation
• H04L 29/06 - Commande de la communication; Traitement de la communication caractérisés par un protocole

Abrégé

In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as desired for PMOS. At the same time, this configuration scales the threshold back to normal at low input common mode voltages, thereby countering the negative impact of body effect. In short, the body bias applied to the NMOS (or PMOS) device helps in adapting the threshold voltage to the operating condition.

Classes IPC  ?

• H03K 3/01 - Circuits pour produire des impulsions électriques; Circuits monostables, bistables ou multistables - Détails
• H03K 17/16 - Modifications pour éliminer les tensions ou courants parasites
• H03K 17/30 - Modifications pour fournir un seuil prédéterminé avant commutation

Abrégé

A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.

Classes IPC  ?

• H03M 1/06 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques
• H03M 1/66 - Convertisseurs numériques/analogiques

Abrégé

Methods and systems for continuous gain control in a feedback transimpedance amplifier (TIA) may include: in a TIA including a gain stage, a feedback resistance for the gain stage, a current sense resistor, and a feedback current control circuit: receiving an input current at an input of the gain stage: directing a current through the current sense resistor to the feedback current control circuit, and generating an output voltage proportional to the input current and a gain of the TIA. The gain may be configured by providing a proportion (α) of the current through the feedback current control circuit to the input of the gain stage. The proportion α of the current from the feedback current control circuit to the input of the gain stage may be configured by applying a differential voltage to control terminals of a transistor pair in the feedback current control circuit.

Classes IPC  ?

• H03G 3/30 - Commande automatique dans des amplificateurs comportant des dispositifs semi-conducteurs
• H04B 10/40 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs-récepteurs
• H04B 10/564 - Commande de la puissance
• H04B 10/69 - Dispositions électriques dans le récepteur

Abrégé

Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.

Classes IPC  ?

• H03M 1/08 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques du bruit
• H03M 1/12 - Convertisseurs analogiques/numériques
• H03M 1/46 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p.ex. du type à approximations successives avec convertisseur numérique/analogique pour fournir des valeurs de référence au convertisseur

Abrégé

Systems and methods are provided for enhanced parallel bit-interleaving. The parallel bit-interleaving may include, in each of a plurality of cycles, reading a number of bits from an input bitstream; processing the read bits, with the processing including applying a first adjustment to a first combination of bits that includes the read bits and additional bits, wherein each of the additional bits includes a previously read bit in the input bitstream or a pre-set bit; when one or more conditional criteria are met, applying a second adjustment to a second combination of bits that includes bits corresponding to previously read bits, wherein the conditional criteria include completing processing of a full column; writing into memory a number of bits corresponding to the first combination of bits and/or the second combination of bits; and reading from the memory a number of bits, for generating an output corresponding to the particular cycle.

Classes IPC  ?

• G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
• H03M 13/27 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes utilisant des techniques d'entrelaçage
• H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
• G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]

Abrégé

Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logice modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.

Classes IPC  ?

• H03M 1/38 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p.ex. du type à approximations successives
• H03M 1/04 - Conversion analogique/numérique; Conversion numérique/analogique utilisant des techniques stochastiques
• H03M 1/44 - Comparaisons séquentielles dans des étages disposés en série avec changement de la valeur du signal analogique
• H03M 1/46 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p.ex. du type à approximations successives avec convertisseur numérique/analogique pour fournir des valeurs de référence au convertisseur
• H03M 1/00 - Conversion analogique/numérique; Conversion numérique/analogique

Abrégé

Methods and systems are provided for replacing hardware during active communications. A replacement circuit may be added into a communication system during active communications with a link peer, with a circuit being replaced handling signals communicated with the link peer. The replacement circuit may be configured to handle a first subset of the signals communicated with the link peer, with the circuit being replaced being configured to handle a second subset of the signals communicated with the link peer. Signals of the first subset and the second subset may differ based on at least one signal related attribute. After ensuring that the replacement circuit is operating correctly, the replacement circuit may be configured to handle all signals communicated with the peer link, and the circuit being replaced may be configured for removal. The replacement circuit and the circuit being replaced may interact during the replacement sequence.

Classes IPC  ?

• H04B 7/26 - Systèmes de transmission radio, c. à d. utilisant un champ de rayonnement pour communication entre plusieurs postes dont au moins un est mobile

Abrégé

Systems and methods are provided for managing dynamic element matching (DEM) in digital-to-analog converters (DACs). One or more parameters associated with the DAC and/or a signal being converted via the DAC; and based on the one or more parameters, conditions affecting dynamic element matching in the DAC may be assessed. Based on the assessing of the conditions, one or more adjustments may be determined and dynamically applied to the dynamic element matching in the DAC.

Classes IPC  ?

• H03M 1/06 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques
• H03M 1/10 - Calibrage ou tests
• H03M 1/66 - Convertisseurs numériques/analogiques

Abrégé

Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone.

Classes IPC  ?

• H03M 1/66 - Convertisseurs numériques/analogiques
• H03M 1/00 - Conversion analogique/numérique; Conversion numérique/analogique
• H03M 1/12 - Convertisseurs analogiques/numériques
• H03M 1/18 - Commande automatique pour modifier la plage des signaux que le convertisseur peut traiter, p.ex. réglage de la plage de gain
• H03M 1/36 - Valeur analogique comparée à des valeurs de référence uniquement simultanément, c. à d. du type parallèle
• H03M 1/70 - Commande automatique pour modifier la plage du convertisseur
• H03M 1/74 - Conversion simultanée
• H04B 1/40 - Circuits

Abrégé

Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may comprise at least two processing paths, each comprising at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may comprise adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.

Classes IPC  ?

• H04B 1/04 - Circuits
• H03F 1/32 - Modifications des amplificateurs pour réduire la distorsion non linéaire
• H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
• G11B 20/22 - Traitement du signal, non spécifique du procédé d'enregistrement ou de reproduction; Circuits correspondants pour diminuer les distorsions
• H03M 1/06 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques
• H04B 1/10 - Dispositifs associés au récepteur pour limiter ou supprimer le bruit et les interférences
• H03M 1/66 - Convertisseurs numériques/analogiques

Abrégé

Methods and systems are provided for aligning devices separated by physical barriers. A first electronic device may be paired with a second electronic device, with the first electronic device and the second electronic device being on opposite sides of a physical barrier. Wireless communication of signals between the first electronic device and the second electronic device may then be configured to nullify or reduce signals in areas other than a region within the barrier between a signal transmission component of the first electronic device and a signal reception component of the second electronic device. Feedback for enabling aligning the first electronic device with the second electronic device may be provided, such as to user of one or both of the first electronic device and the second electronic device. Providing the feedback may include generating visual and/or audio cues to enable the aligning.

Classes IPC  ?

• H04B 5/00 - Systèmes de transmission à induction directe, p.ex. du type à boucle inductive
• H04B 5/02 - Systèmes de transmission à induction directe, p.ex. du type à boucle inductive utilisant un émetteur-récepteur

Abrégé

Methods and systems are provided for low-power decoding. An example system may include one or more storage circuits and a decoder circuit. The decoder circuit may implement a plurality of nodes for use during decoding, including at least one data generating node and at least one data checking node, and the storage circuits may store status information associated with the nodes, the status information indicating when each corresponding node is locked or unlocked. During decoding operations, the decoder circuit may set the status information to lock one or more of the nodes based on one or more locking conditions, and may cease decoding based on one or more ceasing conditions. The decoder circuit may locks a data generating node when a corresponding calculated value meets a particular condition, and may lock a data checking node when all data generating nodes associated with it are locked.

Classes IPC  ?

• H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
• H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
• H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue

Abrégé

Enhanced multi-channel sensor interfaces with programmable signal adjustments are provided. An example sensor interface may include an input selector that selects one or more sensor signals from a plurality of sensor signals based on input selection control signal; an offset generator that generates an offset signal based on an offset control signal; and a programmable signal adjuster that adjusts at least one selected sensor signal based on the generated offset signal and a signal adjustment control signal. The sensor interface may include a control interface unit that generates the input selection control signal, the offset control signal, and the signal adjustment control signal. The sensor interface may include a comparator that compares output of the programmable signal adjuster with a reference signal, and provides based on the comparison an output configured for use in performing offset correction. The programmable signal adjuster may generate a number of selectable gains.

Classes IPC  ?

• G01D 18/00 - Test ou étalonnage des appareils ou des dispositions prévus dans les groupes
• G01D 5/16 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensible; Moyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminé; Transducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension en faisant varier la résistance

Abrégé

Methods and systems are provided for gain control during communications. A first electronic device may communicated data to a second electronic device; may monitor conditions and/or parameters affecting estimated reception performance at the second electronic device; and may communicated to the second electronic device, via a connection separate from and different than a connection used in communicating the data, information relating to the monitored conditions, to enable adjusting functions relating to reception of the data at the second electronic device. Based on the received information, at least one reception related function in the second electronic device may be controlled. The controlling may include determining, based on the received information, adjustments to the at least one reception related function or to a related parameter. The at least one reception related function may include applying gain to at least a portion of signals received by the second electronic device.

Classes IPC  ?

• H04B 1/00 - TRANSMISSION - Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission
• H03M 1/50 - Convertisseurs analogiques/numériques avec conversion intermédiaire en intervalle de temps
• H03M 1/12 - Convertisseurs analogiques/numériques
• H04B 17/21 - Surveillance; Tests de récepteurs pour la correction des mesures
• H04B 17/24 - Surveillance; Tests de récepteurs avec rétroaction des mesures vers l’émetteur
• H03M 1/18 - Commande automatique pour modifier la plage des signaux que le convertisseur peut traiter, p.ex. réglage de la plage de gain

Abrégé

Systems and methods are provided for adaptive control of pre-distortion during signal transmissions. While applying pre-distortion during processing of an input signal for transmission, feedback data may be generated based on a plurality of feedback signals, and adjustments to the pre-distortion may be applied to the pre-distortion based on the feedback data. Each of feedback signals corresponds to a particular processing stage performed during the processing of the input signal. Generating the feedback data comprises applying adjustments to the plurality of feedback signals based on a type and/or a source of at least one feedback signal, with the adjustments comprising one or more of: applying a gain to one of the plurality of feedback signals; applying a delay to one of the plurality of feedback signals; and modifying a first one of the plurality of feedback signals based on a second one of the plurality of feedback signals.

Classes IPC  ?

• H04L 27/36 - Circuits de modulation; Circuits émetteurs
• H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p.ex. réseaux de mise en forme adaptatifs
• H03F 1/32 - Modifications des amplificateurs pour réduire la distorsion non linéaire
• H04B 15/00 - Suppression ou limitation du bruit ou des interférences

Abrégé

Systems and methods are provided for detection and compensation of frequency drifts. Frequency related information may be determined for each of one or more channels in an input signal, and a frequency drift may be determined based on the determined frequency related information of the one or more channels. Frequency related adjustments may be determined based on the frequency drift, and the frequency related adjustments may be applied to different circuits used during one or more of: receiving of the input signal, processing of the input signal, processing of an intermediate signal generated based on the processing of the input signal, and generating of an output signal corresponding to the input signal. Applying the frequency related adjustments may be configured to meet one or more criteria.

Classes IPC  ?

• H03B 5/18 - Elément déterminant la fréquence comportant inductance et capacité réparties
• H03L 7/00 - Commande automatique de fréquence ou de phase; Synchronisation
• H03L 1/00 - Stabilisation du signal de sortie du générateur contre les variations de valeurs physiques, p.ex. de l'alimentation en énergie

Abrégé

Systems and methods are provided for digital-to-analog converters (DACs) with enhanced dynamic element matching (DEM) and calibration. DEM may be adapted based on assessment of one or more conditions that may affect the DACs or DEM functions thereof. The one or more condition may comprise amount of signal backoff. The adaption may comprise switching the DEM function (as a whole, or partially—e.g., individual DEM elements) on or off based on the assess conditions. The DACs may incorporate use of calibration. The DEM and/or the calibration may be applied to only a portion of the DAC, such as a particular segment (e.g., a middle segment comprising bits between the MSBs and the LSBs).

Classes IPC  ?

• H03M 1/48 - Convertisseurs à asservissement
• H03M 1/06 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques
• H03M 1/10 - Calibrage ou tests
• H03M 1/66 - Convertisseurs numériques/analogiques

Abrégé

A digital-to-analog converter (DAC) may have an encoder that generates a multi-bit output based on a multi-bit input, a plurality of first converter elements, with each first converter element generating an output according to a single bit of the multi-bit output of the encoder; and a combiner that generates a combined output based on combining outputs from the plurality of first converter elements. The number of bits in the multi-bit input being two or more and the number of bits in the multi-bit output being greater than the number of bits in the multi-bit input. The DAC may also have one or more second converter elements, with second converter element generating an output according to a single bit, and the combiner may generates the combined output based on combining outputs from the plurality of first converter elements with outputs from the one or more second converter elements.

Classes IPC  ?

• H03M 1/06 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques
• H03M 1/08 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques du bruit
• H03M 1/74 - Conversion simultanée
• H03M 1/66 - Convertisseurs numériques/analogiques

Abrégé

Systems and methods are provided for dynamically biasing power amplifiers. A power amplifier (PA) that amplifies an input signal may be controlled based on processing of the input signal. The controlling may include adjusting biasing applied to the power amplifier (PA). The processing of the input signal may include applying clipping to the input signal and determining one or more parameters of the input signal. The biasing applied to the power amplifier (PA) may be adjusted based on the one or more parameters of the input signal. The clipping may be configured such that signals applied to positive and negative sides of the power amplifier (PA) are not differential.

Classes IPC  ?

• H03F 3/21 - Amplificateurs de puissance, p.ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs
• H03F 3/45 - Amplificateurs différentiels
• H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p.ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire

Abrégé

Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor, wherein: source terminals of both a diode-connected transistor and a second MOS transistor are coupled to the gate terminal of the switching MOS transistor; drain terminals of both the diode-connected transistor and the second MOS transistor are coupled to a source terminal of a third MOS transistor, the third MOS transistor coupled in series with a fourth MOS transistor; and a drain terminal of the fourth MOS transistor is coupled to ground. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage to activate the pull-down path.

Classes IPC  ?

• H03K 17/16 - Modifications pour éliminer les tensions ou courants parasites
• H03K 17/06 - Modifications pour assurer un état complètement conducteur

Abrégé

Nonlinearity correction in a device that performs analog-to-digital conversion on received analog signals, may be calibrated by generating correction-parameters estimation which when applied to the total spectral content reduces distortion resulting from said nonlinearity in originally-unoccupied spectral regions. Digital signals generated based on sampling of the received analog signals may then be corrected, to remove nonlinearity related distortion, based on the estimated correction-parameters. The nonlinearity calibration may be performed during reception and handling of said analog signals. The correction-parameters may be generated based on signals located in particular spectral regions, such as the originally-unoccupied spectral regions. These signals may be injected within the device, into the particular spectral regions, and the signal may have known characteristics to enable estimating the required correction.

Classes IPC  ?

• H03M 1/10 - Calibrage ou tests
• H03M 1/12 - Convertisseurs analogiques/numériques

Abrégé

fs is the full-scale voltage of the ADC.

Classes IPC  ?

• H03M 1/12 - Convertisseurs analogiques/numériques
• H03M 1/06 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques
• H03M 1/44 - Comparaisons séquentielles dans des étages disposés en série avec changement de la valeur du signal analogique
• H03M 1/46 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p.ex. du type à approximations successives avec convertisseur numérique/analogique pour fournir des valeurs de référence au convertisseur

Abrégé

Aspects of a method and system for high-speed, low-power optical communications are provided. In one embodiment, a system for optical communications comprises a digital-to-analog converter (DAC), a driver, and a transmit optical subsystem. The DAC is operable to receive a digital code of a plurality of digital codes and output an analog current signal having an analog current level of a plurality of analog current levels. The driver is operable to condition the analog current signal output from the digital-to-analog converter. The transmit optical subsystem is operable to generate an optical power signal from the conditioned analog current signal. A mapping between the plurality of digital codes and the plurality of analog current levels is dynamically controlled according to one or more characteristics of the optical power signal. The one or more characteristics comprise or a symbol amplitude sensitivity and/or a nonlinearity that may be temperature dependent.

Classes IPC  ?

• H04B 10/079 - Dispositions pour la surveillance ou le test de systèmes de transmission; Dispositions pour la mesure des défauts de systèmes de transmission utilisant un signal en service utilisant des mesures du signal de données
• H04B 10/564 - Commande de la puissance
• H04B 10/40 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs-récepteurs

Abrégé

Systems and methods are provided for digital-to-analog conversions with adaptive digital offsets. A digital offset may be determined and applied to a digital input to a digital-to-analog converter (DAC), and digital-to-analog conversions are then applied via the DAC to the digital input with the digital offset. The digital offset may be set to account for one or more conditions relating to inputs to the DAC, with the one or more conditions affecting switching characteristics of one or more of a plurality of conversion elements in the DAC. The digital offset may be determined dynamically and adaptively, such as based on the input and/or conditions relating to the input. The adjustments may be selectively applied to the digital offset for particular input conditions.

Classes IPC  ?

• H03M 1/06 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques
• H03M 1/10 - Calibrage ou tests
• H03M 1/68 - Convertisseurs numériques/analogiques à conversions de sensibilités différentes, c. à d. qu'une conversion se rapportant aux bits les plus significatifs et une autre aux bits les moins significatifs

Abrégé

Methods and systems for crest factor reduction may comprise generating an original waveform, generating a distortion signal by reducing a crest factor of the original waveform, generating an error signal by subtracting out the original waveform from the distortion signal, and generating a conditioned waveform by adding the error signal to the original waveform. The crest factor of the original waveform may be reduced based on spectral mask requirements. The crest factor of the original waveform may be reduced using a limiter. The power amplifier may comprise a programmable gain amplifier (PGA). The distortion signal may be generated based on a PGA model and/or a predistortion model. A signal from an output of the PA may be fed back to the PGA model. The PGA model may be dynamically configured. The crest factor of the original waveform may be reduced in an analog domain and/or a digital domain.

Classes IPC  ?

• H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p.ex. réseaux de mise en forme adaptatifs
• H04B 1/04 - Circuits
• H03F 3/213 - Amplificateurs de puissance, p.ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
• H03F 3/24 - Amplificateurs de puissance, p.ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
• H03F 3/195 - Amplificateurs à haute fréquence, p.ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
• H03F 1/32 - Modifications des amplificateurs pour réduire la distorsion non linéaire
• H03G 3/30 - Commande automatique dans des amplificateurs comportant des dispositifs semi-conducteurs

Abrégé

A communication receiver which applies signal processing for quantitatively estimating receive signal factors such as communication channel quality, signal characteristics, and overall system received bit error rate (BER) or packet error rate (PER) and which applies a general algorithm for mapping these estimated factors to control receiver performance and minimize power consumption.

Classes IPC  ?

• H04W 52/02 - Dispositions d'économie de puissance
• H04B 1/10 - Dispositifs associés au récepteur pour limiter ou supprimer le bruit et les interférences
• H04L 27/06 - Circuits de démodulation; Circuits récepteurs
• H03G 3/20 - Commande automatique
• H04L 1/20 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue en utilisant un détecteur de la qualité du signal
• H04W 88/02 - Dispositifs terminaux
• H04B 17/00 - Surveillance; Tests

Abrégé

Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.

Classes IPC  ?

• H03M 1/00 - Conversion analogique/numérique; Conversion numérique/analogique
• H03M 1/12 - Convertisseurs analogiques/numériques
• H03M 1/46 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p.ex. du type à approximations successives avec convertisseur numérique/analogique pour fournir des valeurs de référence au convertisseur
• H03M 1/08 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques du bruit

Abrégé

Systems and methods are provided for parallel column twist interleaving. Parallel bit-interleaving with column twist may be applied to an input bitstream based on one or more interleaving parameters. Bits in the input bitstream may be read, in sets having size based on a first interleaving parameter, and may then be processed based on a second interleaving parameter. The processing may comprise applying a shift to a combination of bits that include a current bit set and additional bits corresponding to previously processed bit sets and/or pre-set bits. The shift may be determined based on a column twist associated with the current corresponding. Bits generated based on processing in current and/or previous cycles may be stored into memory, and bits may be read from the memory, based on a third interleaving parameter, for generating an output interleaved bitstream.

Classes IPC  ?

• G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
• G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]

Abrégé

Systems and methods are provided for a successive approximation register (SAR) analog-to-digital converter (ADC) with an ultra-low burst error rate. Analog-to-digital conversions may be applied via a plurality of successive conversion cycles, with each conversion cycle corresponding to a particular bit in a corresponding digital output. Meta-stability may be detected during each one of the plurality of successive conversion cycles, and for each one of the plurality of successive conversion cycles, a next one of the plurality of successive conversion cycles may be triggered based on a cycle termination event. After completion of all of the plurality of successive conversion cycles, a meta-stability state of each of the plurality of successive conversion cycles may be assessed, and the digital output may be controlled based on the assessment.

Classes IPC  ?

• H03M 1/38 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p.ex. du type à approximations successives
• H03M 1/46 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p.ex. du type à approximations successives avec convertisseur numérique/analogique pour fournir des valeurs de référence au convertisseur
• H03M 1/12 - Convertisseurs analogiques/numériques
• H03M 1/00 - Conversion analogique/numérique; Conversion numérique/analogique
• H03M 1/06 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques

Abrégé

x where x ranges from 0 to m−1 and m is a number of single switched capacitors per input line.

Classes IPC  ?

• H03M 1/12 - Convertisseurs analogiques/numériques
• H03M 1/06 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques
• H03M 1/44 - Comparaisons séquentielles dans des étages disposés en série avec changement de la valeur du signal analogique

Abrégé

Systems and methods are provided for peak to average power ratio (PAPR) reduction in multichannel digital front-ends (DFEs). A transmitter may be configured to reduce PAPR during multichannel transmission, with the reducing comprising: generating a plurality of frequency-domain symbols, each of which corresponding to a particular one of a plurality of subcarriers; assigning the subcarriers to a plurality of channels, wherein a number of channels is less than a number of subcarriers; and generating a plurality of time-domain signals corresponding to the channels. An adjustment to reduce PAPR may be applied to at least one of the time-domain signals, with the adjustment being based on symbols boundaries. The adjustment may comprise sign inversion. Adjusted and unadjusted waveforms may be generated for two or more of the time-domain signals; and selection may be made between generated adjusted waveforms based on particular criteria. The criteria may comprise lowest peak.

Classes IPC  ?

• H03D 1/04 - Modifications de démodulateurs pour réduire les parasites dus aux signaux non désirés
• H03K 5/01 - Mise en forme d'impulsions
• H04B 1/10 - Dispositifs associés au récepteur pour limiter ou supprimer le bruit et les interférences
• H04L 25/08 - Modifications pour réduire les perturbations; Modifications pour réduire les effets des défauts de ligne
• H04L 27/26 - Systèmes utilisant des codes à fréquences multiples
• H03D 3/00 - Démodulation d'oscillations modulées en angle
• H04B 15/00 - Suppression ou limitation du bruit ou des interférences
• H03D 1/06 - Modifications de démodulateurs pour réduire la distorsion, p.ex. par réaction négative

Abrégé

Systems and methods are provided for handling interference during communication of signals. A control signal based on leakage between the transmit path and the receive path, at least one signal applied in the transmit path during transmission of signals, and at least one signal generated in the receive path during processing of received signals. The control signal may then be applied into the receive path for use in completing processing of the received signals. One or more characteristics associated with the control signal may be set and/or adjusted based on one or more control signals applied in the transmit path. Characteristics of signals in the transmit path that may leak into the receive path may be tracked, and the control signal may be adjusted based on these Characteristics. Transmit power may be tracked, and the control signal may be adjusted based on the tracking of the transmit power.

Classes IPC  ?

• H04B 1/525 - Dispositions hybrides, c. à d. dispositions pour la transition d’une transmission bilatérale sur une voie à une transmission unidirectionnelle sur chacune des deux voies ou vice versa avec des moyens de réduction de la fuite du signal de l’émetteur vers le récepteur
• H04B 1/12 - Montages de neutralisation, d'équilibrage ou de compensation

Abrégé

A first microwave backhaul transceiver may comprise a reflector and a signal processing subassembly. The signal processing subassembly may comprise a plurality of antenna elements positioned at a focal plane of the reflector. The signal processing subassembly may process a plurality of microwave signals corresponding to the plurality of antenna elements using a corresponding plurality of phase coefficients and a corresponding plurality of amplitude coefficients. The signal processing subassembly may adjust a radiation pattern of the plurality of antenna elements during operation of the signal processing subassembly through adjustment of the phase coefficients and/or the amplitude coefficients.

Classes IPC  ?

• H04W 16/28 - Structures des cellules utilisant l'orientation du faisceau
• H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
• H01Q 3/40 - Dispositifs pour changer ou faire varier l'orientation ou la forme du diagramme de directivité des ondes rayonnées par une antenne ou un système d'antenne faisant varier la distribution de l’énergie à travers une ouverture rayonnante faisant varier la phase par des moyens électriques avec une matrice faisant varier l'angle de déphasage
• H04B 1/40 - Circuits
• H04W 88/08 - Dispositifs formant point d'accès
• H01Q 25/00 - Antennes ou systèmes d'antennes fournissant au moins deux diagrammes de rayonnement
• H04B 1/10 - Dispositifs associés au récepteur pour limiter ou supprimer le bruit et les interférences
• H04B 7/10 - Diversité de polarisation; Diversité de direction
• H04W 64/00 - Localisation d'utilisateurs ou de terminaux pour la gestion du réseau, p.ex. gestion de la mobilité

Abrégé

A system comprises a modulator circuit, a test signal generator circuit, and a control circuit. The modulator circuit is operable to generate a data-carrying signal based on a reference signal. The test signal generator circuit is operable to generate a test signal based on the reference signal. The control circuit is operable to determine current status of a microwave backhaul link. The control circuit is operable to configure a nominal frequency at which the test signal generator circuit generates the test signal based on the determined status of the microwave backhaul link. The control circuit is operable to determine an amount of whitespace to have on either side of the test signal based on the current status of the microwave backhaul link. The control circuit is operable to configure the modulator circuit such that the data-carrying signal has the determined amount of whitespace surrounding the nominal frequency of the test signal.

Classes IPC  ?

• H04L 25/08 - Modifications pour réduire les perturbations; Modifications pour réduire les effets des défauts de ligne
• H04L 27/12 - Circuits de modulation; Circuits émetteurs
• H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
• H04B 1/10 - Dispositifs associés au récepteur pour limiter ou supprimer le bruit et les interférences
• H04B 17/00 - Surveillance; Tests
• H04L 1/24 - Tests pour s'assurer du fonctionnement correct
• H04L 27/00 - Systèmes à porteuse modulée

Abrégé

A communications network comprises performance determination circuitry and link control circuitry. The performance determination circuitry is operable to determine performance of a microwave backhaul link between a first microwave backhaul transceiver and a second microwave backhaul transceiver. The microwave backhaul link backhauls traffic of a mobile access link. The link control circuitry is operable to, in response to an indication from the performance determination circuitry that the performance of the microwave backhaul link has degraded, adjust one or more signaling parameters used for the mobile access link. The link control circuitry is operable to, in response to the indication that the performance of the microwave backhaul link has degraded, adjust one or more signaling parameters used for the backhaul link in combination with the adjustment of the parameter(s) of the access link.

Classes IPC  ?

• H04W 24/02 - Dispositions pour optimiser l'état de fonctionnement
• H04W 72/08 - Affectation de ressources sans fil sur la base de critères de qualité
• H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
• H04B 7/155 - Stations terrestres
• H04W 88/08 - Dispositifs formant point d'accès

Abrégé

Methods and systems for cross-protocol time synchronization may comprise, for example, in a premises-based network: receiving, by a network controller located at a root node in the premises, signals that conform to one or more first communications protocol; bridging said received signals to conform to a second communications protocol different from the one or more first communications protocol; and communicating said bridged signals to one or more networked devices within said premises-based wired network, wherein only signals conforming to said second communications protocol are concurrently communicated in a frequency range that is independent of frequency range limitations of the one or more first communications protocol and of the second communications protocol, and that is limited only by a frequency range of wiring in the premises-based network. One of the signals conforming to the one or more first communications protocol comprises a data over cable service interface specification (DOCSIS) signal.

Classes IPC  ?

• H04N 21/2381 - Adaptation du flux multiplexé à un réseau spécifique, p.ex. un réseau à protocole Internet [IP]
• H04N 21/4363 - Adaptation du flux vidéo à un réseau local spécifique, p.ex. un réseau IEEE 1394 ou Bluetooth® 
• H04N 21/61 - Structure physique de réseau; Traitement de signal
• H04N 7/10 - Adaptations à la transmission par câble électrique
• H04N 21/214 - Plate-forme spécialisée de serveur, p.ex. serveur situé dans un avion, un hôtel ou un hôpital

Abrégé

An integrated circuit voltage regulator includes a transconductor first stage; and a negative impedance cancellation stage, where the negative impedance cancellation stage comprises cross-coupled transistors at outputs of said transconductor first stage, and resistors in the transconductor first stage and the negative impedance cancellation stage introduce zeros in a transfer function, compensating for parasitic poles. The resistors may compensate for parasitic capacitance inherent in transistors. Load transistors may be coupled to outputs of the transconductance first stage. The voltage regulator may be implemented in a Complementary Metal-Oxide-Semiconductor (CMOS) structure, which may be a system-on-chip integrated circuit. The voltage regulator may provide immunity to power supply noise. The negative impedance cancellation stage may include differential input transistors coupled to the cross-coupled transistors.

Classes IPC  ?

• G05F 1/63 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée est indifféremment du type alternatif ou continu utilisant des impédances variables en série avec la charge comme dispositifs de réglage final
• G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
• G05F 1/46 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu
• G05F 3/24 - Régulation de la tension ou du courant là où la tension ou le courant sont continus utilisant des dispositifs non commandés à caractéristiques non linéaires consistant en des dispositifs à semi-conducteurs en utilisant des combinaisons diode-transistor dans lesquelles les transistors sont uniquement du type à effet de champ

Abrégé

Methods and systems for reliable bootstrapping switches may comprise sampling a received signal with a bootstrapping switch, where the bootstrapping switch comprises a switching metal-oxide semiconductor (MOS) transistor having a pull-down path coupled to a gate terminal of the switching MOS transistor, wherein: source terminals of both a diode-connected transistor and a second MOS transistor are coupled to the gate terminal of the switching MOS transistor; drain terminals of both the diode-connected transistor and the second MOS transistor are coupled to a source terminal of a third MOS transistor, the third MOS transistor coupled in series with a fourth MOS transistor; and a drain terminal of the fourth MOS transistor is coupled to ground. The third and fourth MOS transistors may be in series with the second MOS transistor. A gate terminal of the fourth transistor may be switched from ground to a supply voltage to activate the pull-down path.

Classes IPC  ?

• H03K 17/16 - Modifications pour éliminer les tensions ou courants parasites
• H03K 17/06 - Modifications pour assurer un état complètement conducteur

Abrégé

Systems and methods are provided for powering Multimedia over Coax Alliance (MoCA) devices. An electronic device that is configured for use in a multimedia over coax alliance (MoCA) network may include a communication circuit operable to communicate multimedia over coax alliance (MoCA) based signals over coax cabling in the MoCA network, and one or more power circuits operable to support supplying and/or drawing power over the coax cabling in the MoCA network, to enable powering the electronic device and/or one or more other electronic devices in the MoCA network. The power circuits may include one or more of: a power regulator circuit that draws power from the coax cabling and/or regulates use of the power, a power source circuit that supplies power into the coax cabling, and a power management circuit that manages power related operations in the electronic device and/or in the MoCA network.

Classes IPC  ?

• H04B 3/00 - Systèmes à ligne de transmission
• H04B 3/54 - Systèmes de transmission par lignes de réseau de distribution d'énergie
• H04L 12/28 - Réseaux de données à commutation caractérisés par la configuration des liaisons, p.ex. réseaux locaux [LAN Local Area Networks] ou réseaux étendus [WAN Wide Area Networks]

Abrégé

The use of traffic flag symbols allows a large number of CPEs to transmit traffic notifications to a network controller. In some such embodiments, hundreds of CPEs simultaneously transmit traffic flags on different subcarriers of a channel. For example, in a MoCA2 based access network, up to 480 CPEs can transmit flags in only 5 μs in the 100 MHz-wide channel.

Classes IPC  ?

• H04L 12/911 - Contrôle d’admission au réseau et allocation de ressources, p.ex. allocation de bande passante ou renégociation en cours de communication
• H04L 12/833 - Marquage des paquets ou modification de la priorité des paquets en raison de congestion ou pour empêcher une congestion
• H04L 12/891 - Commande de flux sur liens ou flux agrégés

Abrégé

mem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.

Classes IPC  ?

• G11C 5/14 - Dispositions pour l'alimentation
• G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p.ex. compteurs de rafraîchissement défectueux
• G11C 29/04 - Détection ou localisation d'éléments d'emmagasinage défectueux

Abrégé

Aspects of a method and apparatus for communicating electronic service guide information in a satellite television system are provided. A satellite communication system may receive a signal via an interface to a satellite dish, and receive data from a network via a second interface (e.g., an interface to a LAN or a WAN, such as the Internet). The satellite communication system may be operable to channelize the received satellite signal into a plurality of channels, wherein a first channel of the plurality of channels carries electronic service guide (ESG) data. The satellite communication system may select which of the plurality of channels to input to a demodulator based, at least in part, on whether ESG data is available via the second interface. A second channel carrying media data may be input to the demodulator while the ESG data is available via the second interface.

Classes IPC  ?

• H04N 5/445 - Circuits de réception pour visualisation d'information additionnelle
• H04N 21/482 - Interface pour utilisateurs finaux pour la sélection de programmes
• H04N 21/61 - Structure physique de réseau; Traitement de signal
• H04N 21/462 - Gestion de contenu ou de données additionnelles, p.ex. création d'un guide de programmes électronique maître à partir de données reçues par Internet et d'une tête de réseau ou contrôle de la complexité d'un flux vidéo en dimensionnant la résolution o
• H04N 21/436 - Interfaçage d'un réseau de distribution local, p.ex. communication avec un autre STB ou à l'intérieur de la maison
• H04N 21/438 - Interfaçage de la voie descendante du réseau de transmission provenant d'un serveur, p.ex. récupération de paquets MPEG d'un réseau IP

Abrégé

Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.

Classes IPC  ?

• H03M 1/06 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques
• H03M 1/12 - Convertisseurs analogiques/numériques
• H03M 1/10 - Calibrage ou tests
• H03M 1/50 - Convertisseurs analogiques/numériques avec conversion intermédiaire en intervalle de temps
• H04W 56/00 - Dispositions de synchronisation

Abrégé

Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the multiple operating zones is characterized by more stringent performance criteria than the other operating zones. Thus, such data converters may receive an input signal and generate an output signal from the input signal per the transfer function and the more stringent performance criteria in the appropriate operating zone.

Classes IPC  ?

• H03M 1/00 - Conversion analogique/numérique; Conversion numérique/analogique
• H03M 1/36 - Valeur analogique comparée à des valeurs de référence uniquement simultanément, c. à d. du type parallèle
• H03M 1/74 - Conversion simultanée
• H04B 1/40 - Circuits

Abrégé

An automatic gain control loop disposed in a receiver is adapted to compensate for varying levels of out of band interference sources by adaptively controlling the gain distribution throughout the receive signal path. One or more intermediate received signal strength indicator (RSSI) detectors are used to determine a corresponding intermediate signal level. The output of each RSSI detector is coupled to an associated comparator that compares the intermediate RSSI value against a corresponding threshold. The take over point (TOP) for gain stages is adjusted based in part on the comparator output values. The TOP for each of a plurality of gain stages may be adjusted in discrete steps or continuously.

Classes IPC  ?

• H03G 3/20 - Commande automatique
• H03G 3/30 - Commande automatique dans des amplificateurs comportant des dispositifs semi-conducteurs
• H04B 1/16 - Circuits
• H04B 17/318 - Force du signal reçu

Abrégé

Methods and systems for efficient multi-polarization communications are presented. An array based communications system may comprises an antenna array operably connected to a first polarization path and a second polarization path. Each polarization path may comprise an analog frequency conversion circuit, a digital beamforming circuit, and a cross-polarization interference suppression circuit. To save power while communicating with one or more link partners, one or both of the first polarization path and the second polarization path may be selectively enabled or disabled in accordance with temperature, bandwidth, and/or power consumption requirements.

Classes IPC  ?

• H04B 15/00 - Suppression ou limitation du bruit ou des interférences
• H01Q 21/24 - Combinaisons d'unités d'antennes polarisées dans des directions différentes pour émettre ou recevoir des ondes polarisées circulairement ou elliptiquement ou des ondes polarisées linéairement dans n'importe quelle direction
• H01Q 1/38 - Forme structurale pour éléments rayonnants, p.ex. cône, spirale, parapluie formés par une couche conductrice sur un support isolant
• H01Q 3/24 - Dispositifs pour changer ou faire varier l'orientation ou la forme du diagramme de directivité des ondes rayonnées par une antenne ou un système d'antenne faisant varier l'orientation, par commutation de l'énergie fournie, d'un élément actif rayonnant à un autre, p.ex. pour commutation du lobe
• H01Q 3/40 - Dispositifs pour changer ou faire varier l'orientation ou la forme du diagramme de directivité des ondes rayonnées par une antenne ou un système d'antenne faisant varier la distribution de l’énergie à travers une ouverture rayonnante faisant varier la phase par des moyens électriques avec une matrice faisant varier l'angle de déphasage
• H01Q 13/02 - Cornets de guide d'onde
• H01Q 21/06 - Réseaux d'unités d'antennes, de même polarisation, excitées individuellement et espacées entre elles

Abrégé

Methods and systems for multi-path video and network channels may comprise a communication device comprising a wideband tuner (WB) and a narrowband tuner (NB). A video channel and a network channel may be received in the WB when the device is operating in a first stage. A video channel and a network channel may be received in the WB and the network channel may also be received in the NB when the device is operating in a second stage. The network channel may be received in the NB when the device is operating in a third stage. The reception of the network channel from both the WB and NB may enable a continuous reception of the network channel in a transition between the first and third stages. The WB may be operable to receive a plurality of channels and the NB may be operable to receive a single channel.

Classes IPC  ?

• G06F 3/00 - Dispositions d'entrée pour le transfert de données destinées à être traitées sous une forme maniable par le calculateur; Dispositions de sortie pour le transfert de données de l'unité de traitement à l'unité de sortie, p.ex. dispositions d'interface
• H03K 9/00 - Démodulation d'impulsions qui ont été modulées par un signal à variation continue
• H04N 21/426 - Structure de client; Structure de périphérique de client Éléments internes de client
• H04N 21/443 - Procédés de système d'exploitation, p.ex. démarrage d'un boîtier décodeur STB, implémentation d'une machine virtuelle Java dans un boîtier décodeur STB ou gestion d'énergie dans un boîtier décodeur STB
• H04N 21/61 - Structure physique de réseau; Traitement de signal
• H04N 21/438 - Interfaçage de la voie descendante du réseau de transmission provenant d'un serveur, p.ex. récupération de paquets MPEG d'un réseau IP

Abrégé

Methods and systems for improved matching for on-chip capacitors may comprise in a semiconductor die comprising an on-chip capacitor with one or more metal layers: electrically coupling a first set of metal fingers, electrically coupling a second set of metal fingers that are interdigitated with the first set of metal fingers, wherein the first set of metal fingers and the second set of metal fingers are arranged symmetrically in the semiconductor die, and configuring the on-chip capacitor in a plurality of symmetric sections, wherein a boundary between each of the plurality of sections is configured in a zig-zag pattern. The first set of metal fingers and the second set of metal fingers may be arranged with radial symmetry. A first set of metal fingers in a first metal layer may be electrically coupled to a set of metal fingers in a second metal layer.

Classes IPC  ?

• H01L 23/495 - Cadres conducteurs
• H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes

Abrégé

A network device comprising: a first connector for connecting to an external network from which data may be communicated using a first frequency band in accordance with a first communications protocol; a second connector for connecting to an on-premises network; and circuitry residing in a signal path between said first connector and said second connector. The circuitry may be operable to: permit a first portion of the first frequency band to pass from the first connector to the second connector; block a second portion of said first frequency band from passing from the first connector to the second connector; and communicate, via the second connector, signals that are normally communicated in frequency ranges not including the first frequency band, into the on-premises network using the first frequency band. The signals may include packets formatted in accordance with Multimedia over Coax Alliance (MoCA) standards.

Classes IPC  ?

• H04L 12/24 - Dispositions pour la maintenance ou la gestion
• H04L 12/46 - Interconnexion de réseaux
• H04L 12/28 - Réseaux de données à commutation caractérisés par la configuration des liaisons, p.ex. réseaux locaux [LAN Local Area Networks] ou réseaux étendus [WAN Wide Area Networks]
• H04L 12/26 - Dispositions de surveillance; Dispositions de test

Abrégé

An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

Classes IPC  ?

• H03M 1/00 - Conversion analogique/numérique; Conversion numérique/analogique
• H03M 1/06 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques

Abrégé

Methods and systems for frequency generation may comprise a circuit with a first input coupled to receive a first satellite signal at a first satellite downlink frequency, a second input coupled to receive a second satellite signal at a second satellite downlink frequency, and a first analog-to-digital converter (ADC) having an input coupled to receive the first satellite signal. The first ADC may be configured to create a first digital output signal representing the first satellite signal. A second ADC having an input coupled to receive the second satellite signal may be configured to create a second digital output representing the second satellite signal. The circuit may comprise a dielectric resonator oscillator having an output and a clock generator circuit having an input coupled to the oscillator output and configured to output one or more clocks used by the first and second ADCs.

Classes IPC  ?

• H03M 1/00 - Conversion analogique/numérique; Conversion numérique/analogique
• H03M 1/12 - Convertisseurs analogiques/numériques
• H03B 5/30 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique
• H03B 5/18 - Elément déterminant la fréquence comportant inductance et capacité réparties
• H04N 5/445 - Circuits de réception pour visualisation d'information additionnelle
• H04N 5/44 - Circuits de réception
• H04H 40/90 - Dispositions caractérisées par des circuits ou composants spécialement adaptés à la réception spécialement adaptés aux systèmes de radiodiffusion couverts par les groupes spécialement adaptés à la réception de la radiodiffusion par satellite

Abrégé

A first microwave backhaul transceiver may comprise a plurality of antenna elements. The transceiver may determine atmospheric conditions between it and one or more potential link partners, and adjust a radiation pattern of the plurality of antenna elements based on the determined atmospheric conditions. A first radiation pattern of the plurality of antenna elements may correspond to a first microwave backhaul link between the first microwave transceiver and a second microwave backhaul transceiver. A second radiation pattern of the plurality of antenna elements may correspond to a second microwave backhaul link between the first microwave transceiver and a third microwave backhaul transceiver. The transceiver may adjust the radiation pattern based on characteristics of data to be transmitted, and based on a routing table it maintains.

Classes IPC  ?

• H04B 1/40 - Circuits
• H04W 16/28 - Structures des cellules utilisant l'orientation du faisceau
• H01Q 3/40 - Dispositifs pour changer ou faire varier l'orientation ou la forme du diagramme de directivité des ondes rayonnées par une antenne ou un système d'antenne faisant varier la distribution de l’énergie à travers une ouverture rayonnante faisant varier la phase par des moyens électriques avec une matrice faisant varier l'angle de déphasage
• H04W 88/08 - Dispositifs formant point d'accès

Abrégé

An electronic receiver may generate a differential detection sequence based on a received symbol sequence and based on a m-symbol delayed version of the received symbol sequence, where m is an integer greater than 1. The particular differential detection sequence may be a result of an element-by-element multiplication of the particular received symbol sequence and the conjugate of an m-symbol delayed version of the particular received symbol sequence. The receiver may calculate differential decision metrics based on the differential detection sequence and based on a set of differential symbol sequences generated from the set of possible transmitted symbol sequences. The receiver may generate a decision as to which of a set of possible transmitted symbol sequences resulted in the received symbol sequence, where the decision is based on the differential decision metrics and the set of possible transmitted symbols sequences.

Classes IPC  ?

• H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p.ex. réseaux de mise en forme adaptatifs
• H04B 1/16 - Circuits

Abrégé

Systems and methods for converting analog signals to digital signals. A reference slice is associated with each of a plurality of active slices to balance the loading on an active sampling track and hold amplifier within each active slice. Alternatively, the reference slice is split into a portion having a reference ADC that is shared by a plurality of partial reference slices, each partial reference slice having a partial reference input module.

Classes IPC  ?

• H03M 1/06 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques
• H03M 1/38 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p.ex. du type à approximations successives
• H03M 1/12 - Convertisseurs analogiques/numériques

Abrégé

Methods and systems for charge compensation for switched-capacitor circuits may comprise, in an electronics device comprising a first voltage source, a switched capacitor load, and a switched capacitor compensation circuit: switching a capacitor in the switched capacitor load from a first voltage to a second voltage; providing a charge to the switched capacitor load from the switched capacitor compensation circuit without requiring added charge from the first voltage source. A reference voltage may be generated utilizing the first voltage source. A replica reference voltage for the switched capacitor compensation circuit may be generated utilizing a second voltage source. The replica reference voltage may be equal to the reference voltage. The replica reference voltage may be equal to a supply voltage, VDD, for circuitry in the electronics device. Capacitors may couple outputs of the first and second voltage sources to ground.

Classes IPC  ?

• H03M 1/06 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques
• H03H 19/00 - Réseaux utilisant des éléments différents en fonction du temps, p.ex. filtres à N voies
• H03M 1/12 - Convertisseurs analogiques/numériques
• H03M 1/66 - Convertisseurs numériques/analogiques

Abrégé

Systems and methods for communicating content between nodes of a network, wherein particular nodes of the network are members of a sub network. Flows can be admitted to a subnetwork, depending upon available bandwidth as allocated to the sub networks of the network. Each sub network has a unique password when privacy is enabled on the sub network.

Classes IPC  ?

• H04L 9/00 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité
• H04L 29/06 - Commande de la communication; Traitement de la communication caractérisés par un protocole
• H04L 12/64 - Systèmes de commutation hybrides
• H04L 12/28 - Réseaux de données à commutation caractérisés par la configuration des liaisons, p.ex. réseaux locaux [LAN Local Area Networks] ou réseaux étendus [WAN Wide Area Networks]
• H04L 29/08 - Procédure de commande de la transmission, p.ex. procédure de commande du niveau de la liaison

Abrégé

Aspects of a method and system for feedback during optical communications are provided. In one embodiment, a system for optical communications comprises a predistortion module, a feedback subsystem, a transmit optical subsystem, and an external modulator. The predistortion module is operable to receive an input digital signal and modify the input digital signal to produce a digital predistorted signal. The transmit optical subsystem is operable to generate an optical signal from the digital predistorted signal. The modification of the input digital signal is dynamically controlled by the feedback subsystem according to one or more characteristics of the optical signal as determined by the feedback subsystem. The amplitude of the external modulator output is also dynamically controlled by the feedback subsystem.

Classes IPC  ?

• H04B 10/04 - Emetteurs
• H04B 10/40 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs-récepteurs
• H04B 10/516 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs - Détails du codage ou de la modulation
• H04B 10/58 - Compensation pour sortie d’émetteur non linéaire
• H04B 10/69 - Dispositions électriques dans le récepteur
• H04B 10/2507 - Dispositions spécifiques à la transmission par fibres pour réduire ou éliminer la distorsion ou la dispersion
• H04B 10/079 - Dispositions pour la surveillance ou le test de systèmes de transmission; Dispositions pour la mesure des défauts de systèmes de transmission utilisant un signal en service utilisant des mesures du signal de données

Abrégé

A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. A sampled loop filter (SLPF) in the phase locked loop may capture charge from a charge pump (CHP) in the phase locked loop and the charge is captured at a frequency corresponding to the frequency of the reference clock signal. Opening a switch of the SLPF may hold the captured charge during a phase comparison and closing the switch may release the captured charge. The switch is controlled utilizing a control signal. By utilizing the SLPF in the phase locked loop, the phase locked loop may eliminate, at an output of the CHP, disturbance which is associated with duty cycle errors of the crystal clock signal.

Classes IPC  ?

• H03L 7/08 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase
• H03L 7/18 - Synthèse de fréquence indirecte, c. à d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle
• H03L 7/093 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
• H03L 7/085 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie
• H03L 7/089 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence engendrant des impulsions d'augmentation ou de diminution

Abrégé

A first network device may measure one or more values of one or more parameters corresponding to a plurality of links and/or devices of the network. The first network device may compare the measured one or more values of the one or more parameters to an expected one or more values of the one or more parameters. The first network device may determine whether to transmit data onto a network path between the first device and one of the plurality of devices based on a result of the comparison, wherein at least one of the plurality of links and/or devices are not part of the network path. The first network device may be operable to utilize the discovered parameter values to generate a security key which may be utilized to encrypt and/or scramble content prior to transmitting the content onto the network.

Classes IPC  ?

• H04L 9/00 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité
• H04K 1/10 - Communications secrètes en utilisant deux signaux transmis simultanément ou successivement
• H04L 29/06 - Commande de la communication; Traitement de la communication caractérisés par un protocole
• G06F 21/00 - Dispositions de sécurité pour protéger les calculateurs, leurs composants, les programmes ou les données contre une activité non autorisée
• G06F 21/10 - Protection de programmes ou contenus distribués, p.ex. vente ou concession de licence de matériel soumis à droit de reproduction
• H04L 9/18 - Chiffrement par modification sérielle et continue du flux d'éléments de données, p.ex. systèmes de codage en continu
• H04L 9/08 - Répartition de clés
• H04K 1/00 - Communications secrètes
• H04K 1/02 - Communications secrètes par addition d'un second signal pour rendre le signal désiré inintelligible

Abrégé

In an example implementation of this disclosure, a message passing low density parity check (LDPC) decoder may, during decoding of a first group of bits, lock a first variable node upon a bit-value probability of the first variable node reaching a determined threshold, and lock a first check node upon all variable nodes connected to the first check node being locked. The LDPC decoder may cease decoding the first group of bits upon all variable nodes of the LDPC decoder being locked, all check nodes of the LDPC decoder being locked, reaching a maximum number of iterations, or reaching a timeout. During a particular iteration of the decoding of the first group of bits in which the first variable node is locked, the LDPC decoder may refrain from generating a bit-value probability for the locked first variable node.

Classes IPC  ?

• H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
• H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
• H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue

Abrégé

In a first configuration, circuitry of a fiber node may be configured to modulate an optical carrier by an analog upstream electrical signal received via the electrical network. In a second configuration, the circuitry may be configured to digitize the analog upstream electrical signal to generate a digitized upstream signal, and modulate the optical carrier with the digitized upstream signal. An optical receiver of the fiber node may be configured to convert a downstream optical signal to a downstream electrical signal. In the first configuration, the downstream electrical signal may be a first analog signal and the circuitry may be configured to output the first analog signal into the electrical network. In a third configuration, the downstream electrical signal is a digitized waveform and the circuitry is configured to convert the digitized waveform to a second analog signal and output the second analog signal into the electrical network.

Classes IPC  ?

• H04B 10/25 - Dispositions spécifiques à la transmission par fibres
• H04B 10/40 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs-récepteurs
• H04B 10/50 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs
• H04B 10/60 - Récepteurs
• H04L 27/00 - Systèmes à porteuse modulée
• H04B 10/2581 - Transmission multimode
• H04B 10/2575 - Radio sur fibre, p.ex. signal radio modulé en fréquence sur une porteuse optique

Abrégé

An array based communications system may comprise a plurality of element processors. Each element processor may comprise a combining circuit, a crest factor circuit, and a phase shifter circuit. The combining circuit may produce a weighted sum of a plurality of digital datastreams. The crest factor circuit may be operable to determine whether the weighted sum has a power above or below a power threshold. If the power is above the power threshold, the crest factor circuit is operable to reduce the power. If the power is below the power threshold, the crest factor circuit is operable to increase the power. The phase shifter circuit may introduce a phase shift to out-of-band components of the weighted sum according to the power increase or the power decrease by the crest factor circuit.

Classes IPC  ?

• H01Q 1/24 - Supports; Moyens de montage par association structurale avec d'autres équipements ou objets avec appareil récepteur
• H01Q 1/38 - Forme structurale pour éléments rayonnants, p.ex. cône, spirale, parapluie formés par une couche conductrice sur un support isolant
• H01Q 13/02 - Cornets de guide d'onde
• H01Q 21/22 - Réseaux d'unités d'antennes, de même polarisation, excitées individuellement et espacées entre elles les unités d'antennes du réseau étant excitées d'une façon non uniforme en amplitude ou en phase, p.ex. réseau à prises ou réseau bidirectionnel

Abrégé

Aspects of methods and systems for transceiver array synchronization are provided. An array based communications system comprises a plurality of transceiver circuits and an array coordinator. Each transceiver circuit of the plurality of transceiver circuits comprises a plurality of wireless transmitters and a local oscillator generator. Each wireless transmitter of the plurality of wireless transmitters is able to modulate a local oscillator signal from the local oscillator generator based on a weighted sum of a plurality of digital datastreams. The array coordinator is able to adjust a phase of a first local oscillator signal based on a phase difference between the first local oscillator signal and a second local oscillator signal. The first local oscillator signal is generated by a first local oscillator generator of a first transceiver circuit. The second local oscillator signal is generated by a second local oscillator generator of a second transceiver circuit.

Classes IPC  ?

• H04B 1/04 - Circuits
• H04B 1/38 - TRANSMISSION - Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission Émetteurs-récepteurs, c. à d. dispositifs dans lesquels l'émetteur et le récepteur forment un ensemble structural et dans lesquels au moins une partie est utilisée pour des fonctions d'émission et de réception
• H04B 7/185 - Stations spatiales ou aériennes
• H04B 17/11 - Surveillance; Tests d’émetteurs pour l’étalonnage
• H04B 17/21 - Surveillance; Tests de récepteurs pour la correction des mesures
• H04B 17/18 - Surveillance en fonctionnement normal

Abrégé

Systems and methods are provided for band-limited digital pre-distortion (DPD) expansion estimation and curve adjustment. Pre-distortion adjustments may be applied during processing of an input signal, and expansion introduced as result of applying the pre-distortion adjustments may then be estimated. Expansion adjustments may then be determined based on the estimated expansion, and the expansion adjustments may be applied in a feedback manner during subsequent processing operations.

Classes IPC  ?

• H03F 1/32 - Modifications des amplificateurs pour réduire la distorsion non linéaire
• H03F 3/24 - Amplificateurs de puissance, p.ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
• H04B 1/04 - Circuits

Abrégé

Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.

Classes IPC  ?

• H03L 7/00 - Commande automatique de fréquence ou de phase; Synchronisation
• H03L 7/085 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie
• H03L 7/197 - Synthèse de fréquence indirecte, c. à d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle une différence de temps étant utilisée pour verrouiller la boucle, le compteur comptant entre des nombres variables dans le temps ou le diviseur de fréquence divisant par un facteur variable dans le temps, p.ex. pour obtenir une division de fréquence
• H03L 7/093 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
• H03L 7/099 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle

Abrégé

Methods and systems for a distributed transmission line multiplexer for a multi-core multi-mode voltage-controlled oscillator (VCO) may comprise a plurality of voltage controlled oscillators (VCOs) arranged adjacent to each other, where each of the plurality of VCOs are operable to generate an output signal at a configurable frequency, an impedance matching circuit comprising a respective driver and impedance matching elements coupled to each of the plurality of VCOs, and an output device coupled to the impedance matching circuit. The impedance matching elements may include capacitors and inductors. Between each adjacent pair of the respective drivers coupled to each of the plurality of VCOs, the impedance matching elements may include two inductors coupled in series between the drivers and a capacitor coupled to ground and to a common node between the two inductors. Impedance values of the capacitors and inductors may be configurable. The impedance matching elements may include a resistor coupled to a bias voltage VDD and to a common node with a capacitor that is coupled to ground, where the common node is coupled to one of the inductors. The output device may include a prescaler that is an integer or fractional frequency-N divider, or a buffer. The respective drivers coupled to each of the plurality of VCOs may be configured to provide a constant output power no matter which of said plurality of VCOs is enabled.

Classes IPC  ?

• H03B 5/12 - Eléments déterminant la fréquence comportant des inductances ou des capacités localisées l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
• H03H 11/30 - Adaptation automatique de l'impédance de source à l'impédance de charge
• H03B 1/00 - PRODUCTION D'OSCILLATIONS, DIRECTEMENT OU PAR CHANGEMENT DE FRÉQUENCE, À L'AIDE DE CIRCUITS UTILISANT DES ÉLÉMENTS ACTIFS QUI FONCTIONNENT D'UNE MANIÈRE NON COMMUTATIVE; PRODUCTION DE BRUIT PAR DE TELS CIRCUITS - Détails
• H03B 27/00 - Générateurs fournissant plusieurs oscillations de même fréquence, mais de phases différentes, autres qu'en simple opposition de phase
• H03B 5/00 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée
• H03B 25/00 - Production simultanée, au moyen d'un oscillateur non synchronisé, d'oscillations de fréquences différentes

Abrégé

A method, system and computer program for decompressing video data, storing the compressed video data in such a way that random access is possible and the data can be mapped efficiently into existing memory systems and interface protocols. The compression is accomplished via lossless compression using an algorithm optimized for video data. Due to the compressed format, data transmission consumes less bandwidth than using uncompressed data and prevents degradation in the decoded video.

Classes IPC  ?

• H04N 19/423 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques - caractérisés par les détails de mise en œuvre ou le matériel spécialement adapté à la compression ou à la décompression vidéo, p.ex. la mise en œuvre de logiciels spécialisés caractérisés par les dispositions des mémoires
• H04N 19/426 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques - caractérisés par les détails de mise en œuvre ou le matériel spécialement adapté à la compression ou à la décompression vidéo, p.ex. la mise en œuvre de logiciels spécialisés caractérisés par les dispositions des mémoires utilisant des procédés de diminution de taille de mémoire
• H04N 19/91 - Codage entropique, p.ex. codage à longueur variable ou codage arithmétique
• H04N 19/46 - Inclusion d’information supplémentaire dans le signal vidéo pendant le processus de compression
• H04N 19/48 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant des techniques de traitement dans le domaine compressé autres que le décodage, p.ex. modification de coefficients de transformées, de données de codage à longueur variable ou de données de codage par longueur de plage
• H04N 19/433 - Matériel spécialement adapté à l’estimation ou à la compensation de mouvement caractérisé par des techniques d’accès à la mémoire
• G06F 12/02 - Adressage ou affectation; Réadressage
• G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
• G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
• H04N 19/176 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c. à d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p.ex. un objet la zone étant un bloc, p.ex. un macrobloc

Abrégé

A first microwave backhaul assembly comprises a first antenna, a front-end circuit, an inter-backhaul-assembly interface circuit, and an interference cancellation circuit. The first antenna is operable to receive a first microwave signal. The front-end circuit is operable to convert the first microwave signal to a lower-frequency digital signal, wherein the lower-frequency digital signal has energy of a second microwave signal and energy of a third microwave signal. The inter-backhaul-assembly interface circuit is operable to receive information from a second microwave backhaul assembly. The interference cancellation circuit is operable to use the information received via the inter-backhaul-assembly interface circuit during processing of the lower-frequency digital signal to remove, from the first microwave signal, the energy of the third microwave signal. The information received via the inter-backhaul-assembly interface may comprise a signal having energy of the second microwave signal.

Classes IPC  ?

• H04B 1/10 - Dispositifs associés au récepteur pour limiter ou supprimer le bruit et les interférences
• H01Q 25/00 - Antennes ou systèmes d'antennes fournissant au moins deux diagrammes de rayonnement
• H01Q 19/18 - Combinaisons d'éléments actifs primaires d'antennes avec des dispositifs secondaires, p.ex. avec des dispositifs quasi optiques, pour donner à une antenne une caractéristique directionnelle désirée utilisant des surfaces réfléchissantes comportant plusieurs surfaces réfléchissantes
• H01Q 19/13 - Combinaisons d'éléments actifs primaires d'antennes avec des dispositifs secondaires, p.ex. avec des dispositifs quasi optiques, pour donner à une antenne une caractéristique directionnelle désirée utilisant des surfaces réfléchissantes où les surfaces sont concaves la source rayonnante primaire étant un élément rayonnant unique, p.ex. un dipôle, une fente, une terminaison de guide d'onde
• H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p.ex. réseaux de mise en forme adaptatifs
• H04B 1/12 - Montages de neutralisation, d'équilibrage ou de compensation

Abrégé

Methods and systems for a multi-core multi-mode voltage-controlled-oscillator (VCO) may comprise generating a plurality of oscillating signals utilizing a plurality of voltage controlled oscillators (VCOs) arranged symmetrically on an integrated circuit, where interconnects for the VCOs may be arranged in quiet zones at locations equidistant from each pair of the plurality of VCOs. An interconnection ring may be centered within the arranged VCOs that comprises at least two conductive lines that couple to output terminals of each of said plurality of VCOs. The plurality of VCOs may receive control signals from interconnects coupled to at least one conductive line in the interconnection ring. The plurality of VCOs may receive control signals from a conductive line in said interconnection ring. A positive terminal of a first VCO of a pair of adjacent VCOs of the plurality of VCOs may be coupled to a same conductive line of the interconnection ring as a negative terminal of a second of the pair of adjacent VCOs. The interconnection ring ay be circular. Impedances may couple the VCOs to the interconnection ring. Bias signals may be communicated to each of the plurality of VCOs from the interconnection ring. The plurality of VCOs may include four VCOs arranged equidistant from a center point.

Classes IPC  ?

• H03K 3/03 - Circuits astables
• H03B 5/20 - Elément déterminant la fréquence comportant résistance, et soit capacité, soit inductance, p.ex. oscillateur à glissement de phase
• H03L 7/23 - Synthèse de fréquence indirecte, c. à d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant plus d'une boucle avec des compteurs d'impulsions ou des diviseurs de fréquence
• H03B 27/00 - Générateurs fournissant plusieurs oscillations de même fréquence, mais de phases différentes, autres qu'en simple opposition de phase

Abrégé

Systems and methods for dynamically adjusting the gain in a receiver front end to have a desired amount of headroom, based upon a measurement of the signal to noise ratio (SNR) of the output of a digital to analog converter and the amount of degradation to the SNR due to previous adjustments to the gain.

Classes IPC  ?

• H04L 27/08 - Dispositions de régulation d'amplitude
• H04B 1/10 - Dispositifs associés au récepteur pour limiter ou supprimer le bruit et les interférences
• H03G 3/30 - Commande automatique dans des amplificateurs comportant des dispositifs semi-conducteurs
• H04B 17/336 - Rapport signal/interférence ou rapport porteuse/interférence
• H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission

Abrégé

Systems and methods are provided for detection and compensation of dielectric resonator oscillator frequency drift. DRO frequency drift detection and compensation may comprise, for a received input signal, detecting one or more channels in the input signal, determine frequency offset for each of the detected channels; determining determine dielectric resonator oscillator (DRO) frequency drift based on combining frequency offsets of the detected channels, and determining, based on the DRO frequency drift, one or more adjustments for compensating for the DRO frequency drift. The DRO frequency drift may be determined based on analysis of an intermediate signal generated during processing of the input signal.

Classes IPC  ?

• H03L 7/00 - Commande automatique de fréquence ou de phase; Synchronisation
• H03B 5/18 - Elément déterminant la fréquence comportant inductance et capacité réparties
• H03L 1/00 - Stabilisation du signal de sortie du générateur contre les variations de valeurs physiques, p.ex. de l'alimentation en énergie

Abrégé

Systems and methods for dynamically adjusting transmit gain in a transceiver. The gain is adjusted in order to provide the maximum gain. The amount of distortion is measured. The gain is increased until the distortion reaches a predetermined limit. The gain of several components can be adjusted independently.

Classes IPC  ?

• H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p.ex. réseaux de mise en forme adaptatifs
• H03G 3/30 - Commande automatique dans des amplificateurs comportant des dispositifs semi-conducteurs
• H03G 3/20 - Commande automatique
• H04L 27/36 - Circuits de modulation; Circuits émetteurs
• H04B 17/13 - Surveillance; Tests d’émetteurs pour l’étalonnage d’amplificateurs de puissance, p.ex. de gain ou de non-linéarité
• H04B 17/14 - Surveillance; Tests d’émetteurs pour l’étalonnage de l’ensemble voie d’émission/voie de réception, p.ex. bouclage d’autotest
• H03G 3/34 - Commande automatique dans des amplificateurs comportant des dispositifs semi-conducteurs rendant l'amplificateur muet en l'absence de signal
• H03F 3/19 - Amplificateurs à haute fréquence, p.ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs
• H03F 3/24 - Amplificateurs de puissance, p.ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie

Abrégé

Methods and systems are provided for enhanced digital-to-analog conversions. A segmentation-based digital-to-analog converter (DAC) may be configured for applying digital-to-analog conversions to N-bit inputs. The segmentation-based DAC may comprise a plurality of DAC elements, with each DAC element being operable to apply digital-to-analog conversion based on a single bit, and an encoder operable to generate an x-bit output. The number of DAC elements may be different than number of bits (N) in inputs to the DAC. One or more bits of the N-bit input may be applied to the encoder to generate the x-bit output, with each bit in the x-bit output being applied to a corresponding one of the plurality of DAC elements. Remaining one or more bits of the N-bit input, if any, may be applied directly to a corresponding one or more of the plurality of DAC elements.

Classes IPC  ?

• H03M 1/06 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques
• H03M 1/08 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques du bruit
• H03M 1/74 - Conversion simultanée
• H03M 1/66 - Convertisseurs numériques/analogiques

Abrégé

Systems and methods for provided for reducing interference caused by leakage of signals generated by a spread spectrum phase lock loop (SS PLL). Output of SS PLL may be processed to reduce interference. For example, a sinusoidal spreading signal may be used to spread the output of the SS PLL. A notch filter tracks the frequency of the output of the SS PLL to steer the notch in the filter to the instantaneous frequency output from the SS PLL, thus allowing the notch filter to be placed in the path of signals that have unwanted leakage from the SS PLL.

Classes IPC  ?

• H04B 1/00 - TRANSMISSION - Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission
• H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p.ex. en utilisant une boucle verrouillée en phase
• H04B 1/12 - Montages de neutralisation, d'équilibrage ou de compensation
• H04B 1/69 - Techniques d'étalement de spectre
• H04B 15/04 - Réduction des perturbations parasites dues aux appareils électriques avec des moyens disposés sur ou à proximité de la source de perturbation la perturbation étant causée par des ondes essentiellement sinusoïdales, p.ex. dans un récepteur ou un enregistreur à bande magnétique
• H03L 7/18 - Synthèse de fréquence indirecte, c. à d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle

Abrégé

Aspects of methods and systems for PAPR reduction in a microwave backhaul outdoor unit are provided.

Classes IPC  ?

• H04B 3/36 - Circuits de répéteur
• H04B 1/04 - Circuits

Abrégé

Systems and methods for controlling a power amplifier includes combining a digital modulated data signal with a digital bias signal to generate a combined digital signal, the digital bias signal generated based on an envelope for the modulated data signal; converting, by a digital-to-analog converter, the combined digital signal into a combined analog signal, the combined analog signal comprising an analog modulated data signal and an analog envelope bias signal; and separating the analog modulated data signal and the analog bias signal onto separate signal paths, wherein the converting is performed using a single digital-to-analog converter.

Classes IPC  ?

• H04B 1/04 - Circuits
• H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p.ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
• H03F 3/191 - Amplificateurs accordés
• H03G 3/00 - Commande de gain dans les amplificateurs ou les changeurs de fréquence
• H03F 1/32 - Modifications des amplificateurs pour réduire la distorsion non linéaire
• H03F 3/19 - Amplificateurs à haute fréquence, p.ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs
• H03F 3/21 - Amplificateurs de puissance, p.ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs
• H03H 21/00 - Réseaux adaptatifs
• H04B 1/00 - TRANSMISSION - Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission

Abrégé

A transmitter comprises a first peak-to-average-power ratio (PAPR) suppression circuit and a second peak-to-average-power ratio (PAPR) suppression circuit. The first PAPR suppression circuit may receive a first sequence of time-domain symbols to be transmitted, alter the first sequence based on each of a plurality of symbol ordering and/or inversion descriptors to generate a corresponding plurality of second sequences of time-domain symbols, measure a PAPR corresponding to each of the second sequences, select one of the plurality of symbol ordering and/or inversion descriptors based on the measurement of PAPR, and convey the selected one of the symbol ordering and/or inversion descriptors to the second PAPR suppression circuit. The second PAPR suppression circuit may receive the first sequence of time-domain symbols to be transmitted, and alter the first sequence based on the selected one of the symbol ordering and/or inversion descriptors to generate a reordered and/or inverted symbol sequence.

Classes IPC  ?

• H04L 27/26 - Systèmes utilisant des codes à fréquences multiples
• H04J 11/00 - Systèmes multiplex orthogonaux

Abrégé

Systems and methods for canceling cross-coupled satellite signals in a LNB IC include receiving a first satellite signal at a first pin of the LNB IC and adjusting the first satellite signal by applying a first adaptive filter to the first satellite signal signal, the first adaptive filter having first filter coefficients; combining the adjusted first satellite signal with a second satellite signal received at a second pin of the LNB IC to generate a first combined satellite signal; measuring the total output power of the combined satellite signal; changing the filter coefficients of the first adaptive filter; remeasuring the total output power of the first combined satellite signal after the changing of the first filter coefficients to determine whether the total power of the first combined satellite signal has decreased.

Classes IPC  ?

• H04B 7/185 - Stations spatiales ou aériennes
• H04B 1/10 - Dispositifs associés au récepteur pour limiter ou supprimer le bruit et les interférences
• H04H 40/90 - Dispositions caractérisées par des circuits ou composants spécialement adaptés à la réception spécialement adaptés aux systèmes de radiodiffusion couverts par les groupes spécialement adaptés à la réception de la radiodiffusion par satellite
• G01S 19/36 - Récepteurs - Détails de construction ou détails de matériel ou de logiciel de la chaîne de traitement des signaux concernant l'étage d'entrée du récepteur

Abrégé

A method and system for duty-cycled high speed clock and data recovery with forward error correction are provided. The system operates on a first digital signal comprising a first plurality of samples and a second digital signal comprising a second plurality of samples. The second plurality of samples may be a subset of the first plurality of samples, for example, if the first and second pluralities of samples are generated by one analog-to-digital converter. A clock and data recovery module is operable to produce a timing indication according the second digital signal. The second plurality of samples is sampled intermittently. The discontinuity between bursts of samples in the second signal corresponds to a duty cycle. A forward error correction module is operable to produce a digital error-corrected signal according to the first digital signal and the timing indication.

Classes IPC  ?

• H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
• H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
• H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue

Abrégé

Systems and methods are provided for receiver nonlinearity estimation and cancellation. During processing of received radio frequency (RF) signals, it may be determined when one or more other signals, different from the received RF signals, cause nonlinearity affecting processing of the RF signals, and one or more cancellation adjustments may be applied during processing of the RF signals, for mitigating effects of the nonlinearity. Determining the one or more cancellation adjustments may be based on narrowband (NB) estimation of the effects of the nonlinearity, and the one or more cancellation adjustments may be configured as wideband (WB) corrections. The NB estimation may be applied based on channelization of the received RF signals. The NB estimation may comprise generating reference nonlinearity information relating to the one or more other signals, and generating, based on the reference nonlinearity information, control data for configuring the one or more cancellation adjustments.

Classes IPC  ?

• H04B 1/12 - Montages de neutralisation, d'équilibrage ou de compensation
• H04B 1/04 - Circuits

Abrégé

Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.

Classes IPC  ?

• H03M 1/38 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p.ex. du type à approximations successives
• H03M 1/04 - Conversion analogique/numérique; Conversion numérique/analogique utilisant des techniques stochastiques
• H03M 1/44 - Comparaisons séquentielles dans des étages disposés en série avec changement de la valeur du signal analogique
• H03M 1/46 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p.ex. du type à approximations successives avec convertisseur numérique/analogique pour fournir des valeurs de référence au convertisseur
• H03M 1/00 - Conversion analogique/numérique; Conversion numérique/analogique

Abrégé

A network device may be operable to receive an indication from a cable modem termination system (CMTS) that media access control (MAC) management messages will be transmitted by the CMTS at fixed intervals. Subsequent to receiving the indication, the network device may be operable to power down one or more components of the network device and set a sleep timer to a value equal to an integer multiple of the fixed interval minus a transition period. The network device may power up the one or more components of the network device upon expiration of the sleep timer. The network device may power up the one or more components of the network device upon an amount of traffic in a buffer of the network device reaching a threshold.

Classes IPC  ?

• G06F 1/32 - Moyens destinés à économiser de l'énergie
• H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
• H04W 52/02 - Dispositions d'économie de puissance
• H04L 12/28 - Réseaux de données à commutation caractérisés par la configuration des liaisons, p.ex. réseaux locaux [LAN Local Area Networks] ou réseaux étendus [WAN Wide Area Networks]

Abrégé

Methods and systems are provided for noise suppression in data, particularly data comprising video and/or audio data. An input adjustment, based on a corresponding input adjustment value, may be applied to received input data that comprises video and/or audio data; and an output adjustment, based on a corresponding output adjustment value, may be applied to output data corresponding to previously processed received input data. The input adjustment value may be re-calculated based on an outcome of applying the input adjustment to the received data, and when a change occurs in the input adjustment value the change in the input adjustment value may be applied to subsequent received input data, and at the same time, and based on the change in the input adjustment value, a corresponding change may be applied at least some of data corresponding to previously processed received input data.

Classes IPC  ?

• H04N 5/21 - Circuits pour la suppression ou la diminution de perturbations, p.ex. moiré ou halo
• G06F 7/48 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés
• G06F 5/01 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour le décalage, p.ex. la justification, le changement d'échelle, la normalisation
• H04N 5/60 - Circuits de réception pour les signaux du canal son