A memory system is connectable to a host and includes a nonvolatile memory including a plurality of memory cells, a data buffer connected to the nonvolatile memory, and a memory controller configured to control the nonvolatile memory and including a tag recognition circuit. The tag recognition circuit is configured to recognize whether a storage state tag is assigned to first data in the data buffer, wherein the storage state tag indicates a mode of writing the first data in the memory cells.
According to one embodiment, a semiconductor memory device includes a housing and terminals. The housing has a first end edge extending in a first direction and a second end edge opposite to the first end edge. The terminals include signal terminals and include first terminals, second terminals, and third terminals. The first terminals are arranged in the first direction at a position close to the first end edge. The second terminals are arranged in the first direction with intervals at a position closer to the first end edge than the second end edge. The first plurality of terminals are closer to the first end edge than the second plurality of terminals are. The third terminals are arranged in the first direction with intervals at a position closer to the second end edge than the first end edge.
Systems, methods, non-transitory computer-readable media for creating isolation between multiple domains. One system includes a VD level disperser configured to segregate new write commands based on virtual device (VD) identifiers and maintain separate VD specific in-place linked lists. The system further includes a Quality of Service (QOS) level disperser configured to segregate VD specific commands of the VD specific in-place linked lists based on each of the VD specific commands respective QoS domain identifiers and maintain separate QoS domain specific linked lists. The system further includes a superblock level disperser configured to segregate QoS domain specific commands of the QoS domain specific in-place linked lists based on each of the QoS domain specific commands respective superblock or placement identifiers, maintain separate superblock-specific in-place linked lists for each superblock or placement identifier, and provide the superblock-specific in-place linked lists to a write divider.
A semiconductor integrated circuit includes first and second circuits, a smoothing circuit, and a control circuit. The first circuit is configured to generate a first current with a power supply voltage and output the first current to an output terminal. The second circuit is configured to divide the power supply voltage and output a second current corresponding to a divided voltage to the output terminal. The second current is greater than the first current. The control circuit is configured to, in response to an enable signal, turn on the second circuit for a first period of time, during which the controller causes the first and second currents to be supplied to the output terminal, and in response to elapse of the first period of time, turn off the second circuit and cause the first current, and not the second current, to be supplied to the output terminal.
Systems, methods, non-transitory computer-readable media for maintaining predictable latency among tenants. One system includes a die group segregator configured to segregate superblock IDs based on die group IDs. The system further includes a die group manager configured to identify superblocks of the superblock IDs in a first Quality of Service (QoS) domain of a first die group ID and select a first superblock in the first QoS domain based on weights of atomic data unit (ADUs) within each WLSTR. The system further includes a command processing system configured to schedule programming of the at least one WLSTR of the first QoS domain or a second QoS domain to program to a die group, wherein scheduling is based on a first QoS domain weight and a second QoS domain weight, segregate write commands into die units and provide the plural scheduled write commands to a die manager.
A semiconductor device of embodiments includes: a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode and including a first region, a second region, and a third region between the first region and the second region; a gate electrode facing the third region; a first insulating layer facing the first region; a second insulating layer facing the second region; and a gate insulating layer between the gate electrode and the oxide semiconductor layer, containing oxygen (O) and at least one metal element selected from a group consisting of Al, Hf, Zr, La, Y, Zn, In, Sn, and Ga, and having a chemical composition different from that of the oxide semiconductor layer.
According to one embodiment, an etching method includes forming a first film on the inner wall surface of the recess by supplying a precursor including silicon to the recess. The etching method includes oxidizing an upper region of the first film on the inner wall surface by an oxidation process, thereby forming an oxidized portion in the upper region. The etching method includes silylating the oxidized portion by supplying a silylating agent to the recess and etching the recess after supplying the silylating agent to increase the depth of the recess.
An electron microscope includes an electron beam irradiation unit, a subject holding unit that has a subject installation surface, and a second detection unit that detects an EBSD image. In addition, the electron microscope includes an SEM control unit that controls an operation of the subject holding unit, and an EBSD analysis unit that analyzes a crystal structure of a subject based on the EBSD image. The subject holding unit is rotatable around an axis parallel to a direction of irradiation with an electron beam, and is configured such that the subject installation surface is inclinable with respect to a plane perpendicular to the direction of irradiation with the electron beam. The EBSD analysis unit has an MAD value calculation unit that calculates a degree of similarity between the EBSD image and a reflector, and the SEM control unit controls a rotation operation or an inclination operation of the subject holding unit based on the degree of similarity.
G01N 23/203 - Recherche ou analyse des matériaux par l'utilisation de rayonnement [ondes ou particules], p.ex. rayons X ou neutrons, non couvertes par les groupes , ou en utilisant la réflexion de la radiation par les matériaux en mesurant la rétrodiffusion
G01N 23/20025 - Porte-échantillons ou leurs supports
G01N 23/2055 - Analyse des diagrammes de diffraction
G01N 33/204 - Leur structure, p.ex. structure cristalline
A semiconductor memory device includes conductive layers stacked in a stacking direction and extending in a first direction intersecting the stacking direction, semiconductor columns extending in the stacking direction and facing the conductive layers, charge storage films provided between the conductive layers and the semiconductor columns, first and second wirings provided on one side in the stacking direction with respect to the conductive layers, arranged in the first direction, and electrically connected to the semiconductor columns, sense amplifier units electrically connected to the first wirings, and a node electrically and commonly connected to the second wirings. One of the sense amplifier units is electrically connected to K1 number of first wirings (where K1 is an integer of 1 or more). The node is electrically connected to K number of second wirings (where K2 is an integer of 2 or more and is greater than K1).
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
10.
SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor storage device includes a first conductive layer. A stacked body includes a plurality of electrode films and a plurality of first insulating films alternately stacked in a first direction of the first conductive layer, in the first direction. A columnar body includes a semiconductor layer penetrating the stacked body in the first direction. A second insulating film is provided on an inner wall of a slit penetrating the stacked body in the first direction. Wiring is provided at an inside of the second insulating film in the slit, is electrically separated from the plurality of electrode films by the second insulating film, and is electrically connected to the first conductive layer. A third insulating film extends in a first surface intersecting the first direction in the first conductive layer. The third insulating film protrudes from the inner wall of the slit toward the wiring.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
A semiconductor device manufacturing method includes transferring a substrate including a structure that has a first surface at which indium is exposed, and a second surface at which a metal is exposed, to a chamber of a film forming device, supplying an indium reducing gas to the chamber at a first temperature at which indium is able to transition to a gaseous state, and supplying a film forming gas to the chamber at a second temperature higher than the first temperature to form a first film on the first surface and the second surface, after supplying the reducing gas.
A semiconductor memory device includes a sense amplifier provided between a memory cell array and an input/output circuit. The sense amplifier has a data latch circuit operating at a first operating voltage and having first and second nodes, a multiplexer operating at a second operating voltage, and a sense amplifier unit. The first node is connected to the multiplexer and latches a first voltage supplied from the multiplexer in accordance with data to be latched. The second node is connected to the sense amplifier unit and latches a second voltage having a voltage level that is inverted from that of the first voltage. A high-level of the first voltage latched in the first node is at a voltage level of the second operating voltage at a time the first voltage is supplied from the multiplexer and transitions to a voltage level of the first operating voltage thereafter.
A semiconductor memory device includes a memory cell array configured to store data, and a control circuit configured to control a write operation of writing data into the memory cell array. In the write operation, the control circuit is configured to receive first data and second data including a parity bit, generate a parity bit for the first data, check whether the parity bit and the parity bit match with each other, and write the first data into the memory cell array.
A memory system includes a nonvolatile memory; and a controller configured to (i) select one of a plurality of read retry processes having different average required times, respectively, based on reliability of a target area of the nonvolatile memory on which a read process is to be executed and (ii) execute the selected read retry process.
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p.ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
A semiconductor storage device includes a circuit board having a first surface and a second surface opposite to each other; an electronic component disposed on the first surface of the circuit board; a plurality of conductive members disposed on the second surface of the circuit board and electrically coupled to the circuit board, wherein the conductive members each include a conductive material; and an information display region provided on the second surface of the circuit board. The information display region has an information display pattern formed of a coating material or the conductive material of the conductive members.
H05K 5/00 - Enveloppes, coffrets ou tiroirs pour appareils électriques
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
16.
RANDOM NUMBER GENERATION CIRCUIT AND MEMORY SYSTEM
A memory circuit includes a plurality of storage areas each designated by one of a plurality of addresses. The control circuit stores a plurality of values, all of which are different from each other, in the plurality of storage areas, generates a first random number, obtains a first address that is one of the plurality of addresses using the first random number, reads a first value stored in a first storage area designated by the first address, and reads a second value stored in a second storage area designated by a second address. The second address is an address having the largest value among a range of addresses from which the first address can be obtained. The control circuit writes the second value into the first storage area after reading the first value therefrom. The control circuit outputs the first value as one value of an output random number.
A semiconductor device includes an insulating layer, an oxide semiconductor therein and extending in a first direction, a first electrode on an upper end of the semiconductor, a second electrode on a lower end thereof, and a gate electrode in the insulating layer and surrounding the oxide semiconductor. The semiconductor includes a first portion including the upper end, a second portion between the first portion and the lower end, and a first boundary portion between the first and second portions. An upper end of the first portion has a first diameter, a lower end of the first portion has a second diameter equal to or smaller than the first diameter, a lower end of the first boundary portion has a third diameter smaller than the second diameter, and a lower end of the second portion has a fourth diameter equal to or smaller than the third diameter.
A semiconductor storage device includes a stacked body including conductive layers and insulating layers alternately stacked; a first region extending in a first lateral direction and has a width in a second lateral direction; first pillars disposed in a second region on a first side of the first region, and each extending in the stacked body; second pillars disposed in a third region on a second side of the first region, and each extending in the stacked body; a plate-shaped portion disposed in the first region, extending in the first lateral direction, and dividing the stacked body in the second lateral direction; and a semiconductor layer disposed in the first region adjacent to the plate-shaped portion in the second lateral direction, wherein the semiconductor layer has an upper end portion around upper end portions of the first and second pillars, and a lower end portion above an uppermost conductive layer.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
A mass spectrometer includes a beam irradiator configured to emit an ion beam with pulses to irradiate a beam irradiation region along a surface of a sample; a laser irradiator configured to emit laser light with pulses to irradiate a laser irradiation region above the sample; a mass spectrometry unit configured to detects a mass of ion particles released from the sample by the ion beam and ionized by the laser light; and a controller. The controller is configured to: adjust a position of the laser irradiation region; and adjust the position of the laser irradiation region for each irradiation interval of the laser light.
A memory device includes a stacked body including electrode layers and insulating layers; columnar bodies extending through the stacked body; and a contact coupled to a first electrode layer and passing through one or more second electrode layers, the first electrode layer including a first surface and a second surface, the first surface disposed farther away from the second electrode layers than the second surface. The contact includes a first insulating film, a second insulating film, and a metal film. A first end portion of the first insulating film protrudes into the first electrode layer through the second surface. A second end portion of the second insulating film is in contact with a portion of the second surface. A distance t1 between the first end portion and the first surface is shorter than a distance t2 between the second end portion and the first surface.
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
H01L 23/528 - Configuration de la structure d'interconnexion
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
21.
SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY
A semiconductor memory includes a first stacked body, a first separation portion, a second stacked body, a third stacked body, and a bit line. The first stacked body is configured such that a plurality of first insulating films and a plurality of first conductive films are alternately stacked in a first direction. The first separation portion is adjacent to the first stacked body in a second direction intersecting the first direction. The second stacked body is adjacent to the first separation portion in the second direction. The second stacked body is configured such that a plurality of second insulating films and a plurality of second conductive films are alternately stacked in the first direction. The third stacked body is adjacent to the second stacked body in the second direction. The third stacked body is configured such that the plurality of second insulating films and a plurality of third insulating films are alternately stacked in the first direction. At least one layer of a third conductive film among the plurality of second conductive films has a first portion and a second portion. The second portion is located below the first portion in the first direction and is configured to protrude more into the third stacked body than the first portion in the second direction.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
22.
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
According to one embodiment, a method for manufacturing a semiconductor device includes: preparing a first substrate provided with a first film; forming a second film on or above a second substrate; forming a third film on or above the second film; forming a fourth film on or above the third film; forming a stacked body by bonding a main surface of the first film and a main surface of the fourth film; performing irradiation with a laser beam from a side of the second substrate of the stacked body; and separating the second substrate in a state of including at least portion of the second film. The second film and the fourth film each includes a first material. The third film includes a second material different from the first material. The second film and the third film have different composition. The fourth film and the third film have different composition.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
23.
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICE
A semiconductor device includes a first insulating layer; an oxide semiconductor formed in the first insulating layer, extending in a first direction, and having a first end and a second end; a first electrode including a first metal film that includes a first metal atom, and a first conductive film that is formed between the first metal film and the first end of the oxide semiconductor and includes metal oxide; a second electrode in contact with the second end of the oxide semiconductor; at least a pair of gate electrodes that face each other via an insulating film, and are interposed between the first end and the second end of the oxide semiconductor; and a first structure that is separated from the first electrode in a second direction intersecting the first direction, includes at least the first metal atom, and does not include the metal oxide.
A semiconductor device includes: a first electrode, a first insulating layer, a second insulating layer, and a second electrode arranged in a stacking direction; a gate electrode interposed between the first and second insulating layers in the stacking direction, and extending in a first direction; and a channel layer penetrating the gate electrode and coupled to the first electrode and the second electrode. The channel layer has a first cross-sectional area at a height position of the first insulating layer and a second cross-sectional area at a height position of the gate electrode, the first cross-sectional area is larger than the second cross-sectional area. The gate electrode has a wider width at a penetrating portion of the channel layer than any other portions in a second direction intersecting the stacking direction and the first direction.
A semiconductor storage device includes: a stacked body that has a plurality of conductive layers and a plurality of first insulating layers stacked alternately and includes a first region and a second region; one or more first pillars extending in a stacking direction of the stacked body within the first region of the stacked body; and a second pillar extending in the stacking direction within the second region of the stacked body, in which each of the first and second pillars include a semiconductor layer, a second insulating layer, a third insulating layer, and a fourth insulating layer interposed between the second and third insulating layers, the second insulating layer covers a sidewall of the semiconductor layer, the fourth insulating layer covers a sidewall of the second insulating layer and contains a different material from the second and third insulating layers, the third insulating layer covers a sidewall of the fourth insulating layer, an intersection of at least one of the plurality of conductive layers and the first pillar functions as a memory cell, and the third insulating layer of the second pillar is thicker than the third insulating layer of the first pillar in a plane perpendicular to the stacking direction.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
26.
PATTERN DESIGN METHOD AND TEMPLATE MANUFACTURING METHOD
An imprint method includes dividing an outer peripheral portion of a patterned surface including a device pattern into a plurality of regions along a circumferential direction. The imprint method includes disposing a dummy pattern in the outer peripheral portion, causing a pattern density of each of the plurality of regions to fall within a first range based on information regarding the device pattern.
G03F 7/00 - Production par voie photomécanique, p.ex. photolithographique, de surfaces texturées, p.ex. surfaces imprimées; Matériaux à cet effet, p.ex. comportant des photoréserves; Appareillages spécialement adaptés à cet effet
27.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a stack including a conductor layer and an insulator layer, a block insulating layer, a channel layer, a charge storage layer provided between the block insulating layer and the channel layer, and a tunnel layer provided between the charge storage layer and the channel layer, where the charge storage layer includes a first charge storage layer containing Si, N and at least one of Al, Mo, Nb, Hf, Zr, Ti, B, or P, a second charge storage layer containing Si and N, in which Si is contained at a second concentration higher than a first concentration that is a concentration of Si in the first charge storage layer, and provided between the first charge storage layer and the tunnel layer, and a dielectric layer containing at least one of silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or aluminum oxide (AlOx), and provided between the first charge storage layer and the second charge storage layer.
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
28.
SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STORAGE DEVICE
A semiconductor storage device includes a first stacked body in which first conductive layers and first insulating layers are alternately stacked in a stacking direction, a second stacked body above the first stacked body and in which second conductive layers and second insulating layers are alternately stacked in the stacking direction, a contact that extends in the first and second stacked bodies in the stacking direction and is connected to a first conductive layer. The contact has a first portion that extends in the first stacked body and is connected at a lower end portion thereof to the first conductive layer, a second portion that extends in the second stacked body and is connected to an upper end portion of the first portion, the second portion having a cross-section at a lower end portion thereof that is smaller than a cross-section at the upper end portion of the first portion.
H01L 23/528 - Configuration de la structure d'interconnexion
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
29.
STORAGE DEVICE AND METHOD OF MANUFACTURING A STORAGE DEVICE
A storage device includes a memory cell that includes a variable resistance storage element and a switching element connected in series thereto and stacked therewith in a first direction, the switching element including a first electrode, a second electrode that includes a first part formed of a first material to which a first element is added, and a switching material layer that is between the first electrode and the first part of the second electrode and formed of a first insulating material to which the first element is added. The storage device further includes a first insulating layer that surrounds the switching material layer and formed of the first insulating material to which the first element is not added. An outer periphery of the first part of the second electrode and an outer periphery of the switching material layer are aligned in the first direction.
H10N 70/00 - Dispositifs à l’état solide sans barrière de potentiel ni de surface, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p.ex. dispositifs RAM résistifs [ReRAM]
A semiconductor device includes a first semiconductor layer, a plurality of first transistors provided on the first semiconductor layer, an insulating layer provided on the first semiconductor layer and covering the plurality of first transistors, a second semiconductor layer provided in the insulating layer, a plurality of second transistors provided on the second semiconductor layer, and a separation layer that extends through the second semiconductor layer between the plurality of second transistors to separate the plurality of second transistors from each other.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
H10B 41/20 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
H10B 41/41 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique de régions de mémoire comprenant un transistor de sélection de cellules, p.ex. NON-ET
A semiconductor memory device includes a stacked body in which conductive layers are stacked with an insulating layer interposed therebetween, a semiconductor film to provide a channel for a plurality of memory cell transistors having gates electrically connected to the conductive layers of the stacked body, respectively, an insulating film extending in the stacking direction between the conductive layers and the semiconductor film, and a control circuit configured to control a program voltage to be applied to a conductive layer electrically connected to a memory cell transistor that is a target of a write operation, and a transfer voltage to be applied to conductive layers electrically connected to other memory cell transistors that are not the target of the write operation, wherein the control circuit is configured to vary the transfer voltage to be applied depending on a number of bits that are being written in the write operation.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 16/10 - Circuits de programmation ou d'entrée de données
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
According to one embodiment, there is provided a magnetic memory device including a first conductive layer; and a first magnetoresistive effect element and a second magnetoresistive effect element that each extends in a first direction, are provided apart from each other in a second direction crossing the first direction, and are each in contact with the first conductive layer, wherein the first conductive layer includes a first portion that does not overlap with any of the first magnetoresistive effect element and the second magnetoresistive effect element when viewed in the first direction, a second portion that overlaps with a central region of the first magnetoresistive effect element when viewed in the first direction, and a third portion that overlaps with an edge region of the first magnetoresistive effect element when viewed in the first direction.
A plurality of memory cell regions includes a semiconductor layer extending in a first direction and a pillar having a side surface in contact with the semiconductor layer and extending in a second direction. A first conductor includes a first portion extending in the first direction and a plurality of second portions extending in a third direction and connected to the first portion. One of the second portions is in contact with the semiconductor layer. Each of a plurality of contact regions includes a plurality of contacts extending in the second direction. A plurality of groups is arranged in the first direction when viewed in the second direction, each of the groups including one of the plurality of memory cell regions, one of the plurality of second portions, and one of the plurality of contact regions, which are arranged in the first direction when viewed in the second direction.
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
A semiconductor storage device according to an embodiment includes a first chip with memory cells, and a second chip that controls operations performed on the memory cells. The first chip includes a stacked body including a plurality of conductive layers stacked in a first direction, a plurality of pillar structures, a plurality of partitions extending within the stacked body in the first direction and a second direction intersecting the first direction, a pad portion, and a connection structure that electrically connects the pad portion and a circuit provided in the second chip, and includes a plate-shaped part extending in the first direction and one of the second direction and a third direction intersecting the first and second directions.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
A semiconductor memory device includes a first conductive film, a semiconductor layer on the first conductive film, a stacked body having a plurality of conductive layers insulated from each other and stacked above the semiconductor layer in a stacking direction, a semiconductor film extending through the stacked body and the first conductive film in the stacking direction, an insulating film extending in the stacking direction between the plurality of conductive layers in the stacked body and the semiconductor film, and a second conductive film containing carbon, that is in direct contact with the first conductive film and with one end or a side surface of the semiconductor film.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
36.
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A manufacturing method of a semiconductor device, includes mounting on a first substrate a plurality of second substrates at a predetermined interval, the first substrate including a wiring layer, each of the second substrates including a plurality of semiconductor cells separated from each other by a boundary portion, forming a first recess on the first substrate between two of the second substrates that are adjacent to each other, cutting each of the second substrates along the boundary portion thereof to form a gap and a second recess on the first substrate through the gap, forming a sealing member on the first substrate, and cutting the first substrate together with the sealing member along lines extending along and inside the first and second recesses to individualize the semiconductor cells.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/544 - Marques appliquées sur le dispositif semi-conducteur, p.ex. marques de repérage, schémas de test
A memory device includes first and second strings including transistors, a first wiring connected to the first string, a second wiring connected to the second string, a third wiring connected to both strings, and a circuit for executing a write operation on a first transistor of the first string and a second transistor of the second string. The operation includes a first operation by which a first voltage is applied to the wirings and a second operation by which a second voltage is applied to gates of the first and second transistors. When a current flows between the first and third wirings but does not flow between the second and third wirings in the first operation, the circuit causes a third voltage to be applied to the first wiring, and causes a fourth voltage higher than the third voltage to be applied to the second wiring in the second operation.
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
According to one embodiment, in a semiconductor memory device including a first chip and a second chip. The first chip includes a first stacked body, a first semiconductor film, a second stacked body, a second semiconductor film, a contact plug and a first planar wiring line. The contact plug extends in the third direction between the first stacked body and the second stacked body. The first planar wiring line is disposed on a side opposite to the second chip with respect to the first stacked body, the contact plug, and the second stacked body, the first planar wiring line extending in the first direction and the second direction, covering at least the contact plug, and being connected to the contact plug.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
According to an embodiment, there is provided a management method for a manufacturing line. The management method includes obtaining a fluctuation characteristic including at least one of an arrival fluctuation characteristic of a lot to a process area, a capability fluctuation characteristic of the process area, or a stay fluctuation characteristic of the lot in the process area in a manufacturing line in which multiple process areas including the process area are arranged, the multiple process areas each including multiple resources. The management method includes obtaining inventory information regarding an inventory to be provided in the process area depending on the fluctuation characteristic.
A memory device according to an embodiment includes a substrate, first conductive layers, an insulating layer, pillars, and contacts. The first conductive layers are provided above the substrate. The insulating layer is provided above the first conductive layers. The pillars have portions facing the first conductive layers functioning as memory cells. The contacts are connected to the first conductive layers, respectively. Each of the first conductive layers has, between itself and the substrate, a terrace portion not overlapping with another first conductive layer. Each of the contacts penetrates the insulating layer and is, in a bottom portion thereof, connected to the terrace portion of one first conductive layer among the first conductive layers.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
According to one embodiment, a device includes: a memory cell coupled to a bit line and configured to store first data including first, second, and third bits; and a sense amplification circuit configured to perform a first comparison between a bit line voltage and a first reference voltage, and a second comparison between the bit line voltage and a second reference voltage lower than the first reference voltage, and to read the first data from the memory cell based on results of the first and second comparisons. The sense amplification circuit is configured to retain second data having a first code in response to the bit line voltage becoming equal to or lower than the first reference voltage during a first period from a start of operation to a first time point, and retain the first data after the first period.
According to one embodiment, a magnetic memory device includes a lower structure, a bottom electrode provided on the lower structure and formed of a conductive material, a top electrode provided above the bottom electrode, a magnetoresistance effect element provided between the bottom electrode and the top electrode, and an oxide insulating layer including a first portion provided on a side surface of the bottom electrode and a second portion provided on a side surface of the magnetoresistance effect element, and formed of an oxide of the conductive material.
According to one embodiment, a controller, when a first possible storage period corresponding to a first data portion among one or more data portions is equal to or more than a first threshold in one or more possible storage periods, writes the first data portion to one or more second blocks different from one or more first blocks and invalidate the first data portion stored in the one or more first block. When the first possible storage period is less than the first threshold and a period for which the first data portion is stored in the one or more first blocks has reached the first possible storage period, invalidates the first data portion stored in the one or more first blocks.
A semiconductor device of embodiments includes: a first electrode; a second electrode; an oxide semiconductor layer between the electrodes; a gate electrode surrounding the oxide semiconductor layer; a gate insulating layer between the gate electrode and the oxide semiconductor layer and spaced from the first electrode; a first insulating layer between the first electrode and the gate electrode, the gate insulating layer between the first insulating layer and the oxide semiconductor layer; and an intermediate layer between the first electrode and the first insulating layer, including a first region and a second region between the first region and the first insulating layer. The first region contains a first metal element and oxygen, the second region contains a second metal element, and an oxygen concentration in the second region is lower than that in the first region.
A semiconductor device manufacturing method of embodiments includes: forming an insulating film on an outer peripheral portion of a surface of a first substrate; after forming the insulating film, forming a silicon layer in contact with the surface inside the insulating film; and forming a porous silicon layer by making the silicon layer inside the insulating film porous using an anodization method.
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/20 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.
H03K 19/0175 - Dispositions pour le couplage; Dispositions pour l'interface
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
47.
MEMORY CONTROLLER, MEMORY SYSTEM, AND MEMORY CONTROL METHOD
According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.
H03M 13/35 - Protection inégale ou adaptative contre les erreurs, p.ex. en fournissant un niveau différent de protection selon le poids de l'information d'origine ou en adaptant le codage selon le changement des caractéristiques de la voie de transmission
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G11B 20/18 - Détection ou correction d'erreurs; Tests
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 29/04 - Détection ou localisation d'éléments d'emmagasinage défectueux
G11C 29/52 - Protection du contenu des mémoires; Détection d'erreurs dans le contenu des mémoires
H03M 13/29 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes combinant plusieurs codes ou structures de codes, p.ex. codes de produits, codes de produits généralisés, codes concaténés, codes interne et externe
According to one embodiment, a semiconductor memory device includes a nonvolatile memory cell, a detection circuit which detects a first voltage and selects one of a first mode and a second mode based on the first voltage, and a transmitting unit which outputs a first signal corresponding to the one of the first mode and the second mode. The detection circuit selects the first mode when the first voltage is equal to or greater than a determination value, and selects the second mode when the first voltage is less than the determination value. The transmitting unit outputs the first signal of a first amplitude in the first mode, and outputs the first signal of a second amplitude that is smaller than the first amplitude in the second mode.
A device includes a first region including first semiconductor pillars extending through first conductive layers; a second region including second semiconductor pillars extending through second conductive layers; and a third region disposed between the first region and the second region and including insulator columns extending through third conductive layers. The third region includes a fourth region and a fifth region. In the fourth region, one third conductive layer electrically connects one first conductive layer and one second conductive layer to each other, and in the fifth region, one third conductive layer is connected to a contact plug. A first diameter of a first subset of the insulator columns provided in the fourth region is smaller than a second diameter of a second subset of the insulator columns provided in the fifth region.
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
A semiconductor storage device according to an embodiment includes: a stacked body in which a plurality of conductive layers are stacked via an insulating layer and which has a memory region in which a plurality of memory cells are disposed and a staircase region in which end portions of the plurality of conductive layers form a staircase shape. A first region of the staircase region includes a first sub-staircase portion ascending in a first direction toward the memory portion, and a second sub-staircase portion disposed side by side with the first sub-staircase portion in a second direction opposite to the first direction from the first sub-staircase portion and ascending in the second direction.
H10B 99/00 - Matière non prévue dans les autres groupes de la présente sous-classe
H01L 21/308 - Traitement chimique ou électrique, p.ex. gravure électrolytique en utilisant des masques
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H10B 41/20 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
According to one embodiment, a anodization apparatus includes: a first process tank used for an anodization process on a first portion of a substrate; a second process tank provided inside of the first process tank and used for the anodization process on a second portion of the substrate; a first electrolyte supply unit configured to supply a first electrolyte to the first process tank; a second electrolyte supply unit configured to supply a second electrolyte to the second process tank; a retainer configured to retain the substrate; a first electrode provided above the first process tank and/or the second process tank; and a second electrode provided below the first process tank and the second process tank.
According to one embodiment, a memory system includes semiconductor storage devices and a controller device. Each semiconductor storage device includes: first and second signal pads through which command data and address data for instructing one of the semiconductor storage devices to perform a read operation are transmitted; and a status register. A controller device is configured to instruct the one of the semiconductor storage devices to provide a status of the read operation. The one of the semiconductor storage devices is configured to, upon receiving the instruction to provide the status of the read operation, output a ready/busy state stored in the status register through the first signal pad while allowing an input of another command data and another address data through the second signal pad.
According to one embodiment, a memory system includes a nonvolatile memory that includes memory cells. The nonvolatile memory outputs, to a memory controller, first hard bit data of the first bit, second hard bit data of the second bit, third hard bit data of the third bit, and fourth soft bit data related to the first bit, the second bit, and the third bit, in response to a first command set. The nonvolatile memory outputs, to the memory controller, the first hard bit data, the second hard bit data, the third hard bit data, first soft bit data related to the first bit, second soft bit data related to the second bit, and third soft bit data related to the third bit, in response to a second command set.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
54.
SEMICONDUCTOR MANUFACTURING DEVICE, AND SEPARATING MEMBER
A semiconductor manufacturing device includes a substrate supporting unit configured to place a bonded substrate including two substrates bonded to each other; an arm portion disposed next to the substrate supporting unit and configured to move toward and from a bonded portion of the bonded substrate; and a separating member provided on an end of the arm portion and configured to separate the two substrates by the arm portion entering the bonded portion, wherein the separating member includes a first inclined face and a second inclined face that extend toward the bonded portion and are respectively extended from end portions of first and second faces of the separating member. The separating member further includes an aperture portion configured to discharge a fluid toward the bonded portion.
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 21/687 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension en utilisant des moyens mécaniques, p.ex. mandrins, pièces de serrage, pinces
55.
HYDROPHOBIC TREATMENT DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A hydrophobic treatment device includes a placing table configured to place a substrate; a lid facing the placing table; a first supply port provided in the lid, and configured to discharge a hydrophobic gas with respect to the substrate; a second supply port provided in the lid, and configured to discharge an inert gas with respect to an outer periphery of the substrate; and a first adjustment mechanism configured to adjust a position of the second supply port with respect to the substrate by moving the lid in a radial direction of the substrate.
A semiconductor storage device includes first and second chips. The first chip includes a semiconductor substrate having first and second surfaces intersecting a first direction, and a plurality of transistors provided on the first surface of the semiconductor substrate. The plurality of transistors include first and second transistors adjacent to each other in a second direction intersecting the first direction. The semiconductor substrate includes a first insulating member provided between the first transistor and the second transistor and extending in the first direction from the first surface of the semiconductor substrate to a first position between the first surface and the second surface of the semiconductor substrate, and a second insulating member provided at a position overlapping the first insulating member when viewed in the first direction and extending in the first direction from the second surface of the semiconductor substrate to the first position of the semiconductor substrate.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
A storage device includes a first electrode, a second electrode, a first dielectric layer between the first and second electrodes and including oxygen and at least one of hafnium and zirconium, a second dielectric layer between the first electrode and the first dielectric layer, and an intermediate region between the first and second dielectric layers and in which a plurality of metallic portions are provided.
H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
A memory device includes memory cells for each of layers arranged in a first direction, the memory cells of each layer including groups of memory cells, the memory cells of each group being arranged in a second direction intersecting the first direction, the groups being arranged in a third direction intersecting the first and second directions, first wirings arranged in the third direction in each layer and respectively connected to the groups in each layer, first transistors each connected to a corresponding first wiring, second wirings each connected to the first transistors of a corresponding layer, third wirings each extending in the first direction and connected to a memory cell in each layer, and fourth wirings each extending in the first direction and connected to a gate of a corresponding first transistor in each layer.
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A controller of a memory system executes a first operation on storage regions. The first operation includes (i) acquiring first data based on comparison between a determination voltage and a threshold voltage of each memory cell in a first storage region; (ii) calculating a first fail-bit count of the first data; and (iii) executing or skipping a second operation based on the calculated first fail-bit count. The second operation includes (i) acquiring the second data based on comparison between the determination voltage and the threshold voltage of each memory cell in the first storage region; (ii) calculating a second fail-bit count of the second data; and (iii) updating the determination voltage based on the second fail-bit count.
A memory system includes a non-volatile memory with a plurality of pages; and a memory controller configured to write a plurality of data portions into the non-volatile memory, wherein the data portions are specified based on a plurality of write commands received from a host, respectively. The host assigns same setting information to the plurality of write commands. The memory controller is configured to write the plurality of data portions to a plurality of pages, respectively, wherein the plurality of pages correspond to a plurality of continuous addresses among the plurality of pages based on the same setting information.
A memory system includes a nonvolatile memory including a plurality of memory cells, and a controller. The controller is configured to perform a read operation to determine a value of multi-bit data stored in each of the memory cells by using a first plurality of read voltages, and perform an estimation of optimum values of the read voltages. The estimation is performed by applying a second plurality of read voltages to the memory cells and obtaining a first string of bit counts. The estimation is performed further by obtaining a second string of differential bit counts, each of which indicates a difference between adjacent bit counts in the first string of bit counts, extracting a part of the differential bit counts from the second string, and estimating the optimum values of the read voltages using the extracted differential bit counts.
A memory system includes a nonvolatile memory and a controller. The controller is configured to generate an encryption key using health data indicating a deterioration state of the nonvolatile memory and time data, encrypt data with the generated encryption key, and write the encrypted data into the nonvolatile memory. The health data may include a total size of data that has been written into the nonvolatile memory or a total size of data that has been read from the nonvolatile memory.
A semiconductor memory device having first and second physical planes each including a plurality of physical blocks of memory cells, includes a first register in which a first address is to be stored, a second register in which a second address associated with the first address is to be stored, a third register in which third addresses are to be stored, and an address registration unit including a first circuit configured to compare the first address stored in the first register with the third addresses and store the first address in the second register as the second address if the first address does not match any of the third addresses, and a second circuit configured to convert the first address into another address that is stored in the second register as the second address when the first address matches one of the third addresses.
G06F 11/16 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel
G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
A semiconductor device includes a first pad to which a high voltage is to be input, a second pad to which a low voltage is to be input, a third pad to which a ground voltage is to be input, and a protection circuit provided between the first pad and the third pad. The protection circuit includes a first protection element group including a plurality of first transistors arranged in a first direction, a second protection element group including a plurality of second transistors arranged in the first direction and disposed apart from the first protection element group in a second direction orthogonal to the first direction, a guard ring provided around the first and second protection element groups, and an intermediate guard ring provided between the first protection element group and the second protection element group and connected to the third pad via a resistance element.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
65.
COOLING METHOD, ELECTRONIC DEVICE MANUFACTURING METHOD, AND COOLING DEVICE
A cooling method includes placing a container having thermal conductivity in a cooling tank configured to accommodate liquid refrigerant, accommodating an electronic device to be cooled in the container, and immersion cooling the container using the liquid refrigerant in a state where the electronic device remains separate from the liquid refrigerant.
A receiver circuit includes an equalizer configured to process a received signal; a first offset circuit configured to apply a first offset voltage to the processed signal, the first offset voltage having a first polarity; a second offset circuit configured to apply a second offset voltage to the processed signal, the second offset voltage having a second polarity opposite to the first polarity; a first amplification circuit configured to amplify a first output signal provided by the first offset circuit; a second amplification circuit configured to amplify a second output signal provided by the second offset circuit; and a third amplification circuit configured to amplify the processed signal.
A semiconductor storage device includes: a first semiconductor layer; a second semiconductor layer disposed over the first semiconductor layer; a third semiconductor layer disposed over the second semiconductor layer; a stacked body disposed over the first to third semiconductor layers; a pillar penetrating through the stacked body and including a fourth semiconductor layer having a side surface in contact with the second semiconductor layer; and a dividing structure penetrating through the stacked body to reach the first semiconductor layer and separating the stacked body. The dividing structure includes a first portion and a second portion above the first portion, the first portion having a lower portion in contact with the first semiconductor layer and an upper portion located above an upper surface of the second semiconductor layer. A width of the upper portion of the first portion is greater than a width of the lower portion of the first portion.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
A semiconductor storage device includes a multiple multilayer films multiple insulating films that each penetrate the multilayer films, multiple memory pillars provided between the insulating films and that respective penetrate a multilayer film, multiple columnar portions with respective cross-sectional areas larger than that of respective memory pillars at certain surfaces.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
An imprint method forms a pattern by pressing a template including a pattern surface having an uneven portion against an imprinting region of a photocurable imprint material provided on a substrate. The imprint method includes preparing a template having an adjacent light transmission restricting film on a pattern surface, preparing the substrate including the imprint material, and pressing the pattern surface against the imprint material and irradiating the imprint material with light. In irradiating the imprint material with light, the imprint material in the imprinting region and the imprint material raised at an end edge of the pattern surface adjacent to the imprinting region are exposed, the imprint material in the imprinting region is cured and the imprint material is cured while maintaining a height and a shape of the imprint material that is raised at the adjacent position.
G03F 7/00 - Production par voie photomécanique, p.ex. photolithographique, de surfaces texturées, p.ex. surfaces imprimées; Matériaux à cet effet, p.ex. comportant des photoréserves; Appareillages spécialement adaptés à cet effet
A storage device includes a memory cell array, an input/output circuit, and a logic circuit. The input/output circuit including an input/output signal line through which data to be written into the memory cell array is received and data read from the memory cell array is transmitted. The logic circuit is configured to output a first signal to the input/output circuit. The first signal at an active level enables at least a part of the input/output circuit. The logic circuit includes a latch circuit configured to output a second signal at a level corresponding to a value of latched data. The logic circuit receives third, fourth, and fifth signals from an outside of the storage device via the input/output circuit. The logic circuit outputs a negative logical product of the third signal and a logical sum of at least the second, fourth, and fifth signals as the first signal.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p.ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
71.
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE
A semiconductor device includes a first electrode, an oxide semiconductor layer electrically connected to the first electrode and disposed above the first electrode, a gate electrode facing the oxide semiconductor layer with an insulating film interposed therebetween, and a second electrode including a first conductive layer electrically connected to the oxide semiconductor layer and disposed above the oxide semiconductor layer, the first conductive layer containing oxygen, indium, and tin. The second electrode further includes a second conductive layer in contact with the first conductive layer and containing oxygen and a first metal and a third conductive layer in contact with the second conductive layer and containing the first metal.
A memory device includes a memory cell array including a block including a first transistor connected to a first select gate line, a second transistor connected to a second select gate line, and a plurality of memory cells connected in series between the first and second transistors and each connected to one corresponding word line of a plurality of word lines, and a row control circuit that outputs a control signal for setting the block to be in a selected state or an unselected state based on a result of decoding an address, stores information indicating whether the block is a non-defective block, and controls an electrical state of the second select gate line independently of the first select gate line based on the control signal and the information.
According to one embodiment, there is provided a storage device comprising a first memory chip that includes a plurality of first memory cells and that includes a first circuit configured to perform address conversion by using a conversion function; and a second circuit that is connected to the first memory chip and that is configured to set a first parameter for the first memory chip, wherein when a first address is transmitted to the first memory chip from the second circuit, the first address is converted into a second address by the conversion function using the first parameter, and then one of the plurality of first memory cells that corresponds to the second address in the first memory chip is accessed.
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
G11C 29/12 - Dispositions intégrées pour les tests, p.ex. auto-test intégré [BIST]
A semiconductor memory device includes a stacked body including a plurality of conductive layers stacked in a first direction, a pillar structure array including a plurality of pillar structures each extending in the first direction in the stacked body and arranged in a second direction and a third direction, the plurality of pillar structures including a plurality of first pillar structures, each of which is a part of a string of memory cell transistors, a first plate-shaped structure extending in the first and second directions in the stacked body, a second plate-shaped structure extending in the first and third directions in the stacked body and disposed along an end portion of the pillar structure array in the second direction, and a support structure extending in the first direction in the stacked body and disposed where the first plate-shaped structure and the second plate-shaped structure intersect.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
A semiconductor memory device includes a stacked body in which conductive layers and insulating layers are alternately stacked in a first direction, a columnar body in the stacked body and extending in the first direction, and a source line layer. The columnar body includes a core insulating layer, a semiconductor layer surrounding the core insulating layer, and a memory layer surrounding the semiconductor layer. A portion of the source line layer extends in the first direction to be provided in the stacked body, has a side surface in contact with the semiconductor layer and an end face in contact with the core insulating layer, and includes a pointed portion on the end face at an interface of the portion, the core insulating layer, and the semiconductor layer, wherein the end face and the side surface of the semiconductor layer form an acute angle at the pointed portion.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
76.
PATTERN DESIGN METHOD, TEMPLATE MANUFACTURING METHOD, AND PATTERN DESIGN APPARATUS
A pattern design method according to an embodiment is a method to design a pattern of a template used for an imprint process. The imprint process serves to form a predetermined pattern by pressing a shot surface of the template against a surface of a processed layer. The method includes setting an outer edge coverage range corresponding to an outer edge region located a predetermined distance inside an edge of the shot surface of the template. The outer edge coverage range is set to be different from an inner coverage range corresponding to an inner region inside the outer edge region. The method includes designing a pattern in the outer edge region to have a coverage falling within the outer edge coverage range. The method includes designing a pattern in the inner region to have a coverage falling within the inner coverage range.
B41C 1/10 - Préparation de la forme ou du cliché pour l'impression lithographique; Feuilles-mère pour le report d'une image sur la forme
G03F 7/00 - Production par voie photomécanique, p.ex. photolithographique, de surfaces texturées, p.ex. surfaces imprimées; Matériaux à cet effet, p.ex. comportant des photoréserves; Appareillages spécialement adaptés à cet effet
G06F 30/392 - Conception de plans ou d’agencements, p.ex. partitionnement ou positionnement
77.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
The semiconductor device includes a substrate, an oxide semiconductor layer spaced from the substrate in a first direction intersecting with a surface of the substrate, a first wiring opposed to a part of the oxide semiconductor layer, a gate insulating film disposed between the oxide semiconductor layer and the first wiring, a second wiring electrically connected to one end in the first direction of the oxide semiconductor layer, and a first insulating layer disposed on a surface on one side and a surface on the other side in a second direction intersecting with the first direction of the second wiring. The second wiring contains a first metallic element, and the first insulating layer contains the first metallic element and oxygen (O).
A magnetic memory device according to an embodiment includes a magnetic memory device includes first and second interconnect, a memory cell, a transistor, first and second sense amplifiers, and a control circuit. The memory cell includes a magnetoresistive effect element and a selector element. The magnetoresistive effect element and the selector element are coupled in series between the first and second interconnect. In a read operation, the control circuit is further configured to: charge the first interconnect to a first voltage; and discharge the first interconnect via the transistor by applying a second voltage to a gate end of the transistor.
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
According to one embodiment, a semiconductor memory device includes a memory cell including a transistor, an interconnect, and a first circuit. The first circuit performs an erase operation including an erase voltage applying operation of applying an erase voltage between a gate of the transistor and a channel of the transistor via the interconnect, and an erase verify operation of determining a threshold voltage of the memory cell. The first circuit performs a first suspension processing of suspending the erase operation upon receiving a first command during the erase operation. The first circuit performs the erase voltage applying operation or the erase verify operation at the time of resuming the erase operation suspended by the first suspension processing, based on a voltage value of the interconnect at the time of receiving the first command.
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/16 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p.ex. des réseaux, des mots, des groupes
80.
INSPECTION METHOD, INSPECTION PROGRAM, DATA CREATION METHOD, AND STORAGE MEDIUM
According to one embodiment, there is provided an inspection method. The method includes: extracting a skeleton in a plurality of patterns using data including the plurality of patterns; and inspecting whether a pattern width of the plurality of patterns or an inter-pattern distance between the plurality of patterns, satisfies a criterion based on the extracted skeleton.
According to one embodiment, a receiver device includes: a plurality of converters each configured to sample a digital value from an analog signal, each digital value being sampled at different timing; and a digital signal processor configured to calibrate offsets of the digital values. The plurality of converters include a first converter and a second converter. The digital signal processor is configured to: calibrate a first offset caused in the first converter and a second offset caused in the second converter, in a first operation using a first analog signal; and calibrate a third offset that is caused commonly in the first converter for which the first offset is calibrated and the second converter for which the second offset is calibrated, in a second operation using a second analog signal.
According to one embodiment, a memory device includes, a memory cell array including first to fourth sub-arrays, a first bit line coupled to the first sub-array and the second sub-array, a second bit line arranged side by side with the first bit line in a first direction and coupled to the third sub-array and the fourth sub-array, a third bit line arranged at a position different from the first bit line in a second direction and coupled to at least the second sub-array and the third sub-array, a fourth bit line arranged side by side with the third bit line in the first direction and coupled to the fourth sub-array, a first circuit electrically coupled to the first bit line and the second bit line, and a second circuit electrically coupled to the third bit line and the fourth bit line.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H01L 23/482 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
83.
COMMUNICATION SYSTEM, COMMUNICATION DEVICE AND COMMUNICATION METHOD
According to one embodiment, a communication system includes a host controller, communication devices, and a communication path which couples the host controller and the communication devices in a ring shape and configured to transfer a communication frame. The communication frame includes containers. Each of the communication devices includes a first circuit configured to insert and extract first data into and from at least one of the containers, a bus connected to the first circuit, and a second circuit coupled to the bus and configured to transmit and receive second data corresponding to the first data to and from the first circuit. The first data has a first data length which is a fixed length, and the second data has a second data length which is a unit of transfer of the second data and which is a variable length.
A semiconductor memory device comprises: a substrate; a first wiring layer; a second wiring layer provided between the substrate and the first wiring layer; and a memory cell array layer provided between the substrate and the second wiring layer. The memory cell array layer comprises a contact extending in a first direction intersecting with a surface of the substrate. The first wiring layer has a second conductive layer that includes a connecting portion, a pad electrode portion, and a peripheral edge portion. The connecting portion is connected to one end in the first direction of the contact. The second wiring layer has: a first opening which is provided in a region including the connecting portion and the pad electrode portion of the second conductive layer; and a ring-shaped first slit which surrounds the peripheral edge portion of the second conductive layer.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
A memory system includes a memory and a memory controller. The memory controller includes an encoder including a first encoder configured to generate a first codeword from a plurality of first data sections. The first codeword includes a first error correction code parity for correcting errors in number based on a rank in the plurality of first data sections and the first codeword. The first codeword includes a plurality of first bit strings respectively associated with a plurality of columns. The first bit strings each include a plurality of bits respectively associated with a plurality of rows. The memory controller is configured to write the plurality of first bit strings into the plurality of magnetic bodies, respectively, such that the magnetic body in which one of the first bit strings is written is different.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
According to one embodiment, a memory system includes a first memory region, a second memory region, and a controller. The controller is configured to control coupling between the first memory region and the second memory region at one end and a host device at another, generate first interleave setting information corresponding to the first memory region, select the first memory region based on the first interleave setting information when an access request is received from the host device, and update the first interleave setting information to second interleave setting information corresponding to the second memory region and not corresponding to the first memory region based on an amount of accumulated wear in the first memory region.
A semiconductor memory device includes memory layers arranged in a first direction and a via-wiring extending in the first direction. The plurality of memory layers each include a semiconductor layer electrically connected to the via-wiring, a gate electrode opposed to surfaces of the semiconductor layer in the first direction, a memory portion disposed on one side in a second direction with respect to the semiconductor layer, a wiring disposed on the other side in the second direction with respect to the semiconductor layer, and a connection wiring connected to the gate electrode and the wiring. The connection wiring includes a first part extending in the second direction along a side surface of the gate electrode in the third direction and a second part continuous with the first part, extending in the third direction along a side surface of the wiring in the second direction.
According to one embodiment, a memory device includes a first wiring line extending along a first direction, a second wiring line provided on an upper layer side of the first wiring line and extending along a second direction intersecting the first direction, and a memory cell provided between the first wiring line and the second wiring line, and including a magnetoresistance effect element, a switching element, a middle electrode provided between the magnetoresistance effect element and the switching element, and a resistive layer provided between the magnetoresistance effect element and the second wiring line. A resistance of the resistive layer is higher than a resistance of the middle electrode.
According to one embodiment, a semiconductor memory includes a first chip including a substrate and a second chip bonded to the first chip. The second chip includes a first region including the memory cell array and the first shield line, and a second region including a second shield line. The first shield line is provided between the first chip and a memory cell array. The second shield line is provided in a same layer as the first shield line, and is not electrically coupled to the first shield line.
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/16 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p.ex. des réseaux, des mots, des groupes
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
G06F 12/02 - Adressage ou affectation; Réadressage
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
According to one embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of blocks. The controller is electrically coupled to the nonvolatile memory. The controller controls the nonvolatile memory. When receiving, from the host, a first command for changing a state of an allocated block to a reallocatable state in a case where a second command that is yet to be executed or being executed involving read of data from the allocated block has been received from the host, the controller changes the state of the allocated block to the reallocatable state after the second command is finished.
Disclosed herein are related to a system and a method for adjusting a read voltage threshold to read data from a plurality of memory dies of a nonvolatile memory device. Each of the plurality of memory dies comprises a plurality of blocks. A controller in communication with the plurality of memory dies may read, from a first block of the plurality of blocks, data corresponding to a read command received from a host. The controller may determine a bit error rate for the first block based on the data. The controller may update the read voltage threshold for the first block when the bit error rate for the first block exceeds a first error threshold. The read voltage threshold may be stored in the controller.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
Various implementations described herein relate to systems and methods for placing data on a Solid State Drive (SSD), including writing data to a non-volatile memory storage of the SSD, determining one or more of read errors, a number of invalid pages per block, or a read disturb counter for the data, determining access frequency of the data based on the one or more of the read errors, the number of invalid pages per block, or the read disturb counter, and partitioning the non-volatile memory storage into a plurality of regions based on the access frequency.
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
According to one embodiment, a magnetic memory device includes a memory cell. The memory cell includes a switching element, a magnetoresistance effect element, and an electrode that electrically couples the switching element to the magnetoresistance effect element. The electrode includes: a first non-magnetic layer being in contact with the switching element; and a second non-magnetic layer provided on a side opposite to a side on which the switching element is provided with respect to the first non-magnetic layer. The second non-magnetic layer has an amorphous structure and contains a metal oxide or a metal nitride.
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
A memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller is configured to: after transmitting a write command and an address to the nonvolatile memory via a first signal line, transmit dummy data to the nonvolatile memory via the first signal line during at least a portion of a period that is between when the address is transmitted via the first signal line and when write data of the write command is transmitted via the first signal line, and after transmitting the dummy data via the first signal line, transmit a data strobe signal to the nonvolatile memory via a second signal line and transmit the write data of the write command to the nonvolatile memory via the first signal line in synchronization with the data strobe signal.
A memory system includes a nonvolatile memory including a memory cell, and a controller. The controller is configured to write multi-bit data into the memory cell through a first write operation of writing a first part, and not a second part, of the multi-bit data and then a second write operation of writing the first and second parts. The controller is configured to, during writing of the multi-bit data, determine an amount of time that has passed since the first write operation, perform the second write operation in a first manner by inputting the second part, and not the first part, from the controller, when the determined amount is less than a threshold amount, and perform the second write operation in a second manner by inputting the first and second parts from the controller, when the determined amount is greater than the threshold amount.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
97.
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes: a stacked body including conductive layers and insulating layers alternately stacked on top of one another in a vertical direction; a first pillar including a semiconductor layer extending within the stacked body; and a separation layer penetrating through an uppermost one of the conductive layers, or the uppermost conductive layer and an another conductive layer coupled to the uppermost conductive layer in the vertical direction, extending within the stacked body in a first direction that intersects the vertical direction, and separating one or more conductive layers including the uppermost conductive layer in a second direction that intersects the vertical direction and the first direction. The separation layer includes at least a portion extending into the stacked body that is overlapped with the first pillar in the vertical direction, and having a lower end in contact with an upper surface of the first pillar.
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
A memory system includes a plurality of memory chips, a memory, and a controller. The memory chips are capable of operating in parallel. The memory includes a physical channel region and a plurality of virtual channel regions, each corresponding to one of a plurality of processes executed on the memory chips according to the requests. The controller stores the requests issued from the host in the physical channel region in order of acquisition from the host, and an entry for each of the requests in one of the virtual channel regions. When a required degree of parallelism of the processes is less than a threshold, the controller selects a next request to be executed using the physical channel region. When the required degree of parallelism is greater than or equal to the threshold, the controller selects a next request to be executed using one of the virtual channel regions.
A semiconductor manufacturing apparatus includes a bevel processing chamber, a stage on which a first surface of a substrate is to be placed, a first gas supply pipe configured to supply first gas to a first surface side of the substrate, a first ring surrounding the stage and having an outer diameter smaller than a diameter of the substrate, a top plate facing a second surface of the substrate, a second gas supply pipe configured to supply second gas to a second surface side of the substrate, a second ring surrounding the top plate and having an outer diameter smaller than the diameter of the substrate, a first electrode surrounding the first ring, a second electrode surrounding the second ring, a third gas supply pipe configured to supply process gas, and a control circuit that controls plasma processing of a bevel of the substrate using the process gas.
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
H01J 37/32 - Tubes à décharge en atmosphère gazeuse
H01L 21/306 - Traitement chimique ou électrique, p.ex. gravure électrolytique
H01L 21/3065 - Gravure par plasma; Gravure au moyen d'ions réactifs
100.
POLISHING APPARATUS, POLISHING METHOD, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A polishing apparatus according to the present embodiment includes a head, a polishing table, a rotation table, a particle supplier, and one chamber. The head holds an object. The polishing table polishes a polishing target surface of the polishing target object. The rotation table is capable of contacting the polishing target surface. The particle supplier supplies slurry containing particles onto the rotation table so that the particles are fixed onto at least part of the polishing target surface, while the polishing target surface is contacting the rotation table. The one chamber houses the polishing table and the rotation table.
B24B 57/02 - Dispositifs pour l'alimentation, l'application, le triage ou la récupération de produits de meulage, polissage ou rodage pour l'alimentation en produits de meulage, polissage ou rodage à l'état fluide, vaporisés, pulvérisés ou liquéfiés
B24B 7/04 - Machines ou dispositifs pour meuler les surfaces planes des pièces, y compris ceux pour le polissage des surfaces planes en verre; Accessoires à cet effet comportant une table porte-pièce rotative
B24B 41/00 - MACHINES, DISPOSITIFS OU PROCÉDÉS POUR MEULER OU POUR POLIR; DRESSAGE OU REMISE EN ÉTAT DES SURFACES ABRASIVES; ALIMENTATION DES MACHINES EN MATÉRIAUX DE MEULAGE, DE POLISSAGE OU DE RODAGE Éléments constitutifs des machines ou dispositifs à meuler, tels que bâtis, bancs, chariots ou poupées
B24B 49/14 - Appareillage de mesure ou de calibrage pour la commande du mouvement d'avance de l'outil de meulage ou de la pièce à meuler; Agencements de l'appareillage d'indication ou de mesure, p.ex. pour indiquer le début de l'opération de meulage tenant compte de la température pendant le meulage
brevets
