[Problem] To provide a semiconductor manufacturing device which can easily form a pad on a contact plug and a method for manufacturing the semiconductor manufacturing device. [Solution] A semiconductor storage device according to this embodiment comprises a first chip including a transistor and a second chip including a memory cell array. The second chip is provided with a first surface which is bonded to the first chip and a second surface on the opposite side from the first surface. A contact extends between the first surface and the second surface and is provided apart from the memory cell array. A first wiring layer is provided above a first end on the second surface side of the contact and is electrically connected to the contact. A first conductive layer is provided between the first end of the contact and the first wiring layer.
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
According to an embodiment, a semiconductor memory device includes: a first chip including a first memory cell and a second memory cell; a second chip including a third memory cell and a fourth memory cell; and a third chip including a row decoder. In a first program operation of the first memory cell, the row decoder applies a first program voltage to a first word line. In a first program operation of the second memory cell, the row decoder applies a second program voltage higher than the first program voltage to the first word line. In a first program operation of the third memory cell, the row decoder applies a third program voltage to the first word line. In a first program operation of the fourth memory cell, the row decoder applies a fourth program voltage higher than the third program voltage to the first word line.
A semiconductor wafer transport container according to one embodiment comprises a plastic container for accommodating a semiconductor wafer. The vicinity of the surface of the plastic at least at an inner surface of the plastic container is impregnated with an aluminum oxide having a hydroxyl group. A structure in which 1 at% or more of the aluminum oxide is dispersed in the plastic, in terms of the concentration of elemental aluminum, is present at least at a depth within a range of 50 nm to 10 μm inclusive from the inner surface.
H01L 21/673 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants utilisant des supports spécialement adaptés
A semiconductor memory device according to an embodiment of the present invention includes: a first chip including a first pillar having a first memory cell and a second memory cell connected in series; a second chip including a second pillar having a third memory cell and a fourth memory cell connected in series; and a third chip including a row decoder to which each of a first word line connected to a gate of the first memory cell, a second word line connected to a gate of the third memory cell, and a third word line connected to gates of the second memory cell and the fourth memory cell are connected.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
A semiconductor memory device according to an embodiment of the present invention comprises a substrate, first wirings, second wirings, channel portions, first charge accumulation portions, and second charge accumulation portions. The first wirings extend in a first direction, and the second wirings are adjacent to the first wirings in a second direction crossing the first direction, and extend in the first direction. The channel portions are provided between the first wirings and the second wirings, and extend in a third direction crossing the first direction and the second direction. The first charge accumulation portions are provided between the first wirings and the channel portions. The second charge accumulation portions are provided between the second wirings and the channel portions. The first charge accumulation portions adjacent to one another in the third direction are provided to form first gaps therebetween. The second charge accumulation portions adjacent to one another in the third direction are provided to form second gaps therebetween. A first impurity diffusion region and a second impurity diffusion region, in which impurity elements are diffused, are provided in the channel portions between adjacent first charge accumulation portions and between adjacent second charge accumulation portions.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
A semiconductor circuit according to an embodiment includes transistors PM10 to PM12, NM10, and NM11, and a constant current source CS10. The transistor PM10 is connected between nodes VDD and ND10, and a gate end is connected to the node ND 10 through a resistor R10. The transistor PM11 is connected between the nodes VDD and ND11, and a gate end is connected to the node ND10. The node ND11 is connected to an output node OUT. The transistor NM10 is connected between the nodes ND10 and ND12, and a gate end is connected to an input node IN. The transistor NM11 is connected between the nodes ND11 and ND12, and a gate end is connected to an input node /IN. One end and the other end of the constant current source CS10 are connected between the nodes ND12 and VSS. The transistor PM12 is connected between the node VDD and the input node /IN, and a gate end is connected to the gate end of the transistor PM10.
According to an embodiment of the present invention, a semiconductor device comprises a first cell including a first PMOS transistor, a second PMOS transistor arranged side by side with the first PMOS transistor, a first NMOS transistor, a second NMOS transistor arranged side by side with the first NMOS transistor, and a seventh wire electrically connected to none of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor.
H01L 21/82 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
In the present invention, a first string includes a first memory cell transistor, one end of the first string being connected to a first wire, the other end being connected to a second wire. A second string includes a second memory cell transistor, one end of the second string being connected to the first wire, the other end being connected to the second wire. A first power supply line is connected to the gate of the first memory cell transistor via a first transistor and is connected to the gate of the second memory cell transistor via a second transistor. A third string includes a third memory cell transistor, one end of the third string being connected to the first wire, the other end being connected to the second wire. A second power supply line is connected to the gate of the third memory cell transistor and applies a voltage different from that of the first power supply line during data erase.
A semiconductor device according to an embodiment includes: an operational amplifier that has a first input terminal, a second input terminal, and an output terminal, and that outputs a first voltage from the output terminal; a first resistor that has one end connected to the first input terminal, and an other end connected to the output terminal; a plurality of second resistors, each of which has one end connected to the first input terminal and that is serially connected; a plurality of switches, each of which has one end connected to a first node between two adjacent resistors of the plurality of second resistors, and another end connected to a second node, and receives digital code; and a current source circuit that is connected between the second node and a third node. One switch of the plurality of switches turns on, on the basis of the digital code, and the current source circuit applies a first current from part or all of the plurality of second resistors to the third node, via the one switch in the on state.
G11C 7/04 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les effets perturbateurs thermiques
H03M 1/78 - Conversion simultanée utilisant un réseau en échelle
10.
SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR STORAGE DEVICE
A semiconductor storage device according to one embodiment of the present invention has a substrate, a transistor, a layered body, a columnar body, and a source line. The transistor is provided on the substrate. In the layered body, a plurality of gate electrode layers and a plurality of insulation layers are layered alternately one by one in a first direction. The columnar body includes an insulating core, a channel layer, and a memory film. The source line is positioned between the layered body and the substrate, and extends at least in a second direction intersecting the first direction. The columnar body has a first end contacting the source line, and a second end on the opposite side from the first end in the first direction. The width of the first end in the second direction is greater than the width of the second end in the second direction.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
This memory system comprises a non-volatile memory and a controller. The non-volatile memory includes a plurality of storage regions capable of storing user data. The controller acquires first information relating to the number of program/erase cycles with respect to at least one storage region among the plurality of storage regions. The controller performs a data erasure operation with respect to the plurality of storage regions in response to acquisition of the first information. In response to the data erasure operation being completed, the controller acquires second information relating to the number of program/erase cycles with respect to at least one of the storage regions. The controller generates an erasure certificate including the first information and the second information.
Provided are a convenient memory system, a control method therefor, and an information processing device. A memory system 100 according to an embodiment comprises: a non-volatile memory 2 that has memory cells capable of storing user data using a plurality of different storage methods; and a memory controller 1 that controls the non-volatile memory 2. The non-volatile memory 2 is characterized by comprising a firmware storage region 211 for storing firmware and a user data storage region 213 for storing user data, wherein the firmware storage region 211 stores firmware FW1, FW2 corresponding to respective storage methods, and the memory controller 1 controls the setting of the non-volatile memory 2 using firmware corresponding to an externally indicated storage method.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
13.
SUBSTRATE UNIT, MEMORY SYSTEM, AND ELECTRONIC DEVICE
A substrate unit according to an embodiment comprises: a substrate; an electronic component mounted on the substrate; and a joining part that joins together the substrate and the electronic component. The substrate has a first surface facing the electronic component; a hole provided to the first surface; and a first conducting section provided to the first surface and/or to an inner surface of the hole. The electronic component has a first terminal that includes an extension section that extends in a second direction intersecting with a first direction which is the thickness direction of the substrate, at least a portion of the extension section being inserted in the hole. The joining part is conductive and is provided between the first conducting section and the extension section.
[Problem] The purpose of the present invention is to provide a semiconductor device in which warping of a semiconductor package is suppressed. [Solution] A semiconductor device according to the present embodiment comprises a substrate having a first surface and a second surface that is on the reverse side from the first surface. A semiconductor chip is provided to the first surface of the substrate. A first resin layer is provided to the first surface so as to cover the substrate and the semiconductor chip. A first protective layer is provided to the second surface. A first frame layer is provided to the second-surface side along the outer periphery of the substrate, the first frame layer being configured from a first material that has a higher glass transition temperature and a lower thermal expansion coefficient than the first resin layer and being thicker than the substrate.
Provided is a treatment method whereby it becomes possible to treat a mixture containing one or both of a halosilane compound and a hydrolysate of a halosilane compound in a safe manner. According to an embodiment, a treatment method for treating a mixture containing one or both of a halosilane compound and a hydrolysate of a halosilane compound is provided. A treating solution having a pH value of 8 to 14 inclusive in a mass corresponding to 100 times the mass of the mixture or more is brought into contact with the mixture.
C23C 16/44 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c. à d. procédés de dépôt chimique en phase vapeur (CVD) caractérisé par le procédé de revêtement
H01L 21/205 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale en utilisant la réduction ou la décomposition d'un composé gazeux donnant un condensat solide, c. à d. un dépôt chimique
According to an embodiment of the present invention, a semiconductor storage device comprises: a non-volatile memory cell; a sensing circuit that senses a first voltage and selects one of a first mode and a second mode on the basis of the first voltage; and a transmission unit that outputs a first signal corresponding to the one of the first mode and the second mode. The sensing circuit selects the first mode if the first voltage is greater than or equal to an assessment value, and selects the second mode if the first voltage is less than the assessment value. The transmission unit outputs a first signal of a first amplitude during the first mode, and outputs a first signal of a second amplitude, which is smaller than the first amplitude, during the second mode.
This semiconductor memory device has a first conductive layer, a second conductive layer, a first conductive column, a first semiconductor layer, and a first memory layer. The first conductive layer extends in a first direction. The second conductive layer extends in the first direction and aligns with the first conductive layer in a third direction which intersects the first direction. The first conductive column passes through the first conductive layer and the second conductive layer in the third direction. The first semiconductor layer contacts the first conductive layer and the second conductive layer, and faces the first conductive column in the first direction. The first memory layer is positioned between the first semiconductor layer and the first conductive column.
H01L 27/11575 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région limite entre la région noyau et la région de circuit périphérique
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
The present invention improves the degree of integration of a memory. A memory device according to one embodiment of the present invention is provided with a first semiconductor layer, a first conductor layer, a second semiconductor layer, a second conductor layer, a first semiconductor film, a first memory film and a second memory film. The first semiconductor layer, the first conductor layer, the second semiconductor layer and the second conductor layer are arranged in this order in a first direction at a distance from each other. The first semiconductor film extends in the first direction and is in contact with the first semiconductor layer and the second semiconductor layer, while intersecting with the first conductor layer and the second conductor layer. The first memory film is arranged between the first conductor layer and the first semiconductor film. The second memory film is arranged between the second conductor layer and the first semiconductor film.
H01L 27/11575 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région limite entre la région noyau et la région de circuit périphérique
According to an embodiment, this memory system includes a nonvolatile memory that includes a plurality of memory cells, each of which is at least capable of storing a first bit, a second bit, and a third bit, and a memory controller that controls the nonvolatile memory. The nonvolatile memory outputs first hard bit data of the first bit, second hard bit data of the second bit, third hard bit data of the third bit, and fourth soft bit data pertaining to the first, second, and third bits, to the memory controller. The memory controller executes an error correction process using the first hard bit data, the second hard bit data, the third hard bit data, and the fourth soft bit data.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 12/04 - Adressage de mots de longueur variable ou de parties de mots
To improve the operating speed of a semiconductor storage device. The semiconductor storage device according to an embodiment of the present invention comprises: a first memory cell; a word line coupled to the gate of the first memory cell; a first transistor having a first end connected to the word line; and a control circuit that is configured to apply a positive first voltage to the back gate of the first transistor in a read-out operation.
G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
H01L 27/11526 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la région de circuit périphérique
This semiconductor storage device is provided with: a substrate; a first wiring layer that includes a first electroconductive layer and a second electroconductive layer; a second wiring layer provided between the substrate and the first wiring layer; and, a memory cell array layer provided between the substrate and the second wiring layer. The memory cell array layer is provided with: a plurality of third electroconductive layers arranged in a first direction that intersects the surface of the substrate; a semiconductor layer that extends in the first direction and opposes the plurality of third electroconductive layers; and, a charge accumulation layer provided between the plurality of third electroconductive layers and the semiconductor layer. The second wiring layer is provided with: a fourth electroconductive layer connected to one end of the semiconductor layer in the first direction; and, a fifth electroconductive layer that opposes the first electroconductive layer and that is electrically connected to the second electroconductive layer.
H01L 27/11573 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région de circuit périphérique
This semiconductor memory device includes: a plurality of first conductive layers 43 that have gaps therebetween and are aligned in a first direction; a first plug C4 that passes through the plurality of first conductive layers; a second conductive layer IC2a that is connected to the lower end of the first plug below the plurality of first conductive layers; a first transistor Tr below the plurality of first conductive layers; a second transistor AE in a second region DP between the first transistor and a first region below the second conductive layer, the second transistor having a gate electrically connected to the first transistor and a drain electrically connected to the first transistor; and a third transistor AE in the second region, the third transistor having a source and a drain electrically connected to each other.
H01L 27/11573 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région de circuit périphérique
A semiconductor storage device according to one embodiment of the present invention is provided with: a semiconductor layer which extends in a first direction; a gate electrode layer which contains at least one metal element that is selected from the group consisting of tungsten (W), molybdenum (Mo) and cobalt (Co); a charge accumulation layer which is arranged between the semiconductor layer and the gate electrode layer; and a first insulating layer which is arranged between the charge accumulation layer and the gate electrode layer so as to be in contact with the gate electrode layer, while comprising a first region that contains aluminum (Al) and oxygen (O).
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
24.
SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device according to an embodiment comprises: a semiconductor chip 1 having a passivation film 11; and a mounting board 2 having a surface that faces a surface of the semiconductor chip 1 on which the passivation film 11 is provided. The semiconductor chip 1 includes pads 3 formed so as to protrude from an outer surface of the passivation film 11. The mounting board 2 has pads 4, and the pads 3 and the pads 4 come into contact with one another in a state in which an oxide film or adsorbed substance has been removed from a region of contact between the pads 3 and the pads 4.
H01L 23/12 - Supports, p.ex. substrats isolants non amovibles
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 21/3205 - Dépôt de couches non isolantes, p.ex. conductrices ou résistives, sur des couches isolantes; Post-traitement de ces couches
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
Provided is a storage system useful for processing a large amount of data. In this invention, a package stocker can store a plurality of semiconductor packages each comprising one or more non-volatile memory dies. A drive comprises at least one socket to which the semiconductor package can be removably attached, and a controller that controls the one or more non-volatile memory dies of the semiconductor package attached to the socket. A host device is communicably connected to the drive, and is configured to read/write data from/to the one or more non-volatile memory dies of the semiconductor package via the controller. When a first semiconductor package is not attached to the socket of the drive, the host device causes a package conveyance device to convey the first semiconductor package to the socket of the drive such that the first semiconductor package is attached to the socket.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
A semiconductor storage device according to the present invention comprises a substrate, a plurality of memory chips, a controller, a plurality of terminals, a sealing member, and a sheet. The substrate has a first surface and a second surface located on the side opposite the first surface. The plurality of memory chips are mounted on the first surface of the substrate. The controller is mounted on the first surface of the substrate and controls the plurality of memory chips. The plurality of terminals are provided on the second surface of the substrate and include a plurality of test terminals. The sheet is provided on the second surface of the substrate and covers the plurality of test terminals among the plurality of terminals.
H01L 23/34 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température
H01R 12/72 - Dispositifs de couplage pour circuits imprimés rigides ou structures similaires se couplant avec la bordure des circuits imprimés rigides ou des structures similaires
G06K 19/077 - Supports d'enregistrement avec des marques conductrices, des circuits imprimés ou des éléments de circuit à semi-conducteurs, p.ex. cartes d'identité ou cartes de crédit avec des puces à circuit intégré - Détails de structure, p.ex. montage de circuits dans le support
The semiconductor apparatus according to an embodiment of the present invention comprises a substrate, a controller disposed on the substrate, a non-volatile memory disposed on the substrate separate from the controller, a first heat sink disposed in contact with an upper surface of the controller, a second heat sink disposed in contact with an upper surface of the non-volatile memory, and a first resin sealing body for sealing the controller, the non-volatile memory, the first heat sink, and the second heat sink. The first heat sink and the second heat sink are exposed at at least one of an upper surface or a side surface of the first resin sealing body. Provided is a semiconductor apparatus having improved heat dissipation characteristics.
H01L 23/29 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par le matériau
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/28 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p.ex. dissipateurs de chaleur
H01L 25/04 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
This memory system is for realizing a reduction in power consumption and an increase in speed of a reading operation of the memory system. The memory system comprises: a source line; a j-layer string selection line; an i-layer first word line; an i-layer second word line; a select gate line of one layer divided into 2n segments; a plurality of memory pillars; and a control circuit. Each of the plurality of memory pillars includes a first string and a second string. The first string has a first transistor, an i number of first memory cells, and a j number of second memory cells. The first transistor, the i number of first memory cells, and the j number of second memory cells are electrically connected in series. The second string has a second transistor, an i number of third memory cells, and a j number of fourth memory cells. The second transistor, the i number of third memory cells, and the j number of fourth memory cells are electrically connected in series. In the second memory cells and the fourth memory cells, j is equal to or less than n.
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 27/11556 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
This semiconductor memory device comprises: a first wiring; a first memory transistor connected to the first wiring; a first transistor connected between the first wiring and the first memory transistor; a second memory transistor connected to the first wiring in parallel with the first memory transistor; a second transistor connected between the first wiring and the second memory transistor; a second wiring connected to a gate electrode of the first memory transistor; a third wiring connected to a gate electrode of the second memory transistor; a fourth wiring connected to a gate electrode of the first transistor; a fifth wiring connected to a gate electrode of the second transistor; and a control circuit capable of selecting the first memory transistor or the second memory transistor and executing an erase operation to erase data therein. During the erase operation, with the first memory transistor being selected, the control circuit performs control such that the fourth wiring has a voltage higher than the voltage of the second wiring, and the fifth wiring has a voltage higher than the voltage of the fourth wiring.
G11C 16/14 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
G11C 16/16 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p.ex. des réseaux, des mots, des groupes
This semiconductor storage device has a first memory cell group to an eighth memory cell group that are arranged along a first direction; a first word line extending in the first direction; and a first sense amplifier group to an eighth sense amplifier group that are capable of supplying a voltage respectively to the first memory cell group to the eighth memory cell group. The first memory cell group to the eighth memory cell group each have a plurality of memory cells and a plurality of bit lines respectively connected to the plurality of memory cells. When a program voltage is supplied to the first word line in a write operation, the first sense amplifier group supplies a first voltage to a bit line connected to a memory cell to be written among a plurality of memory cells of the first memory cell group, and the second sense amplifier group supplies a second voltage, which is different from the first voltage, to a bit line connected to a memory cell to be written among a plurality of memory cells of the second memory cell group.
G11C 16/24 - Circuits de commande de lignes de bits
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
This memory system for increasing the speed of a read operation in a memory system includes: a first pillar; a first string including a first transistor and a first memory cell; a second string including a second transistor and a second memory cell; a first bit line; a first gate lane; a first word line; a second gate line; a second word line; and a control circuit. The control circuit, when executing a read operation on the first memory cell: applies a read voltage to the first word line; applies, to the second word line, a voltage to turn off the second memory cell regardless of charge accumulated in the second memory cell; applies, to the first gate line, a voltage to turn on the first transistor; and applies, to the second gate line, a voltage to turn on the second transistor.
G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 27/11556 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
The present invention improves the density of a memory cell. A memory device according to one embodiment comprises a first conductor layer (23), a first conductor film (33), a first semiconductor film (31), a second semiconductor film (35), a first insulator film (32), and a second insulator film (34). The first conductor film extends in a first direction above the first conductor layer. The first semiconductor film extends in the first direction between the first conductor layer and the first conductor film, and intersects with the first conductor layer. The second semiconductor film is in contact with the first semiconductor film, extends in the first direction between the first conductor layer and the first conductor film, and opposes the first conductor film. The first insulator film is provided between the first conductor layer and the first semiconductor film. The second insulator film is provided between the first semiconductor film and the second semiconductor film, and the first conductor film.
H01L 27/11565 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la configuration vue du dessus
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
This semiconductor memory device comprises a first memory cell and a second memory cell. In addition, this semiconductor memory device is configured to be able to execute: a first operation, that is, a read operation, a write operation, or an erase operation with respect to the first memory cell; and a second operation, that is, a read operation, a write operation, or an erase operation with respect to the second memory cell. In addition, this semiconductor memory device, when executing the second operation after the execution of the first operation, executes the second operation by using at least a portion of electric charge generated during the execution of the first operation.
H01L 27/11556 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
This memory device includes: a substrate 30; a non-volatile memory 14 that is provided to the substrate 30; a memory controller 13 that is provided to the substrate 30 and is connected to the non-volatile memory 14; and wiring 40 that is provided to the substrate 30 and includes one end section and another end section, said one end section being connected to the memory controller 13. The memory device further includes: a footprint 60 that is provided to the substrate 30 and is connected to the other end section of the wiring 40; an ESD protection element 12A that is provided to the substrate 30 and is connected to the footprint 60; a connection terminal that is provided to the substrate 30 and can electrically connect with a host device; and a via plug that is provided within the substrate, one end section thereof being connected to the other end section of the wiring 40, and the other end section thereof being connected to the connection terminal.
G06K 19/077 - Supports d'enregistrement avec des marques conductrices, des circuits imprimés ou des éléments de circuit à semi-conducteurs, p.ex. cartes d'identité ou cartes de crédit avec des puces à circuit intégré - Détails de structure, p.ex. montage de circuits dans le support
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
Provided is a storage system useful for processing a large amount of data. When a to-be-accessed wafer cassette including a first semiconductor wafer is not connected to a slot of a host device and is stored in a wafer cassette stocker, the host device causes a wafer cassette transport device to transport and connect the to-be-accessed wafer cassette to the slot of the host device. When the to-be-accessed wafer cassette is not connected to the slot of the host device and is not stored in the wafer cassette stocker, the host device causes a wafer transport device to transport the first semiconductor wafer from a wafer stocker to a cassette, causes the cassette to accommodate the first semiconductor wafer in a cassette housing, and causes the wafer cassette transport device to transport and connect, to the slot of the host device, the to be accessed wafer cassette including the first semiconductor wafer.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G11C 5/04 - Supports pour éléments d'emmagasinage; Montage ou fixation d'éléments d'emmagasinage sur de tels supports
G11C 7/04 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les effets perturbateurs thermiques
36.
CASSETTE HOUSING, PROBER, SERVER RACK, AND STORAGE SYSTEM
Provided is a cassette housing capable of adjusting a temperature relating to a semiconductor wafer containing a plurality of non-volatile memory chips. According to an embodiment, a cassette housing has a storage part, a probe card, and a container part. The storage part stores a semiconductor wafer containing a plurality of non-volatile memory chips. The probe card has probes that are to be brought into contact with pad electrodes provided on the semiconductor wafer. The container part contains a heat transfer liquid for cooling or heating the semiconductor wafer stored in the storage part.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G11C 5/04 - Supports pour éléments d'emmagasinage; Montage ou fixation d'éléments d'emmagasinage sur de tels supports
G11C 7/04 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les effets perturbateurs thermiques
The present invention is for suppressing degradation of reliability in communication between a probe card and a wafer. A wafer (10) according to one embodiment of the present invention comprises: a substrate (11) having a first region (RA) and a second region (RB) that do not overlap each other; a first chip unit and a second chip unit (100) that are each provided on the substrate; a first electrode (16A) and a second electrode (16B) each electrically connected to the first chip unit; and a third electrode (16A) and a fourth electrode (16B) that are each electrically connected to the second chip unit. The first electrode and the third electrode are disposed in the first region. The second electrode and the fourth electrode are disposed in the second region. The first region is a region independent of a region where the first chip unit and the second chip unit are provided.
This semiconductor storage device comprises first and second chips. The first chip comprises a first area and a second area. The first area has multiple memory cells, multiple bit lines, multiple word lines, and multiple first bonded electrodes electrically connected to the multiple bit lines. The second area has multiple contacts electrically connected to the multiple word lines, and multiple second bonded electrodes electrically connected to the multiple contacts. The multiple first bonded electrodes each comprise a third bonded electrode and a fourth bonded electrode that are adjacent to each other in a first direction. The multiple second bonded electrodes each comprise a fifth bonded electrode and a sixth bonded electrode that are adjacent to each other in the first direction. The distance from the center position of the third bonded electrode in the first direction to the center position of the fourth bonded electrode in the first direction matches, in a range of 90% to 110%, the distance from the center position of the fifth bonded electrode in the first direction to the center position of the sixth bonded electrode in the first direction.
H01L 27/11526 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la région de circuit périphérique
H01L 27/11573 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région de circuit périphérique
If a consumption current class supported by this removable memory device is another consumption current class that differs from a first consumption current class for which a consumption current value is largest among a plurality of varieties of consumption current classes, a first consumption current value that the removable memory device consumes from a first power source is no greater than a third allowable current value related to the first power source defined by said other consumption current class, and a second consumption current value that the removable memory device consumes from a second power source is no greater than a fourth allowable current value related to the second power source defined by said other consumption current class.
G06K 19/07 - Supports d'enregistrement avec des marques conductrices, des circuits imprimés ou des éléments de circuit à semi-conducteurs, p.ex. cartes d'identité ou cartes de crédit avec des puces à circuit intégré
G06K 7/00 - Méthodes ou dispositions pour la lecture de supports d'enregistrement
G06K 19/077 - Supports d'enregistrement avec des marques conductrices, des circuits imprimés ou des éléments de circuit à semi-conducteurs, p.ex. cartes d'identité ou cartes de crédit avec des puces à circuit intégré - Détails de structure, p.ex. montage de circuits dans le support
This memory system comprises: a first chip including a first plane and a first input/output circuit; and a controller which can issue a command for controlling the first chip. The first plane includes a first memory cell array, and a first latch circuit which can store first readout data read out from the first memory cell array. The first input/output circuit includes a first FIFO circuit which can take in the first readout data from the first latch circuit. The controller can transmit a first command to the first chip for ordering the taking in of the first readout data to the first FIFO circuit from the first latch circuit in a period in which a readout operation is being executed in the first plane.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G06F 12/0862 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec pré-lecture
A semiconductor memory device of an embodiment includes a substrate, a plurality of first conductor layers, a pillar, and a second conductor layer. The plurality of first conductor layers are provided above the substrate, and are separated from each other in a first direction. The pillar is provided penetrating the plurality of first conductor layers, and includes a first semiconductor layer stretched in the first direction. The intersecting portion of the pillar and the first conductor layer functions as a memory cell. The second conductor layer is provided above the plurality of first conductor layers, and is in contact with the first semiconductor layer. The second conductor layer is metal or silicide.
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
42.
SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STORAGE DEVICE
Provided is a semiconductor storage device that allows for an easy erasing operation. This semiconductor storage device comprises: a laminate of a plurality of conductive layers and a plurality of insulating layers; a core insulating layer; a semiconductor layer; and a memory layer provided between the semiconductor layer and the laminate in a first direction. The plurality of conductive layers include: a first selection gate line connected to a gate of a first selection transistor; word lines provided above the first selection gate line and connected to a gate of a memory transistor; and a second selection gate line provided above the word lines and connected to a gate of a second selection transistor. The core insulating layer has an upper surface lower than an upper surface of the second selection gate line with respect to a surface of a semiconductor substrate. The semiconductor layer includes: a first semiconductor part having respective channel-forming regions for the memory transistor and the first and second selection transistors; and a second semiconductor part provided on an upper surface of the core insulating layer. The first semiconductor part has an impurity semiconductor region that contains an impurity element and that overlaps the second selection gate line.
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
A semiconductor storage device of an embodiment comprises a first pin, a first receiving circuit, and a first termination circuit. The first pin receives a first signal and a second signal having an amplitude smaller than an amplitude of the first signal. The first receiving circuit is connected to the first pin, and outputs a third signal, on the basis of the comparison between the first signal and a first voltage. Further, the first receiving circuit outputs a fourth signal having an amplitude smaller than an amplitude of the third signal, on the basis of the comparison between the second signal and a second voltage. The first termination circuit is connected to the first pin, and is disabled when the first pin receives the first signal and enabled when the first pin receives the second signal.
The present invention suppresses an increase in power consumption. A semiconductor storage device of one embodiment comprises a bit line (BL), a memory cell transistor (MT) connected to the bit line, and a capacitor (CAP) connected between the memory cell transistor and the bit line.
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
45.
SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR STORAGE DEVICE
Provided is a highly reliable semiconductor device. This semiconductor device comprises: a semiconductor substrate (10) having a first region (NP1) and a second region (NP2); a first insulator layer (2b); a first gate electrode (3b) having a first semiconductor layer (31b) that contains an impurity, a first conductor layer (32b) that contains titanium, a second conductor layer (33b) that contains nitrogen and either titanium or tungsten, and a third conductor layer (34b) that contains tungsten; a second insulator layer (4b) that is provided on the third conductor layer and that contains oxygen and silicon; a third insulator layer (5b) that is provided on the second insulator layer and that contains nitrogen and silicon; a first contact (CS) provided on the first region; a second contact (CS) provided on the second region; and a third contact (C0) that is provided on the third conductor layer of the first gate electrode and that penetrates through the second insulator layer and the third insulator layer.
While a memory card is in a second operation mode, a host controller according to the present invention monitors a reset signal for the second operation mode and detects that an error has occurred in the second operation mode under the condition that a period in which both a card presence detection signal and the reset signal for the second operation mode are asserted has continued for an amount of time equal to or greater than a first period. In response to the detection of an error occurrence, the host controller generates a first interruption signal for starting a first driver. If the first driver has been started due to the generation of the first interruption signal, the first driver changes the operation mode of the memory card from the second operation mode to a first operation mode by controlling the host controller.
G06K 7/00 - Méthodes ou dispositions pour la lecture de supports d'enregistrement
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G06K 19/077 - Supports d'enregistrement avec des marques conductrices, des circuits imprimés ou des éléments de circuit à semi-conducteurs, p.ex. cartes d'identité ou cartes de crédit avec des puces à circuit intégré - Détails de structure, p.ex. montage de circuits dans le support
47.
STORAGE WAFER AND METHOD FOR PRODUCING STORAGE WAFER
The present invention increases the proportion of acceptable chips on a wafer. A storage wafer according to one embodiment of the present invention is provided with: a first semiconductor (71W); a first element layer (72W) which is provided on the upper surface of the first semiconductor; a first pad (11a) which is provided on the upper surface of the first element layer in a first region; a second pad (11a) which is provided on the upper surface of the first element layer in a second region that is different from the first region; a bonding film (73) which is provided on the upper surface of the first element layer in the second region including the second pad; a second semiconductor (74) which is provided on the upper surface of the bonding film; a second element layer (75) which is provided on the upper surface of the second semiconductor; and a third pad (11b) which is provided on the upper surface of the second element layer.
A semiconductor storage device according to the present embodiment is provided with: a plurality of first conductor layers which are laminated in a first direction and which each contain tungsten; laminated parts laminated alternately with the plurality of first conductor layers; a plurality of insulator films each including a first projection part projecting in a second direction orthogonal to the first direction with respect to the laminated parts; a semiconductor layer extending in the the first direction within a laminated body formed with the plurality of laminated parts and the plurality of first conductor layers; an electric charge storage layer disposed between the plurality of first conductor layers and the semiconductor layer; a plurality of second conductor layers which are disposed in contact with the first conductor layers on the first projection parts in the insulator films and which each have silicon including impurities; and a plurality of contact plugs that are disposed on one of the plurality of second conductor layers so as to be in contact with said one of the second conductor layers, that have conductivity, and that extend in the first direction.
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
49.
MEMORY DEVICE, CONTROL METHOD FOR CONTROLLING MEMORY DEVICE, AND PRODUCTION METHOD FOR MEMORY DEVICE
This memory device comprises: a first non-volatile memory die; a second non-volatile memory die that is layered above the first non-volatile memory die; a controller; and first and second temperature sensors included in the first and second non-volatile memory dies, respectively. The controller reads temperatures measured by the first and second temperature sensors from the first and second non-volatile memory dies. If at least one of the temperatures read from the first and second non-volatile memory dies is higher than or equal to a threshold temperature, the controller reduces the frequency of issuance of a command to the first and second non-volatile memory dies or the rate of access to the first and second non-volatile memory dies.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G11C 5/04 - Supports pour éléments d'emmagasinage; Montage ou fixation d'éléments d'emmagasinage sur de tels supports
G11C 7/04 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les effets perturbateurs thermiques
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
A semiconductor storage device that, according to the embodiments, comprises a first semiconductor layer that extends in a first direction, a second semiconductor layer that extends in the first direction and is provided so as to be separated from the first semiconductor layer in a second direction that intersects the first direction, a first conduction layer that extends in the second direction and intersects the first semiconductor layer and the second semiconductor layer, a first insulation layer that extends in the second direction, intersects the first semiconductor layer and the second semiconductor layer, and is provided at a first distance from the first conduction layer in the first direction, a second conduction layer that extends in the second direction, intersects the first semiconductor layer and the second semiconductor layer, and is provided at the first distance from the first insulation layer in the first direction, and a third conduction layer that extends in the second direction, intersects the first semiconductor layer and the second semiconductor layer, and is provided at the first distance from the second conduction layer in the first direction.
H01L 27/11551 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur
H01L 27/11578 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
A semiconductor storage device according to an embodiment includes a substrate, a first conductor layer, a plurality of second conductor layers, a first semiconductor layer, a pillar, and a contact. The first conductor layer is the first layer above the substrate, and has a portion provided extending in a first direction. The plurality of second conductor layers are layers above the first layer, and are provided mutually separated in a second direction. The first semiconductor layer is a layer above the plurality of second conductor layers, and has a portion provided expanding in a third direction and the first direction. The pillar is provided extending in the second direction, and has a portion provided penetrating the plurality of second conductor layers and the first semiconductor layer. The contact electrically connects between the pillar and the first conductor layer. The pillar includes: a second semiconductor layer provided extending in the second direction; a first insulator layer provided at least between the second semiconductor layer and the plurality of second conductor layers; and a third semiconductor layer that is provided between the second semiconductor layer and the first semiconductor layer, the third semiconductor layer being in contact with each of the second semiconductor layer and the first semiconductor layer.
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
A semiconductor storage device according to one embodiment of the present invention comprises first to ninth conductor layers, first and second insulating members, and first to fourth pillars. The first insulating member is provided along a first direction, and has a portion that is positioned between the second and sixth conductor layers and a portion that is positioned between the third and seventh conductor layers. The second insulating member is provided above the first insulating member along the first direction, and has a portion that is positioned between the fourth and eighth conductor layers and a portion that is positioned between the fifth and ninth conductor layers. The first and second pillars are in contact with the second, third, sixth and seventh conductor layers, while being provided in a third direction so as to sandwich the first insulating member therebetween. The third and fourth pillars are in contact with the fourth, fifth, eighth and ninth conductor layers, while being provided in the third direction so as to sandwich the second insulating member therebetween. The distance between the first pillar and the second pillar in the third direction in a cross-section that comprises the second conductor layer and the sixth conductor layer is shorter than the distance between the first pillar and the second pillar in the third direction in a cross-section that comprises the third conductor layer and the seventh conductor layer. The distance between the third pillar and the fourth pillar in the third direction in a cross-section that comprises the fourth conductor layer and the eighth conductor layer is longer than the distance between the third pillar and the fourth pillar in the third direction in a cross-section that comprises the fifth conductor layer and the ninth conductor layer.
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
53.
SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STORAGE DEVICE
In order to suppress an increase in production burden of a memory cell array, a semiconductor storage device according to an embodiment is provided with a bit line, a capacitor, and a first memory cell transistor and a second memory cell transistor connected in series between the bit line and the capacitor.
H01L 27/11568 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région noyau de mémoire
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
54.
INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING PROGRAM
An information processing apparatus according to an embodiment of the present invention reserves a parking lot for an automobile. The information processing apparatus comprises: a reception unit that receives first information about a destination of the automobile; a first searching unit that searches a route to the destination on the basis of the first information; a second searching unit that searches a first area and a first time in a route to the destination and a vicinity of the route; and a reservation unit that requests reservation of a first parking lot in the first area at the first time using wireless or wired communication without waiting an instruction from a user.
The present invention provides a semiconductor storage device with which heat dissipation efficiency can be improved. This semiconductor storage device is equipped with a body, a memory, a controller, and a plurality of terminals. The plurality of terminals are exposed on a first surface of the body, and include a plurality of signal terminals used in signal transmission. The plurality of terminals form at least a first row and a second row. The first row includes a plurality of terminals aligned in a first direction at positions closer to a first end edge than a second end edge of the body and with spaces therebetween. The second row includes a plurality of terminals aligned in the first direction at positions closer to the second end edge than the first end edge of the body and with spaces therebetween. The region of the first surface of the body between the first row and the second row includes a contact region that is in contact with a heat-conductive member that is disposed on a substrate of a host device electrically connected to the semiconductor storage device.
G06K 19/077 - Supports d'enregistrement avec des marques conductrices, des circuits imprimés ou des éléments de circuit à semi-conducteurs, p.ex. cartes d'identité ou cartes de crédit avec des puces à circuit intégré - Détails de structure, p.ex. montage de circuits dans le support
G11C 5/02 - Disposition d'éléments d'emmagasinage, p.ex. sous la forme d'une matrice
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
56.
SYSTEMS AND METHODS FOR PROTECTING SSDS AGAINST THREATS
Various implementations described herein relate to systems and methods for protecting data stored on a Solid State Drive (SSD) against malware, including determining, by a controller of the SSD, a typical traffic profile, receiving, by the controller, commands from a host, and determining, by the controller, that the commands are likely caused by malware by determining that the commands deviate from the typical traffic profile. In response to determining the commands are likely caused by the malware, the controller performs a malware response action.
The present invention provides a semiconductor storage device with which heat dissipation efficiency can be improved. This semiconductor storage device is equipped with a body, a memory, a controller, and a plurality of terminals. The plurality of terminals are exposed on a first surface of the body, and include a plurality of signal terminals used in signal transmission. The plurality of terminals form at least a first row and a second row. The first row includes a plurality of terminals aligned in a first direction at positions closer to a first end edge than a second end edge of the body and with spaces therebetween. The second row includes a plurality of terminals aligned in the first direction at positions closer to the second end edge than the first end edge of the body and with spaces therebetween. The region of the first surface of the body between the first row and the second row includes a contact region that is in contact with a heat-conductive member that is disposed on a substrate of a host device electrically connected to the semiconductor storage device.
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G06K 19/077 - Supports d'enregistrement avec des marques conductrices, des circuits imprimés ou des éléments de circuit à semi-conducteurs, p.ex. cartes d'identité ou cartes de crédit avec des puces à circuit intégré - Détails de structure, p.ex. montage de circuits dans le support
G11C 5/02 - Disposition d'éléments d'emmagasinage, p.ex. sous la forme d'une matrice
G11C 5/04 - Supports pour éléments d'emmagasinage; Montage ou fixation d'éléments d'emmagasinage sur de tels supports
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
G11C 7/04 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les effets perturbateurs thermiques
58.
SYSTEMS AND METHODS FOR PLP CAPACITOR HEALTH CHECK
Various implementations described herein relate to systems and methods for determining abnormal leakage current of a capacitor by determining a number of recent leakage current values for the capacitor and determining a maximum upper limit, minimum upper limit, maximum lower limit, and minimum lower limit based on leakage current values different from the recent leakage current values. A present upper limit and a present lower limit are determined for the recent leakage current values. Abnormal leakage current is determined in response to determining that the present upper limit being greater than an upper threshold (determined based on the maximum upper limit and the minimum upper limit) or the present lower limit being less than a lower threshold (determined based on the maximum lower limit and the minimum lower limit).
H01M 10/42 - Procédés ou dispositions pour assurer le fonctionnement ou l'entretien des éléments secondaires ou des demi-éléments secondaires
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p.ex. le niveau ou la densité de l'électrolyte
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
Various implementations described herein relate to systems and methods for collecting Solid State Drive (SSD) statistics. A controller, in response to receiving a start command from a host, creates a slot area in a storage device of the SSD corresponding to a slot, collects first statistics data from one or more modules of the SSD, and stores the first statistics data in the slot area. Further, the controller, in response to receiving a stop command, collects second statistics data from the one or more modules and sends the first statistics data and the second statistics data to the host.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G11C 29/56 - Vérification du fonctionnement correct des mémoires; Test de mémoires lors d'opération en mode de veille ou hors-ligne Équipements externes pour test de mémoires statiques, p.ex. équipement de test automatique [ATE]; Interfaces correspondantes
60.
SYSTEMS AND METHODS FOR SCHEDULING FLASH OPERATIONS
Various implementations described herein relate to systems and methods for a solid state drive (SSD) that includes requesting power credits while performing a program or erase operation for a flash memory of the SSD. In response to determining that the requested power credits are rejected, the program or erase operation is suspended and its power credits are released. A read operation may then be performed in response to suspending the program or erase operation and releasing its power credits.
Various implementations described herein relate to correcting errors in Dynamic Random Access Memory (DRAM). A memory controller uses an Error Correcting Code (ECC) to store an encoded data word within a DRAM die. The DRAM die is communicatively coupled the memory controller by a memory data bus. The DRAM die includes on-die error correction for data bits stored in the DRAM. Upon reading the encoded data word, the memory controller corrects and detects one or more errors. The one or more errors are introduced by at least one of the on-die error correction of the DRAM die or the memory data bus.
A memory device according to one embodiment of the present invention has: a first transistor that includes a bit line above a substrate, a first semiconductor layer between the substrate and the bit line, and a first gate electrode that faces the side surface of the first semiconductor layer with a first gate insulation layer interposed therebetween; a second transistor that includes a first memory element between the first transistor and the substrate, a first word line connected to the first gate electrode, a second semiconductor layer between the substrate and the bit line, and a second gate electrode facing the side surface of the second semiconductor layer with a second gate insulation layer interposed therebetween; a second memory element between the second transistor and the substrate; and a second word line adjacent to the first word line in a direction parallel to the surface of the substrate, the second word line being connected to the second gate electrode. The second semiconductor layer is parallel to the surface of the substrate and is adjacent to the first semiconductor layer in a second direction that intersects with the first direction.
This semiconductor memory device is provided with a first memory unit for storing a uniquely assigned first unique number and a first chip address having a smaller number of bits than that of the first unique number and being distinguishable from those of other semiconductor memory devices.
G11C 5/04 - Supports pour éléments d'emmagasinage; Montage ou fixation d'éléments d'emmagasinage sur de tels supports
G11C 8/12 - Circuits de sélection de groupe, p.ex. pour la sélection d'un bloc de mémoire, la sélection d'une puce, la sélection d'un réseau de cellules
64.
MEMORY DEVICE, AND METHOD FOR MANUFACTURING MEMORY DEVICE
A memory device according to an embodiment comprises: a first transistor including a bit line over a substrate, a first semiconductor layer between the substrate and the bit line, and a first gate electrode opposing a side surface of the first semiconductor layer via a first gate insulating layer; a second transistor including a first memory element between the first transistor and the substrate, a first word line connected to the first gate electrode, a second semiconductor layer between the substrate and the bit line, and a second gate electrode opposing a side surface of the second semiconductor layer via a second gate insulating layer; a second memory element between the second transistor and the substrate; and a second word line adjacent to the first word line in a direction parallel to the surface of the substrate and connected to the second gate electrode. The second semiconductor layer is adjacent to the first semiconductor layer in a second direction parallel to the surface of the substrate and transverse to the first direction.
The present invention curbs degradation in communication reliability between a probe electrode and a pad electrode. A storage system of one embodiment is provided with: a wafer comprising a memory chip unit that includes a pad electrode having a first portion and a second portion that are electrically connected to one another, and comprising a memory cell array electrically connected to the pad electrode; and a prober that is capable of holding the wafer and that reads/writes to/from the memory cell array. The prober comprises: a probe card having a probe electrode allowing for contact with the pad electrode, and having a memory controller capable of writing/reading to/from the memory cell array via the probe electrode; and a movement mechanism for causing the probe card or the held wafer to move, in order to bring the pad electrode of the held wafer and the probe electrode into contact. The movement mechanism is capable of executing: a first operation for bringing the probe electrode into contact with the first portion of the pad electrode without coming into contact with the second portion; and a second operation for bringing the probe electrode into contact with the second portion of the pad electrode without coming into contact with the first portion.
The present invention suppresses degradation in reliability of communication between a probe electrode and a pad electrode. A storage system according to one embodiment of the present invention is provided with: a wafer including memory chip units, each of which comprising a pad electrode that has a first portion and a second portion electrically connected to each other and a memory cell array that is electrically connected to the pad electrode; and a prober that can hold the wafer and reads/writes on the memory cell array of the held wafer. The prober includes: a probe card including a probe electrode that can make contact with the pad electrode of the held wafer and a memory controller that is electrically connected to the probe electrode and can perform read/write on the memory cell array via the probe electrode; and a movement mechanism that moves the probe card or the held wafer such that the probe electrode and the pad electrode of the held wafer make contact with each other. The movement mechanism can execute a first operation for bringing the probe electrode into contact with the first portion of the pad electrode and a second operation for bringing the probe electrode into contact with the second portion of the pad electrode.
Provided is a storage device capable of appropriate temperature control. According to an embodiment, the storage device is equipped with a prober and a stocker. The prober writes data to a semiconductor wafer storage that includes a plurality of nonvolatile memory chips, or reads data from the semiconductor wafer storage. The stocker stores the plurality of semiconductor wafers in a state of having been extracted from the prober. The prober has a first temperature control mechanism. The first temperature control mechanism increases the temperature of the semiconductor wafer to a first temperature or higher. The stocker has a second temperature control mechanism. The second temperature control mechanism cools the semiconductor wafer to at or below a second temperature lower than the first temperature.
H01L 21/677 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le transport, p.ex. entre différents postes de travail
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
A storage device comprising a prober and a stocker capable of storing a plurality of semiconductor wafers each including a plurality of non-volatile memory dies. A controller in the prober, if a set of identifying information and an inspection code having a correct correlation is not stored in a first semiconductor wafer transported from the stocker to a stage in the prober, writes the first identifying information and the first inspection code to the first semiconductor wafer. If a set of identifying information and an inspection code having a correct correlation is stored in the first semiconductor wafer, the controller acquires from a host computer or the first semiconductor wafer a first logical/physical address conversion table associated with the identifying information of the first semiconductor wafer.
H01L 21/677 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le transport, p.ex. entre différents postes de travail
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G11C 29/00 - Vérification du fonctionnement correct des mémoires; Test de mémoires lors d'opération en mode de veille ou hors-ligne
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
A semiconductor storage device according to one embodiment of the present invention is provided with: a first delay circuit in which a first signal is delayed and a delay time is variable; a first selection circuit for selecting one of a second signal and a third signal on the basis of the first signal delayed by the first delay circuit; a first output buffer for outputting a fourth signal on the basis of the signal selected by the first selection circuit; a first output pad for outputting the fourth signal to the outside; and a counter capable of counting the number of times of output of the fourth signal.
A method of running a printed circuit board (PCB) trace on a PCB. The PCB comprising a plurality of PCB layers. The method comprising forming a conductive trace on at least one of the plurality of PCB layers; coupling a first portion of the conductive trace to a capacitor formed on at least one of the plurality of PCB layers; coupling a second portion, different from the first portion, of the conductive trace to a conductive material formed within a first via extending through two or more of the plurality of PCB layers; and configurably setting a length of a conductive path of the conductive trace according to a predetermined impedance. The capacitor is separated laterally in a plan view at a first distance from the first via. The length of the conductive trace in the plan view' is greater than the first distance. The conductive path of the conductive trace of the length has the predetermined impedance.
H05K 1/16 - Circuits imprimés comprenant des composants électriques imprimés incorporés, p.ex. une résistance, un condensateur, une inductance imprimés
H05K 1/11 - Eléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
The present invention suppresses an increase in chip size. A memory device according to an embodiment comprises: a plurality of first electrical conductors stacked along a first direction; a second electrical conductor, a third electrical conductor, and a fourth electrical conductor which are stacked on the same layer above the plurality of first electrical conductors; a plurality of fifth electrical conductors stacked along the first direction; a sixth electrical conductor stacked above the plurality of fifth electrical conductors; a first semiconductor extending along the first direction between the second electrical conductor and the sixth electrical conductor; a second semiconductor extending along the first direction between the third electrical conductor and the sixth electrical conductor; and a third semiconductor extending along the first direction between the fourth electrical conductor and the sixth electrical conductor.
H01L 27/11556 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
The present invention limits an increase in the size of a memory array. A memory device according to an embodiment comprises: a first conductor and a charge storage film that extend in a first direction that crosses the surface of a substrate; a first semiconductor of a first conductive type; a second semiconductor and a third semiconductor each of a second conductive type; and a first laminate that includes a second conductor, a first insulator, and a third conductor that each extend in a second direction within a first plane parallel to the surface of the substrate and that are laminated in said order along the first direction. The first conductor, the charge storage film, the first semiconductor, and the first laminate are aligned in said order above the substrate in a third direction that crosses the second direction within the first plane. The second semiconductor makes contact with the first semiconductor and the second conductor between the second conductor or the first insulator and the charge storage film. The third semiconductor makes contact with the first semiconductor and the third conductor between the third conductor or the first insulator and the charge storage film.
H01L 27/11578 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur
H01L 27/11551 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur
73.
SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor storage device according to one embodiment is provided with a first laminate in which a plurality of first electrode layers and a plurality of first insulating layers are alternatingly laminated on a substrate in a first direction perpendicular to the substrate, a plurality of semiconductor films passing through the first laminate in the first direction, a second laminate in which a plurality of second electrode layers and a plurality of second insulating layers are alternatingly laminated on the first laminate in the first direction, and a plurality of contact plugs that pass through the second laminate in the first direction and are individually connected to each of the plurality of semiconductor films and each of the plurality of second electrode layers.
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
A solid state drive (SSD) includes a first storage region classified as byte addressable NV storage region and a controller communicatively coupled to the first storage region by a bus. The controller detects a reduced storage capacity of the first storage region, and in response to the detection, reclassifies the first storage region as a block addressable NV storage region. The SSD dynamically changes byte addressable NV storage regions to block addressable NV storage regions as the byte addressable NV storage regions are degraded, thereby extending the longevity of the SSD.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
75.
SOLID STATE DRIVE SUPPORTING BOTH BYTE ADDRESSABLE PROTOCOL AND BLOCK ADDRESSABLE PROTOCOL
A solid state drive (SSD) enabled to process and store block addressable and byte addressable data, includes a first storage region for storing byte addressable data, a second storage region for storing block addressable data, and an SSD controller coupled to the first storage region and the second storage region by a bus. The SSD controller includes a processor and an interface for receiving data packets from a host. The SSD controller receives a data packet from the host at the interface, determines whether the data packet includes byte addressable data or block addressable data at the processor, selects either the first storage region or the second storage region based on the determination, and stores the data associated with the data packet in the selected storage region.
[Problem] To provide a substrate processing device capable of minimizing variations in the flow speed of a liquid. [Solution] A substrate processing device according to the present embodiment comprises a processing tank which can store a liquid. A plurality of semiconductor substrates are arranged on a conveyance unit such that the surfaces of said plurality of semiconductor substrates face a substantially horizontal direction, and the conveyance unit can convey the plurality of semiconductor substrates into the processing tank. A plurality of liquid supply units can supply a liquid from below the processing tank toward the inner side of the processing tank. A plurality of flow-regulating plates are positioned at one end side and/or the other end side of the arrangement of the plurality of semiconductor substrates. The plurality of flow-regulating plates are provided in a first gap region above the semiconductor substrates, among gaps between the conveyance unit and the side walls of the processing tank at both sides of the conveyance unit, when viewed from the arrangement direction of the plurality of semiconductor substrates.
WHR2WHR2 taken for a process for outputting signals to a controller, and outputs from an output circuit, dummy data preset in signals DQS and /DQS and a signal DQ.
The present invention improves integration density while inhibiting degradation of memory cell properties. A memory device according to one embodiment of the present invention comprises: first and second conductors respectively contained in the same layer in mutually separate first and second stacks; a semiconductor including first and second portions that extend between the first and second stacks in a first direction intersecting the first and second conductors and that are separate from each other in the same layer, and a third portion that electrically connects the first and second portions below the first and second conductors; a first charge storage film between the first conductor and the first portion of the semiconductor; a second charge storage film between the second conductor and the second portion of the semiconductor; a first insulator between the first conductor and the first charge storage film; a second insulator between the second conductor and the second charge storage film; a third insulator between the first insulator and the first charge storage film; and a fourth insulator between the second insulator and the second charge storage film. The permittivity of the third and fourth insulators is greater than the permittivity of the first and second insulators.
H01L 27/11556 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
Various implementations described herein relate to systems and methods for enabling a data lane for communicating messages for each of a plurality of regions of a non-volatile memory. Each of the plurality of regions includes a plurality of dies. The messages for each of the plurality of regions are communicated via the data lane.
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
80.
TWO-LAYERED DETERMINISTIC INTER-PROCESS COMMUNICATION SCHEDULER FOR INPUT OUTPUT DETERMINISM IN SOLID STATE DRIVES
Systems and methods for two-layered or a two-phase deterministic inter-process communication (IPC) scheduling for input output deterministic (IOD) sets also referred to as NVM sets in a solid state drive (SSD) system are provided. In various embodiments, an SSD controller includes an IPC scheduler comprising a first layer NVM set scheduler and a second layer fair share scheduler, configured to receive information messages for NVM sets, operable to prioritize the information messages in IPC queues, and generate an IPC pipeline to be processed for I/O operations.
Various implementations described herein relate to systems and methods for defining an optimal transfer and processing unit (OTPU) size for communicating messages for a plurality of non-volatile memory (NVM) sets of a non-volatile memory of the SSD. Each of the plurality of NVM sets corresponds to one of a plurality of regions of the non-volatile memory. Each of the plurality of regions includes a plurality of dies.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 3/08 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement à partir de, ou vers des supports d'enregistrement distincts, p.ex. carte perforée
82.
SEMICONDUCTOR WAFER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
This semiconductor wafer includes a surface having at least one groove including an inner wall surface. The inner wall surface of the groove is exposed.
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 21/306 - Traitement chimique ou électrique, p.ex. gravure électrolytique
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
According to one embodiment, a semiconductor includes a first surface and a second surface. The semiconductor storage device includes a nonvolatile memory, a controller to control the nonvolatile memory, and terminals exposed in the first surface. The controller transmits first data indicative of a temperature of the controller measured by a temperature sensor, second data indicative of a temperature difference between the temperature of the controller and a temperature of the first surface, and third data indicative of a temperature difference between the temperature of the controller and a temperature of the second surface to a host device.
G06K 19/07 - Supports d'enregistrement avec des marques conductrices, des circuits imprimés ou des éléments de circuit à semi-conducteurs, p.ex. cartes d'identité ou cartes de crédit avec des puces à circuit intégré
G06K 19/077 - Supports d'enregistrement avec des marques conductrices, des circuits imprimés ou des éléments de circuit à semi-conducteurs, p.ex. cartes d'identité ou cartes de crédit avec des puces à circuit intégré - Détails de structure, p.ex. montage de circuits dans le support
G11C 7/04 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les effets perturbateurs thermiques
Various implementations described herein relate to systems and methods for encoding data having input bits to be stored in a non-volatile storage device, including mapping the input bits to a plurality of component codes of an error correction code (ECC) and encoding the input bits as the plurality of component codes, wherein first input bits of the input bits encoded by any of the plurality of component codes are encoded by every other component code of the plurality of component codes in a non-overlapping manner.
Various implementations described herein relate to systems and methods for performing error correction in a flash memory device by determining suggested corrections by decoding a codeword. In addition, whether a first set of the suggested corrections obtained based on a first component code of the plurality of component codes agree with a second set of the suggested corrections obtained based on a second component code of the plurality of component codes is determined. One of accepting the first set of the suggested corrections or rejecting the first set of the suggested corrections is selected based on whether the first set of the suggested corrections and the second set of the suggested corrections agree.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
A resource management system in a data center one or more data storage resource providers and a transaction server. The transaction server is configured to receive, from a client, a request for read and/or write access for a data storage resource, the request comprising one or more specifications, to provide, to the one or more data storage resource providers, at least a portion of the request, and to receive, from the one or more data storage resource providers, respective responses to the request, the responses respectively comprising one or more allocation options. The transaction server is further configured to select one of the one or more allocation options for registration, and register the selected allocation option with a data manager. At least one of the one or more data storage providers is configured to provide the data storage resource in accordance with the registered allocation option.
The semiconductor device according to an embodiment of the present invention includes: a first chip that has a first semiconductor substrate, a first semiconductor element provided on the first semiconductor substrate, a first wiring layer connected to the first semiconductor element, and a first pad connected to the first wiring layer; and a second chip that has a second semiconductor substrate, a second semiconductor element provided on the second semiconductor substrate, a second wiring layer connected to the second semiconductor element, and a second pad connected to the second wiring layer and bonded to the first pad. At least one of the first pad and the second pad has a first metal layer that is bonded to the other pad, a second metal layer that has a coefficient of thermal expansion that is higher than that of the first metal layer, and a barrier metal layer that is provided between the first metal layer and the second metal layer.
H01L 27/00 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun
H01L 21/3205 - Dépôt de couches non isolantes, p.ex. conductrices ou résistives, sur des couches isolantes; Post-traitement de ces couches
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
A semiconductor storage device of an embodiment is provided with: a plurality of first conductive layers stacked on a substrate; a plurality of second conductive layers each stacked between the first conductive layers; a pillar which, in a region in which the plurality of first conductive layers and the plurality of second conductive layers are arranged, extends in a stacking direction of the plurality of first conductive layers and the plurality of second conductive layers, forming a plurality of memory cells at intersections of the plurality of first conductive layers and the plurality of second conductive layers; a first contact plug which, in the region in which the plurality of first conductive layers and the plurality of second conductive layers are disposed, extends in the stacking direction of the plurality of first conductive layers and the plurality of second conductive layers and is connected to the plurality of first conductive layers; and a second contact plug which, in the region in which the plurality of first conductive layers and the plurality of second conductive layers are disposed, extends in the stacking direction of the plurality of first conductive layers and the plurality of second conductive layers and is connected to the plurality of second conductive layers.
H01L 27/11556 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H01L 27/11548 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la région limite entre la région noyau et la région de circuit périphérique
H01L 27/11575 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région limite entre la région noyau et la région de circuit périphérique
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
89.
SYSTEM AND METHOD FOR SERIAL INTERFACE MEMORY USING SWITCHED ARCHITECTURE
A memory system for storing and retrieving data may include a controller, a first switch, a second switch connected to the first switch via an interconnecting bus, and a plurality of memory devices. The controller may have a first serial interface. The first switch may have one or more serial interfaces and one or more memory ports. The first serial interface of the controller may be communicatively connected to a first serial interface of the one or more serial interfaces of the first switch via a first serial bus. Each of the one or more memory ports of the first switch may be communicatively connected to a subset of the plurality of memory devices via a memory bus. The first switch may transfer data between the controller and the subsets of the plurality of memory devices via the one or more memory ports.
A nonvolatile semiconductor storage device according to an embodiment of the present invention is provided with: a plurality of first wiring layers that extend in a first direction and that are aligned along a second direction intersecting the first direction; a plurality of second wiring layers that are provided above the plurality of first wiring layers in a third direction intersecting the first direction and the second direction and that are aligned along the first direction and extend in the second direction; a plurality of first laminated structures including, at intersections of the plurality of second wiring layers and the plurality of first wiring layers, memory cells disposed between the second wiring layers and the first wiring layers; second laminated structures that are adjacent to the plurality of first wiring layers in the second direction and that are aligned along the second direction and contact the second wiring layers; and an insulating layer provided between the plurality of first laminated structures and between a plurality of the second laminated structures. Each of the second laminated structures has a higher Young's modulus than the insulating layer. Provided are: a highly-reliable nonvolatile semiconductor storage device that has excellent mechanical strength and high resistance to pattern short-circuiting and thus improves yields; and a method for manufacturing the same.
H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
H01L 45/00 - Dispositifs à l'état solide spécialement adaptés pour le redressement, l'amplification, la production d'oscillations ou la commutation, sans barrière de potentiel ni barrière de surface, p.ex. triodes diélectriques; Dispositifs à effet Ovshinsky; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives
91.
NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME
According to an embodiment, a nonvolatile semiconductor storage device is provided with: a plurality of first wiring layers extending in a first direction; a plurality of second wiring layers extending over the plurality of first wiring layers in a second direction transverse to the first direction; and a memory cell which is disposed between the second wiring layers and the first wiring layers at intersecting portions of the plurality of second wiring layers and the plurality of first wiring layers, and which includes a cell portion having a variable resistance film and a selector portion having a selector. The first wiring layers and the second wiring layers comprise mutually different materials. Provided are a nonvolatile semiconductor storage device having reduced wiring resistance, and a method for manufacturing the same.
H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
H01L 45/00 - Dispositifs à l'état solide spécialement adaptés pour le redressement, l'amplification, la production d'oscillations ou la commutation, sans barrière de potentiel ni barrière de surface, p.ex. triodes diélectriques; Dispositifs à effet Ovshinsky; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives
H01L 49/00 - Dispositifs à l'état solide non couverts par les groupes et et non couverts par une autre sous-classe; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives
92.
SYSTEMS AND METHODS FOR MANAGING REDUCED POWER FAILURE ENERGY REQUIREMENTS ON A SOLID STATE DRIVE
A system and method for controlling a SSD in response to a power failure event of a main power supply to the SSD. The method includes receiving and storing write commands and associated data payloads for execution on the SSD in volatile memory, detecting the power failure event on the SSD, supplying backup power to the SSD during the power failure event, and executing one or more write commands stored in the volatile memory by storing the associated data payloads in a non-volatile memory on the SSD using the backup power. In response to the execution, removing the one or more write commands from the cache such that one or more unexecuted write commands and the associated data payloads remain in the cache, and storing a list of the one or more unexecuted write commands, but not the associated data payloads, in non-volatile memory using the backup power.
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p.ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 11/20 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel en utilisant un masquage actif du défaut, p.ex. en déconnectant les éléments défaillants ou en insérant des éléments de rechange
According to an embodiment of the present invention, an assessment method is provided. The assessment method involves assessing the progress of a treatment of a by-product produced in a process for reacting a substance containing silicon and a halogen, or reacting a substance containing silicon and a substance containing a halogen. The treatment of the by-product includes bringing a water-containing treatment solution into contact with the by-product to obtain a first solid. The assessment method includes assessing the progress of the treatment of the by-product on the basis of a signal obtained by chemical analysis of Si-α bonding (where α is at least one element selected from the group consisting of F, Cl, Br, and I) and/or Si-H bonding, with respect to the first solid.
H01L 21/31 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour former des couches isolantes en surface, p.ex. pour masquer ou en utilisant des techniques photolithographiques; Post-traitement de ces couches; Emploi de matériaux spécifiés pour ces couches
C23C 16/44 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c. à d. procédés de dépôt chimique en phase vapeur (CVD) caractérisé par le procédé de revêtement
According to an embodiment of the present invention, a processing device is provided, that processes a byproduct produced in a reaction of a source material containing silicon and a halogen or a reaction between a source material containing silicon and a source material containing a halogen. The processing device includes a processing liquid tank, a processing vessel, a supply mechanism, and an exhaust mechanism. The processing liquid tank stores a processing liquid that contains a basic aqueous solution. A member to be processed containing a byproduct is placed in the processing vessel. The supply mechanism supplies the processing liquid from the processing liquid tank to the processing vessel and processes the byproduct in the processing vessel with the supplied processing liquid. The exhaust mechanism discharges, from the processing vessel, gas generated by the reaction between the processing liquid and the byproduct.
H01L 21/205 - Dépôt de matériaux semi-conducteurs sur un substrat, p.ex. croissance épitaxiale en utilisant la réduction ou la décomposition d'un composé gazeux donnant un condensat solide, c. à d. un dépôt chimique
C23C 16/44 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c. à d. procédés de dépôt chimique en phase vapeur (CVD) caractérisé par le procédé de revêtement
Various implementations described herein relate to systems and methods for managing selective erasure in a Solid-State Drive (SSD) including receiving a selective erase command corresponding to erasing valid and invalid data mapped to a logical address and in response to receiving the selective erase command, erasing blocks in which one or more pages mapped to the logical address are located based on a mapping table that maps the logical address to the one or more pages. Both valid data and invalid data may be physically stored in one or more pages.
Various implementations are directed to systems and methods for maintaining integrity and reliability of data in an SSD device using error correction coding. According to certain aspects, for frames of data having an ECC code with two or more sub-codes, while one sub-decoder is not in use it could be used to start a decode of another frame. By "interleaving" and alternating the frames between sub-decoders, two or more frames can be decoded simultaneously in an efficient manner. This can clearly be extended to more sub-codes (i.e. dimensions greater than two).
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
A semiconductor storage device according to an embodiment comprises a plurality of planes and a sequencer. Each of the plurality of planes includes a plurality of blocks which are sets of memory cells. The sequencer executes a first operation and a second operation shorter than the first operation. The sequencer, upon receiving a first command set directing execution of the first operation, executes the first operation. The sequencer, upon receiving a second command set directing execution of the second operation when the first operation is being executed, suspends the first operation and executes the second operation, or executes the second operation in parallel with the first operation, on the basis of the address of a block for the first operation and the address of a block for the second operation.
G11C 16/16 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p.ex. des réseaux, des mots, des groupes
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 16/06 - Circuits auxiliaires, p.ex. pour l'écriture dans la mémoire
This memory system comprises: a plurality of memory packages, an ODT circuit, and a controller. The memory packages are arranged in a pair so as to face each other across a substrate, and are connected to the controller by a common bus. The ODT circuit is disposed in every memory package and suppresses signal reflection. The controller writes or reads data to and from the designated memory package via the common bus, controls the ODT circuit to be turned on and off, and holds an ODT activation condition for turning on the ODT circuit. The ODT activation condition is a two-bit information signal defined by at least a two-cycle periodic signal provided at the head of the control signal. The controller turns on the ODT circuit when an assert state of a chip enable signal CEn acquired twice consecutively by using a periodic signal matches the ODT activation condition.
H01L 21/3065 - Gravure par plasma; Gravure au moyen d'ions réactifs
H01L 21/3213 - Gravure physique ou chimique des couches, p.ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
100.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
[Problem] To provide a semiconductor device in which a plug can be suitably formed on a line, and a method for manufacturing the same. [Solution] According to an embodiment, a semiconductor device is provided with a first insulating film and a plurality of lines provided inside the first insulating film. The device is further provided with: a second insulating film provided on the first insulating film and the plurality of lines; and a conductor provided on a first line among the plurality of lines and having an upwardly protruding shape with respect to the first line inside the second insulating film. The device is further provided with a plug provided on the first line through the conductor. The device is further provided with a first pad provided above the plug and electrically connected to the plug. The device is further provided with a second pad provided on the first pad and electrically connected to the first pad.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 21/3205 - Dépôt de couches non isolantes, p.ex. conductrices ou résistives, sur des couches isolantes; Post-traitement de ces couches
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 23/12 - Supports, p.ex. substrats isolants non amovibles
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H01L 27/11556 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
brevets
