Techniques related to key person recognition in multi-camera immersive video attained for a scene are discussed. Such techniques include detecting predefined person formations in the scene based on an arrangement of the persons in the scene, generating a feature vector for each person in the detected formation, and applying a classifier to the feature vectors to indicate one or more key persons in the scene.
G06V 20/40 - RECONNAISSANCE OU COMPRÉHENSION D’IMAGES OU DE VIDÉOS Éléments spécifiques à la scène dans le contenu vidéo
G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
G06T 7/73 - Détermination de la position ou de l'orientation des objets ou des caméras utilisant des procédés basés sur les caractéristiques
Methods, apparatuses, and computer readable media for critical updates for access points (APs), the apparatus of a first AP of a non-collocated AP MLD, the apparatus comprising processing circuitry configured to: set a value of a non-collocated AP MLD critical update flag subfield to indicate 1, if there is a change to a value in a basic service set (BSS) parameter change count subfield of a MLD parameters field in a reduced neighbor report element for a second AP, the second AP affiliated with the non-collocated AP MLD, where the first AP and the second AP have a setup link for a non-AP MLD associated with the non-collocated AP MLD, and where the first AP and the second AP are part of a different collocated sets, and the processing circuitry further configured to encode for transmission a capability information field, the capability information field comprising the critical update flag subfield.
H04W 60/04 - Rattachement à un réseau, p.ex. enregistrement; Suppression du rattachement à un réseau, p.ex. annulation de l'enregistrement utilisant des événements déclenchés
H04W 76/10 - Gestion de la connexion Établissement de la connexion
Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.
H01L 21/225 - Diffusion des impuretés, p.ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductrices; Redistribution des impuretés, p.ex. sans introduction ou sans élimination de matériau dopant supplémentaire en utilisant la diffusion dans ou hors d'un solide, à partir d'une ou en phase solide, p.ex. une couche d'oxyde dopée
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 21/266 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions en utilisant des masques
4.
FINE-GRAIN OBJECT SEGMENTATION IN VIDEO WITH DEEP FEATURES AND MULTI-LEVEL GRAPHICAL MODELS
Techniques related to automatically segmenting a video frame into fine grain object of interest and background regions using a ground truth segmentation of an object in a previous frame are discussed. Such techniques apply multiple levels of segmentation tracking and prediction based on color, shape, and motion of the segmentation to determine per-pixel object probabilities, and solve an energy summation model to generate a final segmentation for the video frame using the object probabilities.
A processor of an aspect includes a decode unit to decode an instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to determine that an attempted change due to the instruction, to a shadow stack pointer of a shadow stack, would cause the shadow stack pointer to exceed an allowed range. The execution unit is also to take an exception in response to determining that the attempted change to the shadow stack pointer would cause the shadow stack pointer to exceed the allowed range. Other processors, methods, systems, and instructions are disclosed.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
G06F 21/52 - Contrôle des usagers, programmes ou dispositifs de préservation de l’intégrité des plates-formes, p.ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p.ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données
G06F 12/1027 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p.ex. un répertoire de pages actives [TLB]
G06F 12/1081 - Traduction d'adresses pour accès périphérique à la mémoire principale, p.ex. accès direct en mémoire [DMA]
G06F 12/1045 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p.ex. un répertoire de pages actives [TLB] associée à une mémoire cache de données
G06F 12/14 - Protection contre l'utilisation non autorisée de mémoire
G06F 12/1036 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p.ex. un répertoire de pages actives [TLB] pour espaces adresse virtuels multiples, p.ex. segmentation
6.
DATA HANDLING FOR A RADIO ACCESS NETWORK CONTROLLER
A network processing device is connected to a host processor device and receives radio access network data on a network describing attributes of the radio access network (RAN). The network processing device further includes a classification engine to determine a priority level for the RAN data and identify a block of memory of the host processor device for the RAN data associated with the priority level. The classification engine generates a cache line in cache of the network processing device to store the RAN data, where the cache line is associated with the block of memory. The network processing device causes the cache line to be flushed to the block of memory with the RAN data based on the priority level.
The present disclosure is related to Intelligent Transport Systems (ITS), and in particular, to service dissemination basic services (SDBS) and/or collective perception service (CPS) of an ITS Station (ITS-S). Implementations of how the SDBS and/or CPS is arranged within the facilities layer of an ITS-S, different conditions for service dissemination messages (SDMs) and/or collective perception message (CPM) dissemination, and format and coding rules of the SDM/CPS generation are provided.
G08G 1/0967 - Systèmes impliquant la transmission d'informations pour les grands axes de circulation, p.ex. conditions météorologiques, limites de vitesse
G08G 1/14 - Systèmes de commande du trafic pour véhicules routiers indiquant des places libres individuelles dans des parcs de stationnement
H04W 4/40 - Services spécialement adaptés à des environnements, à des situations ou à des fins spécifiques pour les véhicules, p.ex. communication véhicule-piétons
8.
METHODS AND APPARATUS FOR IMMERSION COOLING SYSTEMS
Example method and apparatus, systems, and articles of manufacture for immersion cooling systems are disclosed herein. An example apparatus disclosed herein includes a tank to hold a coolant, an overflow chamber to direct the coolant toward an outlet, and a plate within the overflow chamber, the plate including a plurality of openings, the coolant to pass through at least one of the plurality of openings before reaching the outlet.
Embodiments described herein provide an apparatus comprising an interconnect switch configured to couple with a plurality of graphics processors via a plurality of point-to-point interconnects and one or more processors including a graphics processor coupled with the interconnect switch via a point-to-point interconnect of the plurality of point-to-point interconnects.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
10.
MICROELECTRONIC ASSEMBLY WITH UNDERFILL FLOW CONTROL
A microelectronic assembly comprises a first microelectronic component; a second microelectronic component under an area of the first microelectronic component and coupled to the first component through first interconnect structures within a central region of the area, and second interconnect structures within a peripheral region of the area, adjacent to the central region. A heterogenous dielectric surface on the first or second component or both and within a gap between the first and second components has a first surface composition within the central region and at least a second surface composition within the peripheral region.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
11.
ENHANCED SOUNDING REFERENCE SIGNAL (SRS) POWER CONTROL
A computer-readable storage medium stores instructions for execution by one or more processors of a UE to configure the UE for enhanced SRS power control in a 5G NR network, and to cause the base station to decode RRC signaling received from a base station of a plurality of base stations. The RRC signaling includes an SRS resource configuration. The SRS resource configuration includes at least one SRS resource set configured with a plurality of closed-loop power control states associated with a coherent joint transmission by the UE to the plurality of base stations. A plurality of SRSs is encoded for transmission to the plurality of base stations based on the SRS resource configuration. The plurality of SRSs including a first SRS encoded for transmission to the base station.
Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides a parallel processor comprising a processing cluster coupled with the cache memory. The processing cluster includes a plurality of multiprocessors coupled with a data interconnect, where a multiprocessor of the plurality of multiprocessors includes a tensor core configured to load tensor data and metadata associated with the tensor data from the cache memory, wherein the metadata indicates a first numerical transform applied to the tensor data, perform an inverse transform of the first numerical transform, perform a tensor operation on the tensor data after the inverse transform is performed, and write output of the tensor operation to a memory coupled with the processing cluster.
Embodiments are related to a fifth generation (5G) or sixth generation (6G) wireless communications system and network components to establish secure connections directly between user equipment and network functions in a core network of a 5G or 6G system. Other embodiments are described and claimed.
A graphical representation of an object (e.g., a 2D image) is transformed to a grid representation of the object. The grid representation adopts a structure of a grid. Graph nodes are extracted from the graphical representation and arranged based on the structure. An anchor node may be selected from the graph nodes and assigned to an element of the grid. Other graph nodes can be assigned to other elements of the grid based on their relationships with the anchor node. The grid representation can be processed by a CNN including one or more convolutional layers. A convolutional layer may receive the grid representation, generates variants of the grid representations, and extract features based on the variants. The output of the CNN can be used to determine a condition of the object, e.g., to generate a 3D graphical representation of the object that shows a pose of the object.
A computer model is trained with an architecture including additional training layers relative to the inference architecture. The architecture of a computer model to be used in inference includes a convolutional layer with a number of K × K convolutional filters. For training, the convolutional filters are expanded to a plurality of training layers including a layer with 1 × 1 and K × K filters. The expanded layers may include additional layers than the number of expanded filters in the layer of the inference model. The 1 × 1 expanded layer in training may learn weights for combining the K × K expanded layers, providing a weighted combination of the K ×K filters for the respective channel of the layer of the inference layer.
A computer model for object segmentation in images may be used for multiple input image sizes with shared convolutional layer parameters to be applied across application of the multiple image sizes. The model can also include size-specific parameters for one or more size-dependent layers, such as a normalization layer. The model may be trained with mixed-resolution training images in parallel in which the training image is resized to multiple sizes and the resulting predictions may learn the respective parameters in parallel based on an ensemble prediction as well as distillation from higher to lower resolution input image predictions.
G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
G06V 10/764 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant la classification, p.ex. des objets vidéo
G06V 10/774 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant l’intégration et la réduction de données, p.ex. analyse en composantes principales [PCA] ou analyse en composantes indépendantes [ ICA] ou cartes auto-organisatrices [SOM]; Séparation aveugle de source méthodes de Bootstrap, p.ex. "bagging” ou “boosting”
G06V 10/776 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant l’intégration et la réduction de données, p.ex. analyse en composantes principales [PCA] ou analyse en composantes indépendantes [ ICA] ou cartes auto-organisatrices [SOM]; Séparation aveugle de source Évaluation des performances
17.
APPARATUS AND METHOD FOR BOUNDING VOLUME HIERARCHY (BVH) CONSTRUCTION WITH STOCHASTIC PROCESSING
A method and apparatus for efficiently constructing a bounding volume hierarchy (BVH). For example, one embodiment of an apparatus comprises: a primitive sampler to identify a representative subset of input primitives of a graphics scene; bounding volume hierarchy (BVH) builder hardware logic to construct an approximate BVH based on the representative subset of input primitives; hardware logic to insert input primitives not in the representative subset into leaves of the approximate BVH; and the BVH builder or a different BVH builder to construct a final BVH based on the primitives inserted into the leaves of the approximate BVH.
Technologies for dynamically managing a batch size of packets include a network device. The network device is to receive, into a queue, packets from a remote node to be processed by the network device, determine a throughput provided by the network device while the packets are processed, determine whether the determined throughput satisfies a predefined condition, and adjust a batch size of packets in response to a determination that the determined throughput satisfies a predefined condition. The batch size is indicative of a threshold number of queued packets required to be present in the queue before the queued packets in the queue can be processed by the network device.
A non-Access Point Extremely High Throughput Station (non-AP EHT STA) initiates a Quality-of-Service (QoS) setup by sending a Stream Classification Service (SCS) Request frame to an associated access point (AP). The SCS request frame may be encoded to have a request type field set to “Add” and may contain an SCS Descriptor element having a traffic description field, a traffic classification field, and a Multi-Link Operation (MLO) field. The non-AP EHT STA may decode an SCS Response frame from the AP that indicate whether the QoS setup has been added. The non-AP EHT STA may then exchange a QoS traffic flow with the associated AP in accordance with the QoS setup when the QoS setup has been added. When the QoS traffic flow ends, the non-AP EHT STA may encode a second SCS Request frame for transmission to the AP with the request type field set to “Remove” to delete the QoS setup.
In one embodiment, a package substrate or main circuit board includes electrical connectors arranged in a compressed array pattern, wherein a distance between a connector and its neighboring connectors in a direction of compression is less than a distance between the connector and its neighboring connectors in other directions. The array pattern may be hexagonal or rectangular, and differential pairs of the electrical connectors may be arranged in the direction of compression.
A memory device comprising a memory cell comprising a storage element including a phase change memory; and a bilayer formed on a first side and a second side of the memory cell, the bilayer including an inner layer comprising a first nitride and an outer layer comprising a second nitride.
H01L 45/00 - Dispositifs à l'état solide spécialement adaptés pour le redressement, l'amplification, la production d'oscillations ou la commutation, sans barrière de potentiel ni barrière de surface, p.ex. triodes diélectriques; Dispositifs à effet Ovshinsky; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives
H01L 27/24 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants à l'état solide pour le redressement, l'amplification ou la commutation, sans barrière de potentiel ni barrière de surface
Techniques for instructions for min-max operations are described. An example apparatus comprises decoder circuitry to decode a single instruction, the single instruction to include fields for identifiers of a first source operand, a second source operand, an a destination operand, a field for an immediate operand, and a field for an opcode, the opcode to indicate execution circuitry is to perform a min-max operation, and execution circuitry to execute the decoded instruction according to the opcode to perform the min-max operation to determine a particular operation of five or more minimum and maximum operations in accordance with a value of the immediate operand, perform the determined particular operation on the identified first source operand and the identified second source operand to return a result, and store the result into the identified destination operand. Other examples are described and claimed.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
G06F 7/22 - Dispositions pour le tri ou l'interclassement de données de calculateur sur des supports d'enregistrement continus, p.ex. bande, tambour, disque
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p.ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
23.
SYSTEMS AND METHODS FOR MULTI-MODAL USER DEVICE AUTHENTICATION
Systems and methods for multi-modal user device authentication are disclosed. An example electronic device includes a first sensor, a microphone, a first camera, and a confidence analyzer to authenticate a subject as the authorized user in response to a user presence detection analyzer detecting a presence of the subject and one or more of (a) an audio data analyzer detecting a voice of an authorized user or (b) an image data analyzer detecting a feature of the authorized user. The example electronic device includes a processor to cause the electronic device to move from a first power state to a second power state in response to the confidence analyzer authenticating the user as the authorized user. The electronic device is to consume a greater amount of power in the second power state than the first power state.
A mechanism is described for facilitating the transfer of features learned by a user-independent pre-trained deep neural network to a user-dependent neural network. The mechanism includes extracting a feature learned by a first deep neural network (DNN) model via the framework, wherein the first DNN model is a pre-trained DNN model for computer vision to enable user-independent classification of an object within an input video frame and training, via the deep learning framework, a second DNN model for computer vision based on the extracted feature, the second DNN model an update of the first DNN model, wherein training the second DNN model includes training the second DNN model based on a dataset including user-dependent data.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06N 3/084 - Rétropropagation, p.ex. suivant l’algorithme du gradient
G06F 9/46 - Dispositions pour la multiprogrammation
G06V 10/94 - Architectures logicielles ou matérielles spécialement adaptées à la compréhension d’images ou de vidéos
G06V 10/44 - Extraction de caractéristiques locales par analyse des parties du motif, p.ex. par détection d’arêtes, de contours, de boucles, d’angles, de barres ou d’intersections; Analyse de connectivité, p.ex. de composantes connectées
G06V 20/00 - RECONNAISSANCE OU COMPRÉHENSION D’IMAGES OU DE VIDÉOS Éléments spécifiques à la scène
G06F 18/214 - Génération de motifs d'entraînement; Procédés de Bootstrapping, p.ex. ”bagging” ou ”boosting”
G06F 18/2411 - Techniques de classification relatives au modèle de classification, p.ex. approches paramétriques ou non paramétriques basées sur la proximité d’une surface de décision, p.ex. machines à vecteurs de support
G06F 18/2413 - Techniques de classification relatives au modèle de classification, p.ex. approches paramétriques ou non paramétriques basées sur les distances des motifs d'entraînement ou de référence
G06N 3/044 - Réseaux récurrents, p.ex. réseaux de Hopfield
G06V 10/764 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant la classification, p.ex. des objets vidéo
G06V 10/774 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant l’intégration et la réduction de données, p.ex. analyse en composantes principales [PCA] ou analyse en composantes indépendantes [ ICA] ou cartes auto-organisatrices [SOM]; Séparation aveugle de source méthodes de Bootstrap, p.ex. "bagging” ou “boosting”
G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
25.
NATURAL HUMAN-COMPUTER INTERACTION FOR VIRTUAL PERSONAL ASSISTANT SYSTEMS
Technologies for natural language interactions with virtual personal assistant systems include a computing device configured to capture audio input, distort the audio input to produce a number of distorted audio variations, and perform speech recognition on the audio input and the distorted audio variants. The computing device selects a result from a large number of potential speech recognition results based on contextual information. The computing device may measure a user's engagement level by using an eye tracking sensor to determine whether the user is visually focused on an avatar rendered by the virtual personal assistant. The avatar may be rendered in a disengaged state, a ready state, or an engaged state based on the user engagement level. The avatar may be rendered as semitransparent in the disengaged state, and the transparency may be reduced in the ready state or the engaged state. Other embodiments are described and claimed.
A fused dot-product multiply-accumulate (MAC) circuit may support variable precisions of floating-point data elements to perform computations (e.g., MAC operations) in deep learning operations. An operation mode of the circuit may be selected based on the precision of an input element. The operation mode may be a FP16 mode or a FP8 mode. In the FP8 mode, product exponents may be computed based on exponents of floating-point input elements. A maximum exponent may be selected from the one or more product exponents. A global maximum exponent may be selected from a plurality of maximum exponents. A product mantissa may be computed and aligned with another product mantissa based on a difference between the global maximum exponent and a corresponding maximum exponent. An adder tree may accumulate the aligned product mantissas and compute a partial sum mantissa. The partial sum mantissa may be normalized using the global maximum exponent.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G06F 5/01 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour le décalage, p.ex. la justification, le changement d'échelle, la normalisation
Examples described herein relate to an interface and circuitry coupled to the interface. The circuitry can provide an endpoint for a Datagram Transport Layer Security (DTLS) connection with a first network interface device, provide an endpoint for a second DTLS connection with a second network interface device, provide a transport layer endpoint for the packets received from the first network interface device, and provide a second transport layer endpoint for the packets received from the second network interface device.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
Apparatus and method for efficient BVH construction. For example, one embodiment of an apparatus comprises: a memory to store graphics data for a scene including a plurality of primitives in a scene at a first precision; a geometry quantizer to read vertices of the primitives at the first precision and to adaptively quantize the vertices of the primitives to a second precision associated with a first local coordinate grid of a first BVH node positioned within a global coordinate grid, the second precision lower than the first precision; a BVH builder to determine coordinates of child nodes of the first BVH node by performing non-spatial-split binning or spatial-split binning for the first BVH node using primitives associated with the first BVH node, the BVH builder to determine final coordinates for the child nodes based, at least in part, on an evaluation of surface areas of different bounding boxes generated for each of the child node.
Examples described herein relate to an interface and circuitry coupled to the interface. The circuitry can provide an endpoint for a PSP Security Protocol (PSP) connection to a first network interface device, provide an endpoint for a second PSP connection with a second network interface device, provide a transport layer endpoint for the packets received from the first network interface device, and provide a second transport layer endpoint for the packets received from the second network interface device.
Examples described herein relate to a system. In some examples, the system includes an interface and circuitry, coupled to the interface. In some examples, the circuitry, when operational, is to: based on detection of multiple management controllers, select a primary management controller and a secondary management controller from among the multiple management controllers. In some examples, the primary management controller is to perform at least one different operation than that of the secondary management controller, the primary management controller comprises a baseboard management controller (BMC), the secondary management controller comprises a BMC, and the multiple management controllers are positioned in at least one programmable network interface device and a host system.
G05B 19/042 - Commande à programme autre que la commande numérique, c.à d. dans des automatismes à séquence ou dans des automates à logique utilisant des processeurs numériques
31.
Fabric Die to Fabric Die Interconnect for Modularized Integrated Circuit Devices
The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.
H01L 23/528 - Configuration de la structure d'interconnexion
H03K 19/17704 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle les fonctions logiques étant réalisées par l'interconnexion des lignes et des colonnes
H01L 23/498 - Connexions électriques sur des substrats isolants
32.
AN EDGE-TO-DATACENTER APPROACH TO WORKLOAD MIGRATION
Methods, apparatus, systems, and articles of manufacture to migrate cloud-based workloads are disclosed. An example instructions cause one or more processors to at least execute the instructions to: intercept a call to identify a requested domain to a server; adjust the domain; in response to determining that the adjusted domain resolves, transmit a request to execute a workload scheduled to be executed at the server; load a container corresponding to the workload based on a response from the server; and route a target internet protocol (IP) address resolved by the request domain to the locally loaded container.
Systems and techniques for a System-on-a-Chip (SoC) security plugin are described herein. A component message may be received at an interconnect endpoint from an SoC component. The interconnect endpoint may pass the component message to a security component via a security interlink. The security component may secure the component message, using a cryptographic engine, to create a secured message. The secured message is delivered back to the interconnect endpoint via the security interlink and transmitted across the interconnect by the interconnect endpoint.
G06F 21/72 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits de cryptographie
G09C 1/00 - Appareils ou méthodes au moyen desquels une suite donnée de signes, p.ex. un texte intelligible, est transformée en une suite de signes inintelligibles en transposant les signes ou groupes de signes ou en les remplaçant par d'autres suivant un systèm
G06F 21/85 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs d’interconnexion, p.ex. les dispositifs connectés à un bus ou les dispositifs en ligne
H04L 9/06 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p.ex. système DES
Various examples relate to an apparatus, a device, a method, a computer program, and a non-transitory computer-readable medium for a computer system, to a computer system and to a system. The apparatus comprises interface circuitry, machine-readable instructions, and a processor to execute the machine-readable instructions to obtain a request to perform remote attestation for a trusted execution environment from an application running in the trusted execution environment of the processor, communicate with at least one remote attestation caching server based on the request to perform remote attestation, wherein the communication with the remote attestation caching server comprises providing a plurality of requests to the remote attestation server and obtaining a plurality of responses from the remote attestation caching server, and provide a result of the remote attestation request to the application running in the trusted execution environment after having completed the communication with the remote attestation server.
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache
35.
TRAINING NEURAL NETWORK TROUGH DENSE-CONNECTION BASED KNOWLEGE DISTILLATION
A neural network can be trained through knowledge distillation. A support neural network is generated based on a target neural network. The support neural network is a teacher model, and the target neural network is a student model. The support neural network may have same layers as the target neural networks. Some or all layers of the support neural network may be connected to facilitate data transfer between these layers. The support neural network and target neural network are merged into a merged network. The merged network is trained. At least one layer in the support neural network is connected to a layer in the target neural network to facilitate data transfer from the target neural network to the support neural network during the training. After the training, the target neural network is separated from the merged network and can be used to perform machine learning tasks.
A convolutional layer of a computer model generates a dynamic convolutional filter based on the input feature map of the convolutional layer. The convolutional layer includes an attention model that generates a set of attention weights to dynamically adjust the convolutional filter applied by the model based on the input to the convolutional layer. The attention weights are generated with respect to multiple dimensions, which may include spatial position, input channel, output channel, and a respective combination of a set of static convolutional filters. The weights be generated with respect to each of the static convolutional filters, such that the different types (i.e., dimensions) of the weights may be applied element-wise to the respective convolutional filters and the filters, after application of the weights, may then be combined to generate the dynamic convolutional filter.
A PG Conv layer extract features from grid-structured data samples. The PGConv layer may receive an input feature map including a grid representation of an object, which is generated from a graph representation of the object. The grid representation includes node elements that are arranged in a grid pattern. The PGConv layer may perform padding on the grid representation. The result of the padding is an IFM that includes the node elements and the additional node elements. An additional node element may have a value of zero or a value of a node element in the grid representation. The PGConv layer may also generate an attentive kernel that includes attentive weights determined based on the IFM. The PGConv layer may generate a dynamic kernel based on the attentive kernel and a convolutional kernel generated through training. The PGConv layer may further perform MAC operations on the IFM and the dynamic kernel and generate an OFM.
An apparatus of a Radio Unit device (RU) of an Open Radio Access Network (O-RAN) architecture, a method to be performed at the RU, and a computer-readable medium to perform operations at the RU. The apparatus includes a communication interface, and processing circuitry coupled to the communication interface, the processing circuitry to: make a determination, using one or more low power procedures at the RU, to enter or to exit a low power mode of the RU; and encode for transmission, to a device of the O-RAN including at least one of a Central Unit (CU) or a Distributed Unit (DU) (CU/DU), information on the determination.
The various implementations described herein include methods and devices for preventing unauthorized access to files and networks. In one aspect, a method includes installing a first application at a computing device, the first application designated as writing to user files. Installing the first application includes: (i) storing application data files for the first application within a first portion of the memory, where files stored in the first portion are designated as read-only for the first application; and (ii) allocating a second portion of the memory for user data files to be used by the first application. The method further includes installing a second application at the computing device, the second application designated as writing to application data files. Installing the second application includes: (i) allocating a third portion of the memory for prototype writable application data files; and (ii) allocating a fourth portion of the memory for network-based data access.
G06F 21/00 - Dispositions de sécurité pour protéger les calculateurs, leurs composants, les programmes ou les données contre une activité non autorisée
G06F 21/62 - Protection de l’accès à des données via une plate-forme, p.ex. par clés ou règles de contrôle de l’accès
A request is received over a link that requests a particular line in memory. A directory state record is identified in memory that identifies a directory state of the particular line. A type of the request is identified from the request. It is determined that the directory state of the particular line is to change from the particular state to a new state based on the directory state of the particular line and the type of the request. The directory state record is changed, in response to receipt of the request, to reflect the new state. A copy of the particular line is sent in response to the request
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G06F 12/0808 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec moyen d'invalidation de mémoires cache
G06F 12/0817 - Protocoles de cohérence de mémoire cache à l’aide de méthodes de répertoire
G06F 12/128 - Commande de remplacement utilisant des algorithmes de remplacement adaptée aux systèmes de mémoires cache multidimensionnelles, p.ex. associatives d’ensemble, à plusieurs mémoires cache, multi-ensembles ou multi-niveaux
Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.
H03K 19/17736 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels des ressources de routage
H03K 19/17796 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels pour l'adaptation des paramètres physiques pour la disposition physique des blocs
H04L 41/5019 - Pratiques de respect de l’accord du niveau de service
Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 23/16 - Matériaux de remplissage ou pièces auxiliaires dans le conteneur, p.ex. anneaux de centrage
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H05K 1/11 - Eléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
Techniques for maintaining service continuity in a 5G NR network in communication with a MEC system and an edge application (EDGEAPP) system are disclosed. A notification message originating from a service management function (SMF) of a core network (CN) is decoded at a network exposure function (NEF) of the CN. The notification message includes a UE IP address change of a UE. A private IP address of the UE is determined based on the UE IP address change. A query with the private IP address is encoded for transmission to a NAT server. A response from the NAT server is decoded. The response includes a public IP address and a UE ID of the UE. The public IP address corresponds to the private IP address. A tuple including the UE ID, the public IP address, and the private IP address is generated at the NEF.
A graphics processor can include a processing cluster array including a plurality of processing clusters coupled with the plurality of memory controllers, each processing cluster of the plurality of processing clusters including a plurality of streaming multiprocessors, the processing cluster array configured for partitioning into a plurality of partitions. The plurality of partitions include a first partition including a first plurality of streaming multiprocessors configured to perform operations for a first neural network, The operations for the first neural network are isolated to the first partition. The plurality of partitions also include a second partition including a second plurality of streaming multiprocessors configured to perform operations for a second neural network. The operations for the second neural network are isolated to the second partition and protected from operations performed for the first neural network.
G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
G06F 16/783 - Recherche de données caractérisée par l’utilisation de métadonnées, p.ex. de métadonnées ne provenant pas du contenu ou de métadonnées générées manuellement utilisant des métadonnées provenant automatiquement du contenu
G06F 16/583 - Recherche caractérisée par l’utilisation de métadonnées, p.ex. de métadonnées ne provenant pas du contenu ou de métadonnées générées manuellement utilisant des métadonnées provenant automatiquement du contenu
G06V 10/94 - Architectures logicielles ou matérielles spécialement adaptées à la compréhension d’images ou de vidéos
G06V 40/10 - Corps d’êtres humains ou d’animaux, p.ex. occupants de véhicules automobiles ou piétons; Parties du corps, p.ex. mains
G06V 40/20 - Mouvements ou comportement, p.ex. reconnaissance des gestes
G06F 18/2413 - Techniques de classification relatives au modèle de classification, p.ex. approches paramétriques ou non paramétriques basées sur les distances des motifs d'entraînement ou de référence
G06V 10/764 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant la classification, p.ex. des objets vidéo
The present disclosure is generally related to artificial intelligence (AI) and/or machine learning (ML) workflows including ML entity lifecycle management and reporting mechanisms for reporting the validation performance of an ML entity. An ML training (MLT) function trains an ML model using a training dataset and may validate the ML model using a validation dataset. An MLT report is generated, which includes an attribute indicating the performance of the ML model when performing on training data. To support the ML model validation performance reporting, an attribute is defined in the MLT report to indicate the performance of the ML model when performing on the validation data. The attribute may be a new attribute or an extension/enhancement of an existing attribute in the MLT training report.
Systems, apparatuses and methods may provide for chip technology including a memory structure having stored weights associated with a machine learning (ML) model, a plurality of digital temperature sensors to generate readings, and a classification engine to retrieve the stored weights from the memory structure and adjust the readings from the plurality of digital temperature sensors based on the weights and electrical parameters associated with the chip.
Techniques are provided herein for forming multi-tier memory structures with graded characteristics across different tiers. A given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. Certain geometric or material parameters of the memory structures can be altered in a graded fashion across any number of tiers to compensate for process effects that occur when fabricating a given tier, which also affect any lower tiers. This may be done to more closely match the performance of the memory arrays across each of the tiers.
Techniques are provided herein for forming thin film transistor (TFT) structures having one or more doped contact regions. The addition of certain dopants can be used to increase conductivity and provide higher thermal stability in the contact regions of the TFT. Memory structures having TFT structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the TFT structures within the memory structures may include one or more contacts that are doped with additional elements. The doping profile of the contacts can be tuned to optimize performance, stability, and reliability of the TFT structure. Furthermore, additional doping may be performed within the area beneath the contacts and extending into the semiconductor region.
Techniques are provided herein for forming thin film transistor structures having a laterally recessed gate electrode. The gate electrode may be recessed such that it does not extend under one or both conductive contacts of the transistor. Recessing the lateral dimensions of the gate electrode can reduce gate leakage current and parasitic capacitance. According to an example, a given memory structure generally includes memory cells, with each memory cell having an access device and a storage device. According to some such embodiments, the memory cells are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory cell arrays are formed within the interconnect region. Any of the given TFT structures may include a gate electrode that is laterally recessed such that one or more of the contacts are not directly over the gate electrode.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
51.
ASYMMETRIC SOURCE AND DRAIN CONTACTS FOR A THIN FILM TRANSISTOR (TFT) STRUCTURE
Techniques are provided for making asymmetric contacts to improve the performance of thin film transistors (TFT) structures. The asymmetry may be with respect to the area of contact interface with the semiconductor region and/or the depth to which the contacts extend into the semiconductor region. According to some embodiments, the TFT structures are used in memory structures arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include asymmetric contacts, such as two contacts that each have a different contact area to a semiconductor region, and/or that extend to different depths within the semiconductor region. The degree of asymmetry may be tuned during fabrication to modulate certain transistor parameters such as, for example, leakage, capacitance, gate control, channel length, or contact resistance.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
52.
INLINE CIRCUIT EDIT FOR BACKSIDE POWER DELIVERY WITH DEEP VIA
Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a device layer including a plurality of transistor structures. A front-end routing layer is above the device layer, the front-end routing layer coupled to one or more of the plurality of transistors. A backside metal structure is below the device layer. A conductive feedthrough structure is directly coupling the backside metal structure to the front-end routing layer.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a plurality of conductive lines in a dielectric layer, individual ones of the plurality of conductive lines along a direction and spaced at a same interval. A conductive structure is in the dielectric layer, the conductive structure laterally between but not in contact with a pair of the plurality of conductive lines.
Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a device layer including a plurality of transistor structures. A front-end routing layer is above the device layer, the front-end routing layer coupled to one or more of the plurality of transistors. A backside metal structure is below the device layer. A conductive feedthrough structure is directly coupling the backside metal structure to the front-end routing layer. The conductive feedthrough structure is a monolithic structure extending through the device layer.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a plurality of conductive structures along corresponding ones of a plurality of line tracks along a first direction. The integrated circuit structure also includes a white space track included within the plurality of line tracks, the white space track having a width along a second direction greater than a width of an individual one of the plurality of line tracks, the second direction orthogonal to the first direction. A conductive structure is along the white space track.
A first printed circuit board (PCB) comprises a first hardware interface, compatible with an interface standard, to couple the first PCB to a first socket of a second PCB, which further comprises a second socket, and first and second busses respectively coupled to the first and second sockets. The first PCB comprises a second hardware interface to communicate a first signal, to indicate a total current drawn by multiple PCBs, and a second signal each with a third PCB while the third PCB is coupled to the second PCB at the second socket. The first PCB comprises circuitry to impose a limit on power consumption by the first PCB, circuitry to generate, with the third PCB, the first signal, and circuitry to generate a second signal, which is to provide, for each of the multiple PCBs, an indication of whether respective circuitry of the PCB is to be throttled.
Memory devices having optimized phase change memory (PCM) structures to improve nucleation time variation and methods for forming the phase change memory structures. The PCM structures are composed of layers including a first electrode layer, a PCM layer having a first interface with the first electrode layer comprising a first electrode/PCM interface, and a second electrode layer, having a second interface with the phase change material layer comprising a PCM/second electrode interface. The first electrode/PCM interface and the PCM/second electrode interface are non-flat and configured to reduce statistical variation of nucleation time. Techniques/processes for forming these interfaces include creating serrated or rough edges, forming patterned shapes, and attaching nanodots. The average contact angle of heterogenous nucleation is significantly reduced from the flat surface used in conventional PCM structures, enabling the new PCM structure to exhibit a more controlled nucleation time with less statistical variation.
H01L 45/00 - Dispositifs à l'état solide spécialement adaptés pour le redressement, l'amplification, la production d'oscillations ou la commutation, sans barrière de potentiel ni barrière de surface, p.ex. triodes diélectriques; Dispositifs à effet Ovshinsky; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives
H01L 27/24 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants à l'état solide pour le redressement, l'amplification ou la commutation, sans barrière de potentiel ni barrière de surface
Various examples relate to methods, computer programs, non-transitory computer-readable media, apparatuses, devices, computer systems, and a system for evaluating one or more hardware tracing records related to a hardware tracing operation or for processing a piece of software. A method for evaluating one or more hardware tracing records related to a hardware tracing operation comprises obtaining a hardware tracing record, the hardware tracing record comprising a custom information and a memory address within a deterministic distance of an instruction having triggered the hardware tracing record, identifying, based on the memory address within the deterministic distance of the instruction having triggered the hardware tracing record, a binary module containing the instruction, determining, whether a pre-defined identifier is stored at a pre-defined memory address range relative to the memory address within the deterministic distance of the instruction in the binary module, and processing information on the hardware tracing record if the pre-defined identifier is stored at the pre-defined memory address range relative to the memory address within the deterministic distance of the instruction.
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
60.
BLOCK-WISE PRUNING OF WEIGHTS IN DEEP NEURAL NETWORK
Weights can be pruned during DNN training to increase sparsity in the weights and reduce the amount of computation required for performing the deep learning operations in DNNs. A DNN layer may have one or more weight tensors corresponding to one or more output channels of the layer. A weight tensor has weights, the values of which are determined by training the DNN. A weight tensor may have a dimension corresponding to the input channels of the layer. The weight tensor may be partitioned into subtensors, each of which has a subset of the input channels. The subtensor may have the same number of input channels. One or more subtensors may be selected, e.g., based on the weights in the one or more subtensors. The weights in a selected subtensor are pruned, e.g., changed to zeros. The weights in an unselected subtensor may be modified by further training the DNN.
The present disclosure provides mechanisms to support collection of measurements data to support radio access network (RAN) intelligence. The present disclosure contains concepts, use cases, requirements, and solutions for collecting the measurement data to support artificial intelligence (AI) and/or machine learning (ML) enabled RAN, wherein the AI/ML functions reside in the RAN, a network function(s), management function(s), and/or in an Operation, Administration, and Maintenance function(s).
An apparatus and system of providing a service-based architecture in a 6G system are described. Control plane details are provided for a central unit¬ control plane (CU-CP) of a next generation NodeB (xNB) that has direct access to network functions (NFs) over a service based interface (SBI). Protocol details for distributed non-access stratum (NAS) and hypertext transfer protocol (HTTP) messages between a user equipment (UE) and NF are provided. In addition, details for enhanced distributed unit (eDU) are provided to support multiple distributed user plane (UP) entities and corresponding UP configuration for a UE.
H04W 92/14 - Interfaces entre des dispositifs formant réseau hiérarchiquement différents entre des contrôleurs de points d'accès et un dispositif formant réseau fédérateur
63.
FLEXIBLE PROVISIONING OF COHERENT MEMORY ADDRESS DECODERS IN HARDWARE
Embodiments of apparatuses, methods, and systems for flexible provisioning of coherent memory address decoders in hardware are disclosed. In an embodiment, an apparatus includes a plurality of address decoders and a plurality of configuration storage locations. Each of the configuration storage locations corresponds to one of the plurality of address decoders to configure the corresponding one of the plurality of address decoders to decode based on a corresponding one of a plurality of decode rules. Each of the plurality of configuration storage locations is allocated to one of a plurality of memory tiers.
An electronic system includes a first substrate including first solder bumps on a bottom surface, the first solder bumps having a first solder bump surface opposite from the bottom surface; a processor integrated circuit (IC) die including at least one processor mounted on a top surface of the first substrate; and a companion component to the processor IC. The companion component includes a second substrate, second solder bumps, and third solder bumps. The second solder bumps include a second solder bump surface, and the third solder bumps include a third solder bump surface at a different height than the second solder bump surface. The second solder bump surface contacts the top surface of the first substrate and the third solder bump surface is at a same height as the first solder bump surface.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
65.
DIELECTRIC SIDEWALL FEATURES FOR TUNING THIN FILM TRANSISTOR (TFT) PARASITICS
Techniques are provided herein for forming transistor devices with reduced parasitic capacitance, such as transistors used in a memory structure. In an example, a given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT), and the storage device may include a capacitor. Any of the given TFTs may include a dielectric liner extending along sidewalls of the TFT. The TFT includes a recess (e.g., a dimple) that extends laterally inwards toward a midpoint of a semiconductor region of the TFT. The dielectric liner thus also pinches or otherwise extends inward. This pinched-in dielectric liner may reduce parasitic capacitance between the contacts of the TFT and the gate electrode of the TFT. The pinched-in dielectric liner may also protect the contacts from forming too deep into the semiconductor region.
Techniques for forming thin film transistors (TFTs) having multilayer contact structures. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, and a conductive contact that contacts at least a portion of the semiconductor region. In some other cases, the conductive contact comprises a multilayer structure having at least a first material layer on the at least a portion of the semiconductor region, at least a second material layer on the first material layer, and a conductive fill material over the first and second material layers. In some other cases, the conductive contact comprises a multilayer structure having (1) a graded material layer on the at least a portion of the semiconductor region and (2) a conductive fill material over the graded material layer, wherein the graded material layer comprises a concentration gradient of a given element.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
67.
MULTI-LAYERED OR GRADED SEMICONDUCTOR REGION IN THIN FILM TRANSISTOR (TFT) STRUCTURES
Techniques for forming thin film transistors (TFTs) having multilayer and/or concentration gradient semiconductor regions. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, and a semiconductor region on the gate dielectric. In some cases, the semiconductor region includes a plurality of compositionally different material layers, at least two layers of the different material layers each being a semiconductor layer. In some other cases, the semiconductor region includes a single layer having a material concentration gradient extending from a bottom surface of the single layer (adjacent to the gate dielectric) to a top surface of the single layer. The integrated circuit further includes first and second conductive contacts that each contact a respective portion of the semiconductor region. One example application of the techniques is with respect to forming backend (within the interconnect region) memory structures configured with multilayer and/or concentration gradient TFTs.
Techniques are provided herein for forming thin film transistor structures having co-doped semiconductor regions. The addition of insulating dopants can be used to improve the performance, stability, and reliability of the TFT. A given TFT structure within an array of similar TFT structures formed in an interconnect region may include a semiconductor region that is co-doped with one or more additional elements. The doping profile can be tuned to optimize performance, stability, and reliability of the TFT structure. In some embodiments, the doping profile causes an overall reduction in the conductivity of the semiconductor region, leading to a higher threshold voltage. Designing access devices (in, for example, a DRAM architecture) with higher threshold voltages can be beneficial for improving reliability of the memory cell.
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
Techniques are provided herein for forming thin film transistor structures having a multilayer and/or concentration gradient gate dielectric. Such a gate dielectric can be used, to tune the performance and/or reliability of the transistor. According to some such embodiments, memory structures having thin film transistor (TFT) structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include a multilayer and/or graded gate dielectric that includes at least two or more different dielectric layers and/or a material concentration gradient through a thickness of the gate dielectric.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
70.
DIE STACKING PACKAGE ARCHITECTURE FOR HIGH-SPEED INPUT/OUTPUT WITH THROUGH-DIELECTRIC VIAS
Embodiments of a microelectronic assembly comprise a package substrate, a first integrated circuit (IC) die, a second IC die between the first IC die and the package substrate, a dielectric material between the first IC die and the package substrate, and a plurality of vias through the dielectric material, the vias coupling the first IC die and the package substrate. The microelectronic assembly is in a space defined by three mutually orthogonal axes, a first axis, a second axis and a third axis; the package substrate, the first IC die and the second IC die are mutually parallel in first planes defined by the first axis and the third axis; the vias are in one or more second planes defined by the second axis and the third axis; and the vias are inclined at an angle not equal to ninety degrees around the first axis.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
71.
PROVISIONING A REFERENCE VOLTAGE BASED ON AN EVALUATION OF A PSEUDO-PRECISION RESISTOR OF AN IC DIE
Techniques and mechanisms for determining a reference voltage which is to be provided with an integrated circuit (IC) die. In an embodiment, the IC die comprises a resistor, and a hardware interface which accommodates coupling of the IC die to a test unit. The test unit provides functionality to perform an evaluation of a resistance of the resistor, wherein said resistance is indicative of the respective resistances of one or more other resistors of the IC die. Based on the evaluation, the test unit provides to the IC die an indication of a scale factor, wherein the reference voltage is generated based on the scale factor. In another embodiment, the IC die further comprises an amplifier circuit which receives the reference voltage, wherein a variable resistance circuit of the IC die is configured based on an output of the amplifier circuit.
The present disclosure is directed to a reinforcement system including: a framed pellicle including: a center part of a pellicle surrounded by a peripheral part of the pellicle, wherein the peripheral part is adhered to a pellicle frame; and an edge reinforcement for reinforcing the framed pellicle, positioned at a boundary between the center part of the framed pellicle and the pellicle frame.
G03F 1/64 - Pellicules, p.ex. assemblage de pellicules ayant une membrane sur un cadre de support; Leur préparation caractérisés par les cadres, p.ex. du point de vue de leur structure ou de leur matériau
G01L 1/14 - Mesure des forces ou des contraintes, en général en mesurant les variations de la capacité ou de l'inductance des éléments électriques, p.ex. en mesurant les variations de fréquence des oscillateurs électriques
G01P 13/00 - Indication ou enregistrement de l'existence ou de l'absence d'un mouvement; Indication ou enregistrement de la direction d'un mouvement
G01L 1/16 - Mesure des forces ou des contraintes, en général en utilisant les propriétés des dispositifs piézo-électriques
G01P 15/00 - Mesure de l'accélération; Mesure de la décélération; Mesure des chocs, c. à d. d'une variation brusque de l'accélération
Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a first conductive line and a second conductive line in a first dielectric layer, the second conductive line laterally spaced apart from the first conductive line. The integrated circuit structure also includes a first conductive via and a second conductive via in a second dielectric layer, the second dielectric layer over the first dielectric layer, the second conductive via laterally spaced apart from the first conductive via, the first conductive via vertically over and connected to the first conductive line, and the second conductive via vertically over but separated from the second conductive line.
Microstrip routing circuits with dielectric films are disclosed. A disclosed example apparatus includes a substrate, the substrate having a first side and a second side opposite the first side, the first side and the second side defining a height of the substrate, traces on the first side of the substrate, and a dielectric film positioned on the first side to cover at least a portion of the traces.
H01P 11/00 - Appareils ou procédés spécialement adaptés à la fabrication de guides d'ondes, résonateurs, lignes ou autres dispositifs du type guide d'ondes
H05K 1/03 - Emploi de matériaux pour réaliser le substrat
H05K 3/28 - Application de revêtements de protection non métalliques
75.
DETECTION AND CALCULATION OF HEART RATE RECOVERY IN NON-CLINICAL SETTINGS
A wearable device measures heart rate recovery of a user in a non-clinical setting. The wearable device comprises a heart rate detector configured to detect heart rate data of the user, an activity sensor configured to detect motion of the user, and a processor. The processor is configured to identify a start of an activity by the user using the motion detected by the activity sensor. Responsive to detecting the start of the activity, the processor monitors the motion detected by the activity sensor to identify an end of the activity. A regression analysis is performed on heart rate data detected by the heart rate detector during a period of time after the end of the activity, and the heart rate recovery of the user is determined using the regression analysis.
Examples described herein relate to multiple processor nodes which are physically separate with interfaces to a common network interface. A local processor can run a timing recovery algorithm, and tune the master timer to align with the network domain to cause the master timer and network timing domains to be in the same domain. A common master timer can be used to align time stamps of independent processor nodes. A processor node can use the common master timer as a reference and the processor does not need to communicate with another processor to synchronize its timer.
G06F 1/14 - Dispositions pour le contrôle du temps, p.ex. horloge temps réel
H04L 43/106 - Surveillance active, p.ex. battement de cœur, utilitaire Ping ou trace-route en utilisant des informations liées au temps dans des paquets, p.ex. en ajoutant des horodatages
Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.
An apparatus to facilitate computing efficient cross channel operations in parallel computing machines using systolic arrays is disclosed. The apparatus includes a plurality of registers and one or more processing elements communicably coupled to the plurality of registers. The one or more processing elements include a systolic array circuit to perform cross-channel operations on source data received from a single source register of the plurality of registers, wherein the systolic array circuit is modified to: receive inputs from the single source register at different stages of the systolic array circuit; perform cross-channel operations at channels of the systolic array circuit; bypass disabled channels of the systolic array circuit, the disabled channels not used to compute the cross-channel operations; and broadcast a final result of a final stage of the systolic array circuit to all channels of a destination register.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p.ex. plusieurs processeurs de données à instruction unique
79.
METHOD AND SYSTEM OF IMAGE HASHING OBJECT DETECTION FOR IMAGE PROCESSING
A method and system of image hashing object detection for image processing are provided. The method comprises the following steps: obtaining image head class input data and image tail class input data differentiated from the head class input data and respectively of two images each of an object to be classified; respectively inputting the head and tail class input data into two separate parallel representation neural networks being trained to respectively generate head and tail features, wherein the representation neural networks share at least some representation weights used to form the head and tail features; inputting the head and tail features into at least one classifier neural network to generate class-related data; generating a class-balanced loss of at least one of the classes of the class-related data comprising factoring an effective number of samples of individual classes; and rebalancing an output sample distribution among the classes at the representation neural networks, classifier neural networks, or both by using the class-balanced loss.
G06V 10/764 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant la classification, p.ex. des objets vidéo
G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
G06V 10/776 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant l’intégration et la réduction de données, p.ex. analyse en composantes principales [PCA] ou analyse en composantes indépendantes [ ICA] ou cartes auto-organisatrices [SOM]; Séparation aveugle de source Évaluation des performances
Methods, apparatuses, and computer readable media for non-collocated AP multi-link devices (MLD) transition, where an apparatus of a non-collocated AP MLD comprises processing circuitry configured to: encode a management frame, the management frame comprising a neighbor report element, the neighbor report element including a recommended AP field and a multi-link element, the recommended AP field indicating an identification of a recommended AP, the multi-link element comprising a collocated AP MLD field, the collocated AP MLD field indicating an identification of a collocated AP MLD, where the recommended AP is affiliated with the collocated AP MLD, and where the processing circuitry is further configured to: configure the non-collocated AP MLD to transmit the management frame to a non-AP MLD.
Examples described herein relate to a in a group of servers: the servers attempting to perform timing synchronization based on a first group of timing signals sent via a first path. In some examples, the first comprises a first connection and based on disruption of communications by the first connection between servers in the group of servers. In some examples, the servers attempting to perform timing synchronization based on a second group of timing signals sent via a second path. In some examples, the second path does not traverse the first connection.
An inter-die double data rate (DDR) data transfer scheme is provided. In particular, the data transfer scheme utilizes an error correction code (ECC) encoding scheme that exploits the DDR property that a single microbump defect can only yield four possible error scenarios. A specialized single error correcting, double error detecting, and double adjacent error correcting (SEC-DED-DAEC) encoding scheme that imposes at least four parity check matrix constraints may be used. Configured and operated in this way, a fewer number of parity check bits are required to detect data bit errors associated with a single defective microbump.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
H03M 13/29 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes combinant plusieurs codes ou structures de codes, p.ex. codes de produits, codes de produits généralisés, codes concaténés, codes interne et externe
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
83.
PROGRAM EXECUTION STRATEGIES FOR HETEROGENEOUS COMPUTING SYSTEMS
An offload analyzer analyzes a program for porting to a heterogenous computing system by identifying code objects for offloading to an accelerator. Runtime metrics generated by executing the program on a host processor unit are provided to an accelerator model that models the performance of the accelerator and generates estimated accelerator metrics for the program. A code object offload selector selects code objects for offloading based on whether estimated accelerated times of the code objects, which comprise estimated accelerator times and offload overhead times, are better than their host processor unit execution times. The code object offload selector selects additional code objects for offloading using a dynamic-programming-like performance estimation approach that performs a bottom-up traversal of a call tree. A heterogeneous version of the program can be generated for execution on the heterogeneous computing system.
Embodiments herein describe a FEC codec for generating a check byte for a message. The FEC codec includes a port encoder having a storage unit, a Galois field multiplier, and a sum unit. The storage unit stores a first staged result, which is accumulated based on previous sets of input bytes of the message for all clock cycles from a first clock cycle to a clock cycle immediately prior to the current clock cycle. The Galois field multiplier performs a Galois field multiplication of the first staged result and a power of the alpha to generate a Galois field product. The sum unit performs a Galois field addition on an internal input based on a consolidated byte for the current clock cycle and the Galois field product to generate a second staged result for subsequent use to generate the check byte. Other embodiments may be described and/or claimed.
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation
85.
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES USING MULTIPLE BOTTOM-UP OXIDATION APPROACHES
Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. All nanowires of the vertical arrangement of nanowires are oxide nanowires. A gate stack is over the vertical arrangement of nanowires, around each of the oxide nanowires. The gate stack includes a conductive gate electrode.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
86.
EXTENDED FLOATING-POINT RANGE ADDITION AND MULTIPLICATION
A first storage location is to store a first floating-point data element. The first data element has a sign bit, an N-bit first exponent value, and M bits. A second storage location is to store a second floating-point data element that is to have a same number of bits as the first floating-point data element. The second data element has a sign bit, an N-bit first exponent value, and M bits. The N-bit first exponent value of the second data element is all zeroes and the M bits of the second data element include a significand and a second exponent value. A floating-point arithmetic unit is coupled with the first and second storage locations. The floating-point arithmetic unit is to perform either multiplication or addition on the first and second data elements to generate a result data element based at least in part on the second exponent value.
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p.ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
An apparatus to facilitate enabling late-binding of security features via configuration security controller for accelerator devices is disclosed. The apparatus includes a security controller to manage security and configuration of the apparatus, wherein the security controller comprises a programmable portion and a non-programmable portion, and wherein the security controller is further to: initialize the programmable portion of the security controller as part of a secure boot and attestation chain of trust; receive configuration data for the programmable portion of the security controller, the programmable portion comprising components of the security controller capable of re-programming; verify and validate the configuration data as originating from a secure and trusted source; and responsive to successful verification and validation of the configuration data, re-program, during runtime of the apparatus, the programmable portion of the security controller using configurations that are based on a security threat model for a given deployment.
G06F 21/85 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs d’interconnexion, p.ex. les dispositifs connectés à un bus ou les dispositifs en ligne
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
G06F 30/398 - Vérification ou optimisation de la conception, p.ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 30/331 - Vérification de la conception, p.ex. simulation fonctionnelle ou vérification du modèle par simulation avec accélération matérielle, p.ex. en utilisant les réseaux de portes programmables [FPGA] ou une émulation
G06F 9/50 - Allocation de ressources, p.ex. de l'unité centrale de traitement [UCT]
G06F 15/177 - Commande d'initialisation ou de configuration
G06F 21/71 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information
G06F 21/73 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par création ou détermination de l’identification de la machine, p.ex. numéros de série
G06F 21/53 - Contrôle des usagers, programmes ou dispositifs de préservation de l’intégrité des plates-formes, p.ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p.ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par exécution dans un environnement restreint, p.ex. "boîte à sable" ou machine virtuelle sécurisée
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 21/76 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits intégrés à application spécifique [ASIC] ou les dispositifs programmables, p.ex. les réseaux de portes programmables [FPGA] ou les circuits logiques programmables [PLD]
G06F 21/44 - Authentification de programme ou de dispositif
G06F 21/74 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information opérant en mode dual ou compartimenté, c. à d. avec au moins un mode sécurisé
G06F 119/12 - Analyse temporelle ou optimisation temporelle
G06F 21/30 - Authentification, c. à d. détermination de l’identité ou de l’habilitation des responsables de la sécurité
G06F 30/31 - Saisie informatique, p.ex. éditeurs spécifiquement adaptés à la conception de circuits
H04L 9/00 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité
A method is described. The method includes respectively adding respective identifiers of respective queues that provide packets to a CPU to a list in response to the respective queues being deemed quiet. The method includes, as a consequence of an interrupt having been generated in response to one of the respective queues having received a packet, removing the respective identifiers from the list and executing respective poll service handlers for the respective queues. The method includes disabling those of the respective poll service handlers and adding those of the respective identifiers back to the interrupt cause list for those of the respective queues that are again deemed quiet, while, continuing executing others of the respective poll service handlers for others of the respective queues that are not deemed quiet.
Apparatus and method for stack access throttling for synchronous ray tracing. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to manage active ray tracing stack allocations to ensure that a size of the active ray tracing stack allocations remains within a threshold; and an execution unit to execute a thread to explicitly request a new ray tracing stack allocation from the ray tracing acceleration hardware, the ray tracing acceleration hardware to permit the new ray tracing stack allocation if the size of the active ray tracing stack allocations will remain within the threshold after permitting the new ray tracing stack allocation.
Example methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement multi-plane image (MPI) compression are disclosed. Example apparatus disclosed herein include an interface to access an input multiplane image stack corresponding to a source camera viewpoint, the input multiplane image stack including a plurality of texture images and a corresponding plurality of alpha images, ones of the alpha images including pixel values representative of transparency of corresponding pixels in respective ones of the texture images. Disclosed example apparatus also include a compressed image encoder to at least one of (i) convert the plurality of texture images to a single composite texture image to generate a compressed multiplane image stack, or (ii) convert the plurality of alpha images to a single composite alpha image to generate the compressed multiplane image stack. In some disclosed examples, the interface is to output the compressed multiplane image stack.
In various aspects, a radio frequency circuit is provided. The radio frequency circuit may include a substrate that may include a radio frequency front-end to antenna (RF FE-to-Ant) connector. The RF FE-to-Ant connector may include a conductor track structure and a substrate connection structure coupled to the conductor track structure. The substrate may include radio frequency front-end circuitry monolithically integrated in the substrate. The substrate connection structure may include at least one of a solderable structure, a weldable structure, or an adherable structure. The substrate connection structure may be configured to form at least one radio frequency signal interface with an antenna circuit connection structure of a substrate-external antenna circuit. The substrate may include an edge region. The substrate connection structure may be disposed in the edge region.
Technologies for the hierarchical clustering of hardware resources in network function virtualization (NFV) deployments include a compute node that is configured to create a network function profile that includes a plurality of network functions to be deployed on the compute node. Additionally, the compute node is configured to translate the network function profile usable to identify which of the plurality of network functions are to be managed by each of the plurality of interconnected hardware resources into a hardware profile for each of a plurality of interconnected hardware resources. The compute node is further configured to deploy each of the plurality of network functions to one or more of the plurality of interconnected hardware resources based on the hardware profile. Other embodiments are described herein.
G06F 9/50 - Allocation de ressources, p.ex. de l'unité centrale de traitement [UCT]
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
93.
TECHNOLOGIES FOR PROGRAMMING FLEXIBLE ACCELERATED NETWORK PIPELINE USING EBPF
Technologies for programming flexible accelerated network pipelines include a comping device with a network controller. The computing device loads a program binary file that includes a packet processing program and a requested hint section. The binary file may be an executable and linkable format (ELF) file with an extended Berkeley packet filter (eBPF) program. The computing device determines a hardware configuration for the network controller based on the requested offload hints and programs the network controller. The network controller processes network packets with the requested offloads, such as packet classification, hashing, checksums, traffic shaping, or other offloads. The network controller returns results of the offloads as hints in metadata. The packet processing program performs actions based on the metadata, such as forwarding, dropping, packet modification, or other actions. The computing device may compile an eBPF source file to generate the binary file. Other embodiments are described and claimed.
H04L 69/22 - Analyse syntaxique ou évaluation d’en-têtes
H04L 41/00 - Dispositions pour la maintenance, l’administration ou la gestion des réseaux de commutation de données, p.ex. des réseaux de commutation de paquets
94.
IC PACKAGE INCLUDING MULTI-CHIP UNIT WITH BONDED INTEGRATED HEAT SPREADER
A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
Matrix multiplication systolic array feed methods and related processing element (PE) microarchitectures for efficiently implementing systolic array generic matrix multiplier (SGEMM) in integrated circuits is provided. A systolic array architecture may include a processing element array, a column feeder array, and a row feeder array. A bandwidth of external memory may be reduced by a factor of reduction based on interleaving of the matrix data via a feeding pattern of the column feeder array and the row feeder array.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
96.
SECURE APPLICATION COMPUTING ENVIRONMENT IN A FEDERATED EDGE CLOUD
Systems and methods for a secure application computing environment in a federated Edge Cloud are disclosed herein. Application information corresponding to an application from an application provider may be received in a secure environment of a device such as an edge computing node. A trust level for execution of the application may be associated based at least in part on the application information, and based on the associated trust level, a trusted platform may be selected to deploy or launch the application.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
98.
HYBRID FAN-OUT ARCHITECTURE WITH EMIB AND GLASS CORE FOR HETEROGENEOUS DIE INTEGRATION APPLICATIONS
Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
99.
GRAPHICS ARCHITECTURE INCLUDING A NEURAL NETWORK PIPELINE
One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.
Various embodiments herein provide physical uplink control channel (PUCCH) designs for discrete Fourier transform-spread-orthogonal frequency-division multiplexing (DFT-s-OFDM) waveforms for systems operating above the 52.6 GHz carrier frequency. Some embodiments of the present disclosure may be directed to phase tracking reference signal (PT-RS) design for PUCCH with carrier frequencies above 52.6 GHz. Other embodiments may be disclosed and/or claimed.
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
H04J 3/16 - Systèmes multiplex à division de temps dans lesquels le temps attribué à chacun des canaux au cours d'un cycle de transmission est variable, p.ex. pour tenir compte de la complexité variable des signaux, pour adapter le nombre de canaux transmis
