Examples described herein relate to a network interface device comprising: a host interface, a direct memory access (DMA) engine, and circuitry to allocate a region in a cache to store a context of a connection. In some examples, the circuitry is to allocate a region in a cache to store a context of a connection based on connection reliability and wherein connection reliability comprises use of a reliable transport protocol or non-use of a reliable transport protocol.
H04L 47/78 - Architectures d'allocation des ressources
G06F 15/173 - Communication entre processeurs utilisant un réseau d'interconnexion, p.ex. matriciel, de réarrangement, pyramidal, en étoile ou ramifié
H04L 47/80 - Actions liées au type d'utilisateur ou à la nature du flux
H04L 47/762 - Contrôle d'admission; Allocation des ressources en utilisant l'allocation dynamique des ressources, p.ex. renégociation en cours d'appel sur requête de l'utilisateur ou sur requête du réseau en réponse à des changements dans les conditions du réseau déclenchée par le réseau
2.
MULTI- ACCESS EDGE COMPUTING (MEC) APPLICATION REGISTRY IN MEC FEDERATION
Various systems and methods are described implementing a multi-access edge computing (MEC) based system to realize MEC application registration and application data functions for MEC frameworks. In an example, operations are performed at a MEC orchestrator to maintain a registry of applications within a MEC system or among a federation of MEC systems, with the MEC orchestrator performing operations including: identifying, based on the communications with a plurality of MEC hosts, a plurality of applications provided by the MEC hosts in the MEC system (or, by applications provided by a plurality of MEC hosts in a federation); storing and synchronizing application information for the plurality of applications in a registry; and communicating the application information from the registry to an entity of the MEC system or to an entity federated with the MEC system.
H04L 67/289 - Traitement intermédiaire fonctionnellement situé à proximité de l'application consommatrice de données, p.ex. dans la même machine, dans le même domicile ou dans le même sous-réseau
H04L 67/10 - Protocoles dans lesquels une application est distribuée parmi les nœuds du réseau
Systems, apparatuses, methods, and computer-readable media are provided to support multiple codewords and/or transmission of uplink transmissions (e.g., PUSCH) with more than 4 layers. Additionally, embodiments provide techniques for frequency selective precoding for uplink transmission. Other embodiments may be described and claimed.
H04B 7/06 - Systèmes de diversité; Systèmes à plusieurs antennes, c. à d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
A computer-readable storage medium stores instructions to configure a UE for joint channel estimation of uplink transmissions in a Fifth Generation New Radio (5G NR) and beyond wireless network, and to cause the UE to perform operations. The operations include decoding DCI or higher layer signaling received from a base station. The DCI or the higher layer signaling indicates a number of PUSCH repetitions forming the uplink transmissions. The operations further include decoding higher layer signaling received from the base station, the higher layer signaling indicating a size of a time domain window (TDW) associated with the uplink transmissions. The TDW has a number of slots equal to the size. Each of the PUSCH repetitions within the TDW is associated with a same carrier phase and a same transmit power.
Examples described herein relate to a sender process having a capability to select from use of a plurality of connections to at least one target process, wherein the plurality of connections to at least one target process comprise a connection for the sender process and/or one or more connections allocated per job. In some examples, the connection for the sender process comprises a datagram transport for message transfers. In some examples, the one or more connections allocated per job utilize a kernel bypass datagram transport for message transfers. In some examples, the one or more connections allocated per job comprise a connection oriented transport and wherein multiple remote direct memory access (RDMA) write operations for a plurality of processes are to be multiplexed using the connection oriented transport.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
A system management mode (SMM) runtime resiliency manager (SRM) augments computing resource protection policies provided by an SMM policy shim. The SMM shim protects system resources by deprivileging system management interrupt (SMI) handlers to a lower level of privilege (e.g., ring 3 privilege) and by configuring page tables and register bitmaps (e.g., I/O, MSR, and Save State register bitmaps). SRM capabilities include protecting the SMM shim, updating the SMM shim, protecting a computing system during SMM shim update, detecting SMM attacks, and recovering attacked or faulty SMM components.
Various embodiments herein provide techniques related to sixth generation (6G) system architecture and functions. For example, embodiments may relate to one or more of: Design principle and system architecture; Orchestration frontend service; Dynamic device-network computing scaling; RDMA over radio; Cloud workload offloading to network; Computing- embedded air interface; Service chain aware transport; and/or Enabling Al capabilities. Other embodiments may be described and/or claimed.
H04L 41/5051 - Service à la demande, p.ex. définition et déploiement des services en temps réel
H04L 41/0896 - Gestion de la bande passante ou de la capacité des réseaux, c. à d. augmentation ou diminution automatique des capacités
H04L 47/2425 - Trafic caractérisé par des attributs spécifiques, p.ex. la priorité ou QoS pour la prise en charge de spécifications de services, p.ex. SLA
H04L 47/2483 - Trafic caractérisé par des attributs spécifiques, p.ex. la priorité ou QoS en impliquant l’identification des flux individuels
H04W 88/18 - Dispositifs de logistique; Dispositifs de gestion de réseaux
Various embodiments herein are directed to beamforming associated with multiple-input multiple-output (MIMO) modes in open radio access network (O-RAN) systems. In one embodiment, an apparatus comprises: memory to store beamforming configuration information associated with a plurality MIMO modes; and processing circuitry, coupled with the memory to: retrieve the beamforming configuration information from the memory; request, based on the beamforming configuration information, measurements associated with the plurality of MIMO modes; receive the measurements associated with the plurality of MIMO modes; and based on the received measurements, train an artificial intelligence/machine learning (AI/ML) model that is to predict relative beamforming performance between the plurality of MIMO modes.
H04B 7/06 - Systèmes de diversité; Systèmes à plusieurs antennes, c. à d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H04B 7/0452 - Systèmes MIMO à plusieurs utilisateurs
H04B 17/336 - Rapport signal/interférence ou rapport porteuse/interférence
Apparatus, articles of manufacture, and methods for managing processing units are disclosed. An example apparatus includes Apparatus, articles of manufacture, and methods for managing processing units are disclosed. An example apparatus includes first processor circuitry to implement a central processing unit and second processor circuitry to perform at least one of first operations, second operations or third operations to obtain a resource request associated with a first workload; determine if a processing resource of a programmable network device is available to perform processing for the workload; determine if a second workload can be migrated from execution on the programmable network device; based on the determination that the second workload can be migrated, cause the second workload to be migrated; and cause the first workload to execute on the processing resource of the programmable network device.
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
An apparatus and system are described to provide carrier switching rules for multiple aperiodic Sounding Reference Signals (SRS) resource sets triggered by a single downlink control information (DCI). Whether the user equipment (UE) retunes between a source component carrier (CC) and a target CC for an SRS transmission is dependent on a time period between adjacent SRS resource sets in addition to priorities of the SRS transmission on the target CC and a simultaneous transmission on the source CC. In addition, timing of another DCI scheduling the simultaneous transmission received prior to the associated SRS transmission affects which of the simultaneous transmission or the associated SRS transmission is transmitted.
A computer-readable storage medium stores instructions to configure a UE for cross-carrier scheduling of data transmissions in a 5G NR and beyond wireless network, and to cause the UE to perform operations including decoding configuration signaling received from a base station. The configuration signaling indicates a first numerology parameter for a scheduling cell of the base station and a second numerology parameter for a scheduled cell of the base station. DCI is received via a PDCCH of the scheduling cell. The DCI schedules a DL data transmission in the scheduled cell of the base station. The DL data transmission is received via a PDSCH of the scheduled cell when a difference between the first numerology parameter and the second numerology parameter is smaller than or equal to a pre-configured numerology threshold value. The UE refrains from decoding the DL data transmission when the difference is greater than the threshold value.
The present invention relates to an apparatus comprising: memory to store policy statement information for a plurality of radio access network (RAN) automation applications (rApps); and processing circuitry, coupled with the memory, to: retrieve the policy statement information from the memory, wherein the policy statement information includes respective policy scope identifiers for respective rApps in the plurality of rApps; identify a conflict associated with common or overlapping policy scope identifiers between two or more rApps from the plurality of rApps; modify one or more A1 policies associated with an A1 interface connecting a non-real-time (non-RT) RAN intelligence controller (RIC) and a near-real-time (near-RT) RIC to resolve the conflict; and notify the two or more rApps of the modification of the one or more A1 policies.
An apparatus is described. The apparatus includes a logic chip upon which a stack of memory chips is to be placed. The stack of memory chips and the logic chip to be placed within a same package, wherein, multiple memory chips of the stack of memory chips are divided into fractions, and, multiple internal channels within the package that emanate from the logic chip are to be coupled to respective ones of the fractions. The logic chip has a multiplexer. The multiplexer is to multiplex a single input/output (I/O) channel of the package to the multiple internal channels.
The present disclosure provides a resilient (radio) access network ((R)AN) slicing framework encompassing a resource planning engine and distributed dynamic slice-aware scheduling modules at one or more network access nodes, edge compute nodes, or cloud computing service. The resilient (R)AN slicing framework includes resource planning and slice-aware scheduling, as well as signaling exchanges for provisioning resilient (R)AN slicing. The intelligent (R)AN slicing framework can realize resource isolation in a more efficient and agile manner than existing network slicing technologies.
H04W 48/18 - Sélection d'un réseau ou d'un service de télécommunications
H04W 28/24 - Négociation de l'agrément du niveau de service [SLA Service Level Agreement]; Négociation de la qualité de service [QoS Quality of Service]
Examples described herein relate to a first graphics processing unit (GPU) with at least one integrated communications system, wherein the at least one integrated communications system is to apply a reliability protocol to communicate with a second at least one integrated communications system associated with a second GPU to copy data from a first memory region to a second memory region and wherein the first memory region is associated with the first GPU and the second memory region is associated with the second GPU.
G06F 15/173 - Communication entre processeurs utilisant un réseau d'interconnexion, p.ex. matriciel, de réarrangement, pyramidal, en étoile ou ramifié
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
G06T 1/20 - Architectures de processeurs; Configuration de processeurs p.ex. configuration en pipeline
According to various examples, a gesture recognition device is described comprising an input interface configured to receive a sequence of images, each image showing a body part with which a gesture is performed from a viewpoint of a camera and a processor configured to generate a sequence of motion-compensated images from the sequence comprising generating a motion-compensated image for an image of the sequence by compensating the movement of the camera viewpoint from a reference camera viewpoint to the viewpoint from which the image shows the body part based on the image and a motion-compensated image of the sequence generated for a preceding image of the sequence which precedes the image in the sequence and estimate the gesture from the sequence of motion-compensated images.
G06K 9/00 - Méthodes ou dispositions pour la lecture ou la reconnaissance de caractères imprimés ou écrits ou pour la reconnaissance de formes, p.ex. d'empreintes digitales
Signal lines in the pin field of a printed circuit board layout are modified to reduce line impedance and improve signal integrity. The widths of signal lines are extended in the pin field to take full advantage of the available routing space between pads and adjacent signal lines. The signal line extension can be considered a subtractive approach in that the signal lines are extended to occupy the available routing space, with signal line extensions that would otherwise cause design rule violations being subtracted out. The edge of a signal line is extended to a keep-out region associated with a centerline that extends through a plurality of pads arranged in a line and located adjacent to the signal line. The edge of the signal line is also extended to keep-out regions associated with pads in the pin fields.
Methods, apparatus, systems, and articles of manufacture are provided for mixed radix fast Fourier transform (FFT) calculations of graphics processing units (GPUs). An apparatus includes at least one memory, machine readable instructions in the apparatus, and at least one processor circuitry to execute the machine readable instructions to at least factorize input data to identify one or more radix-r blocks for the parallel mixed radix calculation, perform at least one of a decimal-to-base or a base-to-base conversion of the input data prior to a bit reverse routine, the bit reverse routine to yield an output data set, cause a lookup table to be loaded into a memory structure based on a lookup table length, the lookup table populated with the output data set, and perform the parallel mixed radix calculation of the one or more radix-r blocks using the lookup table loaded into the memory structure.
Embodiments of exitless guest to host (G2H) notification are described. In some embodiments, G2H is provided via an instruction. An exemplary processor includes decoder circuitry to decode a single instruction, the single instruction to include a field for an opcode; and execution processing resources to execute the decoded single instruction according to the at least the opcode to cause an exitless guest to host notification from a virtual processor to a physical or virtual processor.
A computing node in an edge computing network includes a network interface card (NIC), memory storing a plurality of digital object representations of a corresponding plurality of participating entities, and processing circuitry. The processing circuitry detects a message from a participating entity of the plurality. The message is received via the NIC and is associated with a messaging service of the edge computing network. The message is mapped to a service class of a plurality of available service classes based on a service request associated with the message. The message is processed to extract one or more characteristics of the service request. A digital object representation of the plurality of digital object representations is updated based on the one or more characteristics of the service request, the digital object representation corresponding to the participating entity.
Methods, apparatus, systems and articles of manufacture are disclosed for scale recovery from monocular video. An example non-transitory computer readable medium comprises instructions that, when executed, cause a machine to at least segment an input image from a monocular video to detect an object in the camera field, estimate camera parameters from the segmented input image, iteratively refine the estimated camera parameters using known object heights, calculate a scale for the video, iteratively refine the scale based on a user input, and report the scaling results for visualization.
G06K 9/00 - Méthodes ou dispositions pour la lecture ou la reconnaissance de caractères imprimés ou écrits ou pour la reconnaissance de formes, p.ex. d'empreintes digitales
Systems, apparatuses and methods may provide for memory cell technology comprising a control gate, a conductive channel, and a charge storage structure coupled to the control gate and the conductive channel, wherein the charge storage structure includes a polysilicon layer and a metal layer. In one example, the metal layer includes titanium nitride or other high effective work function metal.
Particular embodiments described herein provide for an electronic device that can be configured to include a first heat source, a second heat source, and a fan inside a fan enclosure between the first heat source and the second heat source. The fan enclosure includes a main vent to direct air from the fan towards a heatsink and one or more side vents to direct air from the fan towards the first heat source or the second heat source.
A controller is provided. The controller comprises a processor configured to determine multiple power saving modes based on a power saving model of a network communicative road sensing system and on a power saving target assigned to the road sensing system; the multiple power saving modes comprising a first power saving mode for a first power consuming subsystem of the road sensing system and a second power saving mode for a second power consuming subsystem of the road sensing system; generate a recommendation for the road sensing system to operate in accordance with the multiple power saving modes.
Various embodiments herein are directed to time domain bundling of hybrid automatic repeat request-acknowledgement (HARQ-ACK) feedback. Other embodiments may be disclosed or claimed.
INPUT CIRCUITRY FOR AN ANALOG-TO-DIGITAL CONVERTER, RECEIVER, BASE STATION, AND METHOD FOR OPERATING AN INPUT CIRCUITRY FOR AN ANALOG-TO-DIGITAL CONVERTER
Input circuitry for an analog-to-digital converter (ADC) is provided. The input circuitry in- cludes a calibration signal source configured to output a calibration signal for the ADC and an analog circuitry configured to receive and process an analog input signal for the ADC. The analog circuitry is further configured to generate a combined signal by combining the analog input signal and the calibration signal. The input circuitry further includes a buffer amplifier coupled to the analog circuitry and configured to supply a buffered signal to the ADC based on the combined signal. Further, the input circuitry includes neutralization circuitry config- ured to generate, based on the calibration signal, a neutralization signal for mitigating an un- wanted signal component related to a limited reverse isolation of the analog circuitry. The neutralization circuitry is further configured to supply the neutralization signal to at least one of an input node and an intermediate node of the analog circuitry.
A computing node includes a NIC and processing circuitry configured to select a subset of computing resources from a set of available computing resources to initiate a parameter sweep associated with a parameter sweep request received. A plurality of settings is applied to each computing resource of the subset to generate a plurality of resource mappings during the parameter sweep. Each resource mapping of the plurality of resource mappings indicates at least one computing resource of the subset and a corresponding at least one setting of the plurality of settings. Telemetry information for the subset of computing resources is retrieved, the telemetry information is generated during the parameter sweep. A resource mapping of the plurality of resource mappings is selected based on a comparison of the telemetry information with an SLO. A reconfiguration of the available computing resources is performed based on the selected resource mapping.
An embodiment of an integrated circuit may comprise circuitry communicatively coupled to two or more sub-non-uniform memory access clusters (SNCs) to allocate a specified memory space in the two or more SNCs in accordance with a SNC memory allocation policy indicated from a request to initialize the specified memory space. An embodiment of an apparatus may comprise decode circuitry to decode a single instruction, the single instruction to include a field for an opcode, and execution circuitry to execute the decoded instruction according to the opcode to provide an indicated SNC memory allocation policy (e.g., a SNC policy hint). Other embodiments are disclosed and claimed.
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G06F 12/02 - Adressage ou affectation; Réadressage
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
According to various aspects a device is provided, the device including: a first portion including a first antenna array; and a second portion including a second antenna array, wherein the first portion and the second portion are movable with respect to one another, and wherein the first antenna array and the second antenna array are arranged such that in a first relative position of the first portion and the second portion with respect to one another the first antenna array and the second antenna array operate in combination with one another, and in a second relative position of the first portion and the second portion with respect to one another the first antenna array and the second antenna array operate independently of one another.
H01Q 21/29 - Combinaisons d'unités d'antennes de types différents interagissant entre elles pour donner une caractéristique directionnelle désirée
H01Q 3/26 - Dispositifs pour changer ou faire varier l'orientation ou la forme du diagramme de directivité des ondes rayonnées par une antenne ou un système d'antenne faisant varier la distribution de l’énergie à travers une ouverture rayonnante
30.
ANALOG-TO-DIGITAL CONVERTER SYSTEM, RECEIVER, BASE STATION, MOBILE DEVICE AND METHOD FOR ANALOG-TO-DIGITAL CONVERSION
An analog-to-digital converter (ADC) system is provided. The ADC system includes a first signal path. The first signal path includes a first ADC configured to generate first digital data based on an input signal. The first ADC is a time-interleaved ADC including a plurality of sub-ADCs. The first signal path further includes circuitry configured to output activity data indicating at least which of the plurality of sub-ADCs is currently active. The ADC system further includes a correction circuit configured to output digital correction data based on the activity data. Further, the ADC system includes a second signal path coupled in parallel to the first signal path. The second signal path includes a second ADC configured to generate second digital data based on the input signal and a combiner circuit configured to generate modified second digital data by combining the second digital data and the correction data. The ADC system further includes an equalizer configured to generate an equalized output signal of the ADC system based on the first digital data. The equalizer is configured to adjust, based on the modified second digital data, at least one equalization parameter used for generating the equalized output signal of the ADC system.
Techniques are disclosed for the use of local buffers integrated into the execution units of a vector processor architecture. The use of local buffers results in less communication across the interconnection network implemented by vector processors, and increases interconnection network bandwidth, increases the speed of computations, and decreases power usage.
An accelerator includes polynomial multiplier circuitry including at least one modulus multiplier operating according to a mode. The at least one modulus multiplier include a multiplier to multiply two polynomial coefficients to generate a multiplication result, a power of two reducer to reduce the multiplication result to a reduced multiplication result when the mode is a power of two mode, and a prime modulus reducer to reduce the multiplication result to the reduced multiplication result when the mode is a prime modulus mode.
H04L 9/06 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p.ex. système DES
H04L 9/14 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité utilisant plusieurs clés ou algorithmes
H04L 9/30 - Clé publique, c. à d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
A computing platform comprising a first computer system including a first host and a first accelerator communicatively coupled to the first host, including a first memory, a first page table to perform a translation of virtual addresses to physical addresses in the first memory and a first trusted agent to validate the address translations.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 21/74 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information opérant en mode dual ou compartimenté, c. à d. avec au moins un mode sécurisé
G06F 21/79 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données dans les supports de stockage à semi-conducteurs, p.ex. les mémoires adressables directement
A computing platform comprising a plurality of disaggregated data center resources and an infrastructure processing unit (IPU), communicatively coupled to the plurality of resources, to compose a platform of the plurality of disaggregated data center resources for allocation of microservices cluster.
G06F 21/53 - Contrôle des usagers, programmes ou dispositifs de préservation de l’intégrité des plates-formes, p.ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p.ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par exécution dans un environnement restreint, p.ex. "boîte à sable" ou machine virtuelle sécurisée
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
35.
TECHNOLOGY FOR EARLY ABORT OF COMPRESSION ACCELERATION
An integrated circuit includes a compression accelerator to process a request from software to compress source data into an output file. The compression accelerator includes early-abort circuitry to provide for early abort of compression operations. In particular, the compression accelerator uses a predetermined sample size to compute an estimated size for a portion of the output file. The sample size specifies how much of the source data is to be analyzed before computing the estimated size. The compression accelerator also determines whether the estimated size reflects an acceptable amount of compression, based on a predetermined early-abort threshold. The compression accelerator aborts the request if the estimated size does not reflect the acceptable amount of compression. The compression accelerator may complete the request if the estimated size reflects the acceptable amount of compression. Other embodiments are described and claimed.
G06F 12/0804 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec mise à jour de la mémoire principale
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
Methods and apparatus for mitigating pooled memory cache miss latency with cache miss faults and transaction aborts. A compute platform coupled to one or more tiers of memory, such as remote pooled memory in a disaggregated environment executes memory transactions to access objects that are stored in the one or more tiers. A determination is made to whether a copy of the object is in a local cache on the platform; if it is, the object is accessed from the local cache. If the object is not in the local cache, a transaction abort may be generated if enabled for the transactions. Optionally, a cache miss page fault is generated if the object is in a cacheable region of a memory tier, and the transaction abort is not enabled. Various mechanisms are provided to determine what to do in response to a cache miss page fault.
G06F 12/0842 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement pour multitraitement ou multitâche
G06F 12/0862 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec pré-lecture
A processing apparatus is described herein that includes a general-purpose parallel processing engine comprising a matrix accelerator including one or more systolic arrays, at least one of the one or more systolic arrays comprising multiple pipeline stages, each pipeline stage of the multiple pipeline stages including multiple processing elements, the multiple processing elements configured to perform processing operations on input matrix elements based on output sparsity metadata. The output sparsity metadata indicates to the multiple processing elements to bypass multiplication for a first row of elements of a second matrix and multiply a second row of elements of the second matrix with a column of matrix elements of a first matrix.
A processing apparatus described herein includes a general-purpose parallel processing engine comprising a systolic array having multiple pipelines, each of the multiple pipelines including multiple pipeline stages, wherein the multiple pipelines include a first pipeline, a second pipeline, and a common input shared between the first pipeline and the second pipeline.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p.ex. plusieurs processeurs de données à instruction unique
A processing apparatus includes a general-purpose parallel processing engine including a set of multiple processing elements including a single precision floating-point unit, a double precision floating point unit, and an integer unit; a matrix accelerator including one or more systolic arrays; a first register file coupled with a first read control circuit, wherein the first read control circuit couples with the set of multiple processing elements and the matrix accelerator to arbitrate read requests to the first register file from the set of multiple processing elements and the matrix accelerator; and a second register file coupled with a second read control circuit, wherein the second read control circuit couples with the matrix accelerator to arbitrate read requests to the second register file from the matrix accelerator and limit access to the second register file by the set of multiple processing elements.
Examples include techniques to enable quality of service (QoS) control for an accelerator device. Circuitry at an accelerator device implements QoS control responsive to receipt of a submission descriptor for a work request to execute a workload for an application hosted by a compute device coupled with the accelerator device. An example QoS control includes accepting the submission descriptor to a work queue at the accelerator device based on a work size of submission descriptor submissions of the application to the work queue over a unit of time not exceeding a submission rate threshold. The work queue is associated with an operational unit at the accelerator device to execute the workload based on information included in the submission descriptor. The work queue to be shared with at least one other application hosted by the compute device.
G06F 9/48 - Lancement de programmes; Commutation de programmes, p.ex. par interruption
G06F 9/50 - Allocation de ressources, p.ex. de l'unité centrale de traitement [UCT]
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 11/34 - Enregistrement ou évaluation statistique de l'activité du calculateur, p.ex. des interruptions ou des opérations d'entrée–sortie
G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation
41.
SYSTOLIC ARRAY OF ARBITRARY PHYSICAL AND LOGICAL DEPTH
A processing apparatus includes a processing resource including a general-purpose parallel processing engine and a matrix accelerator. The matrix accelerator includes first circuitry to receive a command to perform operations associated with an instruction, second circuitry to configure the matrix accelerator according to a physical depth of a systolic array within the matrix accelerator and a logical depth associated with the instruction, third circuitry to read operands for the instruction from a register file associated with the systolic array, fourth circuitry to perform operations for the instruction via one or more passes through one or more physical pipeline stages of the systolic array based on a configuration performed by the second circuitry, and fifth circuitry to write output of the operations to the register file associated with the systolic array.
Methods and apparatus relating to provision of platform sealing secrets using a Physically Unclonable Function (PUF) with Trusted Computing Based (TCB) Recoverability are described. In an embodiment, decode circuitry decodes an instruction to determine data to be cryptographically protected and a challenge for a Physically Unclonable Function (PUF) circuitry. Execution circuitry executes the decoded instruction to cryptographically protect the data in accordance with a key, wherein the PUF circuitry is to generate the key in response to the challenge. Other embodiments are also disclosed and claimed.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
43.
HARDWARE-ASSISTED CORE FREQUENCY AND VOLTAGE SCALING IN A POLL MODE IDLE LOOP
A hardware controller within a core of a processor is described. The hardware controller includes telemetry logic to generate telemetry data that indicates an activity state of the core; core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state; and a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.
G06F 1/3209 - Surveillance d’une activité à distance, p.ex. au travers de lignes téléphoniques ou de connexions réseau
G06F 1/324 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par réduction de la fréquence d’horloge
G06F 1/3234 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise
44.
QUEUE SCALING BASED, AT LEAST, IN PART, ON PROCESSING LOAD
Examples described herein relate to one or more processors that execute a number of polling threads based on a number of queue identifiers, wherein at least one of the queue identifiers is associated with one or more queues. In some examples, the one or more processors selectively adjust a number of queue identifiers based on a load level of a queue. In some examples, the load level of a queue indicates a number of packets processed per unit of time. In some examples, the number of queue identifiers is no more than a number of configured queues. In some examples, the one or more queues are associated with a queue exclusively allocated to a thread for reading or writing.
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV, between the first and second microelectronic components, the TMV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the mold material including a second conductive pathway electrically coupled to the TMV; and a third microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TMV, the first microelectronic component, and the third microelectronic component.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p.ex. dissipateurs de chaleur
46.
PROGRAMMABLE FABRIC-BASED INSTRUCTION SET ARCHITECTURE FOR A PROCESSOR
A semiconductor device may include a programmable fabric and a processor (130). The processor may utilize one or more extension architectures (400). At least one of these extension architectures (400) may be used to integrate and/or embed the programmable fabric into the processor (130) as part of the processor (130). Specifically, a buffer of the extension architecture (400) may be used to load data to and store data from the programmable fabric.
Examples described herein relate to an apparatus that includes a network interface device comprising circuitry to identify at least one congested queue, predict occupancy level of the at least one congested queue when at least one sender is predicted to receive at least one congestion notification and transmit the at least one congestion notification to the at least one sender through zero or more intermediate nodes. In some examples, to identify at least one congested queue, the circuitry is to identify the at least one congested queue based on at least one fill level. In some examples, to identify at least one congested queue, the circuitry is to identify the at least one congested queue based on at least one predicted fill level at a predicted time the at least one sender receives the at least one congestion notification.
Methods, apparatus, systems, and articles of manufacture are disclosed to align processing events. An example apparatus includes a comparator to compare a value of a counter to a threshold value, the threshold value associated with an amount of time to defer provision of a first or second input signal to a corresponding first or second IP device, respectively, signal deferring circuitry to defer provision of the first or second input signals to a corresponding one of the first or second IP devices based on an output of the comparator, deferral of the first or second input signals to cause alignment of first and second processing events performed by the first and second IP devices, respectively, and power controlling circuitry to cause the first and second IP devices to power down based on completion of the first and second processing events.
Binary sparse encoding of data can be used to reduce an amount of data read from the stochastic associative memory while processing a query. Read performance of the stochastic associated memory is optimized to enhance the query throughput by modifying access patterns to reduce the time to read the stochastic associated memory. Read performance of the stochastic associative memory can be further improved through the use of cluster aware sharding and replication for parallelized similarity search. Clusters are partitioned across multiple Dual In-line Memory Modules (DIMMs), each DIMM including stochastic associative memory, to achieve maximum latency advantage.
A computer platform is disclosed. The computer platform comprises a central processing unit (CPU) including at least one socket having a plurality of tiles and control circuitry to partition the socket into a plurality of sub-sockets and assign a unique identity to each of the plurality of sub-sockets for security verification, wherein each sub-socket comprises at least one of the plurality of tiles to operate as a cluster of resources.
G06F 21/85 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs d’interconnexion, p.ex. les dispositifs connectés à un bus ou les dispositifs en ligne
An apparatus to facilitate mitigation of side-channel attacks in a computer system platform is disclosed. The apparatus comprises a cryptographic circuitry, including a plurality of crypto functional units (CFUs) to perform cryptographic algorithms; and jammer circuitry to generate noise to protect the plurality of CFUs from side-channel attacks.
The platform data aging for adaptive memory scaling described herein provides technical solutions for technical problems facing power management for electronic device processors. Technical solutions described herein include improved processor power management based on a memory region life-cycle (e.g., short-lived, long-lived, static). In an example, a short-term memory request is allocated to a short-term memory region, and that short-term memory region is powered down upon expiration of the lifetime of all short-term memory requests on the short-term memory region. Multiple memory regions may be scaled down (e.g., shut down) or scaled up based on demands for memory capacity and bandwidth.
G06F 12/123 - Commande de remplacement utilisant des algorithmes de remplacement avec listes d’âge, p.ex. file d’attente, liste du type le plus récemment utilisé [MRU] ou liste du type le moins récemment utilisé [LRU]
G06F 12/14 - Protection contre l'utilisation non autorisée de mémoire
G06F 1/3234 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise
G06F 12/02 - Adressage ou affectation; Réadressage
53.
HANDLING UNALIGNED TRANSACTIONS FOR INLINE ENCRYPTION
Methods and apparatus relating to handling unaligned transactions for inline encryption are described. In an embodiment, cryptographic logic circuitry receives a plurality of incoming packets and store two or more incoming packets from the plurality of incoming packets in memory. The cryptographic logic circuitry is informs software in response to detection of the two or more incoming packets. Other embodiments are also disclosed and claimed.
G06F 21/72 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits de cryptographie
G06F 21/79 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données dans les supports de stockage à semi-conducteurs, p.ex. les mémoires adressables directement
H04L 9/06 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p.ex. système DES
Methods, apparatus, systems and articles of manufacture are disclosed to perform machine-learning model operations on sparse accelerators. An example apparatus includes first circuitry, second circuitry to generate sparsity data based on an acceleration operation, and third circuitry to instruct one or more data buffers to provide at least one of activation data or weight data based on the sparsity data to the first circuitry, the first circuitry to execute the acceleration operation based on the at least one of the activation data or the weight data.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
A microelectronic assembly is provided, comprising: a first integrated circuit (IC) die at a first level, a second IC die at a second level, and a third IC die at a third level, the second level being in between the first level and the third level. A first interface between the first level and the second level is electrically coupled with high-density interconnects of a first pitch and a second interface between the second level and the third level is electrically coupled with interconnects of a second pitch. In some embodiments, at least one of the first IC die, second IC die, and third IC die comprises another microelectronic assembly. In other embodiments, at least one of the first IC die, second IC die, and third IC die comprises a semiconductor die.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
56.
RANGE-DOPPLER CONSISTENCY FOR RADAR GHOST TARGET DETECTION
Systems, apparatuses, and methods to response to distinguish a ghost target from an actual target based on radar signals and ranges determined from the radar signals. In particular, the disclosure provides an intrusion detection system receiving ranges and velocities for targets detected based on radar signals, determining a potential ghost target from the received velocities and confirming the potential ghost target based on estimated ranges and perturbations of the vehicle speed.
G01S 7/41 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe utilisant l'analyse du signal d'écho pour la caractérisation de la cible; Signature de cible; Surface équivalente de cible
G01S 13/56 - Discrimination entre objets fixes et mobiles ou entre objets se déplaçant à différentes vitesses pour la détection de présence
G01S 13/931 - Radar ou systèmes analogues, spécialement adaptés pour des applications spécifiques pour prévenir les collisions de véhicules terrestres
Systems, apparatuses, and methods to identify bus-off and masquerade attacks against ECUs transmitting on a communication bus from behind a gateway coupled to the communication bus. The disclosure further describes systems, apparatuses, and methods to mitigate against bus-off attacks made against an ECU coupled to a communication bus through a gateway.
The present disclosure describes a digital signal processing (DSP) block (26) that includes a columns (102) of weight registers (104) that can receive values and inputs that can receive multiple first values and multiple second values, where the multiple first values may be stored in the weight registers (104) after being received at the inputs. Additionally, the DSP block (26) includes multipliers (108) that, in a first mode of operation, simultaneously multiply each of the first values by a value of the multiple second values. The DSP block (26), in a second mode of operation, enables a first column (102) of multipliers (108) of the multipliers (108) to multiply each of multiple third values by each of multiple fourth values, where at least one of the multiple third values or fourth values includes more bits than the first values and second values.
Methods, systems and apparatuses may provide for technology that identifies first graphics data that is associated with spatially proximate positions. The technology identifies second graphics data that is associated with spatially proximate positions, and interleaves the first and the second graphics data across a plurality of storage tiles.
Examples described herein relate to a network interface device that comprises circuitry, when operational, to select a platform to execute a function and based on load of the platform, selectively cause the function to execute on one or more other platforms to attempt to achieve or finish before the time-to-completion. In some examples, the circuitry is to detect progress of function execution to determine whether completion of execution of the function is predicted to not finish within the time-to-completion and cause the function to execute on one or more other platforms based on completion of execution of the function predicted to not finish within the time-to-completion.
G06F 11/20 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel en utilisant un masquage actif du défaut, p.ex. en déconnectant les éléments défaillants ou en insérant des éléments de rechange
G06F 9/48 - Lancement de programmes; Commutation de programmes, p.ex. par interruption
61.
USER-PRESENCE BASED ADJUSTMENT OF DISPLAY CHARACTERISTICS
Methods, apparatus, systems, and articles of manufacture for applying selective adjustment of displays are disclosed herein. An example apparatus to control an operating characteristic such as a brightness of a display of an electronic device includes a face analyzer to identify a presence of a face of a user relative to the device based on image data generated by an image sensor of the electronic device, and a correlation analyzer to determine a correlation of the detected presence and a first device interaction event. In response to the correlation, the correlation analyzer is to apply a display brightness adjustment rule to selectively adjust the brightness of the display from a first setting to a second setting after a first time interval.
Embodiments disclosed herein include semiconductor dies with hybrid bonding layers and multi-die modules that are coupled together by hybrid bonding layers. In an embodiment, a semiconductor die comprises a die substrate, a pad layer over the die substrate, where the pad layer comprises first pads with a first dimension and a first pitch and second pads with a second dimension and a second pitch. In an embodiment, the semiconductor die further comprises a hybrid bonding layer over the pad layer. In an embodiment, the hybrid bonding layer comprises a dielectric layer, and an array of hybrid bonding pads in the dielectric layer, wherein the hybrid bonding pads comprise a third dimension and a third pitch.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
63.
APPARATUS AND METHOD FOR COHERENT ERROR MITIGATION USING CLIFFORD GATE INJECTION
Apparatus and method for actively mitigating coherent errors by modifying an original quantum circuit, inserting Clifford gate operations at intermediate stages. Embodiments of the apparatus and method may perform CGI statically, at the compiling stage, and/or dynamically, at the control processing stage. The insertion of Clifford gates takes advantage of the symmetries in a quantum circuit and actively cancels coherent errors, maintaining the quantum processor in a state as close as possible to the original tune-up environment.
Various systems and methods are described for implementing trust authority or trust attestation verification operations, including for Trust-as-a-Service or Attestation-as-a-Service implementations, in accordance with the techniques discussed herein. In various examples, operations and configurations are described to enable service-to-service attestation using a trust authority, to operate an attestation service, and to coordinate trust operations between relying and requesting parties.
G06F 21/64 - Protection de l’intégrité des données, p.ex. par sommes de contrôle, certificats ou signatures
G06F 21/53 - Contrôle des usagers, programmes ou dispositifs de préservation de l’intégrité des plates-formes, p.ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p.ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par exécution dans un environnement restreint, p.ex. "boîte à sable" ou machine virtuelle sécurisée
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
65.
COMPUTING DEVICES AND METHOD AND COMPUTING DEVICE FOR INITIALIZING A COMPUTING DEVICE
Various examples of the present disclosure relate to a computing device, and to a method and computer program for initializing a computing device. The computing device comprises a memory device, configured to store firmware for at least a first processing unit and a second processing unit. The computing device comprises a first processing unit, configured to obtain the firmware for the first processing unit from the memory device, and to initialize itself using the firmware obtained from the memory device. The computing device comprises a second processing unit, configured to obtain the firmware for the second processing unit from the memory device, and to initialize itself using the firmware obtained from the memory device.
A intergrated circuit (10), a method, a system and an apparatus for memory mirroring at page granularity on demand. The integrated circuit (10) may comprise first circuitry (11) to manage a memory in accordance with a page size and a channel interleave granularity, and second circuitry (12) coupled to the first circuitry (11), the second circuitry (12) to store data in a primary region of the memory at a primary address, and manage a mirror of the data in a secondary region of the memory at a secondary address at a regional granularity on demand at run time.
A processing device (30, 710) for reducing scan traffic is provided. The processing device (30, 710) comprises one or more interfaces (32, 718) configured to transmit information to at least one register access interface (759, 761) and processing circuitry (34) configured to control the one or more interfaces. Further, the processing circuitry (34) is configured to obtain register parameters of at least one functional unit (760, 762) of a processing unit (750) and to generate an improved bulk register comprising the register parameters of the at least one functional unit.
Apparatus, articles of manufacture, and methods for managing processing units are disclosed. Examples disclosed herein facilitate the management of systems that utilize heterogenous processing units, XPUs, etc. to efficiently utilize such processing units. For example, some apparatus, articles of manufacture, and methods facilitate resource sharing, resource allocation, and/or kernel generation based on hardware resources.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
69.
DYNAMIC SELECTION OF TOLLING PROTECTION MECHANISMS AND MULTI-CHANNEL MANAGEMENT
Techniques are disclosed for dynamically selecting out of band emission protection mechanisms to protect the usage of other frequency bands, as well as techniques for managing the scheduling and transmission of safety related messages having different communication latency requirements.
Methods and devices configured to determine, for a slot including a plurality of symbols allocated for downlink data, a downlink data block allocation scheme with a number of blocks of downlink data that remain constant or monotonically decrease starting at a designated symbol of the plurality of symbols allocated for downlink data; generate a voltage profile corresponding to the downlink data block allocation scheme, where the voltage profile includes a plurality of bias voltages; and apply a bias voltage selected from the plurality of bias voltages to a power amplifier in a transmission chain of the base station.
H04W 52/52 - Commande de puissance d'émission [TPC Transmission power control] utilisant des circuits ou des amplificateurs de commande automatique de gain [AGC Automatic Gain Control]
H04W 52/14 - Analyse séparée de la liaison montante ou de la liaison descendante
Embodiments in accordance with this disclosure provide a system and method for automatic content-dependent image processing algorithm selection. The method can include obtaining one or more frames of a video sequence; dividing the individual frames into sections; automatically determining whether to apply at least one non-neural network image processing algorithm or at least one neural network image processing algorithm to the individual sections depending on at least one content-based criterium; and applying at least one determined algorithm to at least one of the sections to process the image data of the sections.
H04N 19/109 - Sélection du mode de codage ou du mode de prédiction parmi plusieurs modes de codage prédictif temporel
H04N 19/176 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c. à d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p.ex. un objet la zone étant un bloc, p.ex. un macrobloc
G06T 3/40 - Changement d'échelle d'une image entière ou d'une partie d'image
Embodiments described herein may be related to apparatuses, processes, and techniques related to glass interposers or substrates that may be created using a glass etching process to enable highly integrated modules. Planar structures, which may be vertical planar structures, created within the glass interposer may be used to provide shielding for conductive vias in the glass interposer, to increase the signal density within the glass substrate and to reduce cross talk. Other embodiments may be described and/or claimed.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
73.
DIMM SOCKET WITH SEATING FLOOR TO MEET BOTH LONGER LENGTH EDGE CONTACTS AND SHORTER LENGTH EDGE CONTACTS
The present disclosure relates to an apparatus. The apparatus includes a DIMM socket having a seating floor that is to meet both longer length contacts and shorter length contacts of a DIMM when the DIMM is fully seated in the socket, wherein the DIMM is unable to rotate while within the socket in a manner that damages pins of the socket.
An integrated circuit (IC) package may be fabricated having an interposer, one or more microfluidic channels through the interposer, a first IC chip attached to a first side of the interposer, and a second IC chip attached to a second side of the interposer, where the first side of the interposer includes first bond pads coupled to first bond pads of the first IC chip, and the second side of the interposer includes second bond pads coupled to first bond pads of the second IC chip. In an embodiment of the present description, a liquid cooled three-dimensional IC (3DIC) package may be formed with the IC package, where at least two IC devices may be stacked with a liquid cooled interposer. In a further embodiment, the liquid cooled 3DIC package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/367 - Refroidissement facilité par la forme du dispositif
75.
PACKAGE SUBSTRATE WITH GLASS CORE HAVING VERTICAL POWER PLANES FOR IMPROVED POWER DELIVERY
Embodiments disclosed herein include package substrates and methods of forming such package substrates. In an embodiment the package substrate comprises a core and buildup layers on the core. In an embodiment, first level interconnect (FLI) pads are on a topmost buildup layer, and the FLI pads have a pitch. In an embodiment, a plurality of vertically oriented planes are embedded in the core, and the vertically oriented planes are spaced at the pitch.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die-level interposer having a first surface and an opposing second surface; a first die coupled to the first surface of the die-level interposer by a first hybrid bonding region having a first pitch; a second die coupled to the second surface of the die-level interposer by a second hybrid bonding region having a second pitch different from the first pitch; and a third die coupled to the second surface of the die-level interposer by a third hybrid bonding region having a third pitch different from the first and second pitches.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/14 - Supports, p.ex. substrats isolants non amovibles caractérisés par le matériau ou par ses propriétés électriques
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
An apparatus is described. The apparatus includes a dual-in line memory module (DIMM) socket having a first latch and a second latch. One of the first latch and the second latch having a feature for a user to apply force to release a DIMM from the DIMM socket. The other of the first latch and the second latch not having a feature for the user to apply force so that one end of the DIMM releases before an opposite end of the DIMM during release of the DIMM from the DIMM socket.
H01R 13/633 - Moyens additionnels pour faciliter l'engagement ou la séparation des pièces de couplage, p.ex. moyens pour aligner ou guider, leviers, pression de gaz pour la séparation uniquement
H01R 12/73 - Dispositifs de couplage pour circuits imprimés rigides ou structures similaires se couplant avec la bordure des circuits imprimés rigides ou des structures similaires se raccordant à d'autres circuits imprimés rigides ou à des structures similaires
H01R 13/635 - Moyens additionnels pour faciliter l'engagement ou la séparation des pièces de couplage, p.ex. moyens pour aligner ou guider, leviers, pression de gaz pour la séparation uniquement par une pression mécanique, p.ex. par la force d'un ressort
Embodiments disclosed herein include electronic packages with a core that includes an optical waveguide and methods of forming such electronic packages. In an embodiment, a package substrate comprises a core, and a photonics die embedded in the core. In an embodiment, the electronic package further comprises an optical waveguide embedded in the core. In an embodiment, the optical waveguide optically couples the photonics die to an edge of the core.
This disclosure relates to apparatuses, systems, and methods for scheduling user equipment (UE) transmissions, and in particular for scheduling UE transmissions in a 5G New Radio system with a split architecture. The scheduler selects a beamforming algorithm for a UE group that includes a first UE and a second UE, where the beamforming algorithm is based on characteristics of the beamforming algorithm and/or the UE group. The scheduler determines an effective SINR for the UE group based on the beamforming algorithm and determines a summed proportion fair metric for the UE group based on the effective SINR for the UE group. The scheduler schedules a transmission for either the first UE or the UE group, based on a proportional fair metric for the first UE and the summed proportional fair metric for the UE group.
H04B 7/0452 - Systèmes MIMO à plusieurs utilisateurs
H04B 7/06 - Systèmes de diversité; Systèmes à plusieurs antennes, c. à d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H04W 24/02 - Dispositions pour optimiser l'état de fonctionnement
80.
GLASS-BASED CAVITY AND CHANNELS FOR COOLING OF EMBEDDED DIES AND 3D INTEGRATED MODULES USING PACKAGE SUBSTRATES WITH GLASS CORE
Embodiments disclosed herein include package substrates and methods of forming such package substrates. In an embodiment a package substrate comprises a core with a first surface and a second surface opposite from the first surface. In an embodiment, a buildup layer is over the first surface of the core. In an embodiment, a channel is through the core, where the channel extends in a direction that is substantially parallel to the first surface.
G06K 9/00 - Méthodes ou dispositions pour la lecture ou la reconnaissance de caractères imprimés ou écrits ou pour la reconnaissance de formes, p.ex. d'empreintes digitales
82.
DATA FUNCTIONS AND PROCEDURES IN THE NON-REAL TIME RADIO ACCESS NETWORK INTELLIGENT CONTROLLER
This disclosure describes systems, methods, and devices related to data functions. A device may identify a first request received from a data consumer non-RT RIC application (rApp), wherein the first request is received over an R1 termination interface. The device may cause to send a first response to the data consumer rApp in response to the first request. The device may identify a data producer rApp by checking a data catalog in order to satisfy the first request. The device may cause to send a notification frame to the data consumer rApp over the R1 termination interface indicating that data will be delivered to the data consumer rApp.
H04W 24/02 - Dispositions pour optimiser l'état de fonctionnement
H04L 41/0246 - Normalisation; Intégration Échange ou transport d’informations de gestion de réseau en utilisant l’Internet; Intégration de serveurs de gestion du Web dans des éléments de réseau; Protocoles basés sur les services du Web
H04L 41/0893 - Affectation de groupes logiques aux éléments de réseau
H04L 41/16 - Dispositions pour la maintenance, l’administration ou la gestion des réseaux de commutation de données, p.ex. des réseaux de commutation de paquets en utilisant l'apprentissage automatique ou l'intelligence artificielle
83.
RADIO EQUIPMENT DIRECTIVE SOLUTIONS FOR REQUIREMENTS ON CYBERSECURITY, PRIVACY AND PROTECTION OF THE NETWORK
The present disclosure discusses various implementation solutions to meet the requirements of the European Union's Radio Equipment Directive (RED). Various testing architectures and test services are provided for each of the RED requirements that allow for reproducible validation and/or verification of radio equipment. Other aspects may be described and/or claimed.
H04L 41/40 - Dispositions pour la maintenance, l’administration ou la gestion des réseaux de commutation de données, p.ex. des réseaux de commutation de paquets en utilisant la virtualisation des fonctions réseau ou ressources, p.ex. entités SDN ou NFV
84.
METHODS AND APPARATUS TO MODIFY PRE-TRAINED MODELS TO APPLY NEURAL ARCHITECTURE SEARCH
Methods, apparatus, systems, and articles of manufacture to modify pre-trained models to apply neural architecture search are disclosed. Example instructions, when executed, cause processor circuitry to at least access a pre-trained machine learning model, create a super-network based on the pre-trained machine learning model, create a plurality of subnetworks based on the super-network, and search the plurality of subnetworks to select a subnetwork.
In one embodiment, an apparatus includes: a plurality of cores to execute instructions; a firmware agent to execute a first firmware; a Peripheral Component Interconnect Express (PCIe) interface to communicate with a device via a PCIe link; and a boot agent coupled to the PCIe interface to download the PCIe firmware from a non-volatile memory and provide the PCIe firmware to the PCIe interface. The PCIe interface may receive a PCIe firmware for the PCIe interface before the firmware agent is to receive the first firmware. Other embodiments are described and claimed.
A z-disaggregated integrated circuit package substrate assembly comprises a first substrate component (a coreless patch), a second substrate component (a core patch), and a third substrate component (an interposer). The coreless patch comprises thinner dielectric layers and higher density routing and can comprise an embedded bridge to allow for communication between integrated circuit dies attached to the coreless patch. The core layer acts as a middle layer interconnect between the coreless patch and the interposer and comprises liquid metal interconnects to connect the core patch physically and electrically to the coreless patch and the interposer. Core patch through holes comprise liquid metal plugs. Some through holes can be surrounded by and coaxially aligned with magnetic plugs to provide improved power signal delivery. The interposer comprises thicker dielectric layers and lower density routing. The substrate assembly can reduce cost and provide improved overall yield and electrical performance relative to monolithic substrates.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p.ex. structures d'interconnexions enterrées
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
A die assembly comprising: a first component layer having conductive through-connections in an insulator, a second component layer comprising a die, and an active device layer (ADL) at an interface between the first component layer and the second component layer. The ADL comprises active elements electrically coupled to the first component layer and the second component layer. The die assembly further comprises a bonding layer electrically coupling the ADL to the second component layer. In some embodiments, the die assembly further comprises another ADL at another interface between the first component layer and a package support opposite to the interface. The first component layer may comprise another die having through-substrate vias (TSVs). The die and the another die may be fabricated using different process nodes.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/075 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 23/29 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par le matériau
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
88.
PACKAGE WITH EMBEDDED DEVICE CAVITY PROVIDED BY SPACED INTERPOSERS
An electronic substrate may be fabricated having a primary interposer comprising a laminate with a metal via through the laminate, two or more secondary interposers attached to a first side of the primary interposer, where respective sidewalls of the two or more secondary interposers define one or more recesses over the primary interposer, and an embedded component within a recess of the one or more recesses defined by the respective sidewalls of the two or more secondary interposers. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/04 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/13 - Supports, p.ex. substrats isolants non amovibles caractérisés par leur forme
89.
USES OF CODED DATA AT MULTI-ACCESS EDGE COMPUTING SERVER
An apparatus of an edge computing node, a method, and a machine-readable storage medium. The apparatus is to decode messages from a plurality of clients within the edge computing network, the messages including respective coded data for respective ones of the plurality of clients; computing estimates of metrics related to a global model for federated learning using the coded data, the metrics including a gradient on the coded data; use the metrics to update the global model to generate an updated global model, wherein the edge computing node is to update the global model by calculating the gradient on the coded data based on a linear fit of the global model to estimated labels from the federated learning; and send a message including the updated global model for transmission to at least some of the clients.
H04L 67/289 - Traitement intermédiaire fonctionnellement situé à proximité de l'application consommatrice de données, p.ex. dans la même machine, dans le même domicile ou dans le même sous-réseau
90.
DYNAMIC INTERRUPT STEERING AND PROCESSOR UNIT IDLE STATE DEMOTION
Dynamic interrupt steering remaps the handling of interrupts away from processor units executing important workloads. During the operation of a computing system, important workload utilization rates for processor units handling interrupts are determined and those processor units with utilization rates about a threshold value are made unavailable for handling interrupts. Interrupts are dynamically remapped to processor units available for interrupt handling based on processor unit idle state and, in the case of heterogeneous computing systems, processor unit type. Processor units are capable of idle state demotion by, in response to receiving a request to enter into a deep idle state, determining if its interrupt handling rate is greater than a threshold value, and if so, placing itself into a shallower idle state than requested. This avoids the computing system from incurring the expensive idle state exit latency and power costs associated with exiting from a deep idle state.
Embodiments disclosed herein comprise package substrates and methods of forming package substrates. In an embodiment, a package substrate comprises a core substrate. A hole is disposed into the core substrate, and a via is disposed in the hole. In an embodiment, the via completely fills the hole. In an embodiment, a method of forming a package substrate comprises exposing a region of a core substrate with a laser. In an embodiment, the laser changes the morphology of the exposed region. The method may further comprise etching the core substrate, where the exposed region etches at a faster rate than the remainder of the core substrate to form a hole in the core substrate. The method may further comprise disposing a via in the hole.
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
92.
DOUBLE FETCH FOR LONG BURST LENGTH MEMORY DATA TRANSFER
For a memory device where a data fetch accesses N/2 data bits, and the memory device is to transfer N bits over a data burst of length M in response to a read command, the memory device accesses the same bank twice to access the N bits. Instead of accessing N/2 bits from two different banks, the memory device accesses a single bank twice. The memory device can control the timing of the data transfer to enable sending all N data bits to the memory controller for the read command. The memory device can send data as a first transfer of burst length M/2 of a first N/2 data bit portion and a second transfer of burst length M/2 of a second N/2 data bit portion.
Examples described herein relate to a switch device. The switch device can perform replication of content stored in a source memory region to two or more memory regions available from two or more nodes, wherein the two or more memory regions available from two or more nodes are identified to the circuitry for use to store replicated content. The two or more nodes can be on different racks than that of a memory device that stores the source memory region. The switch device can select the two or more memory regions available from two or more nodes based, at least, in part on resiliency criteria associated with the two or more nodes.
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p.ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 15/173 - Communication entre processeurs utilisant un réseau d'interconnexion, p.ex. matriciel, de réarrangement, pyramidal, en étoile ou ramifié
94.
ENHANCED SERVICE CLASSIFICATION FOR SERVICE FUNCTION CHAINING IN NEXT GENERATION CELLULAR NETWORKS
This disclosure describes systems, methods, and devices related to service function chaining classification in wireless networks. A communications network system may include a first cellular network device configured to: receive service data adaptation protocol (SDAP) data from a user equipment (UE) device, the SDAP data comprising a SDAP header; identify a service chaining function (SFC) service identifier of the SDAP header; determine that the SFC service identifier is indicative of a SFC service profile, the SFC service profile indicative of quality of service (QoS) traffic characteristics; identify a SFC traffic flow associated with the SFC service identifier; and transmit the SDAP data to a second cellular network device; and wherein the second cellular network device is configured to: receive the SDAP data from the first cellular network device; and transmit the SDAP data to a service function of the system.
A controlling means for a light detection and ranging (LIDAR) system is provided, including a means for determining a current operational state of the LIDAR system regarding a predefined threshold state; and switch the LIDAR system from a first operational mode to a second operational mode when the determined operational state exceeds the predefined threshold state, wherein the second operational mode corresponds to an operational power of at least one operational means of the LIDAR system being lower than in the first operational mode.
G01S 7/491 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe - Détails des systèmes non pulsés
H02J 9/00 - Circuits pour alimentation de puissance de secours ou de réserve, p.ex. pour éclairage de secours
G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
G01S 7/481 - Caractéristiques de structure, p.ex. agencements d'éléments optiques
A light detection and ranging system is provided, which includes an output to output coherent laser light; an optical frequency discriminator configured to apply optical frequency discrimination to a portion of the coherent laser light to generate frequency discriminated laser light; and a processor configured to determine laser phase noise in the frequency discriminated laser light; to determine a laser phase noise compensation using the determined laser phase noise; and to apply the laser phase noise compensation to a received light signal corresponding to the output coherent laser light.
G01S 7/4911 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe - Détails des systèmes non pulsés Émetteurs
G01S 17/32 - Systèmes déterminant les données relatives à la position d'une cible pour mesurer la distance uniquement utilisant la transmission d'ondes continues, soit modulées en amplitude, en fréquence ou en phase, soit non modulées
G01S 7/481 - Caractéristiques de structure, p.ex. agencements d'éléments optiques
A light detection and ranging system is provided. The light detection and ranging system includes a LIDAR scanning mirror; a processor configured to control the LIDAR scanning mirror; a first position sensor configured to determine a first position and a second position sensor configured to detect a second position of the LIDAR scanning mirror. The processor is configured to determine whether an eye-safety criterion is met based on the first position and the second position, and control light output of the LIDAR system based on whether the eye-safety criterion is met.
An integrated circuit (IC) package, comprising a die having a first set of interconnects of a first pitch, and an interposer comprising an organic substrate having a second set of interconnects of a second pitch. The interposer also includes an inorganic layer over the organic substrate. The inorganic layer comprises conductive traces electrically coupling the second set of interconnects with the first set of interconnects. The die is attached to the interposer by the first set of interconnects. In some embodiments, the interposer further comprises an embedded die. The IC package further comprises a package support having a third set of interconnects of a third pitch, and a second inorganic layer over a surface of the interposer opposite to the die. The second inorganic layer comprises conductive traces electrically coupling the third set of interconnects with the second set of interconnects.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/14 - Supports, p.ex. substrats isolants non amovibles caractérisés par le matériau ou par ses propriétés électriques
H01L 23/498 - Connexions électriques sur des substrats isolants
99.
PHYSICAL DOWNLINK CONTROL CHANNEL (PDCCH) MONITORING FOR CROSS-CARRIER SCHEDULING
Various embodiments may relate to physical downlink control channel (PDCCH) monitoring in association with cross-carrier scheduling. In particular, some embodiments are directed to scheduling a transmission on a primary cell (PCell) or primary secondary cell (PSCell) considering secondary cell (SCell) dormancy switching or SCell activation states. Other embodiments may be disclosed or claimed.
This disclosure describes systems, methods, and devices related to enhanced time-sensitive networking (TSN) configuration. A device may identify a frame received from a TSN domain comprising wired and wireless TSN traffic. The device may decode the frame to extract one or more fields, wherein the one or more fields comprise bridge parameters. The device may determine based on the bridge parameters whether a port associated with the device is wireless capable.
H04W 84/12 - Réseaux locaux sans fil [WLAN Wireless Local Area Network]
H04L 69/22 - Analyse syntaxique ou évaluation d’en-têtes
H04L 101/663 - Adresses de couche transport, p.ex. aspects des ports du protocole de contrôle de transmission [TCP] ou des ports du protocole de datagramme utilisateur [UDP]
H04L 12/44 - Réseaux en étoile ou réseaux arborescents
brevets
