Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 27/08 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type
2.
VERTICAL SOLID-STATE TRANSDUCERS AND HIGH VOLTAGE SOLID-STATE TRANSDUCERS HAVING BURIED CONTACTS AND ASSOCIATED SYSTEMS AND METHODS
Solid-state transducers (“SSTs”) and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. The SST can further include a plurality of first contacts at the first side and electrically coupled to the first semiconductor material, and a plurality of second contacts extending from the first side to the second semiconductor material and electrically coupled to the second semiconductor material. An interconnect can be formed between at least one first contact and one second contact. The interconnects can be covered with a plurality of package materials.
H01L 33/62 - Dispositions pour conduire le courant électrique vers le corps semi-conducteur ou depuis celui-ci, p.ex. grille de connexion, fil de connexion ou billes de soudure
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
H01L 25/075 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
H01L 27/15 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants semi-conducteurs avec au moins une barrière de potentiel ou une barrière de surface, spécialement adaptés pour l'émission de lumière
H01L 33/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails
H01L 33/06 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les corps semi-conducteurs ayant une structure à effet quantique ou un superréseau, p.ex. jonction tunnel au sein de la région électroluminescente, p.ex. structure de confinement quantique ou barrière tunnel
H01L 33/32 - Matériaux de la région électroluminescente contenant uniquement des éléments du groupe III et du groupe V de la classification périodique contenant de l'azote
H01L 33/38 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les électrodes ayant une forme particulière
H01L 33/64 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les éléments du boîtier des corps semi-conducteurs Éléments d'extraction de la chaleur ou de refroidissement
Methods, systems, and devices for address verification at a memory device are described. The memory device may receive a read command for a read address. Based on the read command, the memory device may read data from the read address and a first set of error detection bits that is based on a write address associated with the data. The memory device may generate, based on the first set of error detection bits and a second set of error detection bits that is based on the read address, an address match signal that indicates whether the read address matches the write address. And the memory device may provide the data and an indication of the address match signal to a host device.
A memory controller and a physical interface layer may accommodate multiple memory types. In some examples, the memory controller and/or PHY may include a register that includes operating parameters for multiple operating modes. Different operating modes may be compatible with different memory types. In some examples, the memory controller and physical interface may be included in a system for testing multiple memory types. The system may provide multiple interfaces for communicating with the memory. The different communication types may be used for performing different tests and/or simulating different types of devices that may utilize the memory.
Methods, systems, and devices for single crystal silicon cores for stacked memory cells are described. A memory device may be formed using silicon cores that are each associated with a set of multiple memory cells. Multiple silicon cores may extend along a first direction, and multiple sleeves of memory materials and conductive materials may be formed around each silicon core. Each sleeve of memory materials may be associated with a respective memory cell and each conductive material may be associated with a word line, such that each silicon core may be associated with multiple memory cells. The respective sleeves of memory materials and conductive materials may be formed from larger sleeves of material that may be etched into sections of the memory materials and the conductive materials along the silicon cores.
H01L 27/1157 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
H01L 27/11524 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
H01L 27/11578 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur
Methods, systems, and devices for differential storage in memory arrays are described. A memory device may include pairs of memory cells configured to store a single logic state (e.g., a single bit of information). Additionally, the memory device may include sense amplifiers configured to sense the logic state based on a difference between a voltage of a first ferroelectric memory cell of the pair of memory cells and a voltage of a second ferroelectric memory cell of the pair of memory cells. In one example, the memory device may include pairs of memory cells within a single memory array on a single level. Here, each memory cell pair may include a memory cells that are each coupled with a same word line and plate line. Additionally, each memory cell pair may include memory cells each coupled with different digit lines.
An electronic device comprising a lower deck and an upper deck adjacent to a source. Each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. Each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. Memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. Dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. Another conductive material is in the upper deck and the lower deck of the one or more non-array regions. Additional electronic devices and related systems and methods of forming an electronic device are also disclosed.
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
H10B 43/20 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
A single memory chip including both memory and storage capabilities on the single chip and accompanying process for forming a memory array including both capabilities is disclosed. In particular, the single chip may incorporate the use of two different chalcogenide materials deposited thereon to implement the memory and storage capabilities. Chalcogenide materials provide flexibility on cell performance, such as by changing the chalcogenide material composition. For the single memory chip, one type of chalcogenide material may be utilized to create memory cells and another type of chalcogenide material may be utilized to create storage cells. The process for forming the memory array includes forming first and second openings in a starting structure and performing a series of etching and deposition steps on the structure to form the memory and storage cells using the two different chalcogenide compositions. The memory and storage cells are independently addressable via wordline and bitline selection.
H01L 27/24 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants à l'état solide pour le redressement, l'amplification ou la commutation, sans barrière de potentiel ni barrière de surface
H01L 45/00 - Dispositifs à l'état solide spécialement adaptés pour le redressement, l'amplification, la production d'oscillations ou la commutation, sans barrière de potentiel ni barrière de surface, p.ex. triodes diélectriques; Dispositifs à effet Ovshinsky; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives
A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.
G06F 12/02 - Adressage ou affectation; Réadressage
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
Apparatuses, systems, and methods for adapting a read disturb scan. One example method can include determining a delay between a first read command and a second read command, incrementing a read count based on the determined delay between the first read command and the second read command, and adapting a read disturb scan rate based on the incremented read count.
A processing device is configured to process an initial set of command types. A command extension module and a digital signature are received. The digital signature is generated based on the command extension module using a private key of a key pair. The command extension module, once installed by the processing device, enables the processing device to process a new command type that is not included in the initial set of command types. The digital signature is verified using a public key of the key pair. Based on a successful verification of the digital signature, the command extension module is temporarily installed by loading the command extension module in a volatile memory device.
G06F 12/02 - Adressage ou affectation; Réadressage
G06F 12/14 - Protection contre l'utilisation non autorisée de mémoire
G06F 21/78 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
12.
INDICATING A STATUS OF A MEMORY BUILT-IN SELF-TEST
Implementations described herein relate to performing a memory built-in self-test and indicating a status of the memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, that the memory built-in self-test is enabled. The memory device may set a DMI bit of the memory device to a first value and perform the memory built-in self-test based on identifying that the memory built-in self-test is enabled. The memory device may set the DMI bit of the memory device to a second value based on a completion of the memory built-in self-test.
A system can include a memory device and a processing device coupled with the memory device. The processing device can receive, from a host system, a command of a type; determine a weighted count of the command according to the type of the command; track, based on the weighted count, a first count of commands of the type; determine whether the first count of commands of the type satisfies a threshold criterion for commands of the type; and responsive to determining that the first count of commands of the type satisfies the threshold criterion, transmit a notification to the host system to refrain from transmitting commands of the type.
A microelectronic device comprising tiers of alternating dielectric materials and conductive materials, pillars extending through the tiers, and a doped dielectric material adjacent to the tiers. The doped dielectric material comprises a heterogeneous chemical composition comprising one or more dopants. Conductive contact structures are in the doped dielectric material. Additional microelectronic devices, microelectronic systems, and methods of forming microelectronic devices are disclosed.
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
15.
DIELECTRIC INTERPOSER WITH ELECTRICAL-CONNECTION CUT-IN
Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a base layer, a dielectric interposer coupled to the base layer and including a first outer surface facing the base layer and an opposing second outer surface facing away from the base layer and spaced apart from the first outer surface in a direction, a first electrical-connection cut-in in the second outer surface that extends, in the direction, toward the first outer surface, and one or more first electrical connections disposed within the first electrical-connection cut-in such that at least a portion of the one or more first electrical connections does not extend, in the direction, beyond the second outer surface.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
16.
MANAGING A MEMORY SUB-SYSTEM USING A CROSS-HATCH CURSOR
One or more data items is received by a processing device managing one or more memory devices partitioned into a plurality of die partitions. The one or more data items is determined to be written sequentially to one or more blocks within a die partition of the plurality of die partitions. Metadata associated with the one or more data items is written sequentially to one or more blocks across the plurality of die partitions.
Disclosed is a three-dimensional memory device. In one embodiment, a device is disclosed comprising a source plate; plugs fabricated on or partially formed in the source plate; a stack formed on the substrate and plugs comprising alternating insulating layers and conductive layers and channel-material strings of memory cells extending through the insulating layers and conductive layers; a first set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the first set of pillars terminates atop a respective plug in the plurality of plugs; and a second set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the second set of pillars terminates in the source plate.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p.ex. structures d'interconnexions enterrées
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/50 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région limite entre la région noyau et la région de circuit périphérique
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 43/50 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région limite entre la région noyau et la région de circuit périphérique
18.
EXTENDED ADDRESS INTERFACE ACTIVATE SEQUENCE USING MODE REGISTER WRITE
A method and a device is provided for implementing a mode register to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command/address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.
An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
Apparatuses, systems, and methods for buffer threshold monitoring to reduce data loss are provided herein. In a number of embodiments of the present disclosure, a method can include buffering data in a first memory device, writing the buffered data from the first memory device to a second memory device, determining that the first memory device is storing at least a threshold amount of data, and sending a first signal to the second memory device in response to determining that the first memory device is storing at least the threshold amount of data, wherein the first signal causes the second memory device to enter an increased write performance mode.
Methods, systems, and devices for dynamic voltage supply for memory circuit are described. An apparatus may adjust a supply voltage based on a process corner and a temperature of the memory system. An apparatus may include a memory array and a controller. The controller may determine a first temperature of the apparatus is less than a first temperature threshold at a first time. The controller may transition a voltage supplied to the controller from a first voltage level to a second voltage level based on determining the first temperature is less than the first temperature threshold. The controller may determine a second temperature is greater than a second temperature threshold at a second time. The controller may transition the voltage supplied to the controller from the second voltage level to the first voltage level based on determining the second temperature is greater than the second temperature threshold.
Methods, systems, and devices for depositing carbon conducting films by atomic layer deposition are described. For instance, a device may react a first precursor with a base material to form a carbon compound on a material, where the first precursor is an acetylene, a diacetylene, a tri-acetylene, a polyacetylene, an alkene, or an arene and includes at least one germanium, silicon, or tin. Additionally, the device may react a second, carbon-containing precursor with the carbon compound to form a layer on the base material.
C23C 16/455 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c. à d. procédés de dépôt chimique en phase vapeur (CVD) caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour introduire des gaz dans la chambre de réaction ou pour modifier les écoulements de gaz dans la chambre de réaction
C01B 32/05 - Préparation ou purification du carbone non couvertes par les groupes , , ,
Systems, apparatuses, and methods related to a controller architecture for read data alignment are described. An example method can include sending a first notification from a physical layer to each of a number of memory controllers, wherein the first notification indicates that the physical layer and/or a memory device coupled to the physical layer is busy, and blocking commands on each of the number of memory controllers in response to receiving the first notification to cause read data alignment. The method can also include sending a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy, and resuming processing commands on each of the number of memory controllers in response to receiving the second notification.
Methods, systems, and devices for speed bins to support memory compatibility are described. A host device may read a value of a register including serial presence detect data of a memory module. The serial presence detect data may be indicative of a timing constraint for operating the memory module at a first clock rate, where the timing constraint and the first clock rate may be associated with a first speed bin. The host device may select, for communication with the memory module, a second speed bin associated with a second clock rate at the host device and the timing constraint, where the host device may support operations according to a set of timing constraints that includes a set of values. The timing constraint may be selected from a subset of the set of timing constraints, where the subset may be exclusive of at least one of the set of values.
Stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a plurality of support members also attached to the package substrate. The plurality of support members can include a first support member and a second support member disposed at opposite sides of the first semiconductor die, and a second semiconductor die can be coupled to the support members such that at least a portion of the second semiconductor die is over the first semiconductor die.
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
26.
CONTROLLER ARCHITECTURE FOR RELIABILITY, AVAILABILITY, SERVICEABILITY ACCESS
An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels can be each organized as a plurality of channel groups that can be operated as independent RAS channels (e.g., channels for independent RAS accesses). Data received at the memory controller via different memory channels of one RAS channel can be aligned at various circuits and/or components of the memory controller.
An antifuse device, including a gate having a gate dielectric layer; a first doping region connected to a first end of the gate; a second doping region connected to a second end of the gate, the second end being opposite to the first end of the gate; a channel that is disposed under the gate and that connects the first doping region and the second doping region; and an interconnection jumper that electrically connects the first doping region and the second doping region.
H01L 29/86 - Types de dispositifs semi-conducteurs commandés uniquement par la variation du courant électrique fourni, ou uniquement par la tension électrique appliquée, à l'une ou plusieurs des électrodes transportant le courant à redresser, amplifier, faire osciller, ou commuter
28.
TEMPERATURE-BASED ERROR MASKING DURING MBIST OPERATION
Methods, apparatuses, and systems related to masking of self-test results are described. A memory device may include a self-test circuit that is configured to selectively suspend collection of test results from one or more portions of a self-test when a temperature of the memory device exceeds a temperature threshold.
According to one or more embodiments of the disclosure, a through-silicon via (TSV)-Bump structure is provide. The TSV-Bump structure comprises a TSV in a semiconductor substrate and a bump on the TSV. The bump includes a conductive plug portion and a step structure portion under the conductive plug portion. The step structure is configured to electrically couple the TSV and the conductive plug portion with each other.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 21/306 - Traitement chimique ou électrique, p.ex. gravure électrolytique
H01L 21/324 - Traitement thermique pour modifier les propriétés des corps semi-conducteurs, p.ex. recuit, frittage
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a data validity metric value with respect to a set of memory cells of the memory device; responsive to determining that the data validity metric value satisfies a first threshold criterion, performing a data integrity check on the set of memory cells to obtain a data integrity metric value; and responsive to determining that the data integrity metric value satisfies a second threshold criterion, performing an error handling operation on the data stored on the set of memory cells to generate corrected data.
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/16 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p.ex. des réseaux, des mots, des groupes
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
Memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory dies. Each memory die of the plurality includes a command/address decoder. The command/address decoders are configured to receive command and address signals from external contacts of the memory device. The command/address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. Each memory die further includes circuitry configured to enable, or disable, or both individual command/address decoders of the plurality of memory dies. In some embodiments, the circuitry can enable a command/address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
G11C 11/407 - Circuits auxiliaires, p.ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture ou la synchronisation pour des cellules de mémoire du type à effet de champ
G11C 29/04 - Détection ou localisation d'éléments d'emmagasinage défectueux
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
32.
LIGHT EMITTING DIODES WITH N-POLARITY AND ASSOCIATED METHODS OF MANUFACTURING
Light emitting diodes (“LEDs”) with N-polarity and associated methods of manufacturing are disclosed herein. In one embodiment, a method for forming a light emitting diode on a substrate having a substrate material includes forming a nitrogen-rich environment at least proximate a surface of the substrate without forming a nitrodizing product of the substrate material on the surface of the substrate. The method also includes forming an LED structure with a nitrogen polarity on the surface of the substrate with a nitrogen-rich environment.
H01L 33/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails
H01L 33/16 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les corps semi-conducteurs ayant une structure cristalline ou une orientation particulière, p.ex. polycristalline, amorphe ou poreuse
H01L 33/32 - Matériaux de la région électroluminescente contenant uniquement des éléments du groupe III et du groupe V de la classification périodique contenant de l'azote
A method and a device is provided for utilizing unused valid (V) bits residing on a previous command to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command/address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.
Solid state lighting (“SSL”) devices with improved contacts and associated methods of manufacturing are disclosed herein. In one embodiment, an SSL device includes an SSL structure having a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The SSL device also includes a first contact on the first semiconductor material and a second contact on the second semiconductor material, where the first and second contacts define the current flow path through the SSL structure. The first or second contact is configured to provide a current density profile in the SSL structure based on a target current density profile.
H01L 33/62 - Dispositions pour conduire le courant électrique vers le corps semi-conducteur ou depuis celui-ci, p.ex. grille de connexion, fil de connexion ou billes de soudure
H01L 33/06 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les corps semi-conducteurs ayant une structure à effet quantique ou un superréseau, p.ex. jonction tunnel au sein de la région électroluminescente, p.ex. structure de confinement quantique ou barrière tunnel
H01L 33/10 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les corps semi-conducteurs ayant une structure réfléchissante, p.ex. réflecteur de Bragg en semi-conducteur
H01L 33/14 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les corps semi-conducteurs ayant une structure contrôlant le transport des charges, p.ex. couche semi-conductrice fortement dopée ou structure bloquant le courant
H01L 33/32 - Matériaux de la région électroluminescente contenant uniquement des éléments du groupe III et du groupe V de la classification périodique contenant de l'azote
H01L 33/36 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les électrodes
H01L 33/38 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les électrodes ayant une forme particulière
H01L 33/44 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les revêtements, p.ex. couche de passivation ou revêtement antireflet
H01L 33/46 - Revêtement réfléchissant, p.ex. réflecteur de Bragg en diélectriques
H01L 33/60 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les éléments du boîtier des corps semi-conducteurs Éléments de mise en forme du champ optique Éléments réfléchissants
35.
Reticle Constructions and Photo-Processing Methods
Some embodiments include a reticle which includes first pattern features and second pattern features. A first optimal dose of actinic radiation is associated with the first pattern features and a second optimal dose of the actinic radiation is associated with the second pattern features. The second pattern features are larger than the first pattern features. Each of the second pattern features has a configuration which includes a central region laterally surrounded by an outer region, with the central region being of different opacity than the outer region. The configurations of the second pattern features balance the second optimal dose of the actinic radiation to be within about 5% of the first optimal dose of the actinic radiation. Some embodiments include photo-processing methods.
G03F 1/38 - Masques à caractéristiques supplémentaires, p.ex. marquages pour l'alignement ou les tests, ou couches particulières; Leur préparation
G03F 1/36 - Masques à correction d'effets de proximité; Leur préparation, p.ex. procédés de conception à correction d'effets de proximité [OPC optical proximity correction]
G03F 7/00 - Production par voie photomécanique, p.ex. photolithographique, de surfaces texturées, p.ex. surfaces imprimées; Matériaux à cet effet, p.ex. comportant des photoréserves; Appareillages spécialement adaptés à cet effet
Systems, methods, and apparatus related to data storage devices. In one approach, a string of storage devices are chained together and coupled to a host device for storing data. Each storage device may, for example, execute read, write, or erase commands received from the host device. Each storage device in the chain is a master to the next storage device in the chain, and each storage device is a slave to the previous storage device in the chain. In one example, the host device is a system-on-chip. The chain can manage itself and is seen as a single large storage space to the host device. The host device does not require knowledge about each individual storage device, and each storage device does not require knowledge about the other storage devices in the chain (other than whether the storage device is attached to another storage device on its master port).
Some embodiments include an integrated assembly having first conductive structures extending along a first direction. Spaced-apart upwardly-opening container-shapes are over the first conductive structures. Each of the container-shapes has a first sidewall region, a second sidewall region, and a bottom region extending from the first sidewall region to the second sidewall region. Each of the first and second sidewall regions includes a lower source/drain region, an upper source/drain region, and a channel region between the upper and lower source/drain regions. The lower source/drain regions are electrically coupled with the first conductive structures. Second conductive structures extend along a second direction which crosses the first direction. The second conductive structures have gate regions operatively adjacent the channel regions. Storage elements are electrically coupled with the upper source/drain regions. Some embodiments include methods of forming integrated assemblies.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
The present disclosure includes apparatuses, methods, and systems for three-state programming of memory cells. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of three possible data states by applying a voltage pulse to the memory cell, determining whether the memory cell snaps back in response to the applied voltage pulse, and applying an additional voltage pulse to the memory cell based on the determination of whether the memory cell snaps back.
Apparatuses, systems, and methods for a damper for a printed circuit board assembly (PCBA). One example apparatus can include a PCBA of a solid state drive (SSD) and a damper configured to contact the PCBA, contact an enclosure of the SSD, and damp shock impulses applied to the SSD.
F16F 15/04 - Suppression des vibrations dans les systèmes non rotatifs, p.ex. dans des systèmes alternatifs; Suppression des vibrations dans les systèmes rotatifs par l'utilisation d'organes ne se déplaçant pas avec le système rotatif utilisant des moyens élastiques
H05K 5/02 - Enveloppes, coffrets ou tiroirs pour appareils électriques - Détails
40.
ERROR DETECTION AND CLASSIFICATION AT A MEMORY DEVICE
Methods, systems, and devices for error detection and classification are described. A memory device may read a codeword from a memory and generate a first set of syndrome bits for the codeword. The memory device may use the first set of syndrome bits to generate a first error detection bit. The memory device may generate a second set of syndrome bits for the codeword and use the second set of syndrome bits to generate a second error detection bit. The memory device may provide the first error detection bit and the second error detection bit to a host device.
G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
Methods, systems, and devices for determining offsets for memory read operations are described. In response to a threshold quantity of pages failing initial reads but being successfully read using a same reference adjustment during re-reads, the offset responsible for the adjustment may be used as a first-applied offset for subsequent re-reads or a baseline offset for subsequent initial reads. After the initial reads begin using the reference adjustment, if a threshold quantity of pages fail initial reads, the offset used for the initial read may be adjusted to be the offset used to perform the successful re-reads. If an updated offset to use a baseline is not identified, the baseline offset may be cleared so the original reference may again be used without adjustment for initial reads.
Described are semiconductor interposer, and microelectronic device assemblies incorporating such semiconductor interposers. The described interposers include multiple redistribution structures on each side of the core; each of which may include multiple individual redistribution layers. The interposers may optionally include circuit elements, such as passive and/or active circuit. The circuit elements may be formed at least partially within the semiconductor core.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/14 - Supports, p.ex. substrats isolants non amovibles caractérisés par le matériau ou par ses propriétés électriques
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
43.
TEMPORARY PARITY BUFFER ALLOCATION FOR ZONES IN A PARITY GROUP
Methods, systems, and apparatuses include allocating a temporary parity buffer to a parity group. A write command is received that includes user data and is directed to a portion of memory included in a zone which is included in the parity group. A memory identifier is determined for the portion of memory. Parity group data is received from the temporary parity buffer using the memory identifier. Updated parity group data is determined using the parity group data and the user data. The updated parity group data is sent to the temporary parity buffer.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
44.
DYNAMIC ADAPTATION OF AUTOMOTIVE AI PROCESSING POWER AND ACTIVE SENSOR DATA
Systems, methods, and apparatus related to dynamically adjusting sensing and/or processing resources of a vehicle. In one approach, sensor data is collected by sensing devices of the vehicle. A controller of the vehicle uses the sensor data to control one or more functions of the vehicle. The controller evaluates the sensor data to determine a context of operation (e.g., weather, lighting, and/or traffic) for the vehicle. Based on the context of operation, the controller adjusts the operation of one or more of the sensing or processing devices in real-time during operation of the vehicle. In one example, the adjustment reduces power consumption by the vehicle.
B60W 60/00 - Systèmes d’aide à la conduite spécialement adaptés aux véhicules routiers autonomes
B60L 58/10 - Procédés ou agencements de circuits pour surveiller ou commander des batteries ou des piles à combustible, spécialement adaptés pour des véhicules électriques pour la surveillance et la commande des batteries
H04W 4/48 - Services spécialement adaptés à des environnements, à des situations ou à des fins spécifiques pour les véhicules, p.ex. communication véhicule-piétons pour la communication dans le véhicule
45.
WAFER-LEVEL SOLID STATE TRANSDUCER PACKAGING TRANSDUCERS INCLUDING SEPARATORS AND ASSOCIATED SYSTEMS AND METHODS
Wafer-level packaging of solid-state transducers (“SSTs”) is disclosed herein. A method in accordance with a particular embodiment includes forming a transducer structure having a first surface and a second surface opposite the first surface, and forming a plurality of separators that extend from at least the first surface of the transducer structure to beyond the second surface. The separators can demarcate lateral dimensions of individual SSTs. The method can further include forming a support substrate on the first surface of the transducer structure, and forming a plurality of discrete optical elements on the second surface of the transducer structure. The separators can form barriers between the discrete optical elements. The method can still further include dicing the SSTs along the separators. Associated SST devices and systems are also disclosed herein.
H01L 33/58 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les éléments du boîtier des corps semi-conducteurs Éléments de mise en forme du champ optique
H01L 27/15 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants semi-conducteurs avec au moins une barrière de potentiel ou une barrière de surface, spécialement adaptés pour l'émission de lumière
H01L 33/46 - Revêtement réfléchissant, p.ex. réflecteur de Bragg en diélectriques
H01L 33/48 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les éléments du boîtier des corps semi-conducteurs
H01L 33/50 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les éléments du boîtier des corps semi-conducteurs Éléments de conversion de la longueur d'onde
H01L 33/54 - Encapsulations ayant une forme particulière
46.
MULTI-SAMPLED, CHARGE-SHARING THERMOMETER IN MEMORY DEVICE
A memory device includes an array of memory cells, a diode having a threshold voltage that changes with temperature, an analog-to-digital converter (ADC), and a pulse generator. The ADC includes a voltage comparator having a positive terminal coupled with the diode. The ADC further includes a first capacitor coupled between a negative terminal of the voltage comparator and ground, and a second capacitor selectively coupled between the first capacitor and a voltage reference node. The second capacitor has a smaller capacitance than that of the first capacitor. The pulse generator is coupled with the ADC and generates pulses. The pulses cause the first capacitor to connect to the second capacitor and equalize charge between the first capacitor and the second capacitor. An inverted signal of the pulses causes the second capacitor to be coupled with the voltage reference node to pre-charge the first capacitor.
G11C 7/04 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les effets perturbateurs thermiques
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
The disclosed embodiments relate to securely booting firmware images. In one embodiment, a method is disclosed comprising receiving, by a memory device, a firmware update; validating, by the memory device, a signature associated with the firmware update; copying, by the memory device, an existing firmware image to an archive location, the archive location storing a plurality of firmware images sorted by version identifiers; booting, by the memory device, and executing the firmware update; and replacing, by the memory device, the firmware update with the existing firmware image stored in the archive location upon detecting an error while booting the firmware update.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p.ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
48.
DIE FAMILY MANAGEMENT ON A MEMORY DEVICE USING BLOCK FAMILY ERROR AVOIDANCE
A target block family of a plurality of block families is identified periodically every predetermined number of program erase cycles (PECs) of a memory device. Each block family includes a plurality of blocks. A respective temporal voltage shift of each block of a subset of blocks of the target block family from each die of a plurality of dies associated with the target block family is obtained. A respective die measurement for each respective die is obtained based on an average of the respective temporal voltage shifts of the subset of blocks from each die. Each respective die to a respective die family of a plurality of consecutive die families is assigned based on the respective die measurement for each respective die.
A storage product having a network interface and a bus switch connecting a random-access memory, a processing device, and a storage device, and connected via an external computer bus to an external processor. The storage product can receive via the network interface first messages and second messages for network storage services. The bus switch is operable to provide a first bus between the processing device and the random-access memory to buffer the first messages into the random-access memory, a second bus between the processing device and the storage device to buffer the second messages into a local memory of the storage device, and a third bus between the processor and the random-access memory to retrieve the first messages from the random-access memory and generate third messages. The storage device is configured to process the second and third messages to provide network storage services.
Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation. The control logic further causes a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage.
Methods, systems, and devices for error detection and classification at a host device are described. A host device may communicate a read command for a codeword stored at a memory device. In response to communicating the read command, the host device may receive the codeword and an error indication bit that indicates whether the memory device detected an error in the codeword. The host device may use the codeword to generate a set of syndrome bits. The host device may determine an error status of the codeword based on the error indication bit for the codeword and the set of syndrome bits for the codeword.
H03M 13/15 - Codes cycliques, c. à d. décalages cycliques de mots de code produisant d'autres mots de code, p.ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
52.
FIN FIELD EFFECT TRANSISTOR SENSE AMPLIFIER CIRCUITRY AND RELATED APPARATUSES AND COMPUTING SYSTEMS
Fin field effect transistor (FinFET) sense amplifier circuitry and related apparatuses and computing systems are disclosed. An apparatus includes a pull-up sense amplifier, a pull-down sense amplifier, column select gates, global input-output (GIO) lines, and GIO pre-charge circuitry. The pull-up sense amplifier includes P-type FinFETs having a first threshold voltage potential associated therewith. The pull-down sense amplifier includes N-type FinFETs having a second threshold voltage potential associated therewith. The second threshold voltage potential is substantially equal to the first threshold voltage potential. The GIO lines are electrically connected to the pull-up sense amplifier and the pull-down sense amplifier through the column select gates. The GIO pre-charge circuitry is configured to pre-charge the GIO lines to a low power supply voltage potential.
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
53.
SEMICONDUCTOR DEVICE HAVING READ DATA BUSES AND WRITE DATA BUSES
An apparatus that includes: a plurality of first data amplifiers arranged in line in a first direction; a plurality of first read data buses each coupled to a corresponding one of the plurality of first data amplifiers, the plurality of first read data buses having different lengths one another; and a plurality of first write data buses each coupled to the corresponding one of the plurality of first data amplifiers, the plurality of first write data buses having different lengths one another. The plurality of first read data buses and the plurality of first write data buses are alternately arranged in parallel in a second direction vertical to the first direction. The plurality of first read data buses are arranged in longest order and the plurality of first write data buses are arranged in shortest order.
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
54.
GLOBAL COLUMN REPAIR WITH LOCAL COLUMN DECODER CIRCUITRY, AND RELATED APPARATUSES, METHODS, AND COMPUTING SYSTEMS
Global column repair with local column decoder circuitry and related apparatuses, methods, and computing systems are disclosed. An apparatus includes global column repair circuitry including column address drivers corresponding to respective ones of column planes of a memory array. The column address drivers are configured to, if enabled, drive a received column address signal to local column decoder circuitry local to respective ones of the column planes. The global column repair circuitry also includes match circuitry and data storage elements configured to store defective column addresses corresponding to defective column planes. The match circuitry is configured to compare a received column address indicated by the received column address signal to the defective column addresses and disable a column address driver corresponding to a defective column plane responsive to a determination that the received column address matches a defective column address associated with the defective column plane.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
A system can include a memory device a memory device comprising multiple dies, and a processing device, operatively coupled with the memory device, to perform various operations including identifying multiple management units to be programmed, where one management unit contains memory cells from a die having one endurance metric and another management unit contains memory cells from a die having another endurance metric, and determining a value of a media endurance metric for each management unit. The operations further include determining, for each management unit, a respective endurance exhaustion parameter defined by a relationship media endurance metrics, and distributing operations to each management unit based on the endurance exhaustion parameter.
Methods, systems, and devices for error status determination at a memory device are described. A memory device may generate, based on syndrome bits for a codeword read from a memory, an error detection signal for the codeword that indicates whether an error has been detected in the codeword. The memory device may generate, based on the syndrome bits, an error correction signal for the codeword that indicates whether an error has been corrected in the codeword. And the memory device may provide an indication of the error detection signal and an indication of the error correction signal to a host device.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
57.
MEMORY WITH DETERMINISTIC WORST-CASE ROW ADDRESS SERVICING, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS
Memory with deterministic worst-case row address servicing is disclosed herein. A method of the present technology comprises (1) updating a counter value corresponding to a memory row of a memory device in response to detecting activation of the memory row; (2) comparing the updated counter value to a worst-case count value; and (3) in response to determining that the updated counter value is greater than the worst-case count value, setting the worst-case count value equal to the updated counter value and storing a memory row address of the memory row as a worst-case memory row address. The counter value can be one of a plurality of counter values, each counter value (a) corresponding to a respective memory row and (b) configured to track a number of activations of the respective memory row. The method can further comprise performing a row disturb refresh operation using the worst-case memory row address.
Example embodiments are directed to a solid-state drive (SSD) enclosure design that is adaptable for different printed circuit board assemblies (PCBA). The SSD enclosure design comprises a three-piece construction that includes a top enclosure, a bottom enclosure, and an intermediate structure. The bottom enclosure is coupled to the top enclosure to form a housing for a PCBA having NOT AND (NAND) devices and a controller. The intermediate structure is coupled to the PCBA and positioned between the top enclosure and the bottom enclosure within the housing. The intermediate structure comprises a plurality of heatsinks to transfer heat from the NAND devices and a controller heatsink to transfer heat from the controller, whereby the type and location of the heatsinks can be changed for a different PCBA without having to change the top enclosure or bottom enclosure. The top enclosure can include vents that allow air to flow through.
Disclosed in some examples, are methods, systems, devices, and machine-readable mediums which provide for more efficient CGRA execution by assigning different initiation intervals to different PEs executing a same code base. The initiation intervals may be a multiple of each other and the PE with the lowest initiation interval may be used to execute instructions of the code that is to be executed at a greater frequency than other instructions than other instructions that may be assigned to PEs with higher initiation intervals.
Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
G11C 29/42 - Dispositifs de vérification de réponse utilisant des codes correcteurs d'erreurs [ECC] ou un contrôle de parité
H03K 19/21 - Circuits OU EXCLUSIF, c. à d. donnant un signal de sortie si un signal n'existe qu'à une seule entrée; Circuits à COÏNCIDENCES, c. à d. ne donnant un signal de sortie que si tous les signaux d'entrée sont identiques
A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of select gate transistors to strings of memory cells. The channel structures can be implemented as a segmented portion for drains and a portion opposite a gate. The segmented portion includes one or more fins and one or more non-conductive regions with both fins and non-conductive regions extending vertically from the portion opposite the gate. Variations of a border region for the portion opposite the gate with the segmented portion can include fanged regions extending from the fins into the portion opposite the gate or rounded border regions below the non-conductive regions. Such select gate transistors can be formed using a single photo mask process. Additional devices, systems, and methods are discussed.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
62.
SEMICONDUCTOR DEVICES COMPRISING TRANSISTORS HAVING INCREASED THRESHOLD VOLTAGE AND RELATED METHODS AND SYSTEMS
A transistor comprising threshold voltage control gates. The transistor also comprises active control gates adjacent opposing first sides of a channel region, the threshold voltage control gates adjacent opposing second sides of the channel region, and a dielectric region between the threshold voltage control gates and the channel region and between the active control gates and the channel region. A semiconductor device comprising memory cells comprising the transistor is also disclosed, as are systems comprising the memory cells, methods of forming the semiconductor device, and methods of operating a semiconductor device.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
Systems, methods, and apparatus related to cruise control for a vehicle. In one approach, speed for a first vehicle is controlled in a first mode using data from sensors. The speed is controlled while keeping at least a minimum distance from a second vehicle being followed by the first vehicle. In response to determining that data from the sensors is not usable to control the first vehicle (e.g., the data cannot be used to measure the minimum distance), the first vehicle changes from the first mode to a second mode. In the second mode, the first vehicle maintains a constant speed and/or obtains additional data from sensors and/or computing devices located externally to the first vehicle. In another approach, the additional data can additionally or alternatively be obtained from a mobile device of a passenger of the first vehicle. The additional data is used to maintain a safe minimum distance from the second vehicle.
Some embodiments include an integrated assembly having a CMOS region. Fins extend across the CMOS region and are on a first pitch. A circuit arrangement is associated with the CMOS region and includes segments of one or more of the fins. The circuit arrangement has a first dimension along a first direction. A second region is proximate the CMOS region. Conductive structures are associated with the second region. The conductive structures extend along a second direction different than the first direction. Some of the conductive structures are electrically coupled with the circuit arrangement. The conductive structures are on a second pitch different from the first pitch. A second dimension is a distance across said some of the conductive structures along the first direction, and the second dimension is substantially the same as the first dimension.
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
65.
EDGE-PROTECTED SEMICONDUCTOR DEVICE ASSEMBLIES AND ASSOCIATED METHODS
The present technology can include a semiconductor device assembly comprising an RDL with a top surface and a side surface intersecting the top surface. The assembly can further comprise a semiconductor device coupled to the top surfaces, and a mold material encasing the semiconductor device (when included) and directly coupled to at least a portion of the top surface and the side surface of the RDL. In other embodiments, the assembly can comprise an RDL with a top surface, a bottom surface opposite thereto, and a sloped side surface extending between the top surface and the bottom surface. The assembly similarly can further comprise a semiconductor device coupled to the top surface, and a mold material encasing the semiconductor device and directly coupled to at least a portion of the top surface and the side surface of the RDL.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
66.
BLOCK FAMILY-BASED ERROR AVOIDANCE FOR MEMORY DEVICES
An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initialize a block family associated with a memory device; initialize a timeout associated with the block family; initializing a low temperature and a high temperature using a reference temperature at the memory device; responsive to programming a block residing on the memory device, associate the block with the block family; and responsive to at least one of: detecting expiration of the timeout or determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, close the block family.
Some embodiments include an integrated assembly having a pillar of semiconductor material. The pillar has a base region, and bifurcates into two segments which extend upwardly from the base region. The two segments are horizontally spaced from one another by an intervening region. A conductive gate is within the intervening region. A first source/drain region is within the base region, a second source/drain region is within the segments, and a channel region is within the segments. The channel region is adjacent to the conductive gate and is vertically disposed between the first and second source/drain regions. Some embodiments include methods of forming integrated assemblies.
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/51 - Matériaux isolants associés à ces électrodes
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10B 51/40 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région de circuit périphérique
H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10B 53/40 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région de circuit périphérique
68.
SECURITY CAPSULE FOR ENABLING RESTRICTED FEATURES OF A MEMORY DEVICE
A processing device initializes a memory device in an unauthenticated state in which the memory device is unable to execute one or more restricted commands. The processing device accesses a security capsule that is digitally signed using a private key. The processing device transitions the memory device to an authenticated state based on verifying that the security capsule is validly signed. The processing device uses a public key corresponding to the private key to verify the security capsule is validly signed. While in the authenticated state, the memory device is able to execute the one or more restricted commands.
G06F 21/79 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données dans les supports de stockage à semi-conducteurs, p.ex. les mémoires adressables directement
G06F 12/14 - Protection contre l'utilisation non autorisée de mémoire
Exemplary methods, apparatuses, and systems include an intelligent boot manager for controlling initialization of components of vehicle computing systems. The intelligent boot manager receives an access request for a vehicle. The intelligent boot manager initializes a set of components of vehicle systems of the vehicle in response to the access request. The intelligent boot manager executes a first portion of code from a read-only memory (ROM) location, the first portion of code configuring a processor to initialize a random-access memory (RAM) location. The intelligent boot manager downloads a set of applications to the RAM location. The intelligent boot manager receives an engine start request for the vehicle, wherein the engine start request is distinct from the access request. The intelligent boot manager initiates an engine start sequence of the vehicle in response to the engine start request.
G07C 9/28 - Enregistrement de l’entrée ou de la sortie d'une entité isolée comportant l’utilisation d’un laissez-passer le laissez-passer permettant le repérage ou signalant la présence
Systems, methods, and apparatuses for data prioritization and selective data processing are described herein. A computing device may receive sensor data and prioritize a first portion of the sensor data over a second portion of the sensor data. The first portion of sensor data may be stored in a first memory that has a higher access rate than a second memory where the second portion of sensor data is stored. The first portion of sensor data may be processed with priority and the second portion of sensor data may be transmitted to a cloud computing device.
A microelectronic device comprises a stack structure, a staircase structure, a first liner material, a liner structure, conductive contact structures, and barrier structures. The stack structure comprises vertically alternating conductive structures and insulative structures arranged in tiers. Each of the tiers individually comprises one of the conductive structures and one of the insulative structures. The staircase structure has steps comprising edges of at least some of the tiers of the stack structure. The first liner material is on the steps of the staircase structure, and the liner structure on the first liner material. The conductive contact structures extend through the first liner material and the liner structure and to the conductive structures of the stack structure. The barrier structures are between the conductive contact structures and the liner structure vertically span substantially the same tiers of the stack structure as the liner structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 27/11556 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
A redundant array of independent disks (RAID) protection can be provided along with other types of error correction code (ECC) schemes that correct either errors in data prior to the data being input to the RAID process or residual errors from the RAID process. The ECC schemes can utilize parity bits generated using a parity matrix whose bit patterns have an amount of bits that can be used to identify a location of the memory system from which data corresponding to the respective bit pattern is read.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
73.
REFRESHING A MEMORY BLOCK ON POWER UP BASED ON AN AGE AND/OR TEMPERATURE CONDITION
In some implementations, a memory device may detect power up and may identify, based on detecting the power up, a plurality of blocks of the memory device for which a power up based refresh determination is to be performed. The memory device may perform the power up based refresh determination on the plurality of blocks. The memory device may determine whether a block, of the plurality of blocks, satisfies at least one of an age condition that is based on a difference between a current time and an opening time associated with opening the block for programming, or a temperature condition that is based on a difference between a current temperature and an opening temperature associated with the block at the opening time. The memory device may selectively refresh the block based on determining whether the block satisfies at least one of the age condition or the temperature condition.
According to one or more embodiments of the disclosure, an apparatus comprising a metal layer and a redistribution layer on the metal layer is provided. The redistribution layer includes an insulating layer, a via, and a redistribution metal layer. The via is in the insulating layer and has a rectangular shape in a plan view. The redistribution metal layer has a first thickness on a shorter side of the rectangular shape of the via and a second thickness on a longer side of the rectangular shape of the via. The second thickness is greater than the first thickness.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
75.
STAGGERED HORIZONTAL CELL ARCHITECTURE FOR MEMORY DEVICES
Methods, systems, and devices for staggered horizontal cell architecture for memory devices are described. Generally, the described techniques provide for a memory device that supports staggered cell architectures and techniques to manufacture the memory device. The memory device may include a stack of materials including alternating layers of dielectric and conductive material. The memory device may include one or more staircase structures coupled with the stack of layers. The memory device may include access lines, such as bit lines, that are staggered according to a pattern, such as a serpentine pattern of dielectric fill surrounding the access lines. The memory device may include a set of repeatable structures that may be interlaced in a staggered configuration. The repeatable structure may include two fins extending in opposite directions and coupled to a respective staircase structure.
Methods, systems, and devices for programming power management circuits in a system are described. An apparatus may include a set of one or more power management circuits configured to provide one or more operating voltages for the apparatus. The apparatus may also include an interface coupled with a controller via a bus. The apparatus may include a first switching circuit configured to isolate the bus from the controller and to couple the bus with a second switching circuit. The second switching circuit may be configured to isolate the set of one or more power management circuits from the controller and to couple the set of one or more power management circuits with the first switching circuit.
G06F 1/3234 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise
A device includes an amplifying device that when in operation transmits a data signal and a reference signal to a decision feedback equalizer (DFE) circuit. The amplifying device includes a variable gain amplifier (VGA) that when in operation generates the reference signal as having a predetermined gain relative to a received input signal and a continuous-time linear equalizer (CTLE) that operate to mitigate inter-symbol interference (IR) on the data signal from a data stream comprising the data signal. The device further includes correction circuitry coupled to the amplifying device, wherein the correction circuitry when in operation mitigates variation in the predetermined gain of the VGA or variation in an output common-mode voltage of the VGA.
Methods, systems, and devices for video stream augmentation using a deep learning device are described. A machine learning device of a vehicle may augment a video stream received from cameras of the vehicle and may output the augmented video stream to a display component of the vehicle. For example, a camera of the vehicle may record a video stream of and a sensor of the vehicle may detect information about an environment associated with the vehicle. The camera and sensor may transmit the video stream and information, respectively, to the machine learning device, which may process and modify the video stream based on parameters of the video stream and/or the information. The machine learning device may transmit the modified video streams to the display component, and the display component may display aspects of the modified video stream on a display of the vehicle, such as a rearview mirror.
G06V 10/77 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant l’intégration et la réduction de données, p.ex. analyse en composantes principales [PCA] ou analyse en composantes indépendantes [ ICA] ou cartes auto-organisatrices [SOM]; Séparation aveugle de source
B60R 1/12 - Ensembles de miroirs combinés avec d'autres objets, p.ex. pendules
B60R 1/22 - Dispositions de visualisation en temps réel pour les conducteurs ou les passagers utilisant des systèmes de capture d'images optiques, p.ex. des caméras ou des systèmes vidéo spécialement adaptés pour être utilisés dans ou sur des véhicules pour visualiser une zone extérieure au véhicule, p.ex. l’extérieur du véhicule
G01S 7/48 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe
G01S 17/08 - Systèmes déterminant les données relatives à la position d'une cible pour mesurer la distance uniquement
G01S 17/89 - Systèmes lidar, spécialement adaptés pour des applications spécifiques pour la cartographie ou l'imagerie
G06V 10/60 - Extraction de caractéristiques d’images ou de vidéos relative aux propriétés luminescentes, p.ex. utilisant un modèle de réflectance ou d’éclairage
G06V 20/40 - RECONNAISSANCE OU COMPRÉHENSION D’IMAGES OU DE VIDÉOS Éléments spécifiques à la scène dans le contenu vidéo
G06V 20/58 - Reconnaissance d’objets en mouvement ou d’obstacles, p.ex. véhicules ou piétons; Reconnaissance des objets de la circulation, p.ex. signalisation routière, feux de signalisation ou routes
H04N 7/18 - Systèmes de télévision en circuit fermé [CCTV], c. à d. systèmes dans lesquels le signal vidéo n'est pas diffusé
79.
APPARATUSES AND METHODS TO DEPRIORITIZE TRAFFIC TO UNAVILABLE MEMORY BANKS
An exemplary memory controller includes a refresh manager circuit configured to provide a refresh command to a memory system via a command and address bus to initiate a refresh operation at a bank of the memory system. In response to provision of the refresh command, the refresh manager circuit is further configured to issue a bank status command to the host to indicate that the bank of the memory system has switched to unavailable.
At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data is provided to the other memory cell of the memory component.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p.ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G11C 29/52 - Protection du contenu des mémoires; Détection d'erreurs dans le contenu des mémoires
81.
METHODS AND SYSTEMS FOR HANDLING DATA RECEIVED BY A STATE MACHINE ENGINE
A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.
G06F 12/0875 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec mémoire cache dédiée, p.ex. instruction ou pile
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 9/448 - Paradigmes d’exécution, p.ex. implémentation de paradigmes de programmation
A read operation is performed on a set of memory cells addressable by a first wordline (WL), wherein the set of memory cells is comprised by an open translation unit (TU_of memory cells of a memory device. Respective threshold voltage offset bins for each WL of a second plurality of WLs coupled to respective sets of memory cells comprised by the open TU are determined based on a threshold voltage offset bin associated with the first WL. Respective default threshold voltages for each WL of the first plurality of WLs are updated based on the respective threshold voltage offset bins for each WL of the second plurality of WLs.
Method of forming an isolation structure might include forming a first conductive region in a first section of a semiconductor material, forming a first trench in a second section of the semiconductor material adjacent a first side of the first section of the semiconductor material and forming a second trench in a third section of the semiconductor material adjacent a second side of the first section of the semiconductor material, extending the first and second trenches to a depth below the first conductive region and removing a portion of the first section of the semiconductor material overlying the first conductive region, forming second and third conductive regions in the semiconductor material below bottoms of the first and second trenches, respectively, and forming a dielectric material overlying the first conductive region and filling the first and second trenches.
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
H10B 41/41 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique de régions de mémoire comprenant un transistor de sélection de cellules, p.ex. NON-ET
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
84.
Redundancy-based error detection in a memory device
Methods, systems, and devices for redundancy-based error detection in a memory device are described. A memory device may read multiple copies of a codeword from memory and generate for each codeword copy an error detection bit that indicates whether the memory device detected an error in that codeword. Additionally, the memory device may compare the codeword copies and generate one or more match bits that indicate whether corresponding portions of the codewords match. Using a combination of the error detection bits and the match bits, the memory device may determine the error status of each codeword.
G06F 11/00 - Détection d'erreurs; Correction d'erreurs; Contrôle de fonctionnement
G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
Aspects of the present disclosure are directed to a memory sub-system with isothermal cooling of components. A PCB assembly may be secured between a heat spreader and a heat sink that are thermally coupled. The heat sink radiates heat absorbed from both sides of the PCB assembly. By connecting the heat spreader to the heat sink, heat is more effectively transferred from the side of the PCB assembly not directly connected to the heat sink. The PCB assembly may be secured between a top enclosure and a bottom enclosure. The top enclosure and the bottom enclosure may be thermally coupled using a vapor chamber. The vapor chamber pumps heat from a higher-temperature side of the PCB assembly to a lower-temperature side of the PCB assembly. By using the vapor chamber to thermally couple the top and bottom enclosures, creation of hot spots is avoided.
A computer having a plurality of accounts and a storage device having a host interface, a controller, non-volatile storage media, and firmware. An account is configured with at least a predetermined speed in accessing the non-volatile storage media by allocating a number of input/output submission queues in the buffer area of the host. The number can be determined from a ratio between the predetermined speed configured for the account and a saturated speed of the storage device with sufficient submission queues. Data access requests from the account are evenly distributed to the submission queues allocated for the exclusive use by the account; and the controller, configured via the firmware, processes with equal priority the submission queues configured for the storage device. Thus, the account can have at least the predetermined speed in accessing the non-volatile storage media, regardless of how other accounts access the storage device.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
Apparatuses, machine-readable media, and methods related to vehicle diagnosis and repair are described. Receiving vehicle status information from a control panel and/or on board diagnostic (OBD) unit of a vehicle at a vehicle diagnosis and repair too can provide valuable information to an owner and/or user of a vehicle. Computing devices (e.g., mobile devices and/or modules having a computing device) can be configured to run an application (e.g., a vehicle diagnosis and repair tool) to determine whether a vehicle needs to be repaired or serviced according to examples of the present disclosure. The vehicle diagnosis and repair tool can receive vehicle status information, determine the repairs and/or service that the vehicle needs, and initiate the vehicle repairs and/or service.
G07C 5/00 - Enregistrement ou indication du fonctionnement de véhicules
G07C 5/08 - Enregistrement ou indication de données de marche autres que le temps de circulation, de fonctionnement, d'arrêt ou d'attente, avec ou sans enregistrement des temps de circulation, de fonctionnement, d'arrêt ou d'attente
Disclosed is a system comprising a memory device and a processing device, operatively coupled with the memory device, to perform operations including identifying a group of memory cells corresponding to a first range of logical block addresses (LBAs). The operations performed by the processing device further include receiving a memory access command with respect to the group of memory cells. The operations performed by the processing device further include responsive to determining that a data structure associated with the group of memory cells references a second range of LBAs, blocking the memory access command; responsive to determining that the first range of LBAs does not include each LBA of the second range of LBAs, performing, on the group of memory cells, a trim operation; and responsive to determining that the data structure indicates the completion of the trim operation, performing a memory access operation specified by the memory access command.
Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.
H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
90.
SCHEDULING OF READ OPERATIONS AND WRITE OPERATIONS BASED ON A DATA BUS MODE
A data bus coupled to a plurality of memory devices is determined to be in a read mode. Responsive to determining that the data bus is in the read mode, a particular read operation identified in a particular memory queue of memory queues that include identifiers of one or more write operations and identifiers of one or more read operations is determined. The particular memory queue includes a highest number of read operations for a memory device of the memory devices. The particular read operation is transmitted from the particular memory queue over the data bus.
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
91.
Array of Memory Cells, Methods Used in Forming an Array of Memory Cells, Methods Used in Forming an Array of Vertical Transistors, Methods Used in Forming an Array of Vertical Transistors, and Methods Used in Forming an Array of Capacitors
A method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above and directly against a first capacitor electrode material. A mask is used to subtractively etch both the transistor material and thereafter the first capacitor electrode material to form a plurality of pillars that individually comprise the transistor material and the first capacitor electrode material. Capacitors are formed that individually comprise the first capacitor electrode material of individual of the pillars. Vertical transistors are formed above the capacitors that individually comprise the transistor material of the individual pillars. Other aspects and embodiments are disclosed, including structure independent of method.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/22 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des éléments ferro-électriques
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10B 53/40 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région de circuit périphérique
92.
IMPROVED MEMORY PERFORMANCE USING MEMORY ACCESS COMMAND QUEUES IN MEMORY DEVICES
Systems and methods are disclosed including a controller and a memory device comprising a first plane and a second plane where each plane is associated with a respective queue maintained by the controller. The local media controller is configured to perform operations comprising storing, in a first queue associated with the first plane, a first plurality of memory access commands; storing, in a second queue associated with the second plane, a second plurality of memory access commands; and processing the first plurality of memory access commands from the first queue and the second plurality of memory access commands from the second queue.
An interposer includes an upper surface for coupling to a chip, a lower surface for coupling to a package substrate, and redistribution layers between the upper surface and the lower surface and including routed conductive lines. A respective one of the routed conductive lines extend between a first location and a second location and includes two or more traces extending substantially in parallel between the first location and the second location. Related devices and methods are also described.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 23/14 - Supports, p.ex. substrats isolants non amovibles caractérisés par le matériau ou par ses propriétés électriques
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
Methods, systems, and devices for plasma-doped trenches for memory are described. A method for forming a memory device with plasma-doped trenches may include forming a stack of materials having alternating layers of polysilicon and oxide materials. A trench may be etched in the stack and doped using a plasma doping process. In some examples, the trench may be doped by applying Boron fluoride, diborane, methane, or Boron and Carbon Hydride gases diluted with Hydrogen (H2) or Helium to the sidewalls and bottom surface of the trench, which may dope portions of the polysilicon material with Boron, Carbon, Fluorine, Helium, or Hydrogen.
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p.ex. structures d'interconnexions enterrées
95.
PROVIDING MULTIPLE ERROR CORRECTION CODE PROTECTION LEVELS IN MEMORY
The present disclosure relates to providing multiple error correction code protection levels in memory. One device includes an array of memory cells and an operating circuit for managing operation of the array. The operating circuit comprises an encoding unit configured to generate a codeword for a first error correction code (ECC) protection level and a second ECC protection level, and decoding unit configured to perform an ECC operation on the codeword at the first ECC protection level and the second ECC protection level. The codeword comprises payload data stored in a plurality of memory cells of the array, and parity data associated with the payload data stored in parity cells of the array.
A multi-interface memory can include a memory package that includes a memory device and host interfaces coupled to the memory device. Each of the host interfaces is configured to operate according to a different protocol. The memory package can be coupled to a host via one or more of the host interfaces. More than one of the host interfaces can share a contact.
A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. The channel-material strings directly electrically couple to conductor material of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises a laterally-outer insulative lining extending longitudinally-along the immediately-laterally-adjacent memory-blocks. The laterally-outer insulative lining has its lowest surface between a top and a bottom of the lowest conductive tier. The laterally-outer insulative lining has its highest surface at or below a lowest surface of the next-lowest conductive tier. Laterally-inner insulating material extends longitudinally-along the immediately-laterally-adjacent memory blocks laterally-inward of the laterally-outer insulative lining. An interface is between the laterally-outer insulative lining and the laterally-inner insulating material. Methods are also disclosed.
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
H01L 27/11556 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
A decoding operation is performed by altering at least one bit of the bit string from a first value to a second value and applying a bit mask to each bit of the bit string that is not altered from the first value to the second value. The decoding operation further includes writing an indication corresponding to a quantity of bits that have been altered from the first value to the second value to an array of memory cells, wherein the indication corresponds to a quantity of errors contained in the bit string, determining that the quantity of errors for the bit string has reached a threshold quantity of errors, and refraining from performing a subsequent operation to alter at least the one bit of the bit string, or a different bit of the bit string, or both, from the first value to the second value in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
H03M 13/15 - Codes cycliques, c. à d. décalages cycliques de mots de code produisant d'autres mots de code, p.ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]
99.
ERROR DETECTION, CORRECTION, AND MEDIA MANAGEMENT ON A DRAM DEVICE
In a memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, the data is corrected and written back to the same memory location. The memory location is re-read. If bit errors are again identified, the memory location is marked for soft or hard repair. If, upon rereading the memory location, additional bit errors are identified, a historical record of memory errors is reviewed to determine if bit errors have occurred previously at the same memory location. If yes, the memory location is again marked for a soft post package repair or a hard post package repair.
Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G11C 29/42 - Dispositifs de vérification de réponse utilisant des codes correcteurs d'erreurs [ECC] ou un contrôle de parité
