A system for and a method of generating an ordered list of instructions comprising a list of pixel coordinates which are vertices (53) of triangles (51) in a strip (50) of a reference input image (33'; Fig. 11) in a source coordinate system (30; Fig. 11) such that transformation of the vertices to a corresponding output image (33; Fig. 10) in a destination coordinate system (32; Fig.11) causes the triangles to be mapped to a block (47) of image data which maps to a block of line memory (or "texture cache"). The method comprises dividing the reference output image into a plurality of tiled sections (35; Fig. 11) in the destination coordinate system. The method comprises, for each section, defining first and second boundaries of an array of strips (50) of pixels (46) in the section by dividing the section into blocks of line memory. The method comprises, for each strip, dividing each set of pixels contained in each strip into a series of ordered triangles, generating a set of destination and source coordinates for each vertex of each triangle in the strip and storing the coordinates of the vertices (53) in source and destination coordinate system (30, 32), in the ordered list of instructions.
H03L 7/08 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase
H03K 5/131 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés contrôlées numériquement
SYNCSYNC) which is externally-triggered and logic (26) configured to compare the number of pulses generated during the synchronisation period with an expected number (25) of pulses to determine a difference value (29) and to adjust the frequency of the oscillator in dependence on the difference value.
H03L 7/181 - Synthèse de fréquence indirecte, c. à d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle le résultat d'un comptage numérique étant utilisé pour verrouiller la boucle, le compteur comptant pendant des intervalles de temps fixes
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G06T 1/20 - Architectures de processeurs; Configuration de processeurs p.ex. configuration en pipeline
G06K 9/00 - Méthodes ou dispositions pour la lecture ou la reconnaissance de caractères imprimés ou écrits ou pour la reconnaissance de formes, p.ex. d'empreintes digitales
G06K 9/46 - Extraction d'éléments ou de caractéristiques de l'image
Oscillator circuitry is disclosed. The oscillator circuitry comprises a free-running oscillator (8) for generating pulses at a frequency, and a frequency adjustment circuit for adaptively adjusting the frequency of the free-running oscillator. The frequency adjustment circuit comprises a counter (15) configured to count a number (24) of pulses (22) generated by the free-running oscillator and logic (26) configured to compare the number of pulses with an expected number (25) of pulses (corresponding to a target frequency) to determine a difference value (29) and to adjust the frequency of the free-running oscillator in dependence on the difference value. The frequency adjustment circuit is configured, in response to receiving a synchronisation pulse (4; Fig. 3), to trigger an update of the number of pulses to be compared.
H03L 7/181 - Synthèse de fréquence indirecte, c. à d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle le résultat d'un comptage numérique étant utilisé pour verrouiller la boucle, le compteur comptant pendant des intervalles de temps fixes
6.
CONTINUOUS-TIME CHOPPER AMPLIFIER WITH AUTO OFFSET CORRECTION
Apparatus for continuous-time chopper amplification with auto offset correction is disclosed. The apparatus comprises a continuous-time, single-stage chopper amplifier. The apparatus comprises a continuous-time, single-stage chopper amplifier comprising a chopper modulator (11) configured to modulate first and second input signals (3, 4) and output first and second modulated signals (12, 15), a first summing unit (16) configured to add the first modulated signal (12) and a first offset correction signal (33) and to output a first corrected modulated signal (12'), a second summing unit (17) configured to add the second modulated signal (15) and a first offset correction signal (33) and to output a second corrected modulated signal (15'), a full-differential amplifier (19) configured to differentially amplify the first and second corrected modulated signal (15') and output first and second differentially amplified signals (20, 21), and a chopper modulator (11) configured to demodulate first and second differentially amplified signals (20, 21) and output first and second output signals (26, 27). The apparatus further comprises an auto offset correction circuit (32) comprising a polarity-determining section (42) arranged to output a polarity signal (P) indicative of whether positive or negative correction is required, and an offset correction generating section (43) arranged to output the first and second offset correction signals (40, 41) in dependence upon the polarity signal. The chopper amplifier is a single-stage amplifier and the fully-differential amplifier is the only amplifier, or the chopper amplifier is a multi-stage amplifier comprising the fully-differential amplifier and at least one other differential amplifier arranged between input terminals and output terminals of the chopper amplifier, and the fully-differential amplifier precedes the at least one other differential amplifier.
H03F 3/187 - Amplificateurs à basse fréquence, p.ex. préamplificateurs à fréquence musicale comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H03F 3/38 - Amplificateurs de courant continu, comportant un modulateur à l'entrée et un démodulateur à la sortie; Modulateurs ou démodulateurs spécialement conçus pour être utilisés dans de tels amplificateurs
1CPGBSBS) to a bootstrap capacitor (17), a pre-driver (18) for generating the drive signal, the pre-driver having a voltage input (20 ) and an output (22) which is coupled to the first output, and a power supply control section (25) comprising first and second switches (28,29). The first and second switches (28, 29) are arranged in series between the first input (7) and the second output ( 16), the second input ( 8 ) is coupled to a node (34) between the first and second switches (29), and the second node (34) is coupled to a voltage input (20 ) of the pre-driver. The first and second switches are selectively operable following switching of the switching element from an ON state to an OFF state and in response to a determination that the source voltage is below a predetermined level, to decouple the second output (16) and in response to determination that the source voltage is above the predetermined level to couple the second output (16) to the second output (16).
sense_insense_in) in dependence upon the voltage, an accumulator (CSOA) storing a value indicative of power dissipated by the transistor and which depends on the current; and a comparator (R, 45, 46) configured to determine whether the value exceeds a threshold value and, in dependence on the value exceeding the threshold value, to generate a signal (SOA_SD) to cause the transistor to be switched off.
H03K 17/082 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension par réaction du circuit de sortie vers le circuit de commande
H03K 17/18 - Modifications pour indiquer l'état d'un commutateur
A network device (1) comprising a set of queues (2) and a time-aware shaper (3) which comprises a set of transmission gates (4) and gate control instructions (5; Fig. 5). The gate control list comprises a set of individual gate control lists (7), each individual gate control list configured to control a respective gate and which comprises a sequence of entries (10), each entry comprising a duration of time (11; Fig. 11).
A semiconductor device (110) has a memory (112) and a control circuit (111). The semiconductor device provides preset data to an external terminal device. The memory (112) stores key information for authenticated encryption. The control circuit (111) divides data into a plurality of divided data while maintaining contiguity in a data array and generates a transmission header on the basis of a signal outputted by encrypting the immediately preceding divided data in the data array. The control circuit (111) generates encryption divided data and an authentication tag that corresponds to the encryption divided data, respectively, from the transmission header, the divided data, and the key information, and outputs the encryption divided data and the authentication tag that corresponds to the encryption divided data in accordance with an order in the data array.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
H04L 9/36 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité avec des moyens pour détecter des caractères non destinés à la transmission
11.
SEMICONDUCTOR DEVICE, UPDATE DATA-PROVIDING METHOD, UPDATE DATA-RECEIVING METHOD, AND PROGRAM
A semiconductor device comprising: a memory (132), a random number generation circuit (135), and a control circuit (131). The memory (132) stores key information, and the random number generation circuit (135) generates a first random number signal and a second random number signal. The control circuit (131) generates a sixth random number signal and a seventh random number signal from the first random number signal and the key information, uses the seventh random number signal for update data to generate encrypted update data, generates the first random number signal and the second random number signal as request signals to be sent to an external terminal device, receives a first response signal and a second response signal from the external device as response signals to the request signals, and generates an eighth random number signal by using the first response signal, the second random number signal, and the sixth random number signal as input signals. When the second response signal and the eighth random number signal match each other, the control circuit (131) provides the encrypted update data to the external terminal device.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
A computer-implemented method of generating functional safety data for a design of an electronic component comprising a plurality of elements is disclosed. The method comprises receiving attribute data (12, 13, 17, 50) for a plurality of elements comprises in an electronic component, such as a microcontroller. The attribute data comprise element data (17) for the plurality of elements, wherein element data for a given element (130) include an identity (131) of the given element and a failure rate characteristic (135) for the given element. The attribute data comprise functionality data (50) for a plurality of element functionalities, wherein functionality data for a given element functionality (140) include an identity (142) of a use case, an identity (144) of an element, an identity (146) of a fault characterisation for providing information about one or more fault models and a configurable data (148) for controlling selection and use of the given functionality data when generating the functional safety data. The method also comprises generating the functional safety data (14; Fig. 1) using the attribute data and storing a report (6; Fig. 1) including the functional safety data.
A first comparator (1) compares first input data with second input data, and provides one when the first input data is larger than the second input data and zero when the first input data is equal to or smaller than the second input data as a first comparison result. A data generator (3) generates data based on the second input data. A second comparator (2) compares the first input data with the generated data, and provide one when the first input data is larger than the generated data and zero when the first input data is equal to or smaller than the generated data as a second comparison result. A data initializer (4) initializes third input data. An adder (5) adds the first and second comparison results to the third input data initialized in advance, and to provide the added data as the current third input data.
G06K 9/56 - Combinaisons de fonctions de prétraitement en utilisant un opérateur local, c. à d. des moyens pour opérer sur un point image élémentaire en fonction des éléments situés à proximité immédiate de ce point
G06T 7/593 - Récupération de la profondeur ou de la forme à partir de plusieurs images à partir d’images stéréo
A semiconductor device according to an embodiment of the present invention is configured such that the thickness of a semiconductor layer of an SOI substrate on which a field-effect transistor constituting an analog circuit is formed is set to 2-24 nm.
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A hardware circuit (1) in which integer numbers are used to represent fixed-point numbers having an integer part and a fractional part is disclosed. The hardware circuit comprises a multiply-accumulate unit (8) configured to perform convolution operations using input data (3) and weights (11) and, in dependence thereon, to generate an intermediate result (12). The hardware circuit comprises a bias bit shifter (18) configured to shift a bias value (16) bitwise by a bias shift value (19) so as to provide a bit-shifted bias value (14), a carry bit shifter (22) configured to shift a carry value (20) bitwise by a carry shift value (23) so as to provide a bit-shifted carry value (15), an adder tree (13) configured to add the intermediate result (12), the bit-shifted bias value (14) and the bit-shifted carry value (15) so as to provide a multiple-accumulate result (24) and a multiply-accumulate bit shifter (25) configured to shift the multiple-accumulate result (24) bitwise by a multiply-accumulate shift value (26) so as to provide a bit-shifted multiply-accumulate result (27). The hardware circuit comprises a post-processing stage (28) configured to receive the bit-shifted multiply-accumulate result and, in dependence thereon, to generate output data. The hardware circuit is configured to receive a set of input data as a series of portions of data and, for each portion of data, to generate a corresponding portion of output data. The hardware circuit further comprises a maximum/minimum handler (30) configured to count, in a given set of output data, first and second numbers of values of output data that exceed a first threshold or fall below a second threshold respectively and to determine whether the first number exceeds a third threshold or the second number exceeds a fourth threshold respectively and, if so, to output a first value (UV) stored in a first table (31) indicative of whether the first number exceeds the third threshold and/or the second number exceeds the fourth threshold for the given set of input data; and a controller (34) configured to update a second value (OCFP) stored in a second table (32) to be used for the next set of input data in dependence of the first value, and to set the bias shift value (19), the carry shift value (23) and the multiply-accumulate shift value (26) in dependence on the updated second value.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06K 9/00 - Méthodes ou dispositions pour la lecture ou la reconnaissance de caractères imprimés ou écrits ou pour la reconnaissance de formes, p.ex. d'empreintes digitales
G06K 9/46 - Extraction d'éléments ou de caractéristiques de l'image
Apparatus for performing offset cancellation is disclosed. The apparatus comprises a gating circuit (6) for receiving an analogue signal (3) from a source (2) and providing a gated analogue signal (9) to an analogue circuit (10), a gating controller (7; 14; Fig. 1) and a digital processor (14; Fig. 1) for receiving a digital signal (13) converted from an analogue output (11) from the analogue circuit (10). The gating circuit comprises at least one path (2), each path respectively comprising, an input terminal (22), an output terminal (23), a node (24) interposed between the input and output terminals, a first transistor (Q1) having a channel arranged between the input terminal and the node, and a second transistor (Q3) having channel arranged between the node and a fixed reference, such as ground (GND). The gating controller is configured, in a first time window (1A), to switch the first transistor so that the input terminal and the output terminal are decoupled and to switch the second transistor so that the node is coupled to the fixed reference. The gating controller is configured, in a second, different time window (1B), to switch the second transistor so that the node and the fixed reference are decoupled and to switch the first transistor so that the input terminal is coupled to the input terminal. The digital processor is configured, in the first time window, to take a first measurement of the digital signal, and, in the second, different time window, to take a second measurement of the digital signal. The digital processor configured to subtract the first measurement from the second measurement.
An ultrasonic flow measurement system is disclosed. The system comprises a signal generator (32) configured to generate a first excitation signal (25) for a first ultrasonic transducer (9) and a second excitation signal (26) for a second, different ultrasonic transducer (10). The system comprises a phase differentiator (33) configured to generate a differential phase angle signal (34) indicative of a difference in phase angle between first and second receive signals (27, 28) received from the first and second transducers which is indicative of flow rate.
G01F 1/66 - Mesure du débit volumétrique ou du débit massique d'un fluide ou d'un matériau solide fluent, dans laquelle le fluide passe à travers un compteur par un écoulement continu en mesurant la fréquence, le déphasage, le temps de propagation d'ondes électromagnétiques ou d'autres types d'ondes, p.ex. en utilisant des débitmètres à ultrasons
A method of determining a probabilistic metric for random hardware failure for an electronic system, such as a microcontroller, which comprises element and safety mechanisms (SMs) is disclosed. The safety mechanisms include first layer safety mechanisms (FL-SMs) and second layer safety mechanism s (SL-SMs). A first layer safety mechanism may provide at least partial coverage of failure of a part and a second layer safety mechanism may provide at least partial coverage of failure of a first layer safety mechanism. The method comprises calculating a first set of probabilities (KSM_D associated with the first layer safety mechanisms, calculating a second set of probabilities (KDvF_n) associated with direct violation faults in the parts and calculating a third set of probabilities (KrvF_n) associated with indirect violation faults in the parts. The method includes obtaining the value of probabilistic metric for random hardware failure in dependence on the first, second and third sets of probabilities.
A communications network controller module (12) for storing media data in memory is disclosed. The module comprises a media access controller (41) and a message handler 5 (42). The message handler is configured, in response to receiving a frame (9) comprising frame data from the media access controller, to identify a frame type for the frame, to identify a target queue (200, 201, …, 20r) in dependence upon the frame type, the target queue comprising a series of data areas (64) in memory (13) reserved for storing frames of the frame type, to obtain a current descriptor address (65) of a 10 current descriptor (63) for the target queue, the current descriptor comprising a descriptor type field (66), a descriptor pointer field (67) and a descriptor data size field (69), and to obtain an address in the series of data areas, to store a part (61) of the frame data at the data area address. The message handler is configured, in dependence upon determining that a descriptor type held in the descriptor type field (66) indicates 15 the frame data part is to be stored contiguously in the series of data areas, to obtain the address at which to store the frame data part by reading the address from a current incremental address register (490, 491, …, 49r) for the target queue.
H04N 21/236 - Assemblage d'un flux multiplexé, p.ex. flux de transport, en combinant un flux vidéo avec d'autres contenus ou données additionnelles, p.ex. insertion d'une adresse universelle [URL] dans un flux vidéo, multiplexage de données de logiciel dans un flu; Remultiplexage de flux multiplexés; Insertion de bits de remplissage dans le flux multiplexé, p.ex. pour obtenir un débit constant; Assemblage d'un flux élémentaire mis en paquets
H04N 21/414 - Plate-formes spécialisées de client, p.ex. récepteur au sein d'une voiture ou intégré dans un appareil mobile
H04N 21/44 - Traitement de flux élémentaires vidéo, p.ex. raccordement d'un clip vidéo récupéré d'un stockage local avec un flux vidéo en entrée ou rendu de scènes selon des graphes de scène MPEG-4
H04L 12/861 - Mise en mémoire tampon de paquets ou mise en file d’attente; Ordonnancement de file d’attente
A device (10) for open load diagnosis of a signal line (4) in a digital system in which a logic state is represented by a band of voltages (20, 21) lying between first and second voltage limits is described. The device is configured to cause the signal line to reach a first, stable voltage lying in the band, to apply a second, different voltage to the signal line lying in the band and without leaving the band, to perform a time constant dependent measurement so as to determine a value of a parameter which is or depends on resistance of a load between the signal line and a reference line, to compare the value of the parameter with a reference value of the parameter and, in dependence on comparison, to signal the result.
G01R 27/16 - Mesure de l'impédance d'un élément ou d'un réseau dans lequel passe un courant provenant d'une autre source, p.ex. câble, ligne de transport de l'énergie
G01R 31/02 - Essai des appareils, des lignes ou des composants électriques pour y déceler la présence de courts-circuits, de discontinuités, de fuites ou de connexions incorrectes de lignes
G01R 31/04 - Essai de connexions, p.ex. de fiches de prises de courant ou de raccords non déconnectables
This semiconductor storage device comprises: a plurality of memory cells arranged in a matrix; word lines provided corresponding to rows of the memory cells; dummy word lines formed in a metal wiring layer adjacent to the metal wiring layer wherein the word lines are formed; a word line driver circuit for driving the word lines; and a dummy word line driver circuit for boosting the word lines on the basis of the interline capacitance between the word lines and the dummy word lines.
A semiconductor device has a semiconductor substrate SB, and a wiring structure formed on the principal plane of the semiconductor substrate SB. The first wiring layer, which is topmost among the plurality of wiring layers included in the wiring structure, includes a pad PD, and the pad PD has a first region for joining copper wire, and a second region for making contact with a probe. A second wiring layer, which is one layer below the first wiring layer among the plurality of wiring layers included in the wiring structure, includes a wiring M6 arranged directly below the pad PD, the wiring M6 is arranged directly below a region other than the first region of the pad PD, and a conductor pattern of the same layer as the wiring M6 is not formed directly below the first region of the pad PD.
H01L 21/3205 - Dépôt de couches non isolantes, p.ex. conductrices ou résistives, sur des couches isolantes; Post-traitement de ces couches
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
A semiconductor storage device comprising: a plurality of memory cells arranged in a matrix; word lines provided corresponding to the memory cell rows; dummy word lines formed in a metal wiring layer adjacent to a metal wiring layer having the word lines formed therein; a word driver circuit that drives the word lines; and a dummy word driver circuit that boosts the word lines on the basis of the inter-line capacity between the word lines and the dummy word lines.
G11C 11/413 - Circuits auxiliaires, p.ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture, la synchronisation ou la réduction de la consommation
A message handler (61, 62) is described. The message handler is configured, in response to receiving a data package (131, 132) which is formatted according to a given communications protocol, such as CAN or Ethernet, and which comprises package- directing data (22; Fig. 4) and payload data (23; Fig. 4), to generate package (14) having a predetermined data format, for example a layer-2 or layer-3 package, which comprises a header (24; Fig. 4) and payload data (25; Fig. 4). The header comprises an address generated in dependence upon the package-directing data and wherein the payload comprises the data package. The package (14) having a predetermined data format may be an IEEE 1722 frame.
According to one embodiment of the present invention, a semiconductor device has a first semiconductor component and a second semiconductor component, which are mounted on a wiring board. The first semiconductor component has a first terminal for performing transmission of first signals between the outside and the first semiconductor component, and a second terminal for performing transmission of second signals between the second semiconductor component and the first semiconductor component. The second semiconductor component has a third terminal for performing transmission of the second signals between the first semiconductor component and the second semiconductor component. The first signals are transmitted at a frequency that is higher than the frequency at which the second signals are transmitted. The second terminal of the first semiconductor component, and the third terminal of the second semiconductor component are electrically connected to each other via the first wiring member. The first terminal of the first semiconductor component is electrically connected to the wiring board not via the first wiring member, but via a first bump electrode.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
An electronic device according to one embodiment of the present invention has a wiring board having first wiring to which a first external terminal is connected, and second wiring to which a second external terminal is connected and which extends along the first wiring. The electronic device further has a semiconductor device that is mounted on the wiring board and is electrically connected to the first wiring and the second wiring, respectively. The electronic device further has a capacitor that is mounted on the wiring board and is electrically connected to the semiconductor device via the first wiring and the second wiring, respectively. The distance between the semiconductor and the capacitor is shorter than the distance between the capacitor and the first external terminal and the second external terminal, respectively.
In order to improve reliability of a semiconductor device, in a semiconductor chip according to one embodiment of the present invention, a recessed and protruding shape is formed in the exposed surface of a rear surface electrode that is formed on the rear surface of the semiconductor chip.
H01L 23/28 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
This semiconductor device includes: a wiring board that is provided with a first surface and a second surface on the reverse side of the first surface; a semiconductor chip, which is provided with a plurality of chip electrodes, and is mounted on the wiring board; a first capacitor, which is disposed at a position overlapping the semiconductor chip in plan view, and which is embedded in the wiring board; and a second capacitor that is disposed between the first capacitor and a peripheral portion of the wiring board in plan view. Furthermore, the second capacitor is inserted into a signal transmission path by being connected in series, said signal transmission path inputting or outputting electric signals with respect to the semiconductor chip.
The semiconductor device according to the present invention is provided with: a plurality of masters (100); a memory controller (400a); buses which connect the plurality of masters (100) to the memory controller (400a); a QoS information register (610) which stores QoS information about the plurality of masters (100); a unit (602) for controlling the number of rights to be granted, which calculates the maximum number of access rights that can be granted, on the basis of free space information about a buffer (401) of the memory controller (400a); a rights grant selection control unit (603a) which selects a master (100) to be granted access rights, on the basis of the QoS information in the QoS information register (610) and on the basis of the maximum number of access rights that can be granted, obtained from the unit (602) for controlling the number of rights to be granted; and request issuance control units (201a) which prevent passage of requests issued by any masters (100) that have not been granted access rights by the rights grant selection control unit (603a).
The present invention prevents deterioration of rewiring due to reaction of the rewiring with water, ions, and the like, said reaction being caused by exposure of the rewiring from an upper layer insulating film. As a means for the prevention, disclosed is a semiconductor device, in which a plurality of wiring layers are formed on an element forming region, and which has rewiring connected to a pad electrode, i.e., the topmost wiring layer. A dummy pattern is disposed in a region closer to a scribe region than the rewiring.
H01L 21/3205 - Dépôt de couches non isolantes, p.ex. conductrices ou résistives, sur des couches isolantes; Post-traitement de ces couches
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
Disclosed is an electronic device wherein: a first semiconductor device having a switching power transistor is mounted on a power wiring board PB1; a semiconductor device PKG6 having a drive circuit that drives the first semiconductor device, and a semiconductor device PKG5 having a control circuit that controls the semiconductor device PKG6 are mounted on a first main surface of a control wiring board PB2; and a semiconductor device PKG4 having a regulator circuit is mounted on a second main surface of the control wiring board PB2. The semiconductor device PKG5 and the semiconductor device PKG6 are mounted on, out of a second region and a third region, the second region of the first main surface of the control wiring board PB2, said second region and third region being adjacent to each other by having therebetween a first region where a plurality of holes HC3 are disposed. The semiconductor device PKG4 is mounted on, out of a fourth region positioned on the reverse side of the second region, and a fifth region positioned on the reverse side of the third region, the fifth region on the second main surface of the control wiring board PB2.
H05K 1/14 - Association structurale de plusieurs circuits imprimés
H02K 11/30 - Association structurelle à des circuits de commande ou à des circuits d’entraînement
H02M 7/48 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande
A plurality of semiconductor devices, each of which has a semiconductor chip that is provided with a high-side MOSFET, and a semiconductor chip that is provided with a low-side MOSFET, are mounted on a wiring board (PB1). The wiring board (PB1) has: a power supply wiring line WV1 that is supplied with a power supply potential; and output wiring lines WD1, WD2, WD3, which electrically connect low-side drain terminals of the semiconductor devices to a plurality of output terminals. The minimum value and the maximum value of the width of a current path in the power supply wiring WV1 are set as a first minimum width and a first maximum width, respectively, and the minimum value and the maximum value of the width of a current path in the output wiring lines WD1, WD2, WD3 are set as a second minimum width and a second maximum width, respectively. In the cases where the first minimum width is smaller than the second minimum width, the first minimum width is larger than the half of the second maximum width, and in the cases where the second minimum width is smaller than the first minimum width, the second minimum width is larger than the half of the first maximum width.
H02M 7/48 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande
33.
LICENSE MANAGEMENT METHOD, SEMICONDUCTOR DEVICE SUITABLE FOR LICENSE MANAGEMENT, AND LICENSE MANAGEMENT SYSTEM
This license management method which includes an execution device for executing software and a software storage device connected to the execution device is provided with a license storage device for storing license information indicating the number of software licenses that are granted, and includes a license management step in which, when software that requires granting of the license thereof is to be downloaded, storing, in the software storage device, of the software to be downloaded or execution, by the execution device, of the software to be downloaded is controlled on the basis of the license information stored in a license storage unit.
According to one embodiment of the present invention, a semiconductor device has a first semiconductor component and a second semiconductor component, which are electrically connected to each other via interposers. The interposers have a plurality of first signal wiring paths, and a plurality of second signal wiring paths which respectively have path distances that are shorter than those of the first signal wiring paths. The first semiconductor component is provided with a first electrode, a second electrode, and a third electrode, which are sequentially disposed in the first direction. The second semiconductor component includes a fourth electrode, a fifth electrode, and a sixth electrode, which are sequentially disposed in the first direction. The first electrode is connected to the fourth electrode via the first signal wiring path, the second electrode is connected to the fifth electrode via the first signal wiring path, and the third electrode is connected to the sixth electrode via the first signal wiring path.
H01L 23/32 - Supports pour maintenir le dispositif complet pendant son fonctionnement, c. à d. éléments porteurs amovibles
H01L 25/04 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
35.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
In order to improve the reliability of a semiconductor device, the present invention embodies a basic concept in which a semiconductor chip (CHP1) mounted on an Ag layer (AGL) is fixed by means of a temporary fixing material (TA) with tacking properties in such a way as to minimize the formation of the temporary fixing material (TA) on the surface of the Ag layer (AGL), which is in a porous state. Specifically, the temporary fixing material (TA) is supplied in such a way that a portion thereof is in contact with a chip mount portion (TAB), while the semiconductor chip (CHP1) is mounted on the Ag layer (AGL) in such a way that a part of the back surface of the semiconductor chip (CHP1) is in contact with the temporary fixing material (TA).
A BGA 9 having a wiring substrate 2, a semiconductor chip 1 secured on the wiring substrate 2, a sealing body 4 for sealing the semiconductor chip 1, and a plurality of soldier balls 5 provided on the bottom-surface side of the wiring substrate 2. The degree of flatness of the top surface 2ia of a first wiring layer 2i of the wiring substrate 2 of the BGA 9 is less than the degree of flatness of a bottom surface 2ib, and a first pattern 2jc provided on a second wiring layer 2j is provided in a position overlapping a first pattern 2ic provided on the first wiring layer 2i. Also, the surface area in plan view of the first pattern 2ic provided on the first wiring layer 2i is greater than the surface area of a plurality of (for example, two) second patterns 2jd provided on the second wiring layer 2j, and a first opening 2jm that exposes a portion of a second insulation layer 2h is formed in the first pattern 2jc provided on the second wiring layer 2j.
In the semiconductor device manufacturing method according to an embodiment of the present invention, a suspension lead is connected to a chip mounting section on which a semiconductor chip is mounted. The suspension lead includes: a first tab connection section connected to the chip mounting section and extending in a first direction; a first branch section provided on the chip mounting section at a position higher than the first tab connection section, and branching in a plurality of directions intersecting the first direction; and a plurality of first exposed-surface connection sections each provided at a position higher than the first branch section and each having one end connected to a portion exposed from a sealed body. The suspension lead further includes a first offset section connected to the first tab connection section and the first branch section, and a plurality of second offset sections each having one end connected to the first branch section and the other end connected to each of the plurality of first exposed-surface connection sections.
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 23/28 - Capsulations, p.ex. couches de capsulation, revêtements
To improve reliability of a semiconductor device. In this semiconductor device manufacturing method, in the cases where a resin entered also into a trench formed in the lower surface of a chip mounting section due to a step for forming a sealing body formed of the resin, the resin embedded in the trench is removed in a step for cleaning the lower surface of the chip mounting section, and in a step for forming a plating film on the lower surface of the chip mounting section, the plating film is also formed on the inner walls of the trench.
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
According to an embodiment of the present invention, a semiconductor device (1) has: a semiconductor substrate; a first well (15) that is provided on the semiconductor substrate; a second well (15) that is provided on the semiconductor substrate; a first fin (11) on the first well; a second fin (21) on the second well; and a first electrode (12a) connected to the first and second fins. The first well and the first fin (11) have a same conductivity type, and the second well and the second fin (21) have different conductivity types.
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
Provided is an electronic device having a first wiring substrate and a semiconductor device mounted on the first wiring substrate. The semiconductor device is equipped with a second wiring substrate having a plurality of terminals, a plurality of first semiconductor chips mounted on the second wiring substrate, and a second semiconductor chip mounted on the second wiring substrate. The first wiring substrate has a first power supply line and a second power supply line which supply a plurality of different types of power supply potential to the second semiconductor chip. The second power supply line is arranged so as to cross the first substrate side of the second wiring substrate and the first chip side of the second semiconductor chip in plan view. The first power supply line is arranged so as to extend through a space between the second power supply line and some of the plurality of first semiconductor chips, towards a region overlapping the second semiconductor chip, in plan view. The area of the region of the first power supply line that overlaps the second power supply line in the thickness direction is smaller than the area of the region of the first power supply line that does not overlap the second power supply line.
H01L 25/04 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
A semiconductor device provided with: a first input/output circuit connected to a first pad; a second input/output circuit disposed in the direction along one side constituted by a chip edge in relation to the first input/output circuit, the second input/output circuit being connected to a second pad; and an ESD protective circuit disposed near the outer-side chip edge of the first and second input/output circuits. The ESD protection circuit is provided with a resistor, a capacitor, an inverter, and an N-channel-type transistor.
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
A semiconductor device (1) according to the present invention is provided with a circuit to be tested (2) that has a scan chain, and a first test control device (3) and a second test control device (4) with which a scan test is performed on the circuit to be tested using the scan chain. The second test control device (4) carries out a second scan test on the circuit to be tested (2). The circuit to be tested (2) commands the first test control device (3) to carry out a first scan test after the second scan test has been carried out. The first test control device (3) carries out the first scan test on the circuit to be tested (2) in accordance with the command from the circuit to be tested (2).
A semiconductor device (9) according to the present invention is provided with a FIFO (91), a test data write circuit (92) for sequentially writing a plurality of test data items to the FIFO (91) in synchronization with a first clock signal (910), and a test control circuit (93) for, in parallel with the writing of the plurality of test data items to the FIFO (91) by the test data write circuit (92) and in synchronization with a second clock signal (920) that is not synchronized with the first clock signal (910), sequentially reading the plurality of test data items stored in the FIFO (91) and carrying out a scan test of a circuit to be tested (94).
A two-row buffer (3) stores first and second rows. An input buffer (2) stores a third row. A gradient calculator (4) calculates first and second gradient values. A vote calculator (5) calculates a vote amount value. A direction calculator (6) calculates a vote direction value. An output buffer (8) stores accumulated vote amount values. An adder (7) adds the vote amount value to the received accumulated vote amount value and replaces the accumulated vote amount value in the output buffer (8) with the added value. The first gradient value is a difference between values of two pixels in the first and third row. The second gradient value is a difference between values of two pixels in the second row. The four pixels are immediately adjacent to a target pixel in the second row. The output buffer (8) outputs all of the accumulated vote amount values to an outside processor.
This analysis device for analyzing operations of a target system has a behavior model which is obtained by modeling the operations of the target system, receives an input of a log in which events occurring when the target system is operated are recorded chronologically, and retrieves, from a plurality of the events chronologically recorded in the log, an event sequence according to the occurrence order obtained by statically analyzing the behavior model. When the target system includes a plurality of subsystems, the behavior model includes a plurality of behavior scenarios which indicate respective behaviors of the plurality of subsystems and a constitution model which indicates an interconnection relationship among the plurality of subsystems. In the behavior scenario, a task to be performed by the corresponding subsystem and an event caused by the task are written. In the log, events caused by the plurality of subsystems and time stamps which indicate the occurrence times of the events by using a time which is common in the whole target system are recorded.
To improve characteristics of a semiconductor device. In a semiconductor device (MISFET) having a gate electrode GE that is formed on a nitride semiconductor layer CH with a gate insulating film GI therebetween, the gate insulating film GI is configured such that the gate insulating film has a first gate insulating film (oxide film formed of a first metal) GIa formed on the nitride semiconductor layer CH, and a second gate insulating film (oxide film formed of a second metal) GIb. The second metal (for instance, Hf) has a lower electronegativity than the first metal (for instance, Al). In this manner, a threshold voltage (Vth) can be shifted in the positive direction by having the electronegativity of the second metal lower than the electronegativity of the first metal. Furthermore, the gate electrode GE is configured such that the gate electrode has a first gate electrode (nitride film formed of a third metal) GEa formed on the second gate insulating film GIb, and a second gate electrode (fourth metal) GEb. Consequently, oxygen is prevented from diffusing to the gate insulating film GI, and fluctuation of the threshold voltage (Vth) can be reduced.
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
47.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
In the present invention, a resin-sealed semiconductor device is configured such that a semiconductor chip CP2 is mounted on a conductive die pad DP via a joint material BD2 having insulating properties, and a semiconductor chip CP1 is mounted thereon via a joint material BD1 having conductive properties. A first length of a portion covered by the joint material BD2 in a first side formed by an intersection of a first surface and a second surface of the semiconductor chip CP2 is longer than a second length of a portion covered by the joint material BD1 in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1.
This semiconductor device is provided with an SRAM circuit. The SRAM circuit includes: a memory array (11) wherein a plurality of memory cells (MC) are disposed in matrix; ground wiring (ARVSS) to which the memory cells (MC) are connected in common; and a first potential control circuit (16) for controlling the potential of the ground wiring (ARVSS) in accordance with operation mode. The first potential control circuit (16) includes a first NMOS transistor (NM10) and a first PMOS transistor (PM10), which are connected in parallel to each other between the ground wiring (ARVSS) and a ground node (VSS) that supplies a ground potential.
G11C 11/412 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules avec réaction positive, c. à d. des cellules ne nécessitant pas de rafraîchissement ou de régénération de la charge, p.ex. multivibrateur bistable, déclencheur de Schmitt utilisant uniquement des transistors à effet de champ
G11C 11/41 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules avec réaction positive, c. à d. des cellules ne nécessitant pas de rafraîchissement ou de régénération de la charge, p.ex. multivibrateur bistable, déclencheur de Schmitt
G11C 11/413 - Circuits auxiliaires, p.ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture, la synchronisation ou la réduction de la consommation
49.
SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SAME
A semiconductor substrate (1) includes a region (AR3) between a region (AR1) and a region (AR2). A control gate electrode (CG) is formed on the upper surface (TS1) of the region (AR1) and a memory gate electrode (MG) is formed on the upper surface (TS2) of the region (AR2). The upper surface (TS2) is lower than the upper surface (TS1), and the region (AR3) has a connection surface (TS3) connecting the upper surface (TS1) and the upper surface (TS2) to each other. The upper-surface-(TS2)-side end part (EP1) of the connection surface (TS3) is disposed near the memory electrode (MG) relative to the upper-surface-(TS1)-side end part (EP2) of the connection surface (TS3), and is disposed lower than the end part (EP2).
In a data processing device of the present invention, which is provided with two duplexed sets of circuit pairs for each of two mutually asynchronous clock domains, an asynchronous transfer circuit is provided for transferring a payload signal between the two sets of circuit pairs. The asynchronous transfer circuit is provided with two sets of bridge circuit pairs connected, respectively, to the two sets of circuit pairs, and asynchronously transfers, along with a payload signal, a control signal indicating the timing at which the payload signal will stabilize at the receiving side. The two sets of bridge circuit pairs and the payload signal can be duplexed, but the control signal is not duplexed and is used in timing control for providing a received payload signal to the duplexed circuit pair at an expected same time difference. As a result, asynchronous transfer is possible between respective duplexed circuits in asynchronous clock domains, and high performance and high reliability can both be achieved.
G06F 11/18 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel en utilisant un masquage passif du défaut des circuits redondants, p.ex. par logique combinatoire des circuits redondants, par circuits à décision majoritaire
In the present invention, on the basis of the basic concept of effective utilization of space produced in a level-3 wiring layer (M3) by a level-0 wiring layer (M0) that can be present due to miniaturization of a FinFET, an auxiliary line AL is disposed in the space produced in the level-3 wiring layer and this auxiliary line AL and a word line WL are electrically connected. Because of this configuration, a countermeasure (solution) based on the new knowledge that the duration of the initial rise in word line is greatly affected by the wiring resistance of the word line is realized, making high-speed operation of SRAM using a FinFET possible.
In the present invention, a MISFET has: a gate electrode formed on a semiconductor substrate with a gate insulation film interposed therebetween; and a source region and a drain region formed within the semiconductor substrate so as to sandwich the gate electrode. A first silicide layer is formed on the surfaces of the source region and drain region, and a second silicide layer is formed on the surface of the gate electrode. The first silicide layer and the second silicide layer are configured from a first metal and silicon, and include a second metal different from the first metal. The concentration of the second metal in the second silicide layer is lower than the concentration of the second metal in the first silicide layer.
H01L 27/115 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
53.
DATA PROCESSING DEVICE, DATA PROCESSING SYSTEM AND METHOD THEREFOR
According to the present invention, a data selector circuit (2) divides a group of data that includes multiple types of data into multiple types of data. In accordance with the types of the multiple types of data, a first compression circuit (4a) and a second compression circuit (4b) compress each of the multiple types of data in parallel. The first compression circuit (4a) compresses data (b1) and obtains compressed data (b2). The second compression circuit (4b) compresses data (c1) and obtains compressed data (c2). A data transmission circuit (6) transmits the compressed data (b2) and the compressed data (c2) to a terminal.
This semiconductor device has: a plurality of wiring lines (WR11) formed above a semiconductor substrate, said wiring lines being formed in a same layer; and a plurality of wiring lines (WR12) formed in the same layer with the wiring lines (WR11). The wiring lines (WR11) extend in the X axis direction in a plan view, and are disposed at a pitch (PT11) in the Y axis direction intersecting the X axis direction, and the wiring lines (WR12) extend in the X axis direction in the plan view, and are disposed at a pitch (PT12) in the Y axis direction. The wiring lines (WR11) are electrically connected to the wiring lines (WR12), respectively, and the pitch (PT11) is smaller than the pitch (PT12).
H01L 27/14 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit ra
H01L 21/3205 - Dépôt de couches non isolantes, p.ex. conductrices ou résistives, sur des couches isolantes; Post-traitement de ces couches
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 21/82 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H04N 5/369 - Transformation d'informations lumineuses ou analogues en informations électriques utilisant des capteurs d'images à l'état solide [capteurs SSIS] circuits associés à cette dernière
A data transfer apparatus (100) includes a processing unit (101), a memory bank array (4), and a memory controller (3). The processing unit (101) outputs a plurality of offset values and a base address. The memory bank array includes a plurality of memory banks (4). The memory controller (3) offsets the base address by the offset values to generate offset addresses, and reads data from the memory bank array (4) using the offset addresses. The memory controller receives the offset values and base address from the processing unit (101).
A semiconductor device PKG has: a semiconductor chip CP; a lead LD3; a wire BW5 that electrically connects a pad electrode PD2 of the semiconductor chip CP and the lead LD3 to each other; a wire BW3 that electrically connects a pad electrode PD3 of the semiconductor chip CP and the lead LD3 to each other; and a sealing body that seals the semiconductor chip, the lead, the pad electrodes, and the wires with a resin. The semiconductor chip CP includes an internal circuit 5b, an internal circuit 5c, and a switch circuit section SW, and signals can be transmitted between the internal circuit 5c and the pad electrode PD3. The switch circuit section SW is a circuit wherein a first state, in which signals can be transmitted between the internal circuit 5b and the pad electrode PD2, and a second state, in which the signals cannot be transmitted between the internal circuit 5b and the pad electrode PD2, can be set. The switch circuit section SW is fixed in the second state during the time when the semiconductor device PKG is operating.
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
This semiconductor device includes first and second semiconductor components, which are mounted on an interposer mounted on a wiring board, and which are electrically connected to each other via the interposer. A plurality of wiring layers of the interposer have first, second, and third wiring layers that are laminated in this order from the reference main surface side. In a first region of the interposer, said first region being sandwiched between the first semiconductor component and the second semiconductor component, the ratio of reference potential wiring in the third wiring layer is higher than the ratio of the reference potential wiring in the first wiring layer. In the first region, the ratio of signal wiring in the first wiring layer is higher than the ratio of the signal wiring in the third wiring layer.
H01L 23/32 - Supports pour maintenir le dispositif complet pendant son fonctionnement, c. à d. éléments porteurs amovibles
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/12 - Supports, p.ex. substrats isolants non amovibles
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
The present invention improves MISFET properties and prevents the disconnection of a silicide layer on a gate electrode of a MONOS memory. As a means of doing so, when jointly mounting a memory cell and a MISFET formed by the so-called gate-last process, a silicide layer is formed on a source-drain region by a salicide process entailing a comparatively high-temperature heat treatment, and thereafter, a silicide layer is formed on the tops of a memory gate electrode and a control gate electrode of the memory cell by a salicide process entailing a comparatively low-temperature heat treatment.
A semiconductor device is provided with: a first circuit; a plurality of pattern generators that are connected to the first circuit and each supply a test pattern to the first circuit; a pattern generator control circuit for controlling each of the plurality of pattern generators; a pattern compressor for compressing the results output from the first circuit in accordance with the supply of the test patterns from the plurality of pattern generators; a pattern compressor control circuit for controlling the pattern compressor; and a self-diagnosis control circuit that is connected to the pattern generator control circuit and pattern compressor control circuit and controls the pattern generator control circuit so that the plurality of pattern generators have different test pattern stop times.
As a means for preventing leakage of a fuse element that has been cut by laser trimming due to conductive residues and the like, when a fuse element is formed on an element separation region within a groove on the primary surface of an epitaxial substrate, an insulation film having high thermal conductivity and relatively low adhesiveness is formed between the element separation region and the fuse element. When laser trimming is performed to cut the fuse element, a portion of the fuse element and the insulation film under that portion of the fuse element are removed.
H01L 21/82 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants
61.
COMMAND EXECUTION CONTROL SYSTEM AND COMMAND EXECUTION CONTROL METHOD
This command execution control system (1) includes: a plurality of command storage units (22) that output commands, on a first-in first-out basis, to each of a plurality of command execution units that execute commands; a command control unit (20) that allocates a sequentially input command to one of the plurality of command storage units (22); and an output control unit (23) that controls the output of commands from the plurality of command storage units. If the input command is a dummy command inserted between commands to maintain an execution order, the command control unit (20) distributes an input command to all of the plurality of command storage units (22). The output control unit (23) suppresses the output of commands to the command execution units from command storage units (22) in which the command to be output is a dummy command, until the command to be output is a dummy command in all of the plurality of command storage units (22).
The semiconductor device (1) according to the present invention is provided with: a plurality of buses (B1—Bm); a control unit (10) which is connected to the plurality of buses (B1—Bm) and which obtains communication specification information, including drive voltage information, from each of a plurality of externally provided modules (M1—Mn) via one of the plurality of buses (B1—Bm); and a switch circuit (13) which establishes connection between the plurality of modules (M1—Mn) and the plurality of buses (B1—Bm) on the basis of the communication specification information about each of the plurality of modules (M1—Mn) as obtained by the control unit (10).
A semiconductor device has: a pad electrode 9a formed on the uppermost layer of a plurality of wiring layers; a base insulation film 11 having an opening 11a on the pad electrode 9a; a base metal film UM formed on the base insulation film 11; a rewiring RM formed on the base metal film UM; and a cap metal film CM formed so as to cover the top surface and side surface of the rewiring RM. In the region on the outer side of the rewiring RM, the base metal film UM, which is of a different material from the rewiring RM, and the cap metal film CM, which is of a different material from the rewiring RM, are formed between the cap metal film CM and the base insulation film 11 formed on the side wall of the rewiring RM, and in the region on the outer side of the rewiring RM, the base metal film UM and the cap metal film CM are directly in contact.
H01L 21/3205 - Dépôt de couches non isolantes, p.ex. conductrices ou résistives, sur des couches isolantes; Post-traitement de ces couches
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
This silicon carbide semiconductor device (1) comprises a silicon carbide substrate (10), a gate insulating film (15), a gate electrode (27) and an interlayer insulating film (2). The silicon carbide substrate (10) has a main surface (10a). The gate insulating film (15) is provided on the main surface (10a) of the silicon carbide substrate (10). The gate electrode (27) is provided on the gate insulating film (15). The interlayer insulating film (2) is provided so as to cover the gate electrode (27). The interlayer insulating film (2) comprises: a first insulating film (2a) that is in contact with the gate electrode (27) and contains silicon atoms, while not containing neither phosphorus atoms nor boron atoms; a second insulating film (2b) that is provided on the first insulating film (2a) and contains phosphorus atoms and/or boron atoms in addition to silicon atoms; and a third insulating film (2c) that contains silicon atoms but does not contain neither phosphorus atoms nor boron atoms. The second insulating film (2b) has a first surface (2b1) that is in contact with the first insulating film (2a), a second surface (2b2) that is on the reverse side of the first surface (2b1), and a third surface (2b3) that connects the first surface (2b1) and the second surface (2b2) with each other. The third insulating film (2c) is in contact with the second surface (2b2) and/or the third surface (2b3).
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 21/283 - Dépôt de matériaux conducteurs ou isolants pour les électrodes
H01L 21/316 - Couches inorganiques composées d'oxydes, ou d'oxydes vitreux, ou de verres à base d'oxyde
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 29/12 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A pipeline ring-bus system includes a ring bus and ring bus registers. Processing elements are connected to the ring bus between a former and latter ring bus registers. Each processing element sends out a request or response. The request or response stored in the former ring bus register is transferred to the latter ring bus register in each clock cycle. Each processing element includes a two-entry buffer. Each processing element receives different requests. Each processing element prepares different responses corresponding to the different requests. The different requests temporally overlap in a pipelined way.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p.ex. plusieurs processeurs de données à instruction unique
A data transfer apparatus (100) including a hierarchy memory system includes: a processing unit (1); a lower hierarchy level memory unit (3); an upper hierarchy level memory unit (2); a data transfer control unit (4); a bus (5); and a temporary memory unit (6). The data transfer control unit (4) reads data elements from the lower hierarchy level memory unit (3) in a single data transfer mode, and stores the read data elements to consecutive addresses in the temporary memory unit (6) as consecutive data. The data transfer control unit (4) reads the consecutive data from the temporary memory unit (6), and sends out the consecutive data to the upper hierarchy level memory unit (2) in a burst data transfer mode.
This electronic device includes a first wiring board, and a semiconductor device mounted on the first wiring board. On a second wiring board of the semiconductor device, a plurality of first semiconductor chips, and a second semiconductor chip that controls the first semiconductor chips are mounted by being aligned with each other. The first semiconductor chips are mounted between a first substrate side of the wiring board, and an extending line of a first chip side of the second semiconductor chip. The first wiring board has: a first power supply line that supplies a first power supply potential to each of the first semiconductor chips; and a second power supply line, which supplies a second power supply potential to the second semiconductor chip, and which has a width that is larger than that of the first power supply line. In a plan view, the second power supply line intersects the first substrate side of the second wiring board, and extends toward the second semiconductor chip from the first substrate side of the second wiring board.
A semiconductor integrated circuit device 1000 is provided with: a first semiconductor chip CHP1 having a first circuit; and a second semiconductor chip CHP2 having a second circuit and being different from the first semiconductor chip. The semiconductor integrated circuit device 1000 is also provided with a control circuit BTCNT for controlling the operations of the first and second circuits according to a control signal during a burn-in test, wherein said control circuit BTCNT controls the first and second circuits so that the amount of stress acting on the first semiconductor chip CHP1 by the operation of the first circuit and the amount of stress acting on the second semiconductor chip CHP2 by the operation of the second circuit are made different from each other during the burn-in test.
This invention provides a semiconductor device that can, for example, exhibit high performance suited to an SR motor. Said semiconductor device is provided with chip-mounting section TAB1, chip-mounting section TAB2, lead LD1A, and lead LD1B. Semiconductor chip CHP1, on which an IGBT is formed, is mounted in chip-mounting section TAB1, and semiconductor chip CHP2, on which a diode is formed, is mounted in chip-mounting section TAB2. Lead LD1A is electrically connected to an emitter-electrode pad EP on semiconductor chip CHP1 via clip CLP1, and lead LD1B is electrically connected to an anode-electrode pad ADP on semiconductor chip CHP2 via clip CLP2. Chip-mounting section TAB1 and chip-mounting section TAB2 are electrically isolated from each other, as are clip CLP1 and clip CLP2.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/28 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H02M 7/48 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande
In an RFIC provided in a semiconductor device in one embodiment, a low-noise amplifier (41) for receiving and a power amplifier (11) for transmitting are connected to a shared antenna connection terminal (5). A circuit (31) that is used for impedance matching is connected between the antenna connection terminal (5) and the LNA (41), and a semiconductor switch (SW1) is connected in parallel with said circuit (31).
H04B 1/48 - Commutation transmission-réception dans des circuits pour connecter l'émetteur et le récepteur à une voie de transmission commune, p.ex. par l'énergie de l'émetteur
A semiconductor device comprising a first memory mat (1L) including a plurality of split-type memory cells (250L); a second memory mat (1R) including a plurality of split-type memory cells (250R); a first control gate line (CGL) connected to a control gate (CG) of a split-type memory cell (100L); and a second control gate line (CGR) connected to a control gate (CG) of a split-type memory cell (100R). The semiconductor device further comprises a first memory gate line (MGL) connected to a memory gate (MG) of a split-type memory cell (100L); and a second memory gate line (MGR) connected to a memory gate (MG) of a split-type memory cell (100R).
The present invention has an electrical fuse (EF1), an insulating film (IL1), an insulating film (IL2), and an insulating film that is formed such that the electrical fuse (EF1), the insulating film (IL1), and the insulating film (IL2) are covered therewith. The electrical fuse (EF1) includes a fuse cutting section (FC1), a first pad section (PD1), and a second pad section (PD2). The fuse cutting section (FC1) is formed between the first pad section (PD1) and the second pad section (PD2) in the first direction, and has a rectangular shape having a first short side and a second short side, which are in the second direction orthogonal to the first direction. The insulating film (IL1) is continuously formed between the first short side and the second short side such that the surface of the fuse cutting section (FC1) is covered therewith. The insulating film (IL2) is formed to planarly surround the insulating film (IL1), and is disposed by being separated from the insulating film (IL1). The stress of the insulating film (IL1) and the insulating film (IL2) is larger than the stress of the insulating film covering the insulating films.
H01L 21/82 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
Provided is a loop antenna (1), comprising: a first electrode terminal (2c) and a second electrode terminal (2d) which is disposed as a pair with the first electrode terminal (2c); and a loop-shaped member (2), one end whereof is connected to the first electrode terminal (2c), the other end whereof is connected to the second electrode terminal (2d), which is coiled in a plurality of loops, and which is formed from a conductive material. The first electrode terminal (2c) and the second electrode terminal (2d) are disposed as a pair about a center line (3) of the loop-shaped member (2). The loop-shaped member (2) further comprises a first loop-shaped member (2a), a second loop-shaped member (2b), and a cross point part (2e). The cross point part (2e) is positioned upon the center line (3) in plan view. The loop-shaped member (2) is joined in an uninterrupted manner, and is formed in a bilaterally symmetrical shape about the center line (3).
The purpose of the present invention is to shorten the length of wiring that connects a photoelectric conversion element and a first transistor and decrease the value of wiring capacity in a semiconductor device that comprises two photoelectric conversion elements within an active area. This semiconductor device comprises a plurality of pixel areas that are arranged in a matrix on a semiconductor substrate (SUB), and each of the plurality of pixel areas is provided with an active area (AR), two photoelectric conversion elements (PD), two stray capacitance areas (FD), and a first transistor (AMI). Each of the plurality of pixel areas includes two transfer transistors (TX) that comprise each of the two photoelectric conversion elements (PD) and each of the two stray capacitance areas (FD). The first transistor (AMI) is arranged within the pixel area between one of the stray capacitance areas (FD) and the other of the stray capacitance areas (FD) in the direction in which the one stray capacitance area (FD) and the other stray capacitance area (FD) are arranged.
To improve semiconductor device characteristics. In a semiconductor device (MISFET) having a gate electrode (GE) formed on a nitride semiconductor layer (CH) via a gate insulating film (GI), the gate insulating film (GI) is configured to have a first gate insulating film (oxide film of a first metal) (GIa) that is formed on the nitride semiconductor layer (CH), and a second gate insulating film (oxide film of a second metal) (GIb). The second metal (for instance, Hf) has a lower electronegativity than the first metal (for instance, Al). Consequently, since negative charges are introduced into the oxide film of the first metal due to interface polarization by having the electronegativity of the second metal lower than that of the first metal, a flat band voltage can be shifted to be positive. Consequently, a threshold voltage that has become negative due to heat treatment of the oxide film of the first metal can be shifted to be positive.
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
76.
METHOD AND APPARATUS FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT LAYOUT
According to one embodiment of the present invention, in a method for designing a semiconductor integrated circuit layout, inhibition regions (DP1-DP5) are set on the basis of defect information (DF1-DF5) of mask blanks (M1-M5). A disposition/wiring tool disposes a plurality of functional modules (40) by avoiding the inhibition regions thus set, and generates a wiring pattern (42) among the functional modules by avoiding the inhibition regions.
H01L 21/82 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants
G03F 1/24 - Masques en réflexion; Leur préparation
G03F 1/70 - Adaptation du tracé ou de la conception de base du masque aux exigences du procédé lithographique, p.ex. correction par deuxième itération d'un motif de masque pour l'imagerie
In the present invention, a semiconductor device comprises: a wiring board having a plurality of wiring layers; a semiconductor chip that has a plurality of electrodes and is mounted onto the wiring board; and a first capacitor that has a first electrode and second electrode and is mounted onto the wiring board. The plurality of wiring layers are provided with a first wiring layer having a first terminal pad electrically connected to the first electrode of the first capacitor, and a second terminal pad electrically connected to the second electrode of the first capacitor. The plurality of wiring layers are also provided with a second wiring layer that is located one layer more inward in the wiring board than the first wiring layer and that has a first conductor pattern of a greater surface area than the first terminal pad and the second terminal pad. In the second wiring layer, the first conductor pattern has an opening formed in a region that overlaps the first terminal pad and the second terminal pad.
According to one embodiment of the present invention, a semiconductor device has a second semiconductor chip mounted on a first rear surface of a first semiconductor chip. The first rear surface of the first semiconductor chip includes: a first region having formed therein a plurality of first rear surface electrodes that are electrically connected to the second semiconductor chip via protruding electrodes; and a second region, which is formed further toward the peripheral end portion side than the first region, and which has a first metal pattern formed therein. The protruding height of the first metal pattern with respect to the first rear surface is less than the protruding heights of the first rear surface electrodes with respect to the first rear surface.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
79.
SEMICONDUCTOR DEVICE, PRE-WRITE PROGRAM, AND RESTORATION PROGRAM
When a first erasure command is received, a control circuit (105) controls the execution of a first pre-write process for increasing both the threshold voltage of a first storage element (102) and the threshold voltage of a second storage element (103), and then, until the threshold voltage of the first storage element (102) and the threshold voltage of the second storage element (103) are lower than a prescribed erasure verification level, controls the execution of an erasure process for reducing both the threshold voltage of the first storage element (102) and the threshold voltage of the second storage element (103). When a second erasure command is received, the control circuit (105) controls the execution of a second pre-write process for increasing the threshold voltage of either the first storage element (102) or the second storage element (103), and then controls the execution of the erasure process.
According to an embodiment of the present invention, in a semiconductor device manufacturing method, a lead frame is prepared, said lead frame having formed therein a groove section such that the lower surfaces of a first lead and a second lead, which are connected between device regions adjacent to each other, are communicated with each other. After a part of a connecting section between the first and second leads is cut using a first blade, metal waste formed in the groove section is removed. After removing the metal waste, a metal film is formed on exposed surfaces of the first and second leads by means of a plating method, then, the remaining part of the connecting section of the first and second leads is cut using a second blade. At that time, cutting is performed such that the second blade is not brought into contact with the groove section.
H01L 21/50 - Assemblage de dispositifs à semi-conducteurs en utilisant des procédés ou des appareils non couverts par l'un uniquement des groupes
H01L 23/28 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
81.
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND POWER SUPPLY SYSTEM
This semiconductor integrated circuit device is provided with: a first voltage terminal; a second voltage terminal; an output terminal; a high-side MOSFET connected between the first voltage terminal and the output terminal; a low-side MOSFET, which is connected between the output terminal and the second voltage terminal, and which has first and second gate electrodes; a drive circuit, which turns on/off the high-side MOSFET and the low-side MOSFET in a complementary manner; and a second gate electrode control circuit that forms a second gate control signal to be supplied to the second gate electrode of the low-side MOSFET. The second gate electrode control circuit is provided with a voltage forming circuit that supplies the second gate electrode of the low-side MOSFET with a negative voltage with respect to a voltage at the source of the low-side MOSFET.
H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
H02M 3/00 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu
H02M 3/135 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type thyratron ou thyristor exigeant des moyens d'extinction utilisant uniquement des dispositifs à semi-conducteurs
H03K 17/695 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ à charges inductives
A control electrode (GE1) is formed at a lower section in a trench (TR1) that is formed in a semiconductor substrate (SUB), and a gate electrode (GE2) is formed at an upper section in the trench (TR1). Insulating films (G1) are formed between the side walls of the trench (TR1) and the control electrode (GE1) and between the bottom surface of the trench and the control electrode, insulating films (G2) are formed between the side walls of the trench (TR1) and the gate electrode (GE2), and an insulating film (G3) is formed between the control electrode (GE1) and the gate electrode (GE2). In a region adjacent to the trench (TR1), there are an n+ type semiconductor region (NR) for a source, a p type semiconductor region (PR) for forming a channel, and a semiconductor region for a drain. Wiring connected to the control electrode (GE1) is not connected to wiring connected to the gate electrode (GE2), and is not connected to wiring connected to the n+ type semiconductor region (NR) for the source.
To improve characteristics of a semiconductor device. This semiconductor device has: a coil (CL1) and wiring (M2), which are formed on an interlayer insulating film (IL2); wiring (M3) formed on the interlayer insulating film (IL3); and a coil (CL2) and wiring (M4), which are formed on the interlayer insulating film (IL4). A distance (DM4) between the coil (CL2) and the wiring (M4) is larger than a distance (DM3) between the coil (CL2) and the wiring (M3) (DM4>DM3). Furthermore, the distance (DM3) between the coil (CL2) and the wiring (M3) is equal to or more than a sum of a film thickness of the interlayer insulating film (IL3) positioned between the coil (CL1) and the coil (CL2), and a film thickness of the interlayer insulating film (IL4). Consequently, a withstand voltage of regions, such as a region between the coil (CL2) and the wiring (M4), can be improved, said regions being susceptible to generating a large voltage difference. Furthermore, a seal ring forming region (1C) that surrounds a transformer forming region (1A) and a peripheral circuit forming region (1B) is provided, and moisture resistance is improved.
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
A p+ back-gate region (PBG) of this semiconductor device is located between first and second sections (P1, P2) of an n+ source region (SR) on a principal surface (S1) and is located closer to an n+ drain region (DR) than the n+ source region (SR) is. This makes it possible to obtain a semiconductor device that has a high on-state breakdown voltage.
A semiconductor device comprises a first silicon piece (G1) comprising a p-type impurity which is a p-channel-type MISFET (1P) gate electrode (G), a second silicon piece (G2) comprising an n-type impurity which is an n-channel-type MISFET (2N) gate electrode (G), and an insulating film (IF1) interposed between the first silicon piece (G1) and the second silicon piece (G2). In addition, a silicide film is continuously formed on the surfaces of the first silicon piece (G1), the insulating film (IF1), and the second silicon piece (G2), and the first silicon piece (G1) and the second silicon piece (G2) are electrically connected with the silicide film (SIL). By way of the insulating film (IF1), interdiffusion of the impurities is prevented.
The purpose of the present invention is to provide a semiconductor device which can achieve reduction of noise. To this end, for example, a semiconductor device is provided with a first area for forming a core circuit portion (CRBK), a power supply voltage line (LNVD1) within the first area, a power supply voltage line (LNVD2) outside the first area, and an on-chip capacitor (CC). The on-chip capacitor (CC) has an upper-portion electrode (UPN) comprising a partial segment of the power supply voltage line (LNVD2), and a lower-portion electrode (LWN) to which a reference power supply voltage (VSS) is supplied, and comprises a unit cell. An internal power supply voltage (VDD) from a power supply source node is supplied to the core circuit portion (CRBK) via the upper-portion electrode (UPN).
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
The purpose of the present invention is to provide a semiconductor device which can achieve reduction of EMI noise. To this end, for example, a semiconductor device is provided with a first area for forming a core circuit portion (CRBK), a first power supply voltage line (LNVD1) within the first area, a first power supply voltage generation circuit (VREG), a first power supply pad (PDvcl) outside the first area, a second power supply voltage line (LNVD2) connecting the first power supply voltage line (LNVD1) and the first power supply pad (PDvcl), and an on-chip capacitor (CC). An external capacitor is connected to the first power supply pad (PDvcl). The on-chip capacitor (CC) has an upper-portion electrode (UPN) comprising a partial segment of the second power supply voltage line (LNVD2), and a lower-portion electrode (LWN) to which a reference power supply voltage (VSS) is supplied. A first power supply voltage (VDD) on the first power supply voltage line (LNVD1) is applied to the first power supply pad (PDvcl) via the upper-portion electrode (UPN).
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
A semiconductor substrate (SUB) having recessed sections (CP1) and recessed sections (CP2), on a main surface. n+ source regions (SR) and an n+ drain region (DR) sandwich the recessed sections (CP1) and the recessed sections (CP2) in the main surface. A p- epitaxial region (EP) and p-type well regions (WL), which become channel-forming regions, are formed in the main surface between the n+ source regions (SR) and the recessed sections (CP1). Gate electrode layers (GE) are formed upon the channel areas, sandwiching a gate insulation film (GI) therebetween, and extend on top of element-separating insulation films (SI) inside the recessed sections (CP1). The recessed sections (CP1) and the recessed sections (CP2) are arranged adjacent to each other, having a substrate protruding section (CV) that protrudes further on the main surface side than the floor of each of the recessed sections (CP1, CP2), interposed therebetween.
A silicon carbide semiconductor device provided with a silicon carbide substrate (10), a gate insulation film (15), and a gate electrode (27). The silicon carbide substrate (10) has a first main surface (10a) and a second main surface (10b) on the side opposite the first main surface (10a). The gate insulation film (15) is provided so as to be in contact with the first main surface (10a) of the silicon carbide substrate (10) The gate electrode (27) is provided on the gate insulation film (15) so that the gate insulation film (15) is interposed between the gate electrode (27) and the silicon carbide substrate (10). With regards to performing a first stress test in which a gate voltage of -5 V is applied for 100 hours to the gate electrode (27) under a temperature of 175ºC, when the threshold voltage prior to performing the first stress test is taken as a first threshold voltage and the threshold voltage after performing the first stress test is taken as a second threshold voltage, the absolute value of the difference between the first threshold voltage and the second threshold voltage is equal to or less than 0.5 V. A silicon carbide semiconductor device in which fluctuations in the threshold voltage can be reduced, and a method for manufacturing the silicon carbide semiconductor device, are thereby provided.
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 29/12 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
90.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME
This semiconductor device has: an inter-layer insulating film (INS2); neighboring Cu wiring (M1W) formed within the inter-layer insulating film (INS2); and an insulating barrier film (BR1) that contacts the surface of the Cu wiring (M1W) and the surface of the inter-layer insulating film (INS2) and that covers the Cu wiring (M1W) and the inter-layer insulating film (INS2). Also, between the neighboring Cu wiring (M1W), the inter-layer insulating film (INS2) has a damage layer (DM1) at the surface thereof, and at a deeper position than the damage layer (DM1), has an electric field limiting layer (ER1) having a higher concentration of nitrogen than that of the damage layer (DM1).
In a semiconductor device (SP1) according to one embodiment, between a substrate layer (2CR) of a wiring board (2) and a semiconductor chip (3), a solder resist film (first insulating layer (SR1)) which adheres closely to the substrate layer, and a resin body (second insulating layer (4)) which adheres closely to the solder resist film and the semiconductor chip, are stacked. Furthermore, the linear expansion coefficient of the solder resist film is greater than or equal to the linear expansion coefficient of the substrate layer, the linear expansion coefficient of the solder resist film is less than or equal to the linear expansion coefficient of the resin body, and the linear expansion coefficient of the substrate layer is less than the linear expansion coefficient of the resin body. According to the configuration, it is possible to suppress damage to the semiconductor device caused by a temperature cycle load, and to improve reliability.
A memory array (101) includes a plurality of twin cells (104), which hold binary data using a difference in threshold voltages between the same, comprising a first storage element (102) and a second storage element (103), which are each electrically rewritable. An output circuit (105), upon receiving a read request for a twin cell (104), masks storage data of the twin cell (104) and outputs the data if the threshold voltage of the first storage element (102) constituting the twin cell (104) is smaller than an erasure assessment level and the threshold voltage of the second storage element (103) constituting the twin cell (104) is smaller than the erasure assessment level.
A memory array (101) includes a plurality of twin cells (104), which hold binary data using a difference in threshold voltages between the same, comprising a first storage element (102) and a second storage element (103), which are each electrically rewritable. A power supply control circuit (105), upon receiving an erase request for twin-cell data, performs setting so that when applying an erase pulse subsequent to a prewrite, in which the threshold voltages of both the first storage element (102) and the second storage element (103) are increased, the voltage of a first bit line (BL) which is connected to the first storage element (102), and the voltage of a second bit line (/BL) which is connected to the second storage element (103), are caused to differ.
A control circuit (105), upon receiving an erase request for twin-cell data, controls execution of first-stage processing in which one or both threshold voltages of both a first storage element (102) and a second storage element (103) are increased until a predetermined write-verify level is reached by the threshold voltages of both the first storage element (102) and the second storage element (103). The control circuit (105), subsequent to execution of the first-stage processing, controls execution of second-stage processing in which both threshold voltages of the first storage element (102) and the second storage element (103) are decreased until a predetermined erase-verify level is reached by the threshold voltages of both the first storage element (102) and the second storage element (103).
A scrambling unit (501) performs processing to scramble, using scrambling data, data to be written to a twin-cell (505) within a first storage unit (502). A write unit (509) writes write-data subsequent to scrambling to the twin-cell (505) within the first storage unit (502). A write unit (511) writes the scrambling data to a memory cell (510) within a second storage unit (503). A descrambling unit (504), using the scrambling data read from the second storage unit (503), performs descrambling processing on the data that have been read out from the first storage unit (502).
In chips for processing image information and the like, multi-port SRAMs are also mounted together with the logic circuits of digital signal processing circuits and the like. Regarding this, if for example, there are 3 ports, 1 port is used as a differential write & read port, and 2 ports are used as single-end dedicated read ports. However, it has become clear that while an embedded SRAM occupies less area in this configuration, there is a problem in that there is only 1 write & read port and that high-speed read characteristics such as in differential reading cannot be expected from single-ended reading. The present application outlines a configuration for an embedded SRAM memory cell structure having 3 differential write & read ports, wherein the center of the cell has, for example, an N-well region disposed therein, and P-well regions are disposed on both sides thereof.
G11C 11/413 - Circuits auxiliaires, p.ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture, la synchronisation ou la réduction de la consommation
G11C 11/41 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules avec réaction positive, c. à d. des cellules ne nécessitant pas de rafraîchissement ou de régénération de la charge, p.ex. multivibrateur bistable, déclencheur de Schmitt
H01L 21/8244 - Structures de mémoires statiques à accès aléatoire (SRAM)
H01L 27/10 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive
H01L 27/11 - Structures de mémoires statiques à accès aléatoire
97.
SWITCHING POWER SOURCE DEVICE, SEMICONDUCTOR DEVICE, AND AC/DC CONVERTER
This switching power source device switches a switching element on and off using PWM control, thereby controlling the current flowing in a coil and obtaining a prescribed direct-current voltage. With this switching power source device, during a PWM ON period for turning the switching element on using the PWM control, switching of the switching element is enabled by a first pulse signal in a first period immediately after the start of the PWM ON period, the signal having a shorter cycle than the PWM cycle and the pulse width being gradually increased. Also, with this switching power source device, after the first period of the PWM ON period has elapsed, switching of the switching element is enabled by a PWM signal based on the PWM control. High-frequency noise can thus be reduced.
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
H02M 7/12 - Transformation d'une puissance d'entrée en courant alternatif en une puissance de sortie en courant continu sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande
98.
MOVING IMAGE ENCODING APPARATUS AND OPERATION METHOD THEREOF
An moving image encoding apparatus (1) executes a moving image encoding process of a syntax element, which is related to a moving image signal (VS) to be encoded, thereby forming an encoded bitstream (CVBS). Prior to the moving image encoding process, a padding process for adding a padding process data (PD) to the moving image signal (VS) is executed, and the horizontal and vertical sizes of the added moving image signal to which the padding process data has been added are set to an integral multiple of the encoded block size of the moving image encoding process. It is determined whether the encoded block of the syntax element belongs to the moving image signal (VS) or to the padding process data (PD). If the encoded block belongs to the former, an encoded bitstream having a large encoding amount is formed. If the encoded block belongs to the latter, an encoded bitstream having a small encoding amount is formed. When the padding process is implemented, the increase in the encoding amount of the encoded bitstream can be reduced.
The system is provided with a monitoring device (10) and a user device. The monitoring device (10) first captures images by a monitor camera, and detects a number N of moving bodies therein. Next, for each of the N moving bodies, the type of moving body is identified, and the distance of the moving body from a predetermined reference location is measured. Next, a first identifier representing the type of moving body, and a second identifier representing the distance of the moving body, are generated for each of the N moving bodies. A data signal containing the N sets of first and second identifiers is then transmitted. Meanwhile, the user device receives the data signal transmitted by the monitoring device (10), recognizes the state of being of the moving bodies on the basis of the N sets of first and second identifiers included therein, and notifies the user thereof through an image (11), voice (12), vibration (13), or the like. As a result, it is possible to reduce the occurrence of accidents with other vehicles or with pedestrians upon encountering an intersection with poor visibility and no traffic signal, a T intersection, or the like, making it possible to achieve improved safety.
A semiconductor device according to one embodiment is a semiconductor device in which a semiconductor chip mounted upon a chip mounting part is sealed with resin, wherein a first member is secured on a chip mounting surface side between the periphery of the semiconductor chip along a first direction, and the periphery of the chip mounting part. In addition, the first member is sealed by the resin. In addition, in plan view, the length of the first portion of the chip mounting part in the first direction is longer than the length of the semiconductor chip in the first direction.
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
brevets
