A method and a compression unit are provided for compressing, into a block of compressed data, a block of sub-primitive presence indications for use in a rendering system. The block of sub-primitive presence indications is subdivided into a plurality of parent regions, each of the parent regions being subdivided into a plurality of child regions. A presence state is identified for each of the child regions based on the sub-primitive presence indications in the block of sub-primitive presence indications. A hierarchical representation of the block of sub-primitive presence indications is stored in the block of compressed data. For each of one or more parent regions whose child regions all have the same identified presence state, parent-level data is included in the hierarchical representation to represent the presence state of the parent region without child-level data for the child regions within the parent region being included in the hierarchical representation. For each of one or more parent regions whose child regions do not all have the same identified presence state, child-level data for the child regions within the parent region is included in the hierarchical representation to represent the presence states for the child regions within the parent region.
A computer-implemented method for selecting numerical formats suitable for use in configuring a hardware implementation of an attention-based neural network. A dataset of test input sequences for the neural network is obtained. Each test input sequence is padded with padding values. For each padded input sequence, a padding mask is generated identifying the part of the padded input sequence that contains the padding values. An attention mask is generated from each padding mask, using an outer product operation. The padded input sequences and attention masks are processed through the neural network. During the processing, statistics are collected, describing ranges of values obtained at various layers of the neural network. Numerical formats are selected for the various layers based on the collected statistics.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
Methods of verifying a property of a hardware design for an integrated circuit to implement a product of power functions of the form x0t0× . . . ×xntn, wherein t0 . . . tn are fixed, rational numbers, x0 . . . xn are floating point inputs, and n is an integer greater than or equal to one. A first verification phase comprises formally verifying that, for any first non-exception input set X=X0, . . . , Xn and any second non-exception input set Y=Y0, . . . , Yn in an input space wherein corresponding inputs have a same mantissa and (t0X0.exp+ . . . +tnXn.exp)−(t0Y0.exp+ . . . +tnYn.exp) is an integer, an instantiation of the hardware design generates outputs X′ and Y′ with a same mantissa and X′exp−(t0X0.exp+ . . . +tnXn.exp)=Y′exp−(t0Y0.exp+ . . . +tnYn.exp); and second verification phase comprises verifying the property for the hardware design for a subset of input sets in the input space, the subset of input sets selected based on exponents sets wherein (t0X0.exp+ . . . +tnXn.exp)−(t0Y0.exp+ . . . +tnYn.exp) is an integer.
A graphics processing system for performing tile-based rendering of a scene that comprises safety-related primitives. The system comprises a plurality of graphics processing units (GPUs), each configured to i) receive tile data identifying one or more protected tiles comprising at least part of a safety-related primitive, ii) process two respective sets of protected tiles, and iii) based on said processing, generate two respective checksums for each respective set of protected tiles. The two respective sets of protected tiles are mutually exclusive, and each respective set and each protected tile being processed by two different GPUs. The system comprises a comparison unit configured to compare one or more pairs of checksums, each pair comprising a respective checksum generated based on a same respective set of protected tiles and generated by different GPUs. The graphics processing system is configured to perform one or more actions based on an outcome of said comparison.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G06T 1/20 - Architectures de processeurs; Configuration de processeurs p.ex. configuration en pipeline
A method and data processing system for implementing inference using an attention-based neural network in a neural network accelerator comprising fixed function hardware. An input sequence for the neural network is padded to a fixed length. A padding mask is generated, identifying the part of the padded input sequence that contains the padding values. An attention mask is generated from the padding mask, using an outer product operation. The padded input sequence and the attention mask are processed to perform the inference using the attention-based neural network. Also disclosed are methods and data processing systems for selecting numerical formats for use in such a neural network, and methods and data processing systems for training such a neural network.
A computer-implemented method of performing intersection testing in a ray tracing system performs intersection testing for each of a plurality of rays against nodes of a hierarchical acceleration structure. The intersection testing for each of the rays comprises, in response to identifying, in a memory, an indication of a re-entry point associated with a ray identifier that is associated with the ray, fetching from the memory the indication of the re-entry point that is associated with the ray identifier, the re-entry point being a node of the hierarchical acceleration structure for which an intersection has been identified for a previously tested ray associated with the ray identifier. The intersection testing for each of the rays further comprises performing intersection testing of the ray against a set of nodes of the hierarchical acceleration structure starting from the re-entry point.
Adder circuits and associated methods for processing a set of at least three floating-point numbers to be added together include identifying, from among the at least three numbers, at least two numbers that have the same sign—that is, at least two numbers that are both positive or both negative. The identified at least two numbers are added together using one or more same-sign floating-point adders. A same-sign floating-point adder comprises circuitry configured to add together floating-point numbers having the same sign and does not include circuitry configured to add together numbers having different signs.
G06F 7/24 - Tri, c. à d. extraction de données d'un ou de plusieurs supports, nouveau rangement des données dans un ordre de succession numérique ou autre, et réinscription des données triées sur le support original ou sur un support différent ou sur une série d
G06F 7/501 - Semi-additionneurs ou additionneurs complets, c. à d. cellules élémentaires d'addition pour une position
H03K 19/20 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion caractérisés par la fonction logique, p.ex. circuits ET, OU, NI, NON
8.
COMPRESSION AND DECOMPRESSION OF SUB-PRIMITIVE PRESENCE INDICATIONS FOR USE IN A RENDERING SYSTEM
Compressed data is decompressed to determine sub-primitive presence indications in a rendering system. A received compressed block of sub-primitive presence indications is subdivided into a plurality of parent regions, each subdivided into a plurality of child regions. A hierarchical representation of the block of sub-primitive presence indications is provided, wherein: (i) for each parent region whose child regions all have the same presence state, parent-level data is included to represent the presence state of the parent region without child-level data for the child regions within the parent region being included in the hierarchical representation, and (ii) for each parent region whose child regions do not all have the same presence state, child-level data for the child regions within the parent region is included in the hierarchical representation to represent the presence states for the child regions within the parent region. If child-level data is included in the hierarchical representation, child-level data for said one of the parent regions is used to determine one or more sub-primitive presence indications in the parent region. If child-level data is not included in the hierarchical representation, parent-level data is used, without child-level data, to determine one or more sub-primitive presence indications in the parent region.
A method and a compression unit are provided for compressing, into a block of compressed data, a block of sub-primitive presence indications for use in intersection testing in a rendering system. An ordered set of patches is obtained which represents the presence indications in the block of sub-primitive presence indications. At least two of the patches in the set of patches partially overlap with each other. Data defining the patches of the set of patches is stored in the block of compressed data. The data defining each of the patches defines a presence state of the patch and a position of the patch within the block of sub-primitive presence indications.
A method and a decompression unit are provided for decompressing compressed data to determine a sub-primitive presence indication for use in intersection testing in a rendering system. A block of compressed data for a block of sub-primitive presence indications is received. An indication of a sample position within the block of sub-primitive presence indications for which a presence indication is to be determined is received. Data defining an ordered set of patches which represents the presence indications in the block of sub-primitive presence indications is read from the block of compressed data. The data defining each of the patches defines a presence state of the patch and a position of the patch within the block of sub-primitive presence indications. At least two of the patches in the set of patches partially overlap with each other. For one or more of the patches, it is determined whether the sample position is within that patch. The presence indication at the sample position is determined based on results of said determining, for one or more of the patches, whether the sample position is within that patch.
The operation of a GPU is controlled based on one or more deadlines by which one or more GPU tasks must be completed and estimates of the time required to complete the execution of a first GPU task (which is currently being executed) and the time required to execute one or more other GPU tasks (which are not currently being executed). Based on a comparison between the deadline(s) and the estimates, context switching may or may not be triggered.
A method of mapping a neural network to hardware uses a binary tree to assess how to split a layer of the neural network into a plurality of hardware passes by determining a starting value of a current depth within the binary tree and arranging the set of coefficients into groups, each corresponding to a node at the current depth. A compressed size of at least one group of coefficients at the current depth is calculated and it is determined whether termination criteria are satisfied. In response to determining that the termination criteria are not satisfied, the current depth is updated and the calculating and determining steps are repeated. In response to determining that termination criteria are satisfied, data is output which defines each of the plurality of hardware passes, wherein the data is dependent upon the current depth.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
13.
PROCESSING FRAGMENTS WHICH HAVE A SHADER-DEPENDENT PROPERTY IN A GRAPHICS PROCESSING SYSTEM
Methods and graphics processing units for processing a plurality of fragments in a graphics processing system. A received first fragment is processed by performing an early depth test with hidden surface removal logic using a depth buffer; in response to the first fragment passing the early depth test, executing one or more instructions of a shader program for the first fragment on the processing logic to determine the property of the first fragment; and after the determination of the property of the first fragment, performing a late depth test on the first fragment with the hidden surface removal logic using the depth buffer. After said receiving a first fragment, a second fragment to be processed is received, wherein the second fragment does not have a shader-dependent property. The second fragment is processed by, before said late depth test is performed on the first fragment, performing an early depth test on the second fragment with the hidden surface removal logic.
Methods and systems for processing data in accordance with a neural network that includes a sequence of layers comprising a first convolution layer, a second convolution layer, and none, one or more than one middle layer between the first and second convolution layers. The method includes: scaling, using hardware logic, a tensor in the neural network, after the first convolution layer and before the second convolution layer, on a per channel basis by a set of per channel activation scaling factors; and implementing, using the hardware logic, the second convolution layer with weights that have been scaled on a per input channel basis by the inverses of the set of per channel activation scaling factors.
A graphics processing system is configured to render primitives using a rendering space that is sub-divided into sections, wherein the graphics processing system includes assessment logic configured to make an assessment regarding the presence of primitive edges in a section, and determination logic configured to determine an anti-aliasing setting for the section based on the assessment.
Methods of arbitrating between requestors and a shared resource wherein for each processing cycle a plurality of select signals are generated and then used by decision nodes in a binary decision tree to select a requestor. The select signals are generated using valid bits and priority bits. Each valid bit corresponds to one of the requestors and indicates whether, in the processing cycle, the requestor is requesting access to the shared resource. Each priority bit corresponds one of the requestors and indicates whether, in the processing cycle, the requestor has priority. Corresponding valid bit and priority bits are combined in an AND logic element to generate a valid_and_priority bit for each requestor. Pair-wise OR-reduction is then performed on both the valid bits and the valid_and_priority bits to generate additional valid bits and valid_and_priority bits for sets of requestors and these are then used to generate the select signal.
A method of converting 10-bit pixel data (e.g. 10:10:10:2 data) into 8-bit pixel data involves converting the 10-bit values to 8-bits using a technique that is selected dependent upon the values of the MSBs of the 10-bit values and setting the value of an HDR flag dependent upon the values of the MSBs. The HDR flag is appended to the 3-bit channel.
H03M 7/30 - Compression; Expansion; Elimination de données inutiles, p.ex. réduction de redondance
H04N 19/103 - Sélection du mode de codage ou du mode de prédiction
H04N 19/119 - Aspects de subdivision adaptative, p.ex. subdivision d’une image en blocs de codage rectangulaires ou non
H04N 19/132 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’élément, le paramètre ou la sélection affectés ou contrôlés par le codage adaptatif Échantillonnage, masquage ou troncature d’unités de codage, p.ex. ré-échantillonnage adaptatif, saut de trames, interpolation de trames ou masquage de coefficients haute fréquence de transformée
H04N 19/176 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c. à d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p.ex. un objet la zone étant un bloc, p.ex. un macrobloc
H04N 19/186 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c. à d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une couleur ou une composante de chrominance
H04N 19/42 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques - caractérisés par les détails de mise en œuvre ou le matériel spécialement adapté à la compression ou à la décompression vidéo, p.ex. la mise en œuvre de logiciels spécialisés
H04N 19/46 - Inclusion d’information supplémentaire dans le signal vidéo pendant le processus de compression
H04N 19/64 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant un codage par transformée utilisant une transformée en sous-bandes, p.ex. ondelettes caractérisé par l’ordonnancement des coefficients ou des bits à transmettre
18.
PRIMITIVE BLOCK GENERATOR FOR GRAPHICS PROCESSING SYSTEMS
Methods and primitive block generators for generating primitive blocks in a graphics processing system. The methods include receiving transformed position data for a current primitive, the transformed position data indicating a position of the current primitive in rendering space; determining a distance between the position of the current primitive and a position of a current primitive block based on the transformed position data for the current primitive; determining whether to add the current primitive to the current primitive block based on the distance and a fullness of the current primitive block; in response to determining that the current primitive is to be added to the current primitive block, adding the current primitive to the current primitive block; and in response to determining that the current primitive is not to be added to the current primitive block, flushing the current primitive block and adding the current primitive to a new current primitive block.
An adder and a method for calculating 2n+x are provided, where x is a variable input expressed in a floating point format and n is an integer. The adder comprises: a first path configured to calculate 2n+x for x<0 and 2n−1≤|x|<2n+1; a second path configured to calculate 2n+x for |x|<2n; a third path configured to calculate 2n+x for |x|≥2n; and selection logic configured to cause the adder to output a result from one of the first, second, and third paths in dependence on the values of x and n.
A decoder decodes a plurality of texels from a received block of texture data encoded according to the Adaptive Scalable Texture Compression (ASTC) format. A parameter decode unit decodes configuration data for the received block of texture data, a colour decode unit decodes colour endpoint data for the plurality of texels in dependence on the configuration data, a weight decode unit decodes interpolation weight data for each of the plurality of texels in dependence on the configuration data, and at least one interpolator unit calculates a colour value for each of the plurality of texels using the interpolation weight data for that texel and a pair of colour endpoints from the colour endpoint data. At least one of the parameter decode unit, colour decode unit and weight decode unit decodes intermediate data from the received block that is common to the decoding of a subset of texels of that block and uses that decoded data as part of the decoding of at least two of the plurality of texels.
H04N 19/436 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques - caractérisés par les détails de mise en œuvre ou le matériel spécialement adapté à la compression ou à la décompression vidéo, p.ex. la mise en œuvre de logiciels spécialisés utilisant des dispositions de calcul parallélisées
H04N 19/44 - Décodeurs spécialement adaptés à cet effet, p.ex. décodeurs vidéo asymétriques par rapport à l’encodeur
21.
GRAPHICS PROCESSING METHOD AND SYSTEM FOR PROCESSING SUB-PRIMITIVES
A graphics processing system configured to use a rendering space which is subdivided into a plurality of tiles, includes geometry processing logic having geometry transform and sub-primitive logic configured to receive graphics data of input graphics data items, and to determine transformed positions within the rendering space of one or more sub-primitives derived from the input graphics data items using a plurality of shader stages; and a tiling unit configured to generate control stream data including sub-primitive indications to indicate which of the sub-primitives are to be used for rendering each tile. The geometry processing logic is configured to write to a memory, for each instance of a pre-determined shader stage, shader stage output data comprising data output from each instance of the pre-determined shader stage used to process the received graphics data.
A method of rendering geometry of a 3D scene for display on a non-standard projection display projects geometry of the 3D scene into a 2D projection plane, wherein image regions are defined in the projection plane, maps the geometry from the projection plane into an image space using transformations, wherein a respective transformation is defined for each image region, and renders the geometry in the image space to determine image values of an image to be displayed on the non-standard projection display. The transformations are configured for mapping the geometry into the image space so as to counteract distortion introduced by an optical arrangement of the non-standard projection display.
H04N 13/344 - Affichage pour le visionnement à l’aide de lunettes spéciales ou de visiocasques avec des visiocasques portant des affichages gauche et droit
23.
IMAGE DATA DECOMPRESSION USING DIFFERENCE VALUES BETWEEN DATA VALUES AND ORIGIN VALUES FOR IMAGE DATA CHANNELS
A decompression method determines image element values from compressed data representing a block of image element values relating to a respective one or more channels. For each of the channels, an indication of a first number of bits representing difference values between the data values and an origin value for the channel is read from the compressed data. For each of the channels, a second number of bits is obtained, wherein representations of the difference values for each of the channels are included in the compressed data using the second number of bits for that channel. The obtained second numbers of bits for the respective channels are used to read the representations of the difference values for the image element values being decompressed. Based on the representations of the difference values, a difference value is determined in accordance with the first number of bits for the channel. For each of the one or more channels, the data value relating to the channel for each of the image element values being decompressed is determined using: (i) the origin value for the channel, and (ii) the determined difference value for the channel for the image element value.
G06F 7/72 - Méthodes ou dispositions pour effectuer des calculs en utilisant une représentation numérique non codée, c. à d. une représentation de nombres sans base; Dispositifs de calcul utilisant une combinaison de représentations de nombres codées et non codées utilisant l'arithmétique des résidus
G06T 3/40 - Changement d'échelle d'une image entière ou d'une partie d'image
A method and compression unit for compressing a block of image data to satisfy a target level of compression, wherein the block of image data comprises a plurality of image element values, each image element value comprising one or more data values relating to a respective channel. For each of the channels: (i) an origin value for the channel for the block is determined, (ii) difference values are determined representing differences between the data values and the determined origin value for the channel for the block, and (iii) a first number of bits for losslessly representing a maximum difference value of the difference values for the channel for the block is determined. The determined first number of bits for each of the channels is used to determine a respective second number of bits for each of the channels, the second number of bits being determined such that representing each of the difference values for the channels with the respective second number of bits satisfies the target level of compression for compressing the block of image data. Compressed data is formed, having for each of the one or more channels an indication of the determined origin value for the channel, an indication of the determined first number of bits for the channel, and representations of the determined difference values for the channel, wherein each of the representations of the determined difference values for the channel uses the determined second number of bits for the channel, such that the target level of compression is satisfied.
G06F 7/72 - Méthodes ou dispositions pour effectuer des calculs en utilisant une représentation numérique non codée, c. à d. une représentation de nombres sans base; Dispositifs de calcul utilisant une combinaison de représentations de nombres codées et non codées utilisant l'arithmétique des résidus
G06T 3/40 - Changement d'échelle d'une image entière ou d'une partie d'image
Systems can identify visible surfaces for pixels in an image (portion) to be rendered. A sampling pattern of ray directions is applied to the pixels, so that the sampling pattern of ray directions repeats, and with respect to any pixel, the same ray direction can be found in the same relative position, with respect to that pixel, as for other pixels. Rays are emitted from visible surfaces in the respective ray direction supplied from the sampling pattern. Ray intersections can cause shaders to execute and contribute results to a sample buffer. With respect to shading of a given pixel, ray results from a selected subset of the pixels are used; the subset is selected by identifying a set of pixels, collectively from which rays were traced for the ray directions in the pattern, and requiring that surfaces from which rays were traced for those pixels satisfy a similarity criteria.
Apparatus identifies a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address. A comparator block performs comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset. Combination logic units receive a predetermined selection of bits of the binary classification dataset and sort its received predetermined selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset. Output generating logic selects between bits belonging to different intermediary binary strings to generate a binary output identifying a set of output memory addresses containing at least one address in the identified subset.
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G06F 12/02 - Adressage ou affectation; Réadressage
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
27.
COMPRESSED RAY DIRECTION DATA IN A RAY TRACING SYSTEM
Ray tracing systems process rays through a 3D scene to determine intersections between rays and geometry in the scene, for rendering an image of the scene. Ray direction data for a ray can be compressed, e.g. into an octahedral vector format. The compressed ray direction data for a ray may be represented by two parameters (u,v) which indicate a point on the surface of an octahedron. In order to perform intersection testing on the ray, the ray direction data for the ray is unpacked to determine x, y and z components of a vector to a point on the surface of the octahedron. The unpacked ray direction vector is an unnormalised ray direction vector. Rather than normalising the ray direction vector, the intersection testing is performed on the unnormalised ray direction vector. This avoids the processing steps involved in normalising the ray direction vector.
Methods and apparatus for compressing image data are described along with corresponding methods and apparatus for decompressing the compressed image data. A decoder unit samples compressed image data including interleaved blocks of data encoding a first image and blocks of data encoding differences between the first image and a second image, the second image being twice the width and the height of the first image. A difference decoder decodes a fetched encoded sub-block of the differences between the first and second images and output a difference quad and a prediction value for a pixel, and a filter sub-unit generates a reconstruction of the image at a sample position using decoded blocks of the first image, the difference quad and the prediction value.
H04N 19/17 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c. à d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p.ex. un objet
H04N 19/34 - Techniques d'échelonnage mettant en œuvre un codage progressif par plans de bits de la couche d'amélioration, p.ex. échelonnage granulaire fin [FGS]
H04N 19/423 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques - caractérisés par les détails de mise en œuvre ou le matériel spécialement adapté à la compression ou à la décompression vidéo, p.ex. la mise en œuvre de logiciels spécialisés caractérisés par les dispositions des mémoires
H04N 19/59 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage prédictif mettant en œuvre un sous-échantillonnage spatial ou une interpolation spatiale, p.ex. modification de la taille de l’image ou de la résolution
Lossy methods and hardware for compressing data and the corresponding decompression methods and hardware are described. The lossy compression method comprises dividing a block of pixels into a number of sub-blocks and then analysing, for each sub-block, and selecting one of a candidate set of lossy compression modes. The analysis may, for example, be based on the alpha values for the pixels in the sub-block. In various examples, the candidate set of lossy compression modes comprises at least one mode that uses a fixed alpha channel value for all pixels in the sub-block and one or more modes that encode a variable alpha channel value.
H03M 7/30 - Compression; Expansion; Elimination de données inutiles, p.ex. réduction de redondance
H04N 19/103 - Sélection du mode de codage ou du mode de prédiction
H04N 19/119 - Aspects de subdivision adaptative, p.ex. subdivision d’une image en blocs de codage rectangulaires ou non
H04N 19/176 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c. à d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p.ex. un objet la zone étant un bloc, p.ex. un macrobloc
H04N 19/186 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c. à d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une couleur ou une composante de chrominance
H04N 19/42 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques - caractérisés par les détails de mise en œuvre ou le matériel spécialement adapté à la compression ou à la décompression vidéo, p.ex. la mise en œuvre de logiciels spécialisés
30.
Methods and Graphics Processing Units for Determining Differential Data for Rays of a Ray Bundle
Graphics processing system configured to perform ray tracing. Rays are bundled together and processed together. When differential data is needed by a shader, the data of a true ray in the bundle can be used rather than processing separate tracker rays.
Ray tracing systems and computer-implemented methods for generating a hierarchical acceleration structure for intersection testing in a ray tracing system. Nodes of the hierarchical acceleration structure are determined, wherein each of the nodes represents a region in a scene, and wherein the nodes are linked to form the hierarchical acceleration structure. Data is stored representing the hierarchical acceleration structure including data defining the regions represented by a plurality of the nodes of the hierarchical acceleration structure. At least one node is an implicitly represented node, wherein data defining a region represented by an implicitly represented node is not explicitly included as part of the stored data but can be inferred from the stored data. Ray tracing systems and computer-implemented methods for performing intersection testing in the ray tracing system determine whether testing of one or more rays for intersection with a region represented by a particular node of a sub-tree is to be skipped.
A tag buffer implements a tag buffer stage of a rasterization phase in a tile-based rendering graphics processing system having a rendering space sub-divided into a plurality of tiles to which primitives can be associated. A buffer stores an identifier that identifies a visible primitive fragment at each sample position of a tile of the plurality of tiles. A look-up table stores an entry for transformed primitive blocks that indicates whether the tag buffer has received information identifying a primitive fragment associated with that transformed primitive block. The tag buffer receives information identifying primitive fragments that have survived a depth test, updates the buffer to indicate that an identified primitive fragment is the visible primitive fragment at the associated sample position, updates the look-up table to indicate which transformed primitive blocks the identified primitive fragments are associated with, and in response to flushing the contents of the buffer, compares the flushed contents of the buffer to the look-up table to thereby identify transformed primitive blocks that did not survive the tag buffer stage.
A graphics processing unit configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles, the graphics processing unit comprising: a plurality of processing cores configured to render graphics data; cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing the set of one or more tiles; similarity indication logic configured to obtain similarity indications between sets of one or more tiles of the rendering space, wherein the similarity indication between two sets of one or more tiles is indicative of a level of similarity between the two sets of tiles according to at least one processing metric; and scheduling logic configured to assign the sets of one or more tiles to the processing cores for rendering in dependence on the cost indications and the similarity indications.
Ray tracing systems have computation units (“RACs”) adapted to perform ray tracing operations (e.g. intersection testing). There are multiple RACs. A centralized packet unit controls the allocation and testing of rays by the RACs. This allows RACs to be implemented without Content Addressable Memories (CAMs) which are expensive to implement, but the functionality of CAMs can still be achieved by implemented them in the centralized controller.
Aspects comprise systems implementing 3-D graphics processing functionality in a multiprocessing system. Control flow structures are used in scheduling instances of computation in the multiprocessing system, where different points in the control flow structure serve as points where deferral of some instances of computation can be performed in favor of scheduling other instances of computation. In some examples, the control flow structure identifies particular tasks, such as intersection testing of a particular portion of an acceleration structure, and a particular element of shading code. In some examples, the aspects are used in 3-D graphics processing systems that can perform ray tracing based rendering.
Ray tracing units, processing modules and methods are described for generating one or more reduced acceleration structures to be used for intersection testing in a ray tracing system for processing a 3D scene. Nodes of the reduced acceleration structure(s) are determined, wherein a reduced acceleration structure represents a subset of the 3D scene. The reduced acceleration structure(s) are stored for use in intersection testing. Since the reduced acceleration structures represent a subset of the scene (rather than the whole scene) the memory usage for storing the acceleration structure is reduced, and the latency in the traversal of the acceleration structure is reduced.
A graphics processing engine has a geometry shading stage having two modes of operation. In the first mode of operation, each primitive output by the geometry shading stage is independent, whereas in the second mode of operation, connectivity between input primitives is maintained by the geometry shading stage. The mode of operation of the geometry shading stage can be determined based on the value of control state data which may be generated at compile-time for a geometry shader based on analysis of that geometry shader.
Methods and storage unit allocators for allocating one or more portions of a storage unit to a plurality of tasks for storing at least two types of data. The method includes receiving a request for one or more portions of the storage unit to store a particular type of data of the at least two types of data for a task of the plurality of tasks; associating the request with one of a plurality of virtual partitionings of the storage unit based on one or more characteristics of the request, each virtual partitioning allotting none, one, or more than one portion of the storage unit to each of the at least two types of data; and allocating the requested one or more portions of the storage unit to the task from the none, one, or more than one portion of the storage unit allotted to the particular type of data in the virtual partitioning associated with the request.
A graphics processing system includes a plurality of processing units, wherein the graphics processing system is configured to process a task first and second times at the plurality of processing units. Data identifying which processing unit of the plurality of processing units the task has been allocated to is consulted on allocating the task to a processing unit for processing for a second time, and, in response, the task is allocated for processing for the second time to any processing unit of the plurality of processing units other than the processing unit to which the task was allocated for processing for a first time.
Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.
In tile-based graphics processing systems, a tiling unit determines which tiles of a rendering space a primitive is in, such that the primitives in a tile can be rendered. Rather than performing tiling calculations for each tile in a bounding box for a primitive, tiling tests can be performed for a subset of the tiles. Then the results of the tiling tests for the subset of tiles can be used to determine whether the primitive is in other tiles which are located within a region bounded by two or more of the tiles of the subset. In this way the tiling process can be implemented without performing tiling calculations for all of the tiles in the bounding box for a primitive. Reducing the number of tiling calculations can help to improve the efficiency of the graphics processing system (in terms of speed and power consumption) for rendering a primitive.
A method and a decompression unit are provided for decompressing compressed data to determine one or more sub-primitive presence indications for use in a rendering system. A block of compressed data for a block of sub-primitive presence indications is received. The block of sub-primitive presence indications comprises a plurality of sub-blocks of sub-primitive presence indications. The block of compressed data comprises, for each of the sub-blocks in the block of sub-primitive presence indications, an index to indicate one of a plurality of candidates for combinations of presence indications. An index is read from the block of compressed data for one of the sub-blocks in the block of sub-primitive presence indications. Candidate data is obtained representing at least a portion of the candidate indicated by the read index. The obtained candidate data is used to determine one or more of the presence indications in the sub-block.
A block of sub-primitive presence indications for use in intersection testing in a rendering system is compressed into a block of compressed data. Spatial decorrelation is performed on the sub-primitive presence indications to determine spatially decorrelated presence indications by, for one or more of the presence indications in the line: (i) determining a predicted value for the presence indication based on one or more other presence indications in the line, and (ii) replacing the presence indication with a value of a difference between the presence indication and the determined predicted value for the presence indication. For each line of presence indications in a second dimension within the block, for one or more of the presence indications in the line: (i) a predicted value for the presence indication is determined based on one or more other presence indications in the line, and (ii) the presence indication is replaced with a value of a difference between the presence indication and the determined predicted value for the presence indication.
Compressed data is decompressed to determine sub-primitive presence indications for intersection testing in a rendering system. Entropy encoded data is read from a block of compressed sub-primitive presence indications data and entropy decoding determines a block of entropy decoded data values. Spatial recorrelation on the block of entropy decoded values determines sub-primitive presence indications. For each line of entropy decoded values in a first dimension: for the entropy decoded values in the line: (i) a predicted value is determined for the entropy decoded value based on other entropy decoded values in the line, and (ii) the entropy decoded value is replaced with a value of a sum of the entropy decoded value and the determined predicted value for the entropy decoded value. For each line of entropy decoded values in a second dimension: for the entropy decoded values in the line: (i) a predicted value for the entropy decoded value is determined based on other entropy decoded values in the line, and (ii) the entropy decoded value is replaced with a value of a sum of the entropy decoded value and the determined predicted value for the entropy decoded value.
A method of feature matching in images captured from camera viewpoints uses the epipolar geometry of the viewpoints to define a geometrically-constrained region in a second image corresponding to a first feature in a first image; comparing the local descriptor of the first feature with local descriptors of features in the second image to determine respective measures of similarity; identifying, from the features located in the geometrically-constrained region, (i) a geometric best match and (ii) a geometric next-best match to the first feature; identifying a global best match to the first feature; performing a first comparison of the measures of similarity for the geometric best match and the global best match; performing a second comparison of the measures of similarity for the geometric best match and the geometric next-best match; and, if thresholds are met, selecting the geometric best match feature in the second image.
A method and a compression unit are provided for compressing, into a block of compressed data, a block of sub-primitive presence indications for use in a rendering system. The block of sub-primitive presence indications comprises a plurality of sub-blocks of sub-primitive presence indications. A plurality of candidates for combinations of presence indications are identified. For each of the sub-blocks in the block of sub-primitive presence indications: one of the candidates to be used to represent the sub-block is selected, and an index to indicate the selected candidate is stored in the block of compressed data.
A hardware unit for manipulating data stored in a memory comprises an internal buffer, a memory reading block, configured to read the data from the memory and write the data to the internal buffer. a memory writing block, configured to read the data from the internal buffer and write the data to the memory. The hardware unit optionally also comprises a control channel between the memory reading block and the memory writing block, wherein the memory reading block and the memory writing block are configured to communicate via the control channel to maintain synchronisation between them when writing the data to the internal buffer and reading the data from the internal buffer, respectively. The hardware unit may be configured to apply one or more transformations to multidimensional data in the memory. The hardware unit may be configured to traverse the multidimensional array using a plurality of nested loops.
A hardware monitor arranged to detect out-of-bounds violations in a hardware design for an electronic device. The hardware monitors include monitor and detection logic configured to monitor the current operating state of an instantiation of the hardware design and detect when the instantiation of the hardware design implements a fetch of an instruction from memory; and assertion evaluation logic configured to evaluate one or more assertions that assert a formal property that compares the memory address of the fetched instruction to an allowable memory address range associated with the current operating state of the instantiation of the hardware design to determine whether there has been an out-of-bounds violation. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design does not cause an instruction to be fetched from an out-of-bounds address.
G06F 30/3323 - Vérification de la conception, p.ex. simulation fonctionnelle ou vérification du modèle utilisant des méthodes formelles, p.ex. vérification de l’équivalence ou vérification des propriétés
G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
G06F 11/34 - Enregistrement ou évaluation statistique de l'activité du calculateur, p.ex. des interruptions ou des opérations d'entrée–sortie
G06F 30/39 - Conception de circuits au niveau physique
Apparatus includes hardware logic arranged to normalise an n-bit input number. The hardware logic comprises at least a first hardware logic stage, an intermediate hardware logic stage and a final hardware logic stage. Each stage comprises a left shifting logic element, the first and intermediate stages each also comprise a plurality of OR-reduction logic elements and the intermediate and final stages each also comprise one or more multiplexers. The OR-reduction logic elements operate on different subsets of bits from the number input to the particular stage. In the intermediate and final hardware logic stages, a first of the multiplexers selects an OR-reduction result received from a previous hardware logic stage and the left shifting logic element is arranged to perform left shifting on the updated binary number received from an immediately previous hardware logic stage dependent upon the selected OR-reduction result.
G06F 5/01 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour le décalage, p.ex. la justification, le changement d'échelle, la normalisation
G06F 7/499 - Maniement de valeur ou d'exception, p.ex. arrondi ou dépassement
A method of rasterising a line in computer graphics determines whether the line's start and/or end is inside a diamond test area within the pixel. If the end is not inside and the start is inside, the pixel is drawn as part of the line. If neither the start nor the end of the line are inside, it is determined whether the line crosses more than one extended diamond edge and if so, it is further determined (i) whether an extended line passing through the start and end is substantially vertical and touches the right point of the diamond area, (ii) if the extended line touches the bottom point of the diamond area, and (iii) whether the extended line is on a same side of each point of the diamond area. If any of (i), (ii) and (iii) is positive, the pixel is drawn as part of the line.
Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant kth difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.
G06F 30/3323 - Vérification de la conception, p.ex. simulation fonctionnelle ou vérification du modèle utilisant des méthodes formelles, p.ex. vérification de l’équivalence ou vérification des propriétés
52.
Method and System for Wirelessly Transmitting Data
Methods and systems for wirelessly transmitting data between Wi-Fi stations without requiring the Wi-Fi stations to be fully connected to the Wi-Fi network. A first Wi-Fi station generates the data to be transmitted. The data comprises status data and/or wake-up data. The first Wi-Fi station then inserts the data in a vendor-specific information element of a probe request frame and wirelessly transmits the probe request frame. The probe request frame is then received by a second Wi-Fi station. If the probe request frame contains wake-up data and the second Wi-Fi station is operating in a low-power mode when it receives the probe request frame, the second Wi-Fi station will wake-up from the low-power mode. If the probe request frame contains status data then the second Wi-Fi station may process the probe request frame and/or forward at least a portion of the received probe request frame to another device.
G08B 25/00 - Systèmes d'alarme dans lesquels l'emplacement du lieu où existe la condition déclenchant l'alarme est signalé à une station centrale, p.ex. systèmes télégraphiques d'incendie ou de police
G08B 25/10 - Systèmes d'alarme dans lesquels l'emplacement du lieu où existe la condition déclenchant l'alarme est signalé à une station centrale, p.ex. systèmes télégraphiques d'incendie ou de police caractérisés par le moyen de transmission utilisant des systèmes de transmission sans fil
53.
Primitive Processing in a Graphics Processing System
A graphics processing system has a rendering space which is divided into tiles. Primitives within the tiles are processed to perform hidden surface removal and to apply texturing to the primitives. The graphics processing system includes a plurality of depth buffers, thereby allowing a processing module to process primitives of one tile by accessing one of the depth buffers while primitive identifiers of another, partially processed tile are stored in another one of the depth buffers. This allows the graphics processing system to have “multiple tiles in flight”, which can increase the efficiency of the graphics processing system.
A reduced noise image can be formed from a set of images. One of the images of the set can be selected to be a reference image and other images of the set are transformed such that they are better aligned with the reference image. A measure of the alignment of each image with the reference image is determined. At least some of the transformed images can then be combined using weights which depend on the alignment of the transformed image with the reference image to thereby form the reduced noise image. By weighting the images according to their alignment with the reference image the effects of misalignment between the images in the combined image are reduced. Furthermore, motion correction may be applied to the reduced noise image.
G06T 7/32 - Détermination des paramètres de transformation pour l'alignement des images, c. à d. recalage des images utilisant des procédés basés sur la corrélation
G06T 5/50 - Amélioration ou restauration d'image en utilisant plusieurs images, p.ex. moyenne, soustraction
G06T 7/30 - Détermination des paramètres de transformation pour l'alignement des images, c. à d. recalage des images
55.
Dedicated Ray Memory for Ray Tracing in Graphics Systems
A ray tracing unit implemented in a graphics rendering system includes processing logic configured to perform ray tracing operations on rays, a dedicated ray memory coupled to the processing logic and configured to store ray data for rays to be processed by the processing logic, an interface to a memory system, and control logic configured to manage allocation of ray data to either the dedicated ray memory or the memory system. Core ray data for rays to be processed by the processing logic is stored in the dedicated ray memory, and at least some non-core ray data for the rays is stored in the memory system. This allows core ray data for many rays to be stored in the dedicated ray memory without the size of the dedicated ray memory becoming too wasteful when the ray tracing unit is not in use.
A method of scheduling tasks in a processor comprises receiving a plurality of tasks that are ready to be executed, i.e. all their dependencies have been met and all the resources required to execute the task are available, and adding the received tasks to a task queue (or “task pool”). The number of tasks that are executing is monitored and in response to determining that an additional task can be executed by the processor, a task is selected from the task pool based at least in part on a comparison of indications of resources used by tasks being executed and indications of resources used by individual tasks in the task pool and the selected task is then sent for execution.
Ray tracing systems and methods for generating a hierarchical acceleration structure for intersection testing. Nodes of the hierarchical acceleration structure are determined, each of the nodes representing a region in a scene, the nodes being linked to form the hierarchical acceleration structure. Data is stored representing the hierarchical acceleration structure. The stored data comprises data defining the regions represented by a plurality of the nodes. At least one node is an implicitly represented node, wherein data defining a region represented by an implicitly represented node is not explicitly included as part of the stored data but can be inferred from the stored data. Also described are ray tracing systems and computer-implemented methods for performing intersection testing in which, based on conditions in the ray tracing system, a determination is made as to whether testing of one or more rays for intersection with a region represented by a particular node of a sub-tree is to be skipped.
A master unit in a core of a plurality of cores in a graphics processing unit receives a set of image rendering tasks, assigns a first subset of the image rendering tasks to a first core of the plurality of cores and assigns a second subset of the image rendering tasks to a second core of the plurality of cores. The master unit transmits the first subset of image rendering tasks to a slave unit of the first core and transmits the second subset of image rendering tasks to a slave unit of the second core. The master unit stores a credit number for each of the first and second cores and adjusts the credit number of the first and second cores by a first amount for each task in the first and second subset of the image rendering tasks. The slave units transmit credit notifications when tasks have been processed and the master unit adjusts the credit numbers when it receives the notifications.
G06T 1/20 - Architectures de processeurs; Configuration de processeurs p.ex. configuration en pipeline
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p.ex. plusieurs processeurs de données à instruction unique
Accumulator hardware logic includes first and second addition logic units and a store. The first addition logic unit comprises a first input, a second input and an output, each of the first and second inputs arranged to receive an input value in each clock cycle. The second addition logic unit comprises a first input that is connected directly to the output of the first addition logic unit. It also comprises a second input and an output. The store is arranged to store a result output by the second addition logic unit. The accumulator hardware logic further comprises shifting hardware and/or negation hardware positioned in a feedback path between the store and the second input of the second addition logic unit. The shifting hardware is configured to perform a shift by a fixed number of bit positions in a fixed direction.
G06F 5/01 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour le décalage, p.ex. la justification, le changement d'échelle, la normalisation
60.
METHODS AND SYSTEMS FOR STORING VARIABLE LENGTH DATA BLOCKS IN MEMORY
A set of two or more variable length data blocks is stored in memory. Each variable length data block has a maximum size of N*B, wherein N is an integer greater than or equal to two, and B is a maximum data size that can be written to the memory using a single memory access request. For each variable length data block of the set, the first P non-overlapping portions of size B of the variable length data block are stored in a chunk of the memory allocated to that variable length data block, wherein P is a minimum of (i) a number of non-overlapping portions of size B of the variable length data block and (ii) X which is an integer less than N. Any remaining portions of the variable length data blocks are stored in a remainder section of the memory shared between the variable length data blocks of the set. Information indicating the size of each of the variable length data blocks in the set is stored in a header.
A method of performing safety-critical rendering at a graphics processing unit within a graphics processing system, the method comprising: receiving, at the graphics processing system, graphical data for safety-critical rendering at the graphics processing unit; scheduling at a safety controller, in accordance with a reset frequency, a plurality of resets of the graphics processing unit; rendering the graphical data at the graphics processing unit; and the safety controller causing the plurality of resets of the graphics processing unit to be performed commensurate with the reset frequency.
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p.ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
G06T 1/20 - Architectures de processeurs; Configuration de processeurs p.ex. configuration en pipeline
A method and system for performing a render using a graphics processing unit that implements a tile-based graphics pipeline where a rendering space is sub-divided into tiles. Geometry data for the render is received, the geometry data including primitives associated with one or more vertex shader programs. The geometry data is processed using the vertex shader programs to generate processed primitives, and it is determined in which tile each of the processed primitives are located. For at least one selected tile there is stored i) a representation of per-tile vertex shader data identifying the one or more vertex shader programs used to generate the processed primitives in that tile, and ii) a representation of per-tile render data that can be used when rendering the processed primitives in that tile in subsequent stages of the graphics pipeline. It is determined whether the output of a previous render for the selected tile(s) can be used as an output for the render by comparing the per-tile vertex shader data of that tile with that of the previous render before comparing the per-tile render data of that tile with that of the previous render.
A graphics processing system for a head mounted display (or other non-standard projection display) comprises a low latency distortion unit which is separate from a graphics processing unit in the graphics processing system. The low latency distortion unit receives pixel data generated by the graphics processing system using a standard projection and performs a mapping operation to introduce distortion which is dependent upon the optical properties of the optical arrangement within the head mounted display. The distorted pixel data which is generated by the low latency distortion unit is then output to the display in the head mounted display.
Methods and intersection testing modules are provided for determining, in a ray tracing system, whether a ray intersects a 3D axis-aligned box representing a volume defined by a front-facing plane and a back-facing plane for each dimension. The front-facing plane of the box which intersects the ray furthest along the ray is identified. It is determined whether the ray intersects the identified front-facing plane at a position that is no further along the ray than positions at which the ray intersects the back-facing planes in a subset of the dimensions, and this determination is used to determine whether the ray intersects the axis-aligned box. The subset of dimensions comprises the two dimensions for which the front-facing plane was not identified, but does not comprise the dimension for which the front-facing plane was identified. It is determined whether the ray intersects the box without performing a test to determine whether the ray intersects the identified front-facing plane at a position that is no further along the ray than a position at which the ray intersects the back-facing plane in the dimension for which the front-facing plane was identified.
A method and apparatus are provided for manufacturing integrated circuits performing invariant integer division x/d. A desired rounding mode is provided and an integer triple (a,b,k) for this rounding mode is derived. Furthermore, a set of conditions for the rounding mode is derived. An RTL representation is then derived using the integer triple. From this a hardware layout can be derived and an integrated circuit manufactured with the derived hardware layout. When the integer triple is derived a minimum value of k for the desired rounding mode and set of conditions is also derived.
G06F 7/38 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
A method and system for performing a render using a graphics processing unit that implements a tile-based graphics pipeline where a rendering space is sub-divided into tiles. Primitives are received that were processed by a geometry processing stage of the graphics pipeline and these are grouped into one or more sets, and a primitive block generated from each set. Primitive block data is stored characterising the content of the one or more primitive blocks. It is determined which tile each of the primitives are located in, and for at least one selected tile a per-tile primitive block list is stored indicating which of the one or more primitive blocks contain primitives located in that tile. It is determined whether the output of a previous render for the selected tile(s) can be used as an output for the render based on the per-tile primitive block list and the primitive block data for the primitive blocks indicated therein, and corresponding data from the previous render.
A graphics processing hardware pipeline is arranged to perform an edge test or a depth calculation. Each hardware arrangement includes a microtile component hardware element, multiple pixel component hardware elements, one or more subsample component hardware elements and a final addition and comparison unit. The microtile component hardware element calculates a first output using a sum-of-products and coordinates of a microtile within a tile in the rendering space. Each pixel component hardware element calculates a different second output using the sum-of-products and coordinates for different pixels defined relative to an origin of the microtile. The subsample component hardware element calculates a third output using the sum-of-products and coordinates for a subsample position defined relative to an origin of a pixel. The adders sum different combinations of the first output, a second output and a third output to generate output results for different subsample positions defined relative to the origin of the tile.
A binary logic circuit for performing an interpolation calculation between two endpoint values E0 and E1 using a weighting index i for generating an interpolated result P, the values E0 and E1 being formed from Adaptive Scalable Texture Compression (ASTC) low-dynamic range (LDR) colour endpoint values C0 and C1 respectively, the circuit comprising: an interpolation unit configured to perform an interpolation between the colour endpoint values C0 and C1 using the weighting index i to generate a first intermediate interpolated result C2; and combinational logic circuitry configured to receive the interpolated result C2 and to perform one or more logical processing operations to calculate the interpolated result P according to the equation P=└((C2<<8)+C2+32)/64┘ when the interpolated result is not to be compatible with an sRGB colour space, and according to the equation P=└((C2<<8)+128·64+32)/64┘ when the interpolated result is to be compatible with an sRGB colour space.
A method and an intersection testing module in a ray tracing system for determining whether a ray intersects a three-dimensional axis-aligned box. It is determined whether a first condition is satisfied, wherein the first condition is, or is equivalent to,
A method and an intersection testing module in a ray tracing system for determining whether a ray intersects a three-dimensional axis-aligned box. It is determined whether a first condition is satisfied, wherein the first condition is, or is equivalent to,
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A method and an intersection testing module in a ray tracing system for determining whether a ray intersects a three-dimensional axis-aligned box. It is determined whether a first condition is satisfied, wherein the first condition is, or is equivalent to,
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A method and an intersection testing module in a ray tracing system for determining whether a ray intersects a three-dimensional axis-aligned box. It is determined whether a first condition is satisfied, wherein the first condition is, or is equivalent to,
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"\[RightBracketingBar]"
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A method and an intersection testing module in a ray tracing system for determining whether a ray intersects a three-dimensional axis-aligned box. It is determined whether a first condition is satisfied, wherein the first condition is, or is equivalent to,
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It is determined whether a second condition is satisfied, wherein the second condition is, or is equivalent to,
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It is determined whether a third condition is satisfied, wherein the third condition is, or is equivalent to,
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The determinations of whether the first, second and third conditions are satisfied are used to determine whether the ray intersects the axis-aligned box. Cx, Cy and Cz are x, y and z components of a position of the centre of the axis-aligned box relative to an origin of the ray, Hx, Hy and Hz are half widths of the axis-aligned box in the x, y and z dimensions, and Dx, Dy and Dz are x, y and z components of a direction vector of the ray.
Methods and graphics processing systems render items of geometry using a rendering space which is subdivided into a plurality of first regions. Each of the first regions is sub-divided into a plurality of second regions. Each of a plurality of items of geometry is processed by identifying which of the first regions the item of geometry is present within, and for each identified first region determining an indication of the spatial coverage, within the identified first region, of the item of geometry, and using the determined indication of the spatial coverage within the identified first region to determine whether to add the item of geometry to a first control list for the identified first region or to add the item of geometry to one or more second control lists for a respective one or more of the second regions within the identified first region. Items of geometry within a second region can then be rendered using: (i) the first control list for the first region of which the second region is a part, and (ii) the second control list for the second region.
A SIMD processing unit processes a plurality of tasks which each include up to a predetermined maximum number of work items. The work items of a task are arranged for executing a common sequence of instructions on respective data items. The data items are arranged into blocks, with some of the blocks including at least one invalid data item. Work items which relate to invalid data items are invalid work items. The SIMD processing unit comprises a group of processing lanes configured to execute instructions of work items of a particular task over a plurality of processing cycles. A control module assembles work items into the tasks based on the validity of the work items, so that invalid work items of the particular task are temporally aligned across the processing lanes. In this way the number of wasted processing slots due to invalid work items may be reduced.
G06T 1/20 - Architectures de processeurs; Configuration de processeurs p.ex. configuration en pipeline
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p.ex. plusieurs processeurs de données à instruction unique
Graphics processing systems can include lighting effects when rendering images. “Light probes” are directional representations of lighting at particular probe positions in the space of a scene which is being rendered. Light probes can be determined iteratively, which can allow them to be determined dynamically, in real-time over a sequence of frames. Once the light probes have been determined for a frame then the lighting at a pixel can be determined based on the lighting at the nearby light probe positions. Pixels can then be shaded based on the lighting determined for the pixel positions.
A memory interface for interfacing between a memory bus and a cache memory. A plurality of bus interfaces are configured to transfer data between the memory bus and the cache memory, and a plurality of snoop processors are configured to receive snoop requests from the memory bus. Each snoop processor is associated with a respective bus interface and each snoop processor is configured, on receiving a snoop request, to determine whether the snoop request relates to the bus interface associated with that snoop processor and to process the snoop request in dependence on that determination.
A binary logic circuit performs an interpolation calculation between two endpoint values E0 and E1 using a weighting index i for generating an interpolated result P, the values E0 and E1 being formed from Adaptive Scalable Texture Compression (ASTC) colour endpoint values C0 and C1 respectively, the colour endpoint values C0 and C1 being low-dynamic range (LDR) or high dynamic range (HDR) values. An interpolation unit performs an interpolation between the values C0 and C1 using the index i to generate a first intermediate interpolated result C2; combinational logic circuitry receives the result C2 and performs logical processing operations to calculate the interpolated result P according to the equation: (1) P=└((C2<<8)+C2+32)/64┘ when the interpolated result is not to be compatible with an sRGB colour space and the colour endpoint values are LDR values; (2) P=└((C2<<8)+128·64+32)/64┘ when the interpolated result is to be compatible with an sRGB colour space and the colour endpoint values are LDR values; and (3) P=(C2+2)>>2 when the colour endpoint values are HDR values.
Rendering systems that can use combinations of rasterization rendering processes and ray tracing rendering processes are disclosed. In some implementations, these systems perform a rasterization pass to identify visible surfaces of pixels in an image. Some implementations may begin shading processes for visible surfaces, before the geometry is entirely processed, in which rays are emitted. Rays can be culled at various points during processing, based on determining whether the surface from which the ray was emitted is still visible. Rendering systems may implement rendering effects as disclosed.
G06F 9/44 - Dispositions pour exécuter des programmes spécifiques
G09G 5/36 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation caractérisés par l'affichage de dessins graphiques individuels en utilisant une mémoire à mappage binaire
A method performed by a graphics processor obtains a starting bounding volume hierarchy (BVH), being a data structure comprising nodes representing different 3D regions of space in a modelled environment, the data structure comprising a tree in which the nodes are arranged hierarchically from a root node down to a plurality of leaf nodes, wherein the region modelled by each leaf node encompasses at least one primitive or part of a primitive. The method further comprises performing one or more iterations, starting with a first iteration which starts with the starting BVH as a current BVH, which search for candidate reinsertions to move input nodes to new parents in the tree to reduce expected computational cost.
An error detection circuit and a method for performing a cyclic redundancy check on a clock gated register signal are disclosed. The error detection circuit comprising a first register, a check bit processing logic and an error detection module. The first register is a clock gated register configured to be updated with a data signal (x) in response to a clock enabling signal. The check bit processing logic configured to, in response to a control signal, update a second register with a check bit, wherein the control signal (b) is the same as the clock enabling signal. The error detection module configured for calculating an indication bit based on at least the output of the first register and the output of the second register.
An error detection circuit and method for performing cyclic redundancy check on a clock gated register signal is disclosed. The error detection circuit comprise a first register, a second register, a third register and an error detection module. The first register is a clock gated register and is configured to be updated with a data signal (x) in response to a clock enabling signal. The second register is configured to be updated with a check bit (c) based on the data signal (x). The check bit is calculated by a check bit calculation unit. The third register is configured to be updated with a current value (b) of the clock enabling signal. The error detection module is configured for calculating an indication bit (I) based on at least the output of the first register, the output of the second register and the output of the third register.
Methods and apparatus for merging tasks in a graphics pipeline in which, subsequent to a trigger to flush a tag buffer, one or more tasks from the flushed tag buffer are generated, each task comprising a reference to a program and plurality of fragments on which the program is to be executed, wherein a fragment is an element of a primitive at a sample position. It is then determined whether merging criteria are satisfied and if satisfied, one or more fragments from a next tag buffer flush are added to a last task of the one or more tasks generated from the flushed tag buffer.
A method of filtering a target pixel in an image forms, for a kernel of pixels comprising the target pixel and its neighbouring pixels, a data model to model pixel values within the kernel; calculates a weight for each pixel of the kernel comprising: (i) a geometric term dependent on a difference in position between that pixel and the target pixel; and (ii) a data term dependent on a difference between a pixel value of that pixel and its predicted pixel value according to the data model; and uses the calculated weights to form a filtered pixel value for the target pixel, e.g. by updating the data model with a weighted regression analysis technique using the calculated weights for the pixels of the kernel; and evaluating the updated data model at the target pixel position so as to form the filtered pixel value for the target pixel.
A multicore graphics processing unit (GPU) and a method of operating a GPU are provided. The GPU comprises at least a first core and a second core. At least one of the cores in the multicore GPU comprises a master unit configured to distribute geometry processing tasks between at least the first core and the second core.
A set of image rendering tasks and state information are distributed in a graphics processing unit (GPU) having a plurality of cores. A first master unit in one of the cores receives the set of image rendering tasks and the state information, and stores the state information in a memory. The first master unit splits the set of image rendering tasks into a first subset of tasks and a second subset of tasks, wherein the first subset of tasks is assigned to the first core, and the second subset of tasks is assigned to the second core. At least a first portion of the state information is transmitted to the first core, and at least a second portion of the state information is transmitted to the second core. The first subset of tasks is transmitted to the first core, and the second subset of tasks is transmitted to the second core.
G06T 1/20 - Architectures de processeurs; Configuration de processeurs p.ex. configuration en pipeline
G06F 9/48 - Lancement de programmes; Commutation de programmes, p.ex. par interruption
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p.ex. plusieurs processeurs de données à instruction unique
83.
HIERARCHICAL TILING IN A GRAPHICS PROCESSING SYSTEM USING CHAIN SORTING OF PRIMITIVES
Tiling engines and methods for hierarchically tiling a plurality of primitives. A chain of sorting units includes a top level sorting unit followed by lower level sorting units, the top level sorting unit determining which of a plurality of regions of a render space each of the plurality of primitives at least partially falls within. For each such region an identifier of that primitive is stored in a queue. Each of the lower level sorting units selects queues of a preceding sorting unit in the chain to process, and determines which of a plurality of sub-regions of the region associated with that queue each of the primitives at least partially falls within. For each such sub-region an identifier of that primitive is stored in a queue of the lower level sorting unit that is associated with that sub-region. An output unit outputs the primitives identified in the queues of the last lower level sorting unit in the chain on a queue by queue basis.
A hardware representation of a fixed logic circuit is derived for performing multiplication of an input x by a constant rational p/q so as to calculate an output y according to a directed rounding or round-to-nearest rounding mode, where p, q are coprime integers, and x is an m-bit input. An infinite CSD expansion of the rational p/q is determined, a truncated summation array of the bits of the CSD expansion of the rational p/q operating on the bits of the input x is formed by discarding at least the kth column of the array below the position of the binary point, where k=└ ln2(mq)┘+1; further truncating the truncated summation array whilst ensuring that
A hardware representation of a fixed logic circuit is derived for performing multiplication of an input x by a constant rational p/q so as to calculate an output y according to a directed rounding or round-to-nearest rounding mode, where p, q are coprime integers, and x is an m-bit input. An infinite CSD expansion of the rational p/q is determined, a truncated summation array of the bits of the CSD expansion of the rational p/q operating on the bits of the input x is formed by discarding at least the kth column of the array below the position of the binary point, where k=└ ln2(mq)┘+1; further truncating the truncated summation array whilst ensuring that
Δ
high
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Δ
low
<
1
q
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A hardware representation of a fixed logic circuit is derived for performing multiplication of an input x by a constant rational p/q so as to calculate an output y according to a directed rounding or round-to-nearest rounding mode, where p, q are coprime integers, and x is an m-bit input. An infinite CSD expansion of the rational p/q is determined, a truncated summation array of the bits of the CSD expansion of the rational p/q operating on the bits of the input x is formed by discarding at least the kth column of the array below the position of the binary point, where k=└ ln2(mq)┘+1; further truncating the truncated summation array whilst ensuring that
Δ
high
-
Δ
low
<
1
q
,
where, for all x, Δhigh is the maximum sum of the partial products discarded from the array and Δlow is the minimum sum of the partial products discarded from the array; determining a corrective constant z in dependence on the rounding mode and the set of partial products discarded from the array such that the output y is correct for all x; and generating a hardware representation of a fixed logic circuit implementing the truncated summation array including the corrective constant z.
G06F 7/57 - Unités arithmétiques et logiques [UAL], c. à d. dispositions ou dispositifs pour accomplir plusieurs des opérations couvertes par les groupes ou pour accomplir des opérations logiques
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
85.
Anisotropic Texture Filtering for Sampling Points in Screen Space
Texture filtering in computer graphics calculates first and second pairs of texture-space basis vectors that correspond to first and second pairs of screen-space basis vectors transformed to texture space under a local approximation of a mapping between screen space and texture space. Based on differences in magnitudes of the vectors of the pairs of texture-space basis vectors, an angular displacement is determined between a selected pair of the first and second pairs of screen-space basis vectors and screen-space principal axes of the local approximation of the mapping that indicate maximum and minimum scale factors of the mapping. The determined angular displacement and the selected pair of screen-space basis vectors are used to generate texture-space principal axes, with a major axis associated with the maximum scale factor of the mapping and a minor axis associated with the minimum scale factor of the mapping. A texture is filtered using the major and minor axes.
A method of scheduling tasks within a GPU or other highly parallel processing unit is described which is both age-aware and wakeup event driven. Tasks which are received are added to an age-based task queue. Wakeup event bits for task types, or combinations of task types and data groups, are set in response to completion of a task dependency and these wakeup event bits are used to select an oldest task from the queue that satisfies predefined criteria.
G06F 9/48 - Lancement de programmes; Commutation de programmes, p.ex. par interruption
G06F 1/329 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par planification de tâches
G06F 9/50 - Allocation de ressources, p.ex. de l'unité centrale de traitement [UCT]
87.
Multi-Viewport Transformation Module for use in 3D Rendering System
A transaction processing circuit in a graphics rendering system receives information identifying a particular vertex of a plurality of vertices in a strip, each of which is associated with a viewport, and selects a plurality of viewports for viewport transformation of the particular vertex by selecting relevant vertices from the vertices in the strip based on a provoking vertex, and selecting the plurality of viewports to comprise the viewport associated with that relevant vertex. Viewport transformation instructions are sent to a viewport transformation module to perform a viewport transformation on untransformed coordinate data for the particular vertex for each of the viewports, wherein the one or more viewport transformation instructions comprises a viewport transformation instruction for each of the plurality of viewports, each viewport transformation instruction comprises information identifying the particular vertex and information identifying one of the plurality of viewports.
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
A graphics processing unit (GPU) processes graphics data using a rendering space which is sub-divided into a plurality of tiles. The GPU comprises cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space. The cost indication for a set of tile(s) is suggestive of a cost of processing the set of one or more tiles. The GPU controls a rendering complexity with which primitives are rendered in tiles based on the cost indication for those tiles. This allows tiles to be rendered in a manner that is suitable based on the complexity of the graphics data within the tiles. In turn, this allows the rendering to satisfy constraints such as timing constraints even when the complexity of different tiles may vary significantly within an image.
Systems and method to implement a geometry processing phase of tile-based rendering. The systems include a plurality of parallel geometry pipelines, a plurality of tiling pipelines and a geometry to tiling arbiter situated between the plurality of geometry pipelines and the plurality of tiling pipelines. Each geometry pipeline is configured to generate one or more geometry blocks for each geometry group of a subset of ordered geometry groups; generate a corresponding primitive position block for each geometry block, and compress each geometry blocks to generate a corresponding compressed geometry block. The tiling pipelines are configured to generate, from the primitive position blocks, a list for each tile indicating primitives that fall within the bounds of that tile. The geometry to tiling arbiter is configured to forward the primitive position blocks generated by the plurality of geometry pipelines to the plurality of tiling pipelines in the correct order based on the order of the geometry groups.
A rendering optimisation identifies a draw call within a current render (which may be the first draw call in the render or a subsequent draw call in the render) and analyses a last shader in the series of shaders used by the draw call to determine whether the last shader samples from the one or more buffers at coordinates matching a current fragment location. If this determination is positive, the method further recompiles the last shader to replace an instruction that reads data from one of the one or more buffers at coordinates matching a current fragment location with an instruction that reads from the one or more buffers at coordinates stored in on-chip registers.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
G09G 5/36 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation caractérisés par l'affichage de dessins graphiques individuels en utilisant une mémoire à mappage binaire
A method and system is provided for culling hidden objects in a tile-based graphics system before they are indicated in a display list for a tile. A rendering space is divided into a plurality of regions which may for example be a plurality of tiles or a plurality of areas into which one or more tiles are divided. Depth thresholds for the regions, which are used to identify hidden objects for culling, are updated when an object entirely covers a region and in dependence on a comparison between a depth value for the object and the depth for the region. For example, if the depth threshold is a maximum depth threshold, the depth threshold may be updated if an object entirely covers the tile and the maximum depth value of the object is less than the maximum depth threshold.
Conservative rasterization hardware comprises hardware logic arranged to perform an edge test calculation for each edge of a primitive and for each corner of each pixel in a microtile. Outer coverage results are determined, for a particular pixel and edge, by combining the edge test results for the four corners of the pixel and the particular edge in an OR gate. Inner coverage results are determined, for a particular pixel and edge, by combining the edge test results for the four corners of the pixel and the particular edge in an AND gate. An overall outer coverage result for the pixel and the primitive is calculated by combining the outer coverage results for the pixel and each of the edges of the primitive in an AND gate. The overall inner coverage result for the pixel is calculated in a similar manner.
Aspects include a multistage collector to receive outputs from plural processing elements. Processing elements may comprise (each or collectively) a plurality of clusters, with one or more ALUs that may perform SIMD operations on a data vector and produce outputs according to the instruction stream being used to configure the ALU(s). The multistage collector includes substituent components each with at least one input queue, a memory, a packing unit, and an output queue; these components can be sized to process groups of input elements of a given size, and can have multiple input queues and a single output queue. Some components couple to receive outputs from the ALUs and others receive outputs from other components. Ultimately, the multistage collector can output groupings of input elements. Each grouping of elements (e.g., at input queues, or stored in the memories of component) can be formed based on matching of index elements.
Methods and parallel processing units for avoiding inter-pipeline data hazards identified at compile time. For each identified inter-pipeline data hazard the primary instruction and secondary instruction(s) thereof are identified as such and are linked by a counter which is used to track that inter-pipeline data hazard. When a primary instruction is output by the instruction decoder for execution the value of the counter associated therewith is adjusted to indicate that there is hazard related to the primary instruction, and when primary instruction has been resolved by one of multiple parallel processing pipelines the value of the counter associated therewith is adjusted to indicate that the hazard related to the primary instruction has been resolved. When a secondary instruction is output by the decoder for execution, the secondary instruction is stalled in a queue associated with the appropriate instruction pipeline if at least one counter associated with the primary instructions from which it depends indicates that there is a hazard related to the primary instruction.
Graphics processing renders primitives using a rendering space which is subdivided into a plurality of regions. A geometry processing phase determines, for each of a plurality of primitives which are present in a region, whether the primitive totally covers the region and stores data for the primitives which are determined to totally cover the region to indicate total coverage of the region. A rendering phase retrieves the stored data for the primitives which are present in the region, selectively processes primitives which are present in the region based on the retrieved data to determine which sample points within the region are covered by the primitives, wherein if the retrieved data includes data which indicates total coverage of the region for a particular primitive then the processing determining sample points is skipped; and determines rendered values at the sample points within the region based on the primitives which cover the respective sample points.
A system and method for coherency gathering for rays in a ray tracing system. The ray tracing system uses a hierarchical acceleration structure comprising a plurality of nodes including upper level nodes and lower level nodes. For each instance where one of the lower level nodes is a child of one of the upper level nodes, an instance transform is defined, specifying the relationship between a first coordinate system of the upper level node and the second coordinate system for that instance of the lower level node. The system provides an instance transform cache for storing a plurality of these instance transforms while conducting intersection testing.
A data processing device for detecting motion in a sequence of frames each comprising one or more blocks of pixels, includes a sampling unit configured to determine image characteristics at a set of sample points of a block, a feature generation unit configured to form a current feature for the block, the current feature having a plurality of values derived from the sample points, and motion detection logic configured to generate a motion output for a block by comparing the current feature for the block to a learned feature representing historical feature values for the block.
A tessellation method uses vertex tessellation factors. For a quad patch, the method involves comparing the vertex tessellation factors for each vertex of the quad patch to a threshold value and if none exceed the threshold, the quad is sub-divided into two or four triangles. If at least one of the four vertex tessellation factors exceeds the threshold, a recursive or iterative method is used which considers each vertex of the quad patch and determines how to further tessellate the patch dependent upon the value of the vertex tessellation factor of the selected vertex or dependent upon values of the vertex tessellation factors of the selected vertex and a neighbor vertex. A similar method is described for a triangle patch.
A method of performing dot product of an array of ‘2k’ floating point numbers comprising two sets of k floating-point numbers ai and bi is disclosed. The method includes receiving both sets of ‘k’ floating point numbers and multiplying each floating point number ai with a floating point number bi to generate k product numbers (zi), each product number (zi) having a mantissa bit length of ‘r’ bits. The method further comprises creating a set of ‘k’ numbers (yi) based on the k product numbers (zi), the numbers (yi) having a bit-length of ‘n’ bits. Further the method includes identifying a maximum exponent sum (emax) among k exponent sums (eabi) of each pair of floating point numbers ai and bi, aligning the magnitude bits of the numbers (yi) based on the maximum exponent sum (emax) and adding the set of ‘k’ numbers concurrently to obtain the dot product.
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p.ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
100.
METHOD AND SYSTEM FOR PROCESSING FLOATING POINT NUMBERS
A method of performing dot product of an array of ‘2k’ floating point numbers comprising two sets of k floating-point numbers ai and bi is disclosed. The method includes receiving both sets of ‘k’ floating point numbers and multiplying each floating point number ai with a floating point number bi to generate k product numbers (zi), each product number (zi) having a mantissa bit length of ‘r+log (k−1)+1’ bits. The method further comprises creating a set of ‘k’ numbers (yi) based on the k product numbers (zi), the numbers (yi) having a bit-length of ‘n’ bits. Further the method includes identifying a maximum exponent sum (emax) among k exponent sums (eabi) of each pair of floating point numbers ai and bi aligning the magnitude bits of the numbers (yi) based on the maximum exponent sum (emax) and adding the set of ‘k’ numbers concurrently to obtain the dot product.
