Abrégé

The present disclosure provides an SOT-MRAM memory cell, comprising: a bottom electrode; a magnetic tunnel junction layer located on the bottom electrode; an orbital Hall effect layer located on the magnetic tunnel junction layer; a first transistor having a drain connected to the orbital Hall effect layer; and a second transistor having a drain connected to the bottom electrode. The present disclosure further provides an SOT-MRAM memory, an operation method, and an SOT-MRAM memory array.

Classes IPC  ?

• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
• G11C 11/18 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des dispositifs à effet Hall

Abrégé

The present disclosure relates to the technical field of artificial neuron memory devices, and provides a reconfigurable neuron device based on ion gate regulation and a manufacturing method therefor. The device comprises: a synthetic antiferromagnetic layer, a metal oxide layer, an ionic liquid layer, and a top electrode layer stacked in sequence from bottom to top. The two opposite edges of the bottom end of the synthetic antiferromagnetic layer are provided with a left boundary antiferromagnetic layer and a right boundary antiferromagnetic layer having opposite magnetization directions, and a magnetic tunnel junction for outputting a spike signal is further provided in the middle of the bottom end of the synthetic antiferromagnetic layer. The metal oxide layer, the ionic liquid layer, and the top electrode layer constitute an ion gate, and the ionic liquid layer comprises positive ions and negative ions. When an input voltage is applied to the top electrode layer, oxygen ions in the metal oxide layer move along with the distribution of the positive ions and the negative ions in the ionic liquid layer to adjust the charge accumulation of a top interface of the synthetic antiferromagnetic layer, so as to regulate the leakage motion speed of a magnetic domain wall at the bottom of the synthetic antiferromagnetic layer by means of an RKKY action.

Classes IPC  ?

• H01L 43/00 - Dispositifs utilisant les effets galvanomagnétiques ou des effets magnétiques analogues; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives
• H01L 43/08 - Résistances commandées par un champ magnétique
• H01L 43/12 - Procédés ou appareils spécialement adaptés à la fabrication ou le traitement de ces dispositifs ou de leurs parties constitutives
• G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques

Abrégé

The present invention provides a three-dimensional reservoir based on a volatile three-dimensional memristor and a manufacturing method therefor. A storage layer, a selection layer and an electrode layer in each through hole in a three-dimensional reservoir form a memristor, i.e., form a reservoir unit, and a three-dimensional reservoir based on a volatile three-dimensional memristor is formed based on a stack structure and a plurality of through holes. Specifically, in the present invention, virtual nodes generated on the basis of the dynamic characteristics of a three-dimensional memristor are used to construct a three-dimensional reservoir. First, an interfacial memristor is constructed and the volatile characteristics thereof are confirmed by means of electrical tests; a vertical three-dimensional array is prepared on the basis of the volatile memristor, and the dynamic characteristics of the device are adjusted by means of a Schottky barrier, different layers of the three-dimensional reservoir respectively corresponding to reservoirs of different layers. Different reservoirs are constructed by respectively regulating devices of different layers, thereby increasing the richness of the virtual nodes, improving the parallelism and the recognition accuracy of a system, and reducing the area of the system.

Classes IPC  ?

• H01L 27/24 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants à l'état solide pour le redressement, l'amplification ou la commutation, sans barrière de potentiel ni barrière de surface

Abrégé

The present invention provides a photolithography device, a gas bath apparatus and a gas bath generator thereof. The gas bath generator comprises a closed annular body. The closed annular body is arranged around a working area. An annular flow channel is formed in the closed annular body. The closed annular body is further provided with circumferentially distributed gas outlets in communication with the annular flow channel. By means of the gas outlets, a closed airflow layer distributed around the working area is generated. The gas bath generator provided by the present invention can be used for a photolithography device and circumferentially arranged around an exposure area of the photolithography device to form a closed airflow layer isolating the exposure area from the outside around the periphery of the exposure area. The present invention solves the problem of how to reduce gas contamination and particle contamination in the silicon wafer microenvironment located in the exposure area of the photolithography device.

Classes IPC  ?

• G03F 7/20 - Exposition; Appareillages à cet effet

Abrégé

A hardware implementation method and apparatus for a reservoir computing model based on a random resistor array, and an electronic device, which relate to the fields of machine learning and artificial intelligence. The method comprises: acquiring a random weight of a reservoir layer, which is generated on the basis of a resistance-variable device crossbar array; applying a breakdown voltage to the resistance-variable device crossbar array, so as to form a randomly distributed random resistance matrix; converting an input signal into a read voltage signal by means of a circuit of a printed circuit board, and performing, on the basis of the read voltage signal and the random resistance matrix, vector matrix multiplication to determine an output voltage signal; and repeating the step of converting an input signal into a read voltage signal by means of the circuit of the printed circuit board and performing, on the basis of the read voltage signal and the random resistance matrix, vector matrix multiplication to determine an output voltage signal, and then simulating a loop iteration process of the reservoir layer. Therefore, the efficient hardware realization of a large-scale random weight and a reservoir computing model is achieved, and in an edge computing application scenario in which the computing power is limited, the possibility is provided for the efficient hardware realization of the reservoir computing model.

Classes IPC  ?

• G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques

Abrégé

The present invention belongs to the technical field of artificial intelligence, and particularly relates to a method for preparing a reservoir element. The method comprises the following steps: a) sequentially arranging, on a substrate, a bottom electrode layer, a dielectric layer, a resistive layer and a top electrode layer, so as to obtain a reservoir element to be annealed; and b) performing annealing processing on the reservoir element to be annealed, so as to obtain a reservoir element, wherein the temperature of the annealing processing ranges from 300ºC to 700ºC, and the time of the annealing processing ranges from 30s to 100s. In the method provided in the present invention, after being prepared, the reservoir element is subjected to rapid annealing processing, such that defects are re-distributed after rapid annealing, thereby forming a more stable membrane; and a ferroelectric O phase can also be introduced into the membrane. By means of rapid annealing processing, the power consumption of a reservoir element can be effectively reduced, and the computing accuracy can be improved.

Classes IPC  ?

• H01L 45/00 - Dispositifs à l'état solide spécialement adaptés pour le redressement, l'amplification, la production d'oscillations ou la commutation, sans barrière de potentiel ni barrière de surface, p.ex. triodes diélectriques; Dispositifs à effet Ovshinsky; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives

Abrégé

Provided in the embodiments of the present application are a semiconductor device and a manufacturing method therefor. The semiconductor device comprises a substrate, a first electrode layer, a functional layer and a second electrode layer, wherein the functional layer is located between the first electrode layer and the second electrode layer, the functional layer comprises a first area, and a second area which surrounds the first area and is of a U-shaped structure, and the orientation of a U-shaped opening of the second area is parallel to the substrate and faces away from the first area, that is, the U-shaped opening faces an outer side; the material of the first area at least comprises germanium; and the second area comprises a U-shaped ferroelectric layer and a U-shaped gate electrode which are sequentially stacked. In the embodiments of the present application, a ferroelectric layer of a U-shaped structure is used as a storage layer of a memory device, and when a gate voltage is kept unchanged, a U-shaped channel can increase an electric field of the ferroelectric layer, thereby increasing a storage window of the whole semiconductor device; and when the storage window of the whole semiconductor device is kept unchanged, the gate voltage can be reduced, thereby reducing the power consumption of the semiconductor device, and improving the performance of the memory device.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

The present application provides a semiconductor device and a manufacturing method therefor. The method comprises: providing a substrate, wherein the substrate is provided with a first source-drain layer, a channel layer and a second source-drain layer that are sequentially stacked, and the periphery of the channel layer is provided with a gate dielectric layer and a gate structure which surround the channel layer in the horizontal direction; forming a spacer layer on the outer side wall of the gate structure; etching the gate structure, so as to reduce the thickness of the gate structure; forming a sacrificial structure covering the gate structure, and a covering layer covering the second source-drain layer, the sacrificial structure and the spacer layer, so that the sacrificial structure is located on the periphery of the second source-drain layer and located on the inner side of the spacer layer; then etching the covering layer to obtain a first contact hole passing through the sacrificial structure, and removing the sacrificial structure at the bottom of the first contact hole to form a gap below the first contact hole; and forming first contact structures in the first contact hole and the gap, thereby realizing self-alignment of the bottoms of the first contact structures and the gate structure, and improving the reliability of a device.

Classes IPC  ?

• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

Disclosed are a nanowire/sheet device and a manufacturing method therefor, and electronic equipment comprising the nanowire/sheet device. According to embodiments, the nanowire/sheet device comprises: a substrate; a nanowire/sheet spaced apart from the surface of the substrate and extending in a first direction; a source/drain layer located at two opposite ends of the nanowire/sheet in the first direction and connected to the nanowire/sheet; a gate stack extending in a second direction intersecting the first direction to surround the nanowires/sheet; and a first side wall disposed on a sidewall of the gate stack, wherein the first side wall comprises a continuously extending material layer having a first portion along the surface of the nanowire/sheet, a second portion along a sidewall of the source/drain layer facing the gate stack, and a third portion along the sidewall of the gate stack facing the source/drain layer, with a slot or interface between the second portion and the third portion.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

Provided in the embodiments of the present application are a semiconductor device and a method for manufacturing same. The method comprises: sequentially forming a first electrode layer, a semiconductor layer and a second electrode layer on a substrate; then etching away part of the semiconductor layer from a side wall of the semiconductor layer to form an opening; then forming a channel layer in the opening and on a side wall of the first electrode layer and a side wall of the second electrode layer, wherein the channel layer comprises a first channel portion located in the opening and a second channel portion other than the first channel portion in the opening; filling the first channel portion with a dummy gate layer; then etching away part of the dummy gate layer from a side wall of the dummy gate layer by taking the second channel portion as a mask; then removing the second channel portion and the first channel portion which is in contact with an upper and a lower surface of the dummy gate layer, so as to form a recess formed by the first electrode layer or the second electrode layer, the channel layer and the dummy gate layer; and filling the recess with a dielectric material to form an isolation side wall, wherein the formed isolation side wall can reduce the parasitic capacitance of a semiconductor device and optimize the performance thereof.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus

Abrégé

Disclosed are a nanowire/sheet component having a crystal sidewall, a manufacturing method therefor, and an electronic device comprising the nanowire/sheet component. According to an embodiment, a nanowire/sheet component may comprise: a substrate; a nanowire/sheet spaced apart from a surface of the substrate and extending along a first direction; a source/drain layer located at two opposite ends of the nanowire/sheet in the first direction and connected to the nanowire/sheet; a gate stack extending along a second direction intersecting the first direction to surround the nanowire/sheet; and a sidewall disposed on a side wall of the gate stack, the sidewall having substantially the same crystal structure as the nanowire/sheet in at least a part of a region adjacent to the nanowire/sheet.

Classes IPC  ?

• H01L 21/336 - Transistors à effet de champ à grille isolée
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

The present invention relates to a vertical MOSFET device and a manufacturing method therefor and the application thereof. The method comprises: forming, on a substrate, a first silicon layer, a first germanium silicon layer, a second germanium silicon layer, a third germanium silicon layer and a second silicon layer which are vertically stacked from bottom to top, wherein the molar content of germanium in the first germanium silicon layer and the molar content of germanium in the third germanium silicon layer are both greater than the content of germanium in the second germanium silicon layer; performing etching to form a nano-stack structure; selectively etching the first germanium silicon layer and the third germanium silicon layer, so as to form a first groove and a third groove; forming inner side walls of extension regions in the first groove and the third groove; selectively etching the second germanium silicon layer, so as to form a gate groove; forming a dummy gate in the gate groove; forming a source electrode and a drain electrode; forming an active region having a shallow trench isolation layer; and removing the dummy gate, so as to form a gate dielectric layer and a gate electrode. The present invention can effectively control the size of a trench, the sizes of inner side walls of extension regions, the size of a gate electrode, etc., and is applicable to nanosheet or nanowire structures.

Classes IPC  ?

• H01L 21/335 - Transistors à effet de champ
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices

Abrégé

A memory device and a manufacturing method therefor, which relate to the technical field of semiconductors. The memory device comprises a substrate; a memory unit array, which is located on the substrate and comprises a plurality of memory units, wherein each memory unit comprises a left laminate and a right laminate, which are arranged at an interval in a horizontal direction, the left laminate and the right laminate each comprise a lower isolation layer, a PMOS layer, a first NMOS layer, an upper isolation layer and a second NMOS layer, which are sequentially arranged on the substrate in a stacked manner, the PMOS layer, the first NMOS layer and the second NMOS layer each comprise a first source/drain layer, a channel layer and a second source/drain layer, which are vertically arranged in a stacked manner, and the channel layer is transversely recessed relative to the first source/drain layer and the second source/drain layer; and grid stacks, which are between the first source/drain layer and the second source/drain layer in a vertical direction, and are arranged on two opposite sides of the channel layer, so as to be embedded into transverse recesses of the channel layer.

Classes IPC  ?

• H01L 27/11 - Structures de mémoires statiques à accès aléatoire
• H01L 21/8244 - Structures de mémoires statiques à accès aléatoire (SRAM)

Abrégé

The invention relates to the technical field of semiconductors. Disclosed are a vertical MOSFET device and a preparation method thereof. The vertical MOSFET device comprises: a substrate; an active region, comprising a first source/drain layer, a channel layer and a second source/drain layer that are sequentially and vertically stacked on the substrate, the periphery of the channel layer being recessed relative to the periphery of the first source/drain layer and the outer periphery of the second source/drain layer; a spacer layer, comprising an upper spacer layer and a lower spacer layer, the upper spacer layer being formed on the lower surface of the second source/drain layer exposed by the recess of the channel layer, the lower spacer layer being formed on the upper surface of the first source/drain layer exposed by the recess of the channel layer, and the upper spacer layer and the lower spacer layer both being in contact with, but not in communication with, a lateral surface of the channel layer; a gate stack, formed at least on the transverse outer periphery of the channel layer and embedded in the groove space between the upper spacer layer and the lower spacer layer.

Classes IPC  ?

• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

The present invention relates to a semiconductor storage unit structure and a preparation method therefor and use thereof, and a semiconductor memory. The semiconductor storage unit structure comprises a substrate, a first transistor layer, an isolation layer and a second transistor layer, wherein the first transistor layer comprises a first stacked structure formed by a first source electrode, a first channel and a first drain electrode which are arranged in a stacked manner from bottom to top, and a first gate electrode located on a side wall of the first stacked structure; and the second transistor layer comprises: a second stacked structure formed by a second drain electrode, a second channel and a second source electrode which are arranged in a stacked manner from bottom to top, and a second gate electrode located on a side wall of the second stacked structure. At least part of the side wall of the second drain electrode is in direct contact with the first gate electrode. The present invention provides a 2T0C-type DRAM unit with an improved structure, has the advantages of vertical stacking integration, a high integration level, low electric leakage, a short refreshing time, etc., and has significant advantages compared with existing 2T0C-type DRAMs.

Classes IPC  ?

• H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
• H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive

Abrégé

A storage device and a method for manufacturing same, and an electronic device comprising a storage device. The storage device comprises a substrate, a storage unit array on the substrate, and a plurality of word lines, which extend in a first direction, on the substrate. The storage unit array comprises a plurality of storage units, which are arranged in rows in the first direction and in columns in a second direction. Each storage unit comprises: an active region, which extends in a third direction, and comprises a vertical stack of a first source/drain layer, a channel layer and a second source/drain layer; and a gate stack, which is located between the first source/drain layer and the second source/drain layer in a vertical direction, and sandwiches the channel layer between at least two opposite sides of the channel layer. First source/drain layers in active regions of each column are continuous, so as to form a bit line, which extends continuously in a zigzag in the second direction. Each word line extends in the first direction, so as to intersect with active regions in a corresponding row, and is electrically connected to the gate stack on two opposite sides of the channel layer of each storage unit.

Classes IPC  ?

• H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire

Abrégé

A memory device, a manufacturing method therefor, and an electronic device comprising the memory device. The memory device may comprise: a substrate; a plurality of word lines on the substrate extending in a first direction; a plurality of bit lines on the substrate extending in a second direction perpendicular to the first direction; and a memory cell array on the substrate comprising a plurality of memory cells electrically connected to corresponding word lines and bit lines, respectively. Each memory cell may comprise: an active region extending in a third direction inclined with respect to the first direction and comprising a vertical stack of a first source/drain layer, a channel layer, and a second source/drain layer; and gate stacks provided between the first source/drain layer and the second source/drain layer in a vertical direction and provided on the opposite sides of the channel layer in a fourth direction orthogonal to the third direction, so as to sandwich the channel layer. A corresponding word line of each memory cell extends across the memory cell in the first direction to be in contact with and electrically connected to the gate stacks on the opposite sides of the memory cell.

Classes IPC  ?

• H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire

Abrégé

The present disclosure provides a memory cell, comprising: a stack layer, stacked on a substrate, and comprising: a plurality of channel holes running through the stack layer and part of the substrate, wherein at least one second laminated material layer in the stack layer after the plurality of channel holes are formed is etched to form an annular limiting structure; a gate dielectric layer, located on the surfaces of the plurality of channel holes which are etched to form the annular limiting structure; a channel layer, located on the surface of the gate dielectric layer; and a resistive layer, located on the surface of the channel layer corresponding to the annular limiting structure. A gate voltage applied to the at least one second laminated material layer and a bit line pulse signal connected to the channel layer are controlled, a resistance state of the resistive layer is changed, and a reading, writing or erasing operation of the memory cell on the resistive layer is implemented. The present disclosure further provides a preparation method for the memory cell, and a three-dimensional memory and an operation method therefor.

Classes IPC  ?

• H01L 27/24 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants à l'état solide pour le redressement, l'amplification ou la commutation, sans barrière de potentiel ni barrière de surface
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS

Abrégé

Disclosed in the present invention is a correction method for a surface plasma photolithographic pattern, comprising: forming multiple test patterns on a test mask, each test pattern at least being represented by a first test parameter and a second test parameter related to the first test parameter; exposing a photoresist layer by using the test mask containing the test patterns to form multiple photoresist patterns, each photoresist pattern at least being represented by a first exposure parameter and a second exposure parameter related to the first exposure parameter; establishing a first data table on the basis of a correspondence between the first test parameters and second test parameters of the test patterns and the first exposure parameters and second exposure parameters of the photoresist patterns; processing the first data table according to the first exposure parameters to obtain a second data table; and correcting second test parameters of multiple design patterns on the basis of the second data table to obtain corrected design patterns, and using the corrected design patterns to manufacture a mask for exposure.

Classes IPC  ?

• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
• G03F 7/20 - Exposition; Appareillages à cet effet

Abrégé

The present invention provides a storage cell, comprising: a channel layer array comprising N channel layers, the N channel layers being vertically provided on a substrate in a first direction, a tunneling layer and a storage layer being sequentially provided outside the N channel layers, and N being a positive integer; N heat conduction cores respectively located in the N channel layers and penetrating through the substrate; and a thermocouple array comprising a thermocouple word line layer growing on the substrate in a negative direction of the first direction and N thermocouple layers located on the thermocouple word line layer, the N thermocouple layers being connected to the N heat conduction cores in a one-to-one correspondence mode. A first potential difference is applied between the thermocouple word line layer and a part of the thermocouple layers in the N thermocouple layers, and the heat conduction core connected to the part of the thermocouple layers is heated, such that the channel layer and the storage layer corresponding to the heat conduction core are respectively kept at a first preset temperature and a second preset temperature under the heat insulation effect of the tunneling layer. The present invention further provides a three-dimensional memory and an operation method therefor.

Classes IPC  ?

• H01L 23/34 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température
• H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
• H01L 27/1157 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
• H01L 27/11556 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H01L 27/11524 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
• G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données

Abrégé

Provided in the embodiments of the present application are a ferroelectric tunnel junction device and a manufacturing method therefor. The ferroelectric tunnel junction device comprises a first electrode, a dielectric layer, a ferroelectric layer and a second electrode, which are sequentially stacked, wherein the thickness of the ferroelectric layer is less than five nanometers. The thickness of the ferroelectric layer is relatively thin, such that a relatively large tunneling current can be provided for the device, and the relatively thin ferroelectric layer can also increase depolarization field strength in the ferroelectric tunnel junction device, accelerate depolarization and reduce a data holding capability, so as to obtain a volatile data storage device. The volatile ferroelectric tunnel junction device can be applied to a reservoir computing network system. A plurality of polarization currents that are collected by the ferroelectric tunnel junction device during a running process are used as virtual nodes of a reservoir computing network system, and data can be input into the plurality of virtual nodes in parallel, that is, the data can be processed in parallel by the reservoir computing network system based on the ferroelectric tunnel junction device, such that the calculation of a neural network model is efficiently performed, and the requirement of the neural network model for efficient training is met.

Classes IPC  ?

• H01L 45/00 - Dispositifs à l'état solide spécialement adaptés pour le redressement, l'amplification, la production d'oscillations ou la commutation, sans barrière de potentiel ni barrière de surface, p.ex. triodes diélectriques; Dispositifs à effet Ovshinsky; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives

Abrégé

Provided is a photoetching quality optimization method, comprising: determining, on the basis of a characteristic matrix method and the Bloch's theorem, a stray item of a wave function introduced from the roughness of the surface of a metal film layer (S101); inputting the stray item of the wave function into a photoetching quality deviation mathematical model for calculation simulation, thereby obtaining an effect analysis curve of the roughness of the metal film layer on the photoetching quality, the effect analysis curve representing an effect result of the roughness of the metal film layer on the photoetching quality (S102); and according to the effect result, reducing the roughness of the surface of the metal film layer and/or providing a metal-dielectric multilayer film structure between a mask above a metal-dielectric unit and air so as to optimize the photoetching quality of the metal-dielectric unit (S103). Provided are a photoetching quality optimization apparatus (1400), an electronic device (1500), a computer-readable storage medium, and a computer program product.

Classes IPC  ?

• G06F 30/23 - Optimisation, vérification ou simulation de l’objet conçu utilisant les méthodes des éléments finis [MEF] ou les méthodes à différences finies [MDF]
• G06F 17/16 - Calcul de matrice ou de vecteur
• G03F 7/20 - Exposition; Appareillages à cet effet

Abrégé

A mask parameter optimization method, comprising: acquiring a test pattern, a light source parameter, and an initial mask parameter, wherein the initial mask parameter comprises a mask thickness and an initial mask side wall angle; generating a plurality of candidate mask parameters according to the initial mask side wall angle in the initial mask parameter, the plurality of candidate mask parameters comprising different mask side wall angles and the same mask thickness; obtaining an imaging contrast ratio of each candidate mask parameter on the basis of the test pattern and the light source parameter; and selecting an optimal mask side wall angle from the plurality of candidate mask parameters according to the imaging contrast ratio. By optimizing the mask parameter of a multilayer film lens structure, the imaging contrast ratio is significantly improved, and the imaging resolution is improved.

Classes IPC  ?

• G03F 1/00 - Originaux pour la production par voie photomécanique de surfaces texturées, p.ex. masques, photomasques ou réticules; Masques vierges ou pellicules à cet effet; Réceptacles spécialement adaptés à ces originaux; Leur préparation
• G03F 1/70 - Adaptation du tracé ou de la conception de base du masque aux exigences du procédé lithographique, p.ex. correction par deuxième itération d'un motif de masque pour l'imagerie
• G03F 7/20 - Exposition; Appareillages à cet effet

Abrégé

An analytic method and device for quantitatively calculating line edge roughness in a plasma ultra-diffraction photoetching process, related to the field of semiconductor manufacturing. The method comprises: determining a theoretical point spread function of a light source on the basis of field intensity distribution data of the light source at an opening of a focusing element in plasma ultra-diffraction photoetching (101); determining a plurality of transverse point width values of a point mapping graph on the basis of the point mapping graph (102); respectively determining an actual point spread function corresponding to the plurality of transverse point width values on the basis of the theoretical point spread function and the plurality of transverse point width values (103); determining an actual line spread function of a line graph on the basis of an attenuation constant and the actual point spread function (104); and determining a line edge roughness theoretical analysis formula of the plasma ultra-diffraction photoetching on the basis of a line edge roughness change value, the exposure dose of the line graph, the near-field photoresist contrast, and the graph logarithmic slope relationship of the line graph (109). The analysis method greatly improves the actual applicability of the surface plasma ultra-diffraction photoetching technology.

Classes IPC  ?

• G03F 7/20 - Exposition; Appareillages à cet effet

Abrégé

Embodiments of the present application provide a fabrication method for a semiconductor device. A photolithographic coating is formed on a structure to be led out. The photolithographic coating comprises a first film layer, a photolithographic film layer and a second film layer. The refractive indexes of the first film layer and the second film layer are both smaller than 1, so that the photolithographic coating forms an optical structure having a relatively high reflection coefficient. The photolithographic coating is exposed by using light of a target wavelength and a mask. The structure is reflected by the photolithographic coating. The structure is used as a mask for imaging to the photolithographic film layer; meanwhile, the pattern of the mask is also imaged to the photolithographic film layer. That is, the patterns of the structure and the mask are both imaged to a target region of the photolithographic film layer, and the target region corresponds to the structure, which achieves the self-alignment of a pattern layer of the structure and a pattern layer in which a contact hole is located. The target region only corresponds to the structure in an overlapping region in which the patterns of the structure and the mask are simultaneously imaged on the photolithographic film layer during one exposure process, which may improve the alignment accuracy between different pattern layers and reduce alignment errors.

Classes IPC  ?

• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou

Abrégé

Embodiments of the present application provide a manufacturing method for a semiconductor device. A photoetching coating is formed on a structure to be led out, the photoetching coating comprises a first film layer, a photoetching film layer and a second film layer, and the refractive indexes of the first film layer and the second film layer are both smaller than 1, so that the photoetching coating forms an optical structure having a relatively high reflection coefficient; the photoetching coating is exposed by utilizing light having a first wavelength, and the structure to be led out is reflected by the photoetching coating; the structure to be led out is used as a mask for imaging to a first area of the photoetching film layer, the photoetching coating is exposed by using light having a second wavelength and the mask, and the pattern of the mask is imaged to a second area of the photoetching film layer, wherein an overlapping area of the first area and the second area is a leading-out area, and the leading-out area corresponds to the structure to be led out. Self-alignment of the layer of the structure to be led out and the layer where a contact hole is located is achieved, and only the overlapping area of imaging on the photoetching film layer in two exposures can correspond to the structure to be led out, so that the alignment precision between different layers can be improved, and alignment errors are reduced.

Classes IPC  ?

• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
• H01L 21/311 - Gravure des couches isolantes
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

An optical method and apparatus for quickly realizing precise calibration of a lithography system, which relate to the field of optics. The optical method for quickly realizing precise calibration of a lithography system comprises: determining a spot width fitting relationship between spot light sources on the basis of field intensity distribution data of the spot light sources at an opening of a focusing element (101); on the basis of the spot width fitting relationship between the spot light sources, determining first correlations between spot widths of the spot light sources and exposure parameters of a photoresist under an optical microscope (102); determining first spot width data sets of the spot light sources on the basis of an optical microscopic image of a spot mapping pattern on a surface of the photoresist (103); on the basis of the first spot width data sets of the spot light sources, determining second correlations between the spot widths of the spot light sources and the exposure parameters of the photoresist (104); and when the first correlations and the second correlations meet a preset condition, determining the exposure parameters of the photoresist by using the first correlations (105). By means of the optical method, exposure parameters can be quickly acquired, and can be measured in a timely manner.

Classes IPC  ?

• G03F 7/20 - Exposition; Appareillages à cet effet

Abrégé

A spintronic device, a storage unit, a storage array, and a read-write circuit, applied to the technical field of integration. The spintronic device comprises: bottom electrodes (101, 104); a spin-orbit coupling layer (102) provided on the bottom electrodes (101, 104); at least one pair of magnetic tunnel junctions (103) provided on the spin-orbit coupling layer (102), each of the magnetic tunnel junctions (103) comprising a free layer (1031), a tunneling layer (1032), and a reference layer (1033) that are successively arranged from bottom to top, and the reference layers (1033) of two magnetic tunnel junctions in each pair of magnetic tunnel junctions (103) being opposite in magnetization direction; and a top electrode (1034) provided on the reference layer (1033) of each of the magnetic tunnel junctions (103).

Classes IPC  ?

• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
• H01L 43/08 - Résistances commandées par un champ magnétique

Abrégé

A correction method for an electron beam proximity effect, comprising first setting an electron beam initial dose for each exposure grid region to calculate a proximity effect energy value that affects the energy distribution of the current exposure grid region when all exposure grid regions other than the current exposure grid region are exposed; calculating an electron beam correction dose of the current exposure grid region; and successively calculating the electron beam correction dose of each exposure grid region in the electron beam exposure layout matrix. Afterward, an iterative calculation is performed T times, and the final electron beam correction dose of each exposure grid region can be obtained. The central exposure energy value of the current exposure grid region and the proximity effect energy value of the current exposure grid region when exposing surrounding exposure grid regions are differentiated, which is convenient for directly solving the incident dose of the current exposure grid region and the amount of calculation is reduced. Furthermore, within a small number of instances of optimization iterative calculations, the incident dose of an electron beam having ideal precision can be obtained. Also disclosed is a correction device for an electron beam proximity effect.

Classes IPC  ?

• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
• G03F 7/20 - Exposition; Appareillages à cet effet

Abrégé

Disclosed are a semiconductor device having a double-gate structure and a manufacturing method therefor, and an electronic apparatus comprising the semiconductor device. According to an embodiment, a semiconductor device comprises a vertical channel portion on a substrate; source/drain portions at the upper and lower ends of the channel portion with respect to the substrate, respectively; and a first gate stack on a first side of the channel portion in a first direction transverse to the substrate and a second gate stack on a second side of the channel portion opposite to the first side in the first direction. The distance between at least one of the upper edge and the lower edge of the end of the first gate stack close to the channel portion in the vertical direction and the corresponding source/drain portion is less than the distance between at least one edge, corresponding to the aforementioned at least one edge, among the upper edge and the lower edge of the end of the second gate stack close to the channel portion in the vertical direction and the corresponding source/drain.

Classes IPC  ?

• H01L 29/786 - Transistors à couche mince
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

A NOR type memory and an electronic device comprising the NOR type memory are disclosed. According to an embodiment, the NOR type memory may comprise a NOR cell array and a peripheral circuit. The NOR cell array may comprise: a first substrate; an array of memory cells on the first substrate, each memory cell comprising a first gate stack extending vertically relative to the first substrate, and an active region surrounding an outer periphery of the first gate stack; a first bond pad electrically connected to the first gate stack; and a second bond pad electrically connected to the active region of the memory cell. The peripheral circuit may comprise: a second substrate; a peripheral circuit element on the second substrate; and a third bond pad, at least a portion of the third bond pad being electrically connected to the peripheral circuit element. The NOR cell array and the peripheral circuit are arranged such that at least some of the first bond pads and the second bond pads are opposite at least some of the third bond pads.

Classes IPC  ?

• H01L 27/11575 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région limite entre la région noyau et la région de circuit périphérique
• H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
• H01L 27/11573 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région de circuit périphérique

Abrégé

Disclosed are a NOR type memory device and a manufacturing method therefor, and an electronic device comprising the NOR type memory device. According to an embodiment, the NOR type memory device may comprise: a memory device layer, which comprises a first source/drain region, a second source/drain region, and a first channel region between the first source/drain region and the second source/drain region; a first gate stack, which extends vertically to pass through the memory device layer, and comprises a first gate conductor layer and a storage functional layer disposed between the first gate conductor layer and the memory device layer, and defines a memory cell at an intersection between the first gate stack and the memory device layer; a selection device layer on the memory device layer, the selection device layer comprising a third source/drain region, a fourth source/drain region, and a second channel region between the third source/drain region and the fourth source/drain region; a second gate stack, which is disposed over the first gate stack and extends vertically to pass through the selection device layer; and a connecting portion, which electrically connects the third source/drain region to the first gate conductor layer.

Classes IPC  ?

• H01L 27/11575 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région limite entre la région noyau et la région de circuit périphérique
• H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
• H01L 27/11573 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région de circuit périphérique

Abrégé

Disclosed are a NOR type memory device and a manufacturing method therefor, and an electronic device comprising the NOR type memory device. According to an embodiment, the NOR type memory device may comprise a first gate stack, which extends vertically on a substrate, and comprises a gate conductor layer and a storage functional layer; and a first semiconductor layer, which extends around an outer periphery of the first gate stack and along a sidewall of the first gate stack. The storage functional layer is disposed between the first semiconductor layer and the gate conductor layer. The first semiconductor layer comprises a first source/drain region, a first channel region and a second source/drain region which are sequentially disposed in a vertical direction. A memory cell is defined at an intersection between the first gate stack and the first semiconductor layer. The NOR type memory device further comprises a conductive shielding layer surrounding an outer periphery of the first channel region of the first semiconductor layer, and a dielectric layer between the first channel region of the first semiconductor layer and the conductive shielding layer.

Classes IPC  ?

• H01L 27/11565 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la configuration vue du dessus

Abrégé

Provided in the present disclosure are a quantiser for use in a ∑-Δ modulator, a ∑-Δ modulator, and a noise shaping method. The quantiser comprises: an integrator, used for producing a quantisation signal of a K-th period in a K-th sampling period according to an internal signal, a quantisation signal of a K-1-th period, a filtered quantisation signal in the K-1-th period, and a filtered quantisation signal in a K-2-th period, wherein K is a positive integer greater than 1; an integrating capacitor, used for storing the quantisation signal of the K-th period and weighting the internal signal in a K+1-th sampling period; a passive low-pass filter, used for collecting quantisation signals of a K-th period in a K-th discharge period, producing a filtered quantisation signal on the basis of same, and feeding back the filtered quantisation signal to the integrator in the K+1-th sampling period and a K+2-th sampling period; and a comparator, used for quantising the quantisation signal of the K-th period in the K-th discharge period in order to output a digital code.

Classes IPC  ?

• H03M 3/00 - Conversion de valeurs analogiques en, ou à partir d'une modulation différentielle

Abrégé

12121212121212122).

Classes IPC  ?

• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 21/8234 - Technologie MIS

Abrégé

Provided in the present disclosure is a memristor, comprising a transistor and a resistive random access memory, wherein a drain of the transistor is connected to a bottom electrode of the resistive random access memory; and the resistive random access memory comprises: the bottom electrode, a resistive random material layer, a current limiting layer and a top electrode from bottom to top, wherein the current limiting layer stabilizes the fluctuation of a low resistance by means of reducing a surge current and optimizing a heat distribution, thereby improving the precision of calculating a Hamming distance.

Classes IPC  ?

• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou

Abrégé

The present disclosure relates to a data recovery method used for a flash memory, comprising: reading data from a flash memory by using a preset read voltage; calculating a check node error rate corresponding to the data; calculating a read voltage adjustment step according to the check node error rate; adjusting the preset read voltage according to the read voltage adjustment step, reading the data from the flash memory by using the adjusted preset read voltage, and repeating from the operation of calculating the check node error rate corresponding to the data to the operation of adjusting the preset read voltage according to the read voltage adjustment step, until the check node error rate is minimal; and selecting a read voltage corresponding to the minimum check node error rate to read the data from the flash memory so as to perform data recovery. In the method, the read voltage adjustment step can be dynamically adjusted so as to reduce the time required for optimal read voltage searching in a reread error correcting algorithm, and reduce unnecessary ECC decoding, thereby reducing the time required for data recovery.

Classes IPC  ?

• G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11

Abrégé

An activation function generator based on a magnetic domain wall driving type magnetic tunnel junction, and a preparation method therefor. The activation function generator comprises: a spin-orbit coupling layer, which is configured to generate a spin-orbit torque; a ferromagnetic free layer, which is formed on the spin-orbit coupling layer, and is configured to provide a magnetic domain wall motion orbit; a non-magnetic barrier layer, which is formed on the ferromagnetic free layer; a ferromagnetic reference layer, which is formed on the non-magnetic barrier layer; a top electrode, which is formed on the ferromagnetic reference layer; an antiferromagnetic pinning layer, which is formed on two ends of the ferromagnetic free layer; and a left electrode and a right electrode, which are respectively formed at two positions on the antiferromagnetic pinning layer.

Classes IPC  ?

• G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
• H01L 43/00 - Dispositifs utilisant les effets galvanomagnétiques ou des effets magnétiques analogues; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives
• H01L 43/02 - Dispositifs utilisant les effets galvanomagnétiques ou des effets magnétiques analogues; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails

Abrégé

Disclosed are an NOR type memory device and a manufacturing method therefor, and an electronic apparatus comprising the NOR type memory device. According to embodiments, the NOR type memory device may comprise: a plurality of device layers stacked on a substrate, wherein each device layer comprises a first source/drain region and a second source/drain region located at two opposite ends in a vertical direction, and a channel region located between the first source/drain region and the second source/drain region in the vertical direction; and a gate stack vertically extending relative to the substrate to pass through the device layers, the gate stack comprising gate conductor layers and memory functional layers arranged between the gate conductor layers and the device layers, and memory cells being defined at intersections of the gate stack and the device layers, wherein the doping concentration in the first source/drain region and the second source/drain region decreases toward the channel region in the vertical direction.

Classes IPC  ?

• H01L 27/11565 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la configuration vue du dessus

Abrégé

Disclosed are an NOR type memory device and a manufacturing method therefor, and an electronic device comprising same. According to embodiments, the NOR type memory device may comprise: a plurality of device layers provided on a substrate, each device layer comprising a stacked layer of a first source/drain layer, a first channel layer, and a second source/drain layer; and a gate stack vertically extending with respect to the substrate to pass through the stacked layer in each device layer, the gate stack comprising a gate conductor layer and a storage function layer provided between the gate conductor layer and the stacked layer, and a storage cell being defined at an intersection of the gate stack and the stacked layer.

Classes IPC  ?

• H01L 27/11565 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la configuration vue du dessus

Abrégé

An NOR-type memory device and a manufacturing method therefor, and an electronic apparatus comprising the NOR-type memory device. According to embodiments, the NOR-type memory device may comprise: a gate stack vertically extending on a substrate and comprising a gate conductor layer and a storage function layer; and a first semiconductor layer and a second semiconductor layer which surround the periphery of the gate stack and extend along the sidewall of the gate stack, the first semiconductor layer and the second semiconductor layer being respectively located at different heights relative to the substrate. The storage function layer is located between the first semiconductor layer and the gate conductor layer and between the second semiconductor layer and the gate conductor layer. Each of the first semiconductor layer and the second semiconductor layer comprises a first source/drain region, a channel region, and a second source/drain region which are sequentially arranged in the vertical direction. Memory units are defined at an intersection of the gate stack and the first semiconductor layer and at an intersection of the gate stack and the second semiconductor layer, respectively.

Classes IPC  ?

• H01L 27/11578 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur

Abrégé

The present invention relates to the technical field of circuit design. Disclosed are a light-emitting drive circuit and method, and a display drive circuit, used for improving the output stability of the light-emitting drive circuit. The light-emitting drive circuit comprises: an input circuit, a first potential control circuit, a second potential control circuit, a first output circuit, and a second output circuit. The method is used for driving the light-emitting drive circuit to output a light-emitting drive signal. The display drive circuit comprises the light-emitting drive circuit.

Classes IPC  ?

• G09G 3/30 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p.ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents

Abrégé

The present disclosure provides a three-state spintronic device, a memory cell, an array, and a read-write circuit. The three-state spintronic device comprises, from bottom to top, bottom electrodes, a magnetic tunnel junction, and a top electrode; the magnetic tunnel junction comprises: a spin-orbit coupling layer, a ferromagnetic free layer, a barrier tunneling layer, a ferromagnetic reference layer, three local magnetic domain wall pinning centers, and magnetic domain wall nucleation centers; the antisymmetric exchange interaction is modulated, and the magnetic domain wall pinning centers are embedded in the interface between a heavy metal and the ferromagnetic free layer; the magnetic domain wall nucleation centers are disposed at two ends of the ferromagnetic free layer; a current pulse flows through the spin-orbit coupling layer to generate a spin current and the spin current is injected into the ferromagnetic free layer. Under the control of the full electric field, the effective field of the spin-orbit torque drives the displacement of a domain wall, the displacement can be modulated by the number of pulses, pulse width and direction of the current, and CMOS process compatibility and high reliability are provided; the present disclosure also provides a three-state read-write circuit and a ternary network computing application scheme thereof, and achieves the high-performance GXNOR operation of a ternary spintronic device.

Classes IPC  ?

• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin

Abrégé

A method for reducing impact of phase grating asymmetry on position measurement precision, comprising the following steps: determining an asymmetry change range according to a design value and processing precision of a phase grating, and then determining an asymmetric grating structure; establishing an asymmetric grating simulation model; inputting the asymmetric grating structure into the asymmetric grating simulation model to simulate a position error curve of each diffraction order within the asymmetry change range; and determining the weight of each diffraction order according to the obtained difference in position error of each diffraction order, to reduce the impact of asymmetric changes. Without a need to measure the morphology of a grating, and only by determining a grating asymmetry change range according to processing precision, the impact of asymmetric changes in the range on position measurement precision can be reduced.

Classes IPC  ?

• G01B 11/00 - Dispositions pour la mesure caractérisées par l'utilisation de techniques optiques
• G03F 9/00 - Mise en registre ou positionnement d'originaux, de masques, de trames, de feuilles photographiques, de surfaces texturées, p.ex. automatique

Abrégé

The present application provides a semiconductor structure and a manufacturing method therefor, and a transistor. A doped structure is provided, and the doped structure may comprise doped elements; the surface of the doped structure is oxidized to form an oxide film, such that the doped elements at an interface between the oxide film and the doped structure would be redistributed, a segregation impurity layer is formed in the doped structure under the oxide film, and the doping concentration of the segregation impurity layer is higher than that of other positions of the doped structure; after the oxide film is removed, a doped structure having a relatively high surface doping concentration can be obtained without an additional doping process, such that after a conductor structure is formed on the segregation impurity layer, the contact resistance between the conductor structure and the doped structure is relatively low, and the device performance is improved.

Classes IPC  ?

• H01L 21/336 - Transistors à effet de champ à grille isolée
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/36 - Corps semi-conducteurs caractérisés par la concentration ou la distribution des impuretés

Abrégé

The present disclosure provides a multi-resistive spin electronic device, comprising: a top electrode and a bottom electrode respectively connected to a read-write circuit; and a magnetic tunnel junction located between the two electrodes and sequentially comprising, from top to bottom, a ferromagnetic reference layer, a barrier tunneling layer, a ferromagnetic free layer, and a spin-orbit coupling layer. Both ends of the ferromagnetic free layer are provided with nucleation centers for generating a magnetic domain wall; the spin-orbit coupling layer is connected to the bottom electrode, generates an electron spin current when applied with a write pulse, and drives the magnetic domain wall to move by means of spin-orbit torque; and interfaces of the spin-orbit coupling layer and the ferromagnetic free layer are provided with a plurality of local magnetic domain wall pinning centers for enhancing the interfacial Dzyaloshinskii-Moriya interaction coefficient strength. The device respectively drives and pins the magnetic domain wall in the ferromagnetic free layer by regulating spin coupling torque and the Dzyaloshinskii-Moriya interaction strength, so as to realize multi-resistive switching under a full electric field condition. The present disclosure further provides an in-memory computing Boolean logic and full-add operator based on the multi-resistive spin electronic device.

Classes IPC  ?

• G11C 11/02 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques
• H01L 43/02 - Dispositifs utilisant les effets galvanomagnétiques ou des effets magnétiques analogues; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails

Abrégé

Provided is a signal driving system with a constant slew rate. The signal driving system comprises: a step voltage generation unit, which is configured to be used for providing multiple voltage signals that progressively change at equal differences; a multiplexer, wherein one input end of the multiplexer is connected to the step voltage generation unit so as to receive the multiple voltage signals that progressively change at equal differences, and the other input end of the multiplexer is connected to a control signal generation unit, and is configured to be used for selectively outputting, under the control by a control signal sent by the control signal generation unit, the multiple voltage signals that progressively change at equal differences; a voltage following unit, which is connected to the multiplexer, and plays a role in isolation and improves driving capability; and an output following unit, which is connected to the voltage following unit and is configured to be used for driving a load unit connected later.

Classes IPC  ?

• H03K 19/0175 - Dispositions pour le couplage; Dispositions pour l'interface

Abrégé

Disclosed are a semiconductor apparatus having a side wall interconnection structure and a manufacturing method for the semiconductor apparatus, and an electronic device comprising the semiconductor apparatus. According to embodiments, the semiconductor apparatus may comprise: a plurality of device stacks, each device stack comprising stacked multi-layer semiconductor devices, and each semiconductor device comprising a first source/drain layer, a channel layer and a second source/drain layer which are stacked in a vertical direction, and a gate electrode surrounding the channel layer; and interconnection structures which are disposed between the plurality of device stacks. Each interconnection structure may comprise an electrical isolation layer and a conductive structure in the electrical isolation layer. At least one of the first source/drain layer, the second source/drain layer, and the gate electrode of each of at least some of the semiconductor devices is in lateral contact with and thus electrically connected to a conductive structure at a corresponding height in the interconnection structure.

Classes IPC  ?

• H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
• H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes

Abrégé

Provided are a resistive random access memory and a preparation method therefor. The resistive random access memory comprises a resistive layer, an upper electrode and a barrier structure, wherein the resistive layer is arranged on a substrate; the upper electrode is arranged on the resistive layer; and the barrier structure is arranged between the resistive layer and the upper electrode, and is used for allowing electrons to pass through a conduction band of the barrier structure when a device executes an erasure operation, thereby preventing a defect from being formed in the resistive layer, resulting in a reverse breakdown of the resistive layer. An oxide layer in a non-complete ratio is added between a resistive layer and an upper electrode, and is taken as a barrier structure, such that during an erasure operation of a device, when an applied erasure voltage is gradually increased, a conduction band energy level of the resistive layer is made even with a conduction band energy level of the oxide layer, and electrons pass through a conduction band of the barrier structure, thereby preventing excessive defects from being formed in the resistive layer. Therefore, a reverse breakdown does not occur in the device, so that the durability of the device is further improved.

Classes IPC  ?

• H01L 45/00 - Dispositifs à l'état solide spécialement adaptés pour le redressement, l'amplification, la production d'oscillations ou la commutation, sans barrière de potentiel ni barrière de surface, p.ex. triodes diélectriques; Dispositifs à effet Ovshinsky; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives
• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou

Abrégé

A read-write method and apparatus for LEPS soft decoding estimation, and an electronic device. The read-write method comprises: sequentially writing code words, which are obtained by encoding information bits, into target storage units of layers of storage unit arrays in a three-dimensional memory in a first direction; randomly reading the target storage units of the layers of storage unit arrays, or sequentially reading the target storage units of the layers of storage unit arrays according to a second direction; and determining an LLR value of the current target storage unit according to a storage time, a threshold voltage partition and a comprehensive distribution state, which correspond to the current target storage unit during reading, and a pre-established LLR table, so as to perform a soft decoding operation on the code words of the target storage unit on the basis of the LLR value of the current target storage unit, wherein the comprehensive distribution state of the target storage unit is determined according to the influence of a reference storage unit on the distribution state of the current target storage unit, and the reference storage unit is determined according to the first direction or according to the first direction and the second direction.

Classes IPC  ?

• G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
• G11C 5/02 - Disposition d'éléments d'emmagasinage, p.ex. sous la forme d'une matrice
• H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité

Abrégé

The present disclosure provides a photoelectric detection device having a closed design and capable of preventing distortion of optical signals, and an implementation method therefor. The photoelectric detection device comprises a vacuum sealed housing, a photoelectric detector array, a photoelectric conversion and synchronous acquisition circuit, and a high-speed transmission circuit board, wherein the vacuum sealed housing comprises a mounting interface for mounting the photoelectric detector array to form a closed space; a detection surface of the photoelectric detector array faces the outer side of the vacuum sealed housing and is used for receiving multi-channel measurement optical signals; the photoelectric conversion and synchronous acquisition circuit and the high-speed transmission circuit board are disposed in the vacuum sealed housing; the photoelectric detector array is connected to the photoelectric conversion and synchronous acquisition circuit by means of signal pins of the photoelectric detector array; the photoelectric conversion and synchronization acquisition circuit is used for synchronously converting the multi-channel measurement optical signals obtained by the photoelectric detector array into multi-channel digital signals; and the high-speed transmission circuit board is used for performing serialized encoding processing on the converted multi-channel digital signals.

Classes IPC  ?

• G01J 1/44 - Circuits électriques
• H04B 10/07 - Dispositions pour la surveillance ou le test de systèmes de transmission; Dispositions pour la mesure des défauts de systèmes de transmission

Abrégé

A method for designing a thin film transistor. The method comprises: calculating feature parameters of searched materials; screening the materials according to a feature parameter threshold value so as to obtain first active layer materials; performing simulation by taking each of the first active layer materials as an active layer material in a thin film transistor device model, so as to obtain a device feature of a thin film transistor device; screening the first active layer materials according to a device feature threshold value so as to obtain a second active layer material; performing testing by taking the second active layer material as the active layer material of the thin film transistor device; and when a test result does not meet a preset requirement, selecting another second active layer material and performing testing again, and when the test result meets the preset requirement, completing the design of the thin film transistor device. In the present invention, a large number of physical properties related to active layer materials of a thin film transistor device, and a corresponding active layer material database can be obtained by means of a simple method, so as to provide theoretical guidance for studying the characteristics of the thin film transistor device.

Classes IPC  ?

• G06F 30/20 - Optimisation, vérification ou simulation de l’objet conçu
• G16C 60/00 - Science informatique des matériaux, c. à d. TIC spécialement adaptées à la recherche des propriétés physiques ou chimiques de matériaux ou de phénomènes associés à leur conception, synthèse, traitement, caractérisation ou utilisation

Abrégé

A pressure sensor based on zinc oxide nanowires and a manufacturing method therefor. The manufacturing method comprises: manufacturing a bottom electrode (201) on a substrate; manufacturing a seed layer (202) on the bottom electrode (201); manufacturing a zinc oxide nanowire layer (203) on the seed layer (202); manufacturing a support layer (204) on the zinc oxide nanowire layer (203); and manufacturing a top electrode (206) on the support layer (204). The pressure sensor based on a-IGZO-TFT and ZnO NWs manufactured by the manufacturing method achieves pressure detection. For pressure sensors made of conventional piezoelectric materials such as ceramic materials, the manufacturing temperature is generally 1000 K or above, while the manufacturing method achieves a technology for manufacturing the pressure sensor at a low temperature.

Classes IPC  ?

• H01L 41/27 - Fabrication de dispositifs piézo-électriques ou électrostrictifs multicouches ou de leurs parties constitutives, p.ex. en empilant des corps piézo-électriques et des électrodes
• H01L 41/18 - Emploi de matériaux spécifiés pour des éléments piézo-électriques ou électrostrictifs
• H01L 29/786 - Transistors à couche mince
• G01L 1/16 - Mesure des forces ou des contraintes, en général en utilisant les propriétés des dispositifs piézo-électriques
• B82Y 40/00 - Fabrication ou traitement des nanostructures

Abrégé

A method for manufacturing a programmable diode, the method comprising the following steps: forming a tungsten plug by using a standard CMOS process; using the tungsten plug as a lower electrode, and depositing a functional layer material, such as a ferroelectric thin film, on the tungsten plug; depositing an upper electrode on the functional layer material; and patterning the upper electrode and a functional layer, so as to complete the manufacturing of a programmable diode. Further disclosed is a ferroelectric memory having a programmable diode manufactured by using the method for manufacturing a programmable diode. In the method for manufacturing a programmable diode disclosed in the present disclosure, the growth of a lower electrode is not required, thereby reducing the complexity of the process. The ferroelectric memory disclosed in the present disclosure is formed by a transistor and a programmable diode. The design is to store information according to the polarity difference of the diode, and therefore, the area of a device can be further reduced, and the storage density can be improved.

Classes IPC  ?

• H01L 27/115 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs

Abrégé

Provided in the present disclosure is a neuron device based on a spin orbit torque. The neural device comprises: an anti-ferromagnetic pinning layer, a first ferromagnetic layer and a spin orbit coupling layer which are formed on a substrate in sequence; a free layer formed on the spin orbit coupling layer and moving a magnetic domain wall according to the spin orbit torque; a tunneling layer formed on the free layer; a left pinning layer and a right pinning layer, which are formed on two sides of the free layer and have opposite magnetization directions; and a reference layer formed on the tunneling layer, wherein the free layer, the tunneling layer and the reference layer form a magnetic tunnel junction, and the magnetic tunnel junction is used for reading neuron signals. Further provided in the present disclosure is a preparation method for the neuron device based on a spin orbit torque.

Classes IPC  ?

• G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
• G06N 3/04 - Architecture, p.ex. topologie d'interconnexion
• G06N 3/08 - Méthodes d'apprentissage
• H01L 43/06 - Dispositifs à effet Hall
• H01L 43/10 - Emploi de matériaux spécifiés

Abrégé

A method for operating a storage unit, a method for operating a resistive random access memory, and an electronic device. The method for operating a storage unit comprises performing write and erase operations on a resistive device. The write operation comprises: applying a write voltage to the resistive device, and determining whether a resistance value of the resistive device reaches a low resistance state threshold value; and when the resistance value of the resistive device reaches the low resistance state threshold value, applying a constant current to the resistive device, wherein a voltage value generated by the constant current on the resistive device is less than a voltage value of the write voltage. The erase operation comprises: applying an erase voltage to the resistive device, and determining whether the resistance value of the resistive device reaches a reference resistance value; and when the resistance value of the resistive device reaches the reference resistance value, applying a constant voltage to the resistive device, wherein a voltage value of the constant voltage is less than a voltage value of the erase voltage. The retention capability of a device in a low resistance state is improved, the uniformity and a data retention characteristic of a resistive device are improved, and the durability of the device is also improved.

Classes IPC  ?

• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou

Abrégé

A packaging method for a semiconductor structure, a packaging structure, and a chip. The packaging method for a semiconductor structure comprises: forming a semiconductor structure on an SOI wafer; depositing, by means of plasma-enhanced chemical vapor deposition (PECVD), silicon oxide on the surface of the semiconductor structure provided with a trench opening; and performing a subsequent packaging process. By sealing a trench opening of a semiconductor structure by using the characteristic of low step coverage of PECVD, the problem of device failures caused by trench blocking due to subsequent filling of a packaging material is solved.

Classes IPC  ?

• G02B 6/132 - Circuits optiques intégrés caractérisés par le procédé de fabrication par le dépôt de couches minces

Abrégé

Provided are a memory circuit structure and method for operation thereof; the memory circuit structure comprises: a storage array, containing at least two memory cells; a decoder, separately connected to the bit and word lines of the memory array; a programming circuit, used for generating a voltage pulse or a constant-current pulse; a polarity switching circuit, connected to the programming circuit and used for switching the programming circuit between voltage programming and current programming under setup and reset operations; a detection circuit, connected to the storage array and used for detecting a detection signal corresponding to the current or voltage of a specific memory cell in the memory array, and feeding the detection signal to a control unit, the detection signal outputted from the detection circuit being used for enabling the polarity switching circuit to switch; and a control unit, used for, according to the detection signal, controlling the polarity switching circuit to perform a switching operation and controlling the pulse output of the programming circuit. The described structure optimizes the durability and retention characteristics of a resistive memory, improving the homogeneity of the resistive state, reducing the bit error rate of the array.

Classes IPC  ?

• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou

Abrégé

The present disclosure belongs to the technical field of memory, and mainly relates to a magneto-resistive device, a method for changing a resistance state thereof and a synaptic learning module. The magneto-resistive device comprises a top electrode, a ferromagnetic reference layer, a tunneling layer, a ferromagnetic free layer, a spin-orbit coupling layer, and a bottom electrode that are sequentially arranged along a preset direction. The spin-orbit coupling layer comprises a first thickness region and a second thickness region, which are alternately distributed, the thickness of the first thickness region and the second thickness region being different. The ferromagnetic free layer comprises a pinning region, and the position of the pinning region is in a one-to-one correspondence with the position of the first thickness region.

Classes IPC  ?

• H01L 43/08 - Résistances commandées par un champ magnétique
• H01L 43/12 - Procédés ou appareils spécialement adaptés à la fabrication ou le traitement de ces dispositifs ou de leurs parties constitutives
• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin

Abrégé

The present disclosure provides a fully electric controlled spintronic neural component, a neural circuit, and a neural network. The neural component comprises: a bottom antiferromagnetic pinning layer ; a synthetic antiferromagnetic layer, formed on the bottom antiferromagnetic pinning layer; a barrier layer formed on the ferromagnetic free layer, wherein a region of a ferromagnetic free layer facing the barrier layer forms a threshold region; a ferromagnetic reference layer formed on the barrier layer, wherein the barrier layer, the ferromagnetic reference layer and the ferromagnetic free layer form a magnetic tunnel junction; a first antiferromagnetic pinning layer and a second antiferromagnetic pinning layer formed on the exposed region of the ferromagnetic free layer except the region facing the barrier layer, the first antiferromagnetic pinning layer and the second antiferromagnetic pinning layer being located on both sides of the barrier layer, wherein the region of the ferromagnetic free layer facing the first antiferromagnetic pinning layer and the second antiferromagnetic pinning layer forms a first pinning region and a second pinning region, respectively; and a first electrode formed on the ferromagnetic reference layer.

Classes IPC  ?

• G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
• H01L 43/06 - Dispositifs à effet Hall

Abrégé

Disclosed are a semiconductor device having a ferroelectric or negative capacitance material layer on a sidewall of a gate electrode, a manufacturing method therefor, and an electronic device comprising the semiconductor device. According to an embodiment, the semiconductor device can comprise: a substrate; a gate electrode that is formed on the substrate; a ferroelectric or negative capacitance material layer that is formed on a sidewall of the gate electrode; and a source region and a drain region that are located on the substrate and are on opposite sides of the gate electrode.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

Disclosed are a nanowire/sheet device having a self-aligned isolation portion, a manufacturing method therefor and an electronic device comprising the nanowire/sheet device. According to embodiments, the nanowire/sheet device may comprise: a substrate; nanowires/sheets spaced apart from a surface of the substrate and extending in a first direction; a gate stack extending in a second direction intersecting the first direction to surround the nanowires/sheets; a side wall formed on the side wall of the gate stack; source/drain layers which are located at two opposite ends of the nanowires/sheets in the first direction and are connected to the nanowires/sheets; and a first isolation portion between the gate stack and the substrate, the first isolation portion being self-aligned to the gate stack.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

Disclosed are a nanowire/nanosheet device having a ferroelectric or negative capacitance material and a manufacturing method therefor, and an electronic device comprising the nanowire/nanosheet device. According to embodiments, a semiconductor can comprise: a substrate; a nanowire/nanosheet that is located on the substrate and spaced apart from the surface of the substrate; a gate electrode surrounding the nanowire/nanosheet; a ferroelectric or negative capacitance material layer formed on the side wall of the gate electrode; and a source/drain layer that is located on two opposite ends of the nanowire/nanosheet and connected to the nanowire/nanosheet.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

Disclosed are a semiconductor device having a ferroelectric/negative capacitor, a method for manufacturing the same, and an electronic device comprising the semiconductor device. According to embodiments, the semiconductor may comprise: a gate electrode and a source/drain electrode formed on a substrate; a positive capacitor formed on the substrate, a first terminal of the positive capacitor being electrically connected to the gate electrode; a ferroelectric or negative capacitor formed on the substrate, a first terminal of the ferroelectric or negative capacitor being electrically connected to the gate electrode. A second terminal of one of the ferroelectric or negative capacitor is electrically connected to a gate voltage application terminal, and a second terminal of the other of the ferroelectric or negative capacitor is electrically connected to the source/drain electrode.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/336 - Transistors à effet de champ à grille isolée
• H01L 27/11507 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec condensateurs ferro-électriques de mémoire caractérisées par la région noyau de mémoire

Abrégé

A complementary memory cell and a production method therefor, and a complementary memory. The complementary storage cell (100) comprises a control transistor (101), a pull-up diode (201), and a pull-down diode (301); the control transistor (101) is used for controlling reading and writing of the complementary storage cell (100); the pull-up diode (201) has one end connected to a positive selection line (401), and the other end connected to a source end of the control transistor (101) for controlling high-level input; the pull-down diode (301) has one end connected to a negative selection line (501), and the other end connected to the source end of the control transistor (101) for controlling low-level input; the pull-up diode (201) and the pull-down diode (301) are symmetrically arranged in a first direction. On the basis of the design of the complementary storage cell (100), the circuit complexity of a memory is greatly reduced, the area size of the memory is reduced, the storage density of the memory is improved, and the power consumption of the memory is also reduced under the condition that the complementary memory can realize original functional characteristics.

Classes IPC  ?

• G11C 11/409 - Circuits de lecture-écriture [R-W]

Abrégé

A device and method for testing the fatigue characteristics of a gating tube (210). The device comprises a voltage dividing element (220) and a counter (103), wherein the voltage dividing element (220) is connected to the gating tube (210) to be tested and is used for dividing the voltage of the gating tube (210) to be tested during the testing process; and the counter (103) is connected to the gating tube (210) to be tested and is used for detecting voltage and/or current changes in the gating tube (210) to be tested. The gating tube (210) to be tested is used as a constituent part of an oscillator (102), such that the device is simpler in structure, and complex circuit compositions, such as a pulse generator and a discrimination circuit, are omitted; in addition, periodic voltage and/or current oscillation are/is realized based on the characteristics of the gating tube (210), the test period is shorter, the test time is shortened, and the device is extremely simple in composition.

Classes IPC  ?

• G01R 31/00 - Dispositions pour tester les propriétés électriques; Dispositions pour la localisation des pannes électriques; Dispositions pour tests électriques caractérisées par ce qui est testé, non prévues ailleurs

Abrégé

The present disclosure provides a symmetrical type memory cell and a BNN circuit. The symmetrical type memory cell comprises a first complementary structure and a second complementary structure; the second complementary structure is symmetrically connected to the first complementary structure in a first direction; the first complementary structure comprises a first control transistor used for being connected to the second complementary structure; the second complementary structure comprises a second control transistor; the drain electrode of the second control transistor and the drain electrode of the first control transistor are symmetrically arranged in the first direction, and are simultaneously connected to a bit line; and the symmetrical type memory cell is used for storing the weight value 1 or 0. By means of the symmetrical type memory cell of the present disclosure, the breakpoint data of the BNN circuit can be kept, power consumption is reduced, the area of a memory is greatly reduced, time delay is reduced, and the BNN circuit can realize a large-scale parallel reasoning operation.

Classes IPC  ?

• G11C 11/22 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des éléments ferro-électriques
• G11C 11/4063 - Circuits auxiliaires, p.ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture ou la synchronisation
• G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
• G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques

Abrégé

A data transmission device and method, applicable to the technical field of information. The device comprises a signal conversion module (30) and a signal transmission module (20). The signal conversion module (30) is used at a data transmission end, and converts an electrical signal including data information into a magnon signal. The signal transmission module (20) transmits the magnon signal including the data information to a data receiving end. The signal conversion module (30) is further used at the data receiving end, and converts the magnon signal including the data information into an electrical signal including the data information. The data transmission method uses magnon signals to perform data transmission, and does not require any voltage or current during the data transmission.

Classes IPC  ?

• G06F 13/40 - Structure du bus

Abrégé

A non-external magnetic field oriented spin flip SOT-MRAM and an array. The SOT-MRAM comprises in sequence from top to bottom: a gating device (1) for turning the SOT-MRAM on or off under the action of an external voltage; a magnetic tunnel junction (2), comprising in sequence from top to bottom a ferromagnetic reference layer, a tunnelling layer, and a ferromagnetic free layer; and a spin orbit coupling layer (3), composed of one or more of heavy metal, doped heavy metal, heavy metal alloy, a double heavy metal layer, semiconductor material, two-dimensional semi-metal material, and antiferromagnetic material; an interlayer exchange coupling effect is used to produce an in-plane effective field in the ferromagnetic free layer and a spin Hall effect is used to produce spin orbit torque, in order to perform deterministic storage of data in the magnetic tunnel junction (2). Using the perpendicular anisotropy of the ferromagnetic layers, SOT-driven magnetic tunnel junction ferromagnetic free layer oriented spin flip is implemented by means of the joint effect of interlayer exchange coupling and spin transfer torque without the assistance of an external magnetic field, and a three-dimensional array structure is achieved.

Classes IPC  ?

• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
• G11C 5/02 - Disposition d'éléments d'emmagasinage, p.ex. sous la forme d'une matrice

Abrégé

A cache device and a manufacturing method therefor, applied to the technical field of caches. The cache device comprises a first field-effect transistor (10), a magnetic tunnel junction, an electrode (17), and a second field-effect transistor (18) which are connected in sequence. The first field-effect transistor (10) is configured to provide a write current and control on/off of the write current by means of the gate. The magnetic tunnel junction comprises a non-ferromagnetic layer (11), a first ferromagnetic layer (12), a tunneling layer (13), a second ferromagnetic layer (14), and a pinning layer (16) which are arranged in sequence; the non-ferromagnetic layer (11) is configured to provide a lateral channel for inputting of the write current; the first ferromagnetic layer (12) is configured to generate a variable first magnetization direction on the basis of a class field spin torque; the tunneling layer (13) is configured to be located in the first ferromagnetic layer (12) and the second ferromagnetic layer (14); the second ferromagnetic layer (14) is configured to have a fixed second magnetization direction; the pinning layer (16) is configured to maintain the second magnetization direction. The electrode (17) is configured to connect the cache device and the second field-effect transistor (18). The second field-effect transistor (18) is configured to control on/off of the second field-effect transistor (18) by means of the gate to read an impedance state.

Classes IPC  ?

• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin

Abrégé

Disclosed is an antiferroelectric memory, comprising: a substrate; a source electrode and a drain electrode, which are arranged on two ends of the substrate; and an antiferroelectric thin-film structure layer, which is arranged on the substrate, the antiferroelectric thin-film structure layer successively comprising, upwards from the substrate, a first antiferroelectric layer, an intermediate electrode, a second antiferroelectric layer and a top electrode, wherein there is a work function difference between the top electrode, the intermediate electrode and the substrate. By means of the antiferroelectric memory provided in the present invention, a double-antiferroelectric sandwich structure is used to simultaneously realize the translation of two antiferroelectric thin-film layer polarization hysteretic curves towards a Y-axis, such that two windows of antiferroelectric thin-film polarization hysteretic curves are both located at the position of zero external voltage.

Classes IPC  ?

• H01L 27/1159 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs les électrodes de grille comprenant une couche utilisée pour ses propriétés de mémoire ferro-électrique, p.ex. semi-conducteur métal-ferro-électrique [MFS] ou semi-conducteur d’isolation métal-ferro-électrique-métal [MFMIS] caractérisées par la région noyau de mémoire

Abrégé

The present invention provides a method and system for improving the performance of a gate tube device, a device, and a medium. The method comprises: determining an operating voltage and a limiting current of a gate tube device during a direct-current operation; applying the operating voltage and the limiting current to the gate tube device until an off-state leakage current is reduced; continuing to apply the operating voltage and the limiting current to the gate tube device until the off-state leakage current is reduced to a minimum value; obtaining a first operating voltage and a first limiting current corresponding to the minimum value of the off-state leakage current, and obtaining an operating voltage interval and a limiting current interval by using the first operating voltage and the first limited current as centers; applying, to the gate tube device, a second operating voltage and a second limiting current within the range of the operating voltage interval and the limiting current interval, so as to perform a direct-current operation or a pulse operation; and determining a reverse operating voltage of the gate tube device, and applying the reverse operating voltage to the gate tube device, so that the gate tube device generates a reset phenomenon.

Classes IPC  ?

• H01L 27/24 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants à l'état solide pour le redressement, l'amplification ou la commutation, sans barrière de potentiel ni barrière de surface
• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou

Abrégé

Disclosed are a resistive random access memory and a preparation method therefor. The resistive random access memory comprises a resistive dielectric layer for resistive memory storage. The resistive dielectric layer comprises a doped dielectric layer. A portion of the doped dielectric layer includes metal atoms having a certain doping concentration, and is used to form an enhanced local electric field in the resistive random access memory, such that the generation location of a conductive channel of the resistive random access memory can be controlled, thereby improving device reliability. The configuration allows the resistive random access memory of the present invention to be forming-free and to stably exhibit a low resistance state in the initial period, thereby preventing the problem of current overshoot during a high-voltage forming process. In addition, the configuration keeps the size of the device of the present application under control and reduces high-voltage power consumption while improving voltage tolerance.

Classes IPC  ?

• H01L 27/24 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants à l'état solide pour le redressement, l'amplification ou la commutation, sans barrière de potentiel ni barrière de surface
• H01L 45/00 - Dispositifs à l'état solide spécialement adaptés pour le redressement, l'amplification, la production d'oscillations ou la commutation, sans barrière de potentiel ni barrière de surface, p.ex. triodes diélectriques; Dispositifs à effet Ovshinsky; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives

Abrégé

xx. The adjustment and control of a high-impedance-state current value of a resistive random access memory are realized by means of adjusting a value x.

Classes IPC  ?

• H01L 45/00 - Dispositifs à l'état solide spécialement adaptés pour le redressement, l'amplification, la production d'oscillations ou la commutation, sans barrière de potentiel ni barrière de surface, p.ex. triodes diélectriques; Dispositifs à effet Ovshinsky; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives

Abrégé

A spin-orbit torque magnetic random access memory (SOT-MRAM) cell, a memory array, and a memory. The SOT-MRAM cell comprises a magnetic tunnel junction and a gate; the gate is a two-dimensional material-based gate; the magnetic tunnel junction is provided above or below the gate; the magnetic tunnel junction comprises an antiferromagnetic layer and a free layer; the free layer is adjacent to the antiferromagnetic layer; when the gate is turned on, the memory cell is turned on, a spin current is generated from a current and is input to the free layer, and under the action of the exchange bias effect of the free layer and the antiferromagnetic layer, the magnetization direction of the free layer is reversed. By using the exchange bias effect and applying the magnetic tunnel junction to optimize the bias voltage, deterministic magnetization reversal of the SOT-MRAM cell at room temperature and zero magnetic field can be achieved without the need to load an external field, thereby achieving the purpose of data writing and implementing the SOT-MRAM cell having a double-ended structure.

Classes IPC  ?

• H01L 43/08 - Résistances commandées par un champ magnétique

Abrégé

A spin-orbit torque magnetic random access memory unit, an array, and a Hamming distance calculation method, the spin-orbit torque magnetic random access memory unit comprising: a magnetic tunnel junction, a first transistor and a second transistor, a drain electrode of the first transistor being connected to the bottom of the magnetic tunnel junction, and the sink electrode of the second transistor being connect to the top of the magnetic tunnel junction. The present invention, in full electric field conditions, makes possible definite spin magnetization flipping without an external magnetic field. At the same time, the invention has the feature of using a non-polar electric current to control resistance states. An array constituted by spin-orbit torque magnetic random access memory units, under peripheral circuit control, implements storage/computation-integrated XOR logic, and thus can be used in hardware implementations of reconstructible highly parallel computing, for example, in-memory Hamming weight and Hamming distance calculations.

Classes IPC  ?

• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin

Abrégé

Disclosed are a vertical semiconductor device with a conductive layer and a manufacturing method therefor, and an electronic device including the device. According to the embodiments, the semiconductor device can comprise: a substrate; a first metallic layer, a channel layer and a second metallic layer which are successively arranged on the substrate; and a gate stack formed around at least part of the periphery of the channel layer, wherein the first metallic layer, the second metallic layer and the channel layer are of a single crystal structure.

Classes IPC  ?

• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

A semiconductor apparatus of a staggered structure and a manufacturing method therefor, and electronic equipment comprising the semiconductor apparatus. The semiconductor apparatus comprises a first device and a second device on a substrate (1001). The first device and the second device each comprise a comb-shaped structure. The comb-shaped structure comprises a first portion extending in the vertical direction relative to the substrate (1001) and one or more second portions extending from the first portion in the lateral direction relative to the substrate (1001) and spaced apart from the substrate (1001). The height of the second portion of the first device in the vertical direction is staggered with respect to the height of the second portion of the second device in the vertical direction. The comb-shaped structure of the first device and the comb-shaped structure of the second device comprise materials different from each other.

Classes IPC  ?

• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices

Abrégé

Provided are a semiconductor device having a square-wave-shaped structure and a manufacturing method therefor, and an electronic apparatus comprising the semiconductor device. The semiconductor device may comprise a semiconductor layer (1031) extending in the shape of a square wave and in a vertical direction relative a substrate (1001); the semiconductor layer (1031) comprises one or more first portions sequentially arranged in the vertical direction and spaced apart from one another, and second portions respectively arranged at and connected to two opposite ends of each first portion; for each first portion, the second portion at one end thereof extends from said end in a direction away from the substrate, and the second portion at the other end thereof extends from said other end in a direction towards the substrate; and first portions which are adjacent in the vertical direction are connected to each other by means of the same second portion.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 21/336 - Transistors à effet de champ à grille isolée
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS

Abrégé

Disclosed are a semiconductor device having a U-shaped structure, a fabricating method therefor, and an electronic device comprising same. According to an embodiment, the semiconductor device may comprise: a first fin and a second fin that extend in a vertical direction with respect to a substrate and are opposed to each other; and a connecting nanosheet, for connecting the bottom ends of the first fin and the second fin to form a U-shaped structure, wherein the connecting nanosheet is spaced apart from the top surface of the substrate.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

The present disclosure provides a memory cell structure, a memory array structure, and a voltage bias method. The memory cell structure comprises: a substrate layer, a well layer, and a transistor. The substrate layer is used for supporting the memory cell structure; the well layer is embedded in the substrate layer, the upper surface of the well layer is flush with the upper surface of the substrate layer, and the transistor is arranged on the well layer. In the present disclosure, deep well bias is performed on the memory cell structure so that a trap voltage of a memory cell can be independently biased into a specific voltage; in conjunction with a redesigned memory cell array structure, most of an applied programming voltage falls on the memory cell structure, thereby reducing the programming voltage of the memory cell, avoiding a gating transistor from being broken down due to an overhigh voltage, and ensuring better reliability of a device and higher area efficiency of the memory cell array structure.

Classes IPC  ?

• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
• H01L 27/24 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants à l'état solide pour le redressement, l'amplification ou la commutation, sans barrière de potentiel ni barrière de surface

Abrégé

Disclosed are a semiconductor device, a fabrication method for same, and an electronic device comprising the semiconductor device. The semiconductor device may comprise: a vertical structure, which extends in a vertical direction relative to a substrate (1001); and a nanosheet, which extends from the vertical structure and is spaced apart from the substrate (1001) in the vertical direction, wherein the nanosheet has a first portion in a first orientation, and at least one of an upper surface and a lower surface of the first portion is not parallel to a horizontal surface of the substrate (1001).

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 21/336 - Transistors à effet de champ à grille isolée
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS

Abrégé

A semiconductor device and a fabrication method therefor, and an electronic device comprising the semiconductor device. The semiconductor device may comprise: a nanochip stack layer on a substrate (1001), the layer comprising a plurality of nanochips that are separated from one another in the vertical direction relative to the substrate (1001); at least nanochip among the plurality of nanochips has a first portion along a first orientation, and at least one among the upper surface and the lower surface of the first portion is not parallel to the horizontal surface of the substrate (1001).

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

A LDPC soft decoding method, a memory, and an electronic device. The method comprises: reading is performed on a memory cell where an information bit has already been coded, and a LLR value for a current memory cell is obtained according to a storage time corresponding to the current memory cell during reading, a threshold voltage partition, and a cumulative distribution, and via referencing a pre-established LLR table; a soft decoding operation is performed on a codeword of the memory cell where an information bit has already been coded according to the LLR value for the read current memory cell; wherein the cumulative distribution for the current memory cell is determined according to the influence of a memory cell adjacent to the current memory cell on a distribution of the current memory cell; input quantities for the pre-established LLR table are: a storage time, a threshold voltage partition, and a cumulative distribution, and an output quantity is an LLR value. The present means of performing decoding on the basis of an LLR value determined by a cumulative distribution reduces bit error rate and improves error correction capability compared to current means for LDPC soft decoding, and also reduces the number of iterations.

Classes IPC  ?

• G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
• G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention

Abrégé

Disclosed are a semiconductor apparatus including a capacitor and a manufacturing method therefor, and an electronic device including the semiconductor apparatus. According to the embodiments, the semiconductor apparatus may include: a vertical semiconductor means, including an active region extending vertically on a substrate; and a capacitor, including a first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode that are sequentially stacked. The first capacitor electrode extends vertically on the substrate and includes a conductive material, and the conductive material includes at least one of semiconductor elements included in the active region of the vertical semiconductor means.

Classes IPC  ?

• H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
• H01L 21/8234 - Technologie MIS

Abrégé

A C-shaped trench semiconductor component, a manufacturing method thereof, and an electronic device comprising said semiconductor component. The semiconductor component may comprise: a trench on a substrate (1001), the trench comprising a bent nanosheet or nanowire having a C-shaped cross-section; source/drain parts located at upper and lower ends of the trench relative to the substrate (1001) respectively; and a gate stack surrounding a periphery of the trench.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

A storage device, a memory and a manufacturing method thereof, an electronic device and a chip, which relate to the technical field of memory, prolong the data storage time of the storage device, and thereby improve the storage capacity of the storage device. The storage device (200) includes a substrate (210), a negative capacitance transistor (M2) formed on the substrate (210), and a capacitor (C2) electrically connected to the negative capacitance transistor (M2). The memory includes the storage device (200) described above, and the storage device is used in the electronic device.

Classes IPC  ?

• H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire

Abrégé

Disclosed is a manufacturing method for a semiconductor device, comprising the following steps: providing a first substrate and a second substrate, the first substrate having a first bonding interconnection surface, and the second substrate having a second bonding interconnection surface; manufacturing a monocrystalline lamination structure on the first substrate, the monocrystalline lamination structure comprising several heterogeneous material layers and second substrate layers which are alternately stacked; manufacturing several nanowires or nanosheets on the first substrate; forming a gate dielectric layer and a gate on the several nanowires or nanosheets; forming a metal contact; forming several layers of interconnect structures on the formed structure; and sequentially forming a metal pad and a passivation layer on the several layers of interconnect structures. The channel material formed by the manufacturing method does not have a lattice defect, which can avoid affecting the performance and reliability of a subsequently formed device, does not cause a limitation to a forming process of a subsequent structure, and has good applicability. The present invention further provides a semiconductor device.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 21/336 - Transistors à effet de champ à grille isolée
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

A two-dimensional material-based gate, a memory unit, an array, and an operating method thereof, the gate comprising: a stack unit. The stack unit is a metal-two-dimensional semiconductor-metal structure, comprising a two-dimensional semiconductor layer and metal layers respectively arranged on the upper and lower surfaces of the two-dimensional semiconductor layer. The number of stack units is N, N≥1, and in each stack unit, the two metal-two-dimensional semiconductor interfaces both form a Schottky contact, and when the two-dimensional material-based gate is powered on, the stack unit comprises two reverse series-connected Schottky diode structures. Or the number of stack units is M, M≥2, and in each stack unit, one of the two metal-two-dimensional semiconductor interfaces forms a Schottky contact and the other interface forms an ohmic contact, and when the two-dimensional material-based gate is powered on, the M stack units comprise M reverse parallel-connected Schottky diode structures.

Classes IPC  ?

• H01L 43/08 - Résistances commandées par un champ magnétique
• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin

Abrégé

A metalized laminate and a manufacturing method therefor, and an electronic device comprising the metalized laminate. The metalized laminate can comprise at least one interconnection line layer and at least one via hole layer alternately provided on a substrate. At least one pair of adjacent interconnection line layer and via hole layer in the metalized laminate comprise an interconnection line in the interconnection line layer and a via hole in the via hole layer, wherein the interconnection line layer is closer to the substrate than the via hole layer. At least a portion of the interconnection line is integrated with the via hole on the at least a portion of the interconnection line.

Classes IPC  ?

• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants

Abrégé

A metalized lamination layer and a manufacturing method therefor, and an electronic device comprising such a metalized lamination layer. The metalized lamination layer may comprise at least one interconnection line layer and at least one via hole layer alternately arranged on a substrate (1001). At least one pair of interconnection line layer and via hole layer in the metalized lamination layer that are adjacent to each other comprises an interconnection line (1015) in the interconnection line layer and a via hole (1115) in the via hole layer. The interconnection line layer is closer to the substrate (1001) than the via hole layer. The outer peripheral side wall of the via hole (1115) on at least part of the interconnection line (1015) does not go beyond the outer peripheral side wall of the at least part of the interconnection line (1015).

Classes IPC  ?

• H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/485 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées formées de structures en couches comprenant des couches conductrices et isolantes, p.ex. contacts planaires
• H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement

Abrégé

A method for preparing a three-dimensional static random-access memory. The method comprises the following steps: preparing a first semiconductor structure (1); bonding a first material layer (11) on a first insulating layer (10); performing a first thinning treatment and a first surface treatment on the first material layer (11) to form a first substrate layer (12); manufacturing several first low-temperature MOS transistors (14) on the first substrate layer (12) at a low temperature, and forming a second insulating layer (20) on the several first low-temperature MOS transistors (14) to form a second semiconductor structure (13); repeating the operation for preparing the second semiconductor structure (13) to form a third semiconductor structure (21); and providing through holes in the first insulating layer (10), the second semiconductor structure (13) and the third semiconductor structure (21) to form an interconnection layer so as to interconnect the first semiconductor structure (1), the second semiconductor structure (13) and the third semiconductor structure (21). By means of the provided preparation method, the quality of a prepared SRAM can be ensured, the area occupied by the SRAM is reduced, and the difficulty of preparing a 3D SRAM can be reduced. In addition, further provided is a three-dimensional static random-access memory.

Classes IPC  ?

• H01L 27/11 - Structures de mémoires statiques à accès aléatoire

Abrégé

Disclosed are a semiconductor device and a manufacturing method therefor, and an electronic device comprising the semiconductor device. According to the embodiment, the semiconductor device may comprise a channel portion, source/drain portions at two opposite sides of the channel portion and connected to the channel portion, and a gate stack intersecting the channel portion. The channel portion comprises a first part extending in a vertical direction relative to a substrate and a second part extending from the first part in a transverse direction relative to the substrate.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

Disclosed are a semiconductor apparatus and a manufacturing method therefor, and an electronic device comprising the semiconductor apparatus. According to the embodiments, the semiconductor apparatus comprises a first device and a second device on a substrate that are opposite each other; the first device and the second device each comprise a channel portion, source and drain portions on two sides of the channel portion that are connected to the channel portion, and a gate stack intersecting the channel portion; the channel portion comprises a first portion extending in a vertical direction relative to the substrate and a second portion extending in a transverse direction relative to the substrate from the first portion; and the second portion of the channel portion of the first device and the second portion of the channel portion of the second device extend in the same or opposite direction.

Classes IPC  ?

• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 21/8234 - Technologie MIS

Abrégé

Disclosed are a semiconductor device and a manufacturing method therefor, and an electronic device comprising the semiconductor device. According to the embodiment, the semiconductor device comprises a channel portion, source/drain portions at two opposite sides of the channel portion and connected to the channel portion, and a gate stack intersecting the channel portion. The channel portion comprises a first part extending in a vertical direction relative to a substrate and a second part extending from the first part to two opposite sides, respectively, in a transverse direction relative to the substrate.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

An integrated method for a silicon optical adapter adapter plate and a three-dimensional architecture, capable of making the chip encapsulation area smaller, and achieving a higher integration level, a smaller electrical signal delay and a higher bandwidth and speed, and an integrated method for a surface electrode ion trap, a silicon optical device and a three-dimensional architecture, an integrated structure and a three-dimensional architecture with a strong stability, miniaturization, versatility and expandability. The integration of the three-dimensional architecture is realized on the basis of the integration of a through-silicon via and a silicon optical device, so that the integrated chip area can be smaller and the integration level can be higher, and the formed three-dimensional architecture has a smaller electrical signal delay and a higher bandwidth and speed. The surface electrode ion trap is integrated with a silicon single-photon avalanche detector or a silicon-based germanium single-photon avalanche detector, a silicon grating and/or a silicon nitride grating and a through-silicon via. After being powered on, the surface electrode ion trap is used to capture ions and trap same in a certain range. A laser source is coupled to the silicon grating and/or the silicon nitride grating by using any coupling mode such as end-face coupling. The laser is emitted to the ions via the silicon grating and/or the silicon nitride grating on three orientations to complete addressing. The ions can undergo energy level transition after being excited by light. After energy level transition, the ions can radiate fluorescent light. The fluorescent light is detected by the silicon single-photon avalanche detector or the silicon-based germanium single-photon avalanche detector, and the detection of quantum bit information is finally completed.

Classes IPC  ?

• H01L 31/0203 - Conteneurs; Encapsulations

Abrégé

Disclosed are a static random access memory (SRAM) cell, and a memory and an electronic device including such a SRAM cell. According to embodiments, the SRAM cell can comprise a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first through gate transistor and a second through gate transistor which are arranged on a substrate in two layers. Each transistor is a vertical transistor. The first pull-up transistor and the second pull-up transistor are disposed on the first layer, the first pull-down transistor, the second pull-down transistor, the first through gate transistor and the second through gate transistor are disposed on a second layer at a different height from the first layer. The area where the first pull-up transistor and the second pull-up transistor are located can at least partially overlap with the area where the first pull-down transistor, the second pull-down transistor, the first through gate transistor and the second through gate transistor are located in the vertical direction relative to an upper surface of the substrate.

Classes IPC  ?

• H01L 27/11 - Structures de mémoires statiques à accès aléatoire

Abrégé

A three-dimensional memory and a manufacturing method therefor. The three-dimensional memory comprises: a storage unit and a logic control unit having front surfaces fitting each other. The logic control unit is connected to a control circuit. The memory is characterized in that a second metal wire and a first metal wire of the storage unit are respectively arranged on upper and lower sides of a channel layer in the storage unit. The first metal wire and the second metal wire are both electrically connected to the control circuit. The second metal wire and the first metal wire are respectively arranged on the upper and lower sides of the channel layer in the storage unit. The first metal wire and the second metal wire are arranged separately, such that distribution of the metal wires is balanced, and deformation of the storage unit is reduced or avoided. The first metal wire and the second metal wire are arranged in a distributed manner, and therefore metal wiring is simplified, such that a layout of connecting lines between the first metal wire and the control circuit, and between the second metal wire and the control circuit are simple, thereby improving connection reliability and solving the problem of poor connection reliability caused by a complex layout and a process defect in the prior art.

Classes IPC  ?

• H01L 27/11529 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la région de circuit périphérique de régions de mémoire comprenant des transistors de sélection de cellules, p.ex. NON-ET

Abrégé

A storage unit and a manufacturing method therefor, and a three-dimensional memory, the storage unit comprising: a first conductivity type substrate; a trench layer stacked on the first conductivity type substrate along a first direction; a second conductivity type conduction layer, comprising a first part and second part passing therethrough, the first part being interposed between the first conductivity type substrate and the trench layer, and the second part being formed in a through hole penetrating the trench layer; a trench channel layer, passing through the trench layer and the first part of the second conductivity type conduction layer along a negative direction to the first direction and extending into the inside of the first conductivity type substrate; and an insulating layer positioned in the trench layer and surrounding the periphery of the trench channel layer; the first conductivity type substrate and the second conductivity type conduction layer respectively provide the carriers needed for read and erase operations. Good conduction can be implemented regardless of how the number of stacked layers of the memory cell increases, and is not affected by the processing problems caused by the continuous increase of the three-dimensional memory.

Classes IPC  ?

• H01L 27/1157 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
• H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
• H01L 27/115 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs

Abrégé

An L-shaped stepped word line structure and a fabrication method therefor, and a three-dimensional memory. The word line structure comprises: a plurality of L-shaped word line units, wherein one side of the long side of each L-shaped word line unit extends along a second direction and is adjacent to a gate line gap, and one side of the short side extends along a first direction and the short side comprises a word line lead-out end; and the word line lead-out ends are formed in a stepped laminated structure. The laminated structure comprises a plurality of laminated pairs formed by an insulating material. The region of one laminated layers in each laminated pair close to the gate line gap is used as a replacement metal region. Each replacement metal region comprises a short side region surface metal layer located on the surface and a short side region internal metal layer located at the interior. In the first direction, the length of the short side region surface metal layers is greater than the length of the short side region internal metal layers, and the word line lead-out ends correspond to the short side region surface metal layers. The word line is guaranteed to not short circuit even when excessively etched in circumstances in which the etching selection ratio is not high enough.

Classes IPC  ?

• H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U