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Classe IPC
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale 2
G06F 5/00 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées 2
G06F 15/00 - TRAITEMENT ÉLECTRIQUE DE DONNÉES NUMÉRIQUES Équipement de traitement de données en général 1
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p.ex. plusieurs processeurs de données à instruction unique 1
G06F 21/60 - Protection de données 1
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1.

METHOD AND APPARATUS FOR ACCELERATED FORMAT TRANSLATION OF DATA IN A DELIMITED DATA FORMAT

      
Numéro de document 02887022
Statut Délivré - en vigueur
Date de dépôt 2013-10-22
Date de disponibilité au public 2014-05-01
Date d'octroi 2021-05-04
Propriétaire IP RESERVOIR, LLC (USA)
Inventeur(s)
  • Henrichs, Michael John
  • Lancaster, Joseph M.
  • Chamberlain, Roger Dean
  • White, Jason R.
  • Sprague, Kevin Brian
  • Tidwell, Terry

Abrégé

Various methods and apparatuses are described for performing high speed format translations of incoming data, where the incoming data is arranged in a delimited data format. As an example, the data in the delimited data format can be translated to a fixed field format using pipelined operations. As another example, the data in the delimited data format can be translated to a mapped variable field format using pipelined operations. A reconfigurable logic device can be used in exemplary embodiments as a platform for the format translation.

Classes IPC  ?

  • G06F 5/00 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées

2.

METHOD AND APPARATUS FOR APPROXIMATE PATTERN MATCHING

      
Numéro de document 02650571
Statut Délivré - en vigueur
Date de dépôt 2007-04-24
Date de disponibilité au public 2007-11-15
Date d'octroi 2015-08-18
Propriétaire IP RESERVOIR, LLC (USA)
Inventeur(s) Taylor, David Edward

Abrégé

A system and method for inspecting a data stream for data segments matching one or more patterns each having a predetermined allowable error, which includes filtering a data stream for a plurality of patterns of symbol combinations with a plurality of parallel filter mechanisms, detecting a plurality of potential pattern piece matches, identifying a plurality of potentially matching patterns, reducing the identified plurality of potentially matching patterns to a set of potentially matching patterns with a reduction stage, providing associated data and the reduced set of potentially matching patterns, each having an associated allowable error, to a verification stage, and verifying presence of a pattern match in the data stream from the plurality of patterns of symbol combinations and associated allowable errors with the verification stage.

3.

FIRMWARE SOCKET MODULE FOR FPGA-BASED PIPELINE PROCESSING

      
Numéro de document 02640140
Statut Délivré - en vigueur
Date de dépôt 2007-01-22
Date de disponibilité au public 2007-08-02
Date d'octroi 2016-06-28
Propriétaire IP RESERVOIR, LLC (USA)
Inventeur(s)
  • Chamberlain, Roger D.
  • Shands, E.F. Berkley
  • Brodie, Benjamin C.
  • Henrichs, Michael
  • White, Jason R.

Abrégé

A firmware socket module is deployed on a reconfigurable logic device, wherein the firmware socket module has a communication path between itself and an entry point into a data processing pipeline, wherein the firmware socket module is configured to provide both commands and target data to the entry point in the data processing pipeline via the same communication path, wherein each command defines a data processing operation that is to be performed by the data processing pipeline, and wherein the target data corresponds to the data upon which the data processing pipeline performs its commanded data processing operation. Preferably, the firmware socket module is configured to provide the commands and target data in a predetermined order that is maintained throughout the data processing pipeline. Also, the firmware socket module may be configured to (1) access an external input descriptor pool buffer that defines the order in which commands and target data are to be provided to the data processing pipeline, and (2) transfer the commands and target data from an external memory to the data processing pipeline in accordance with the identified defined order. Results of the processing by the data processing pipeline are also returned to external memory by the firmware socket module, whereupon those results can be subsequently used by software executing on a computer system.

Classes IPC  ?

  • G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
  • G06F 9/38 - Exécution simultanée d'instructions
  • G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p.ex. plusieurs processeurs de données à instruction unique

4.

INTELLIGENT DATA PROCESSING SYSTEM AND METHOD USING FPGA DEVICES

      
Numéro de document 02523548
Statut Délivré - en vigueur
Date de dépôt 2004-05-21
Date de disponibilité au public 2005-05-26
Date d'octroi 2014-02-04
Propriétaire IP RESERVOIR, LLC (USA)
Inventeur(s)
  • Chamberlain, Roger D.
  • Franklin, Mark Allen
  • Indeck, Ronald S.
  • Cytron, Ron K.
  • Cholleti, Sharath R.

Abrégé

A data processing system comprising: a processing device; and a computer system having a system bus, wherein the computer system is configured to communicate with the processing device over the system bus to control an operation of the processing device; and wherein the processing device comprises a re- configurable logic device configured to receive and process streaming data through a pipeline deployed on the re-configurable logic device, the pipeline comprising a plurality of pipelined data processing engines, the plurality of pipelined data processing engines being configured to perform different processing operations, wherein the pipeline comprises a multi-functional pipeline, and wherein the re-configurable logic device further comprises a control processor, wherein the control processor is configured to controllably activate or deactivate each of the pipelined data processing engines in the pipeline and thereby define a function for the pipeline, the pipeline function being the combined functionality of each activated pipelined data processing engine in the pipeline.

Classes IPC  ?

  • G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale

5.

INTELLIGENT DATA PROCESSING SYSTEM AND METHOD USING FPGA DEVICES

      
Numéro de document 02836758
Statut Délivré - en vigueur
Date de dépôt 2004-05-21
Date de disponibilité au public 2005-05-26
Date d'octroi 2017-06-27
Propriétaire IP RESERVOIR, LLC (USA)
Inventeur(s)
  • Chamberlain, Roger D.
  • Franklin, Mark Allen
  • Indeck, Ronald S.
  • Cytron, Ron K.
  • Cholleti, Sharath R.

Abrégé

For a programmable logic device in communication with a mass storage medium, the programmable logic device being configured to process data moving to or from the mass storage medium in accordance with a template loaded thereon, the template defining one or more processing functions, each function having an associated performance characteristic for data processing performed thereby, a method for selecting a template for programming the programmable logic device, the method comprising: selecting a stored template from a plurality of stored templates for loading into the programmable logic device at least partially on the basis of the associated performance characteristics for each function defined by the templates.

Classes IPC  ?

  • G06F 15/00 - TRAITEMENT ÉLECTRIQUE DE DONNÉES NUMÉRIQUES Équipement de traitement de données en général
  • G06F 21/60 - Protection de données
  • G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

6.

INTELLEGENT DATA STORAGE AND PROCESSING USING FPGA DEVICES

      
Numéro de document 02759064
Statut Délivré - en vigueur
Date de dépôt 2004-05-21
Date de disponibilité au public 2005-03-24
Date d'octroi 2017-04-04
Propriétaire IP RESERVOIR, LLC (USA)
Inventeur(s)
  • Chamberlain, Roger D.
  • Brink, Benjamin M.
  • White, Jason R.
  • Franklin, Mark A.
  • Cytron, Ronald K.

Abrégé

A data processing apparatus comprising: a data storage device for storing data in a compressed format; a processor communicating with the data storage device to store data therein and process data retrieved therefrom; and a reconfigurable logic device for offloading a plurality of processing operations from the processor, the reconfigurable logic device comprising a hardware logic template configured as a data processing pipeline, the data processing pipeline comprising a decompression engine and a downstream search engine. The decompression engine and the search engine are configured to operate in a pipelined manner by performing their respective decompression and search operations simultaneously at hardware processing speeds such that the decompression engine performs the decompression operation on compressed data while at the same time the search engine performs the search operation on decompressed data that was previously decompressed by the decompression engine.

Classes IPC  ?

  • G06F 5/00 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées
  • G06F 9/06 - Dispositions pour la commande par programme, p.ex. unités de commande utilisant des programmes stockés, c. à d. utilisant un moyen de stockage interne à l'équipement de traitement de données pour recevoir ou conserver les programmes