SAMSUNG ELECTRONICS CO, LTD, (République de Corée)
Inventeur(s)
Fan, Su Chen
Pranatharthiharan, Balasubramanian
Greene, Andrew
Xie, Ruilong
Raymond, Mark, Victor
Lian, Sean
Abrégé
Techniques for forming self-aligned contacts by forming gate sidewall spacers and gates before forming the contacts are provided, in one aspect, a method of forming self-aligned contacts includes the steps of: forming multiple gate sidewall spacers on a substrate; burying the gate sidewall spacers In a dielectric; forming gate trenches by selectively rernoving the dielectric from: regions between the gate sidewall spacers in which gates will be formed; forming the gates in the gate trenches; forming contact trenches by selectively removing the dielectric from regions between the gate sidewall spacers in which the self-aligned contacts will be formed; and forming the self-aligned contacts in the contact trenches. A device structure having self-aligned contacts is also provided.
A method of mask correction where two independent process models are analyzed and co-optimized simultaneously. In the method, a first lithographic process model simulation is run on a computer system that results in generating a first mask size in a first process window. Simultaneously, a second hard mask open etch process model simulation is run resulting in generating a second mask size in a second process window. Each first lithographic process model and second hard mask open etch process model simulations are analyzed in a single iterative loop and a common process window (PW) optimized between lithography and etch is obtained such that said first mask size and second mask size are centered between said common PW. Further, an etch model form is generated that accounts for differences in an etched pattern due to variation in three-dimensional photoresist profile, the model form including both optical and density terms that directly relate to an optical image.
G03F 1/70 - Adaptation du tracé ou de la conception de base du masque aux exigences du procédé lithographique, p.ex. correction par deuxième itération d'un motif de masque pour l'imagerie
The present invention discloses a system and method for active power factor correction and current regulation in led circuit. The system (100) used in the LED driver circuit performs active PFC and current regulation through the dynamic input current wave shaping by limiting peak currents. The dynamic wave 5 shaping scheme is realized through hardware and firmware and is used to strike an optimal balance between current accuracy, Power factor, THD and peak inductor currents. The system (100) is versatile enough to improve PF and current accuracy in LED circuits and indimmers circuits.
G05F 1/00 - Systèmes automatiques dans lesquels les écarts d'une grandeur électrique par rapport à une ou plusieurs valeurs prédéterminées sont détectés à la sortie et réintroduits dans un dispositif intérieur au système pour ramener la grandeur détectée à sa va
4.
DYNAMIC BLEED SYSTEM AND METHOD FOR DYNAMIC LOADING OF A DIMMER USING EVENT DRIVEN ARCHITECTURE
The present invention discloses a dynamic bleed system and method for dynamic loading of a dimmer using event driven architecture for LED applications. An integrated event driven LED driver architecture is used to perform dynamic loading (bleed) of triac dimmer to effectively operate in low power LED applications. The bleeder circuit dynamically loads the dimmer when instantaneous cycle by cycle power falls below a specified value and shuts the bleed path when the power is above a specified value. This threshold is programmable with hysteresis and the loading pattern is programmable as well.
G09G 3/36 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p.ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice en commandant la lumière provenant d'une source indépendante utilisant des cristaux liquides
5.
A SYSTEM AND METHOD TO REGULATE PRIMARY SIDE CURRENT USING AN EVENT DRIVEN ARCHITECTURE IN LED CIRCUIT
The present invention discloses a system and method to regulate primary side current using an event driven architecture in led circuit. The system (100) performs a primary side regulation (PSR) of isolated or non-isolated LED driver topology such as fly back system. The primary side peak voltage/current is regulated to achieve desired secondary side currents without the need of additional external components. The architecture combines firmware and hardware to realize PSR. The method (200) may effectively combine input wave shaping (Active PFC), dimming and PSR to achieve accurate secondary side currents. The method (200) corrects the Peak Regulation Voltage/current (PRV) of primary loop to meet desired half cycle reference voltage/current, which in turn achieves the desired secondary loop current in led circuit.
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
In a method for utilizing social networking services of a user to perform online retail services, a processor retrieves a set of contacts, wherein the set of contacts includes a first group of contacts of a first networking service and a second group of contacts of a second networking service, wherein each contact in the set of contacts has a corresponding link to information about that contact. A processor receives a request for an action to be executed, wherein the request includes gifting information, wherein the gifting information specifies a required relationship between the user and the one or more contact of the set of contacts. A processor determines the one or more contacts that have the required relationship with the user, as specified by the gifting information. A processor causes the action to be executed based on the determined one or more contacts.
A conformal doping process for FinFET devices on a semiconductor substrate which includes NFET fins and PFET fins. In a first exemplary embodiment, an N-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in an N-type dopant from the N-type dopant composition into the NFET fins. A P-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in a P-type dopant from the P-type dopant composition into the PFET fins. In a second exemplary embodiment, one of the NFETfins and PFET fins may be covered with a first dopant composition and then a second dopant composition may cover both the NFET fins and the PFET fins followd by an anneal to drive in both dopants.
H01L 21/225 - Diffusion des impuretés, p.ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductrices; Redistribution des impuretés, p.ex. sans introduction ou sans élimination de matériau dopant supplémentaire en utilisant la diffusion dans ou hors d'un solide, à partir d'une ou en phase solide, p.ex. une couche d'oxyde dopée
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
8.
SYSTEM AND METHOD FOR COMMUNITY BASED MOBILE DEVICE PROFILING
A method, computer program product, and system is provided for community based mobile device profiling. In an implementation, a method may include receiving, via a first mobile device, a wireless signal associated with a second mobile device. The method may also include determining an identity of a user associated with the second mobile device. The method may further include establishing at least one setting of the first mobile device based upon, at least in part, a mobile device profile associated with the first mobile device and the identity of the user associated with the second mobile device.
H04W 8/20 - Transfert de données utilisateur ou abonné
9.
THREE-DIMENSIONAL PROCESSING SYSTEM HAVING MULTIPLE CACHES THAT CAN BE PARTITIONED, CONJOINED, AND MANAGED ACCORDING TO MORE THAN ONE SET OF RULES AND/OR CONFIGURATIONS
Three-dimensional processing systems are provided which have multiple layers of conjoined chips, wherein one or more chip layers include processor cores that share cache hierarchies over multiple chip layers. The caches can be partitioned, conjoined, and managed according to various sets of rules and configurations.
A method for providing a matrix material between a bonded pair of substrates with a homogeneous distribution of anisotropic filler particles is provided. Functionalized anisotropic filler particles are mixed uniformly with a matrix material to form a homogenous mixture. A bonded assembly of a first substrate and a second substrate with an array of electrical interconnect structures is placed within a vacuum environment. The homogenous mixture of the matrix material and the anisotropic filler particles is dispensed around the array of electrical interconnect structures. A gas is abruptly introduced into the vacuum environment to induce an implosion of the homogenous mixture. The implosion causes the homogenous mixture to fill the cavity between the first and second substrates without causing agglomeration of the anisotropic filler particles. The mixture filling the space between the first and second substrates has a homogenous distribution of the anisotropic filler particles.
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 21/58 - Montage des dispositifs à semi-conducteurs sur des supports
H01L 21/603 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement impliquant l'application d'une pression, p.ex. soudage par thermo-compression
H01L 21/4763 - Dépôt de couches non isolantes, p.ex. conductrices, résistives sur des couches isolantes; Post-traitement de ces couches
B29C 70/72 - Enrobage d'inserts avec une partie non enrobée, p.ex. extrémités ou parties terminales de composants électriques
11.
POLICY ENFORCEMENT USING NATURAL LANGUAGE PROCESSING
A term of use policy document defines permissible actions that may be implemented by a user using a computing device. A natural language processing (NLP)-based question and answer (Q&A) system is trained to understand the policy document. The device includes a management application that interacts with the Q&A system to identify a policy violation. When the user performs an action on the device, the application converts that action into an NLP query directed to the Q&A system to determine whether the action constitutes a violation. The query may be accompanied by metadata associated with the user, the device or its state. Upon receipt of the query and any associated metadata, the Q&A system determines if the user action is compliant with the policy and returns a response. Based on the response, the user's computing device may take an enforcement action, e.g., restricting or disabling functionality, or issuing a warning.
G06F 21/00 - Dispositions de sécurité pour protéger les calculateurs, leurs composants, les programmes ou les données contre une activité non autorisée
A method for semiconductor fabrication includes providing (404) channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed (406) for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.
ALD of HfxA1yCz films using hafnium chloride (HfC14) and Trimethylaluminum (TMA) precursors can be combined with post-deposition anneal processes and ALD liners to control the device characteristics in high-k metal-gate devices. Variation of the HfC14 pulse time allows for control of the A1 % incorporation in the HfxA1yCz film in the range of 10-13%. Combinatorial process tools can be employed for rapid electrical and materials characterization of various materials stacks. The effective work function (EWF) in metal oxide semiconductor capacitor (MOSCAP) devices with the HfxA1yCz work function layer coupled with ALD deposited HfO2 high-k gate dielectric layers was quantified to be mid-gap at ~4.6 eV. Thus, HfxA1yCz is a promising metal gate work function material allowing for the tuning of device threshold voltages (Vth) for anticipated multi-Vth integrated circuit (IC) devices.
C23C 16/04 - Revêtement de parties déterminées de la surface, p.ex. au moyen de masques
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
14.
HIGH PRODUCTIVITY COMBINATORIAL TECHNIQUES FOR TITANIUM NITRIDE ETCHING
Provided are methods of High Productivity Combinatorial testing of semiconductor substrates, each including multiple site isolated regions. Each site isolated region includes a titanium nitride structure as well as a hafnium oxide structure and/or a polysilicon structure. Each site isolated region is exposed to an etching solution that includes sulfuric acid, hydrogen peroxide, and hydrogen fluoride. The composition of the etching solution and/or etching conditions are varied among the site isolated regions to study effects of this variation on the etching selectivity of titanium nitride relative to hafnium oxide and/or polysilicon and on the etching rates. The concentration of sulfuric acid and/or hydrogen peroxide in the etching solution may be less than 7 % by volume each, while the concentration of hydrogen fluoride may be between 50 ppm and 200 ppm. In some embodiments, the temperature of the etching solution is maintained at between about 40C and 60C.
A method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process is disclosed, including a multi-step residue cleaning, including exposing the substrate to an aqua regia solution, followed by an exposure to a solution having hydrochloric acid and hydrogen peroxide. The SC2 solution can further react with remaining platinum residues, rendering it more soluble in an aqueous solution and thereby dissolving it from the surface of the substrate.
The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Embodiments of the invention provide a multi-step cleaning process, comprising exposing the substrate to a nitric acid solution after a first anneal, followed by an aqua regia solution after a second anneal. The substrate can be optionally exposed to a hydrochloric acid solution afterward to completely remove any remaining platinum residues.
Apparatus for providing semiconductor device with an analysis module to receive device information, a G-function processor producing an ordered relationship representation corresponding to an optimization parameter specification, and a power cell optimizer to produce an optimization parameter from the ordered relationship representation. A method for designing a semiconductor device includes receiving an optimization target specification; receiving an optimization parameter specification corresponding to an optimization parameter; receiving a the target parameter; receiving a G-function corresponding to an ordered relationship representation; optimizing the optimization parameter specification as a function of the predetermined G-function; and producing at least one optimized geometric layout parameter (GLP) by the optimizing, wherein the at least one GLP corresponds to an optimized power cell.
In semiconductor devices, integrity of a titanium nitride material (152) may be increased by exposing the material to an oxygen plasma (110) after forming a thin silicon nitride -based material. The oxygen plasma (110) may result in an additional passivation of any minute surface portions which may not be appropriately covered by the silicon nitride-based material. Consequently, efficient cleaning recipes, such as cleaning processes (111) based on SPM, may be performed after the additional passivation without undue material loss of the titanium nitride material (152). In this manner, sophisticated high-k metal gate stacks may be formed with a very thin protective liner material on the basis of efficient cleaning processes without unduly contributing to a pronounced yield loss in an early manufacturing stage.
In sophisticated manufacturing techniques, the work function and thus the threshold voltage of transistor elements may be adjusted in an early manufacturing stage by providing a work function adjusting species (254A) within the high-k dielectric material (253) with substantially the same spatial distribution in the gate dielectric materials of different thickness. After the incorporation of the work function adjusting species (254A), the final thickness of the gate dielectric materials may be adjusted by selectively forming an additional dielectric layer so that the further patterning of the gate electrode structures (250A, 250B) may be accomplished with a high degree of compatibility to conventional manufacturing techniques. Consequently, extremely complicated processes for re-adjusting the threshold voltages of transistors (260A, 260B) having a different thickness gate dielectric material may be avoided.
[041] A silicon photon detector device and methodology are provided for detecting incident photons in a partially depleted floating body SOI field-effect transistor (310) which traps charges created by visible and mid infrared light in a floating body region (304) when the silicon photon detector is configured in a detect mode, and then measures or reads the resulting enhanced drain current with a current detector in a read mode.
H01L 31/113 - Dispositifs sensibles au rayonnement infrarouge, visible ou ultraviolet caractérisés par un fonctionnement par effet de champ, p.ex. phototransistor à effet de champ à jonction du type conducteur-isolant-semi-conducteur, p.ex. transistor à effet de champ métal-isolant-semi-conducteur
21.
TRANSISTOR-BASED MEMORY CELL AND RELATED OPERATING METHODS
A loadless static random access memory cell (200) includes four transistors (202, 204, 206, 208). The first transistor (202) has a gate terminal (220) corresponding to a word line, a source/drain terminal (222) corresponding to a first bit line (212), and a drain/source terminal (224) corresponding to a first storage node (226). The second transistor (204) has a gate terminal (230) corresponding to the word line (210), a source/drain terminal (232) corresponding to a second bit line (214), and a drain/source terminal (234) corresponding to a second storage node (236). The third transistor (206) has a gate terminal (240) coupled to the second storage node (236), a drain terminal (242) coupled to the first storage node (226), a source terminal (244) corresponding to a reference voltage, and a body terminal (246) directly connected to the third gate terminal (240). The fourth transistor (208) has a gate terminal (250) coupled to the first storage node (226), a drain terminal (252) coupled to the second storage node (236), a source terminal (254) corresponding to the reference voltage, and a body terminal (256) directly connected to the fourth gate terminal (250).
G11C 11/412 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules avec réaction positive, c. à d. des cellules ne nécessitant pas de rafraîchissement ou de régénération de la charge, p.ex. multivibrateur bistable, déclencheur de Schmitt utilisant uniquement des transistors à effet de champ
H01L 21/8244 - Structures de mémoires statiques à accès aléatoire (SRAM)
H01L 27/11 - Structures de mémoires statiques à accès aléatoire
22.
LEAKAGE CONTROL IN FIELD EFFECT TRANSISTORS BASED ON AN IMPLANTATION SPECIES INTRODUCED LOCALLY AT THE STI EDGE
In a static memory cell, the failure rate upon forming contact elements connecting an active region (202C) with a gate electrode structure (210A) formed above an isolation region (203) may be significantly reduced by incorporating an implantation species at a tip portion of the active region (202C) through a sidewalS (203S) of the isolation trench (203T) prior to filling the same with an insulating material. The implantation species may represent a P-type dopant species and/or an inert species for significantly modifying the material characteristics at the tip portion of the active region (202C),
H01L 21/8244 - Structures de mémoires statiques à accès aléatoire (SRAM)
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
H01L 27/11 - Structures de mémoires statiques à accès aléatoire
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
23.
METHOD OF FORMING A MOLECULAR MEMORY ELEMENT IN A VIA HOLE
Memory cells in integrated circuit devices may be formed on the basis of functional molecules (120) which may be positioned within via openings (111 ) on the basis of appropriate patterning techniques, which may also be used for forming semiconductor-based integrated circuits. Consequently, memory cells may be formed on a ''molecular" level without requiring extremely sophisticated patterning regimes, such as electron beam lithography and the like.
H01L 27/28 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants qui utilisent des matériaux organiques comme partie active, ou qui utilisent comme partie active une combinaison de matériaux organiques et d'autres matériaux
G11C 13/02 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou utilisant des éléments dont le fonctionnement dépend d'un changement chimique
H01L 51/05 - Dispositifs à l'état solide qui utilisent des matériaux organiques comme partie active, ou qui utilisent comme partie active une combinaison de matériaux organiques et d'autres matériaux; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de tels dispositifs ou de leurs parties constitutives spécialement adaptés au redressement, à l'amplification, à la génération d'oscillations ou à la commutation et ayant au moins une barrière de potentiel ou une barrière de surface; Condensateurs ou résistances à l'état solide, ayant au moins une barrière de potentiel ou une barrière de surface
H01L 51/00 - Dispositifs à l'état solide qui utilisent des matériaux organiques comme partie active, ou qui utilisent comme partie active une combinaison de matériaux organiques et d'autres matériaux; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de tels dispositifs ou de leurs parties constitutives
24.
SEMICONDUCTOR DEVICE INCLUDING A STRESS BUFFER MATERIAL FORMED ABOVE A LOW-K METALLIZATION SYSTEM
A bump structure or pillar structure formed above a metallization system of a complex semiconductor device may include a stress buffer layer (260), which may efficiently distribute the resulting mechanical stress which may typically occur during the chip package interaction due to a thermal mismatch of these components. The stress buffer layer (260) comprises copper-based buffer regions (265) that cover a significant portion of the overall surface, wherein a thickness of approximately 3- 10 μm may also be used. Moreover, the buffer regions (265) may efficiently replace aluminum as a terminal metal active region.
H01L 23/485 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées formées de structures en couches comprenant des couches conductrices et isolantes, p.ex. contacts planaires
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
25.
UNIFORM HIGH-K METAL GATE STACKS BY ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A METAL SPECIES PRIOR TO GATE PATTERNING
Sophisticated gate electrode structures (235 A, 235B) for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material (212) and subsequently a common gate layer stack is deposited and subsequently patterned.
Methods for fabricating FinFET structures with stress-inducing source/drain-forming spacers and FinFET structures having such spacers are provided herein. In one embodiment, a method for fabricating a FinFET structure comprises fabricating a plurality of parallel fins overlying a semiconductor substrate. Each of the fins has sidewalls. A gate structure is fabricated overlying a portion of each of the fins. The gate structure has sidewalls and overlies channels within the fins. Stress-inducing sidewall spacers are formed about the sidewalls of the fins and the sidewalls of the gate structure. The stress-inducing sidewall spacers induce a stress within the channels. First conductivity-determining ions are implanted into the fins using the stress-inducing sidewall spacers and the gate structure as an implantation mask to form source and drain regions within the fins.
Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode (411) and a P+? substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain (415), through a conductive contact (451), a metal line (459), a second conductive contact (453), an SOI diode (411), isolated from the transistor (409), a third conductive contact (455), a second conductive line (461), and a fourth conductive contact (457) to a P+?-doped substrate contact (449) in the bulk silicon layer (403) of the SOI substrate.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
28.
SEMICONDUCTOR DEVICES WITH IMPROVED LOCAL MATCHING AND END RESISTANCE OF DIFFUSION RESISTORS
Semiconductor devices are formed with reduced variability between close proximity resistors, improved end resistances, and reduced random dopant mismatch. Embodiments include ion implanting a dopant, such as B, at a relatively high dosage, e.g. about 4 to about 6keV, and at a relatively low implant energy, e.g., about 1.5 to about 2E15/cm2.
H01L 21/329 - Procédés comportant plusieurs étapes pour la fabrication de dispositifs du type bipolaire, p.ex. diodes, transistors, thyristors les dispositifs comportant une ou deux électrodes, p.ex. diodes
H01L 27/07 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive les composants ayant une région active en commun
29.
METHOD AND PROCESSOR FOR IMPROVED AES ENCRYPTION AND DECRYPTION
Encrypting information involving the execution of a first instruction and a second instruction on a processor. The first instruction causes the processor to perform an AddRoundKey transformation followed by a ShiftRows transformation. The second instruction causes the processor to perform a ShiftRows transformation followed by a MixColumns transformation. These instructions are useful for performing AES encryption. The first and second instructions also have inverse modes that may be used to perform AES decryption.
H04L 9/06 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p.ex. système DES
30.
ENHANCED ELECTROMIGRATION PERFORMANCE OF COPPER LINES IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES BY SURFACE ALLOYING
In sophisticated semiconductor devices, the electromigration performance of copper metal lines at the top interface thereof may be enhanced by forming a copper alloy (132C) that is locally restricted to the interface (132S). To this end, an appropriate alloy-forming species, such as aluminum, may be provided on the basis of a non-masked deposition process and may be subsequently removed by a non-masked etch process, wherein the characteristic of the resulting alloy may be adjusted during an intermediate heat treatment.
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
31.
ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A GATE DIELECTRIC CAP LAYER MATERIAL PRIOR TO GATE DIELECTRIC STABILIZATION
Sophisticated gate electrode structures may be formed by providing a cap layer (121) including a desired species that may diffuse into the gate dielectric material (110) prior to performing a treatment for stabilizing the sensitive gate dielectric material (110). In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.
In a semiconductor device comprising sophisticated high-k metal gate structures formed in accordance with a replacement gate approach, semiconductor-based resistors may be formed above isolation structures (103D) substantially without being influenced by the replacement gate approach. Consequently, enhanced area efficiency may be achieved compared to conventional strategies, in which the resistive structures may have to be provided on the basis of a gate electrode metal, while, nevertheless, a low parasitic capacitance may be accomplished due to providing the resistive structures above the isolation structure.
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
33.
INTERCONNECT STRUCTURE FOR A SEMICONDUCTOR DEVICE WITH A RESILIENT STRESS ABSORBER AND RELATED METHOD OF MANUFACTURE
A semiconductor device (50) having a device substrate (102) is provided The semiconductor device (50) comprises an electrically conductive pad (110) formed overlying the device substrate (102) an electrically conductive platform (160) formed overlying the electrically conductive pad (110) and a pillar interconnect (180) formed on the electrically conductive platform (160) the electrically conductive platform (160) having a perimeter portion (162) extending away from the electrically conductive pad (110) and a capping portion (170) atop the perimeter portion (162), wherein the electrically conductive platform (160) encloses a cavity located between the capping portion (170), the perimeter portion (162) and the electrically conductive pad (110), a cushioning material (140) being disposed in the cavity, the cushioning material (140) being intended to act as a resilient stress absorber upon application of force on the pillar interconnect (180).
H01L 23/485 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées formées de structures en couches comprenant des couches conductrices et isolantes, p.ex. contacts planaires
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
34.
METAL OXIDE SEMICONDUCTOR DEVICES HAVING DOPED SILICON-COMPRISING CAPPING LAYERS AND METHODS OF MANUFACTURING THE SAME
Methods are provided for forming a semiconductor device (10, 100) comprising a semiconductor substrate (14, 110). In one embodiment, the method includes the steps of: forming a high-k dielectric layer (24, 140) overlying the semiconductor substrate; forming a metal-comprising gate layer (48, 166) overlying the high-k dielectric layer; forming a doped silicon-comprising capping layer (52, 170) overlying the metal-comprising gate layer; and depositing a silicon-comprising gate layer (60, 178) overlying the doped silicon-comprising capping layer.
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/51 - Matériaux isolants associés à ces électrodes
35.
SHORT CHANNEL TRANSISTOR WITH REDUCED LENGTH VARIATION BY USING AMORPHOUS ELECTRODE MATERIAL DURING IMPLANTATION
In sophisticated transistor elements, enhanced profile uniformity along the transistor width direction may be accomplished by using a gate material (212) in an amorphous state, thereby reducing channeling effects and line edge roughness. In sophisticated high-k metal gate approaches, an appropriate sequence may be applied to avoid a change of the amorphous state prior to performing the critical implantation processes for forming drain and source extension regions (204) and halo regions (205).
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 21/266 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions en utilisant des masques
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 21/3213 - Gravure physique ou chimique des couches, p.ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
H01L 29/51 - Matériaux isolants associés à ces électrodes
36.
ETCHING SYSTEM AND METHOD FOR FORMING MULTIPLE POROUS SEMICONDUCTOR REGIONS WITH DIFFERENT OPTICAL AND STRUCTURAL PROPERTIES ON A SINGLE SEMICONDUCTOR WAFER
Disclosed is an electrochemical etching system with localized etching capability. The system allows multiple different porous semiconductor regions to be formed on a single semiconductor wafer. Localized etching is achieved through the use of one or more stationary and/or movable computer-controlled inner containers operating within an outer container. The outer container holds the electrolyte solution and acts as an electrolyte supply source for the inner container(s). The inner container(s) limit the size of the etched region of the semiconductor wafer by confining the electric field. Additionally, the current amount passing through each inner container during the electrochemical etching process can be selectively adjusted to achieve a desired result within the etched region. Localized etching of sub-regions within each etched region can also be achieved through the use of different stationary and/or moveable electrode structures and shields within each inner container. Also disclosed are associated method embodiments.
C25F 7/00 - PROCÉDÉS POUR LE TRAITEMENT D'OBJETS PAR ENLÈVEMENT ÉLECTROLYTIQUE DE MATIÈRE; APPAREILLAGES À CET EFFET Éléments de construction des cellules, ou leur assemblage, pour l'enlèvement électrolytique de matières d'objets; Entretien ou conduite
C25F 3/14 - Attaque de surface localisée, c. à d. gravure
A data processing device [100] is disclosed that includes multiple processing cores [110, 120, 130], where each core is associated with a corresponding cache [112, 122, 132]. When a processing core is placed into a first sleep mode [220], the data processing device initiates a first phase [220]. If any cache probes are received at the processing core during the first phase, the cache probes are serviced [230]. At the end of the first phase, the cache corresponding to the processing core is flushed [240], and subsequent cache probes are not serviced at the cache. Because it does not service the subsequent cache probes, the processing core can therefore enter another sleep mode, allowing the data processing device to conserve additional power.
Methods of fabricating a semiconductor device (100) on and in a semiconductor substrate (110) having a first region (180) and a second region (200) are provided. In accordance with an exemplary embodiment of the invention, a method comprises forming a first gate stack (124) overlying the first region (180) and a second gate stack (128) overlying the second region (200), etching into the substrate (110) first recesses (142) and second recesses (142), the first recesses (142) aligned at least to the first gate stack (124) in the first region (180), and the second recesses (142) aligned at least to the second gate stack (128) in the second region (200), epitaxially growing a first stress-inducing monocrystalline material (150) in the first and second recesses (142), removing the first stress-inducing monocrystalline material (150) from the first recesses (142), and epitaxially growing a second stress-inducing monocrystalline material (170) in the first recesses (142), wherein the second stress-inducing monocrystalline material (170) has a composition different from the first stress-inducing monocrystalline material (150).
A method for determining an operating point of a shared resource. The method includes receiving indications of access demand to a shared resource from each of a plurality of functional units and determining a maximum access demand from among the plurality of functional units based on their respective indications. The method further includes determining a required operating point of the shared resource based on the maximum access demand, wherein the shared resource is shared by each of the plurality of functional units, comparing the required operating point to a present operating point of the shared resource, and changing to the required operating point from the present operating point if the required and present operating points are different.
Electromigration behavior in complex metallization systems of semiconductor devices may be enhanced at critical areas between a metal line and a via by locally forming a copper/silicon compound. In some illustrative embodiments, the formation of the copper/ silicon compound may be combined with other treatments for cleaning the exposed surface areas and/or modifying the molecular structure thereof.
Bonding wires (252A) for sophisticated bonding applications may be efficiently formed on the basis of a corresponding template device (200) that may be formed on the basis of semiconductor material (201), such as silicon, in combination with associated fabrication techniques, such as lithography and etch techniques. Hence, any appropriate diameter and cross-sectional shape may be obtained with a high degree of accuracy and reliability.
In sophisticated semiconductor devices (200), stress-inducing materials (230, 240) may be provided above the basic transistor devices (222) without any etch control or etch stop materials, thereby enabling an efficient de-escalation of the surface topography, in particular above field regions including closely spaced polysilicon lines (222). Furthermore, an additional stress-inducing material (235) may be provided on the basis of the superior surface topography, thereby providing a highly efficient strain-inducing mechanism in performance-driven transistor elements (222P, 222N).
A semiconductor package is provided having reduced tensile stress. The semiconductor package includes a package substrate and a semiconductor die. The semiconductor die is coupled electrically and physically to the package substrate and includes a stress relieving layer incorporated therein. The stress relieving layer has a predetermined structure and a predetermined location within the semiconductor die for reducing tensile stress of the semiconductor package during heating and cooling of the semiconductor package.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
44.
SEMICONDUCTOR DEVICE COMPRISING EFUSES OF ENHANCED PROGRAMMING EFFICIENCY
In sophisticated integrated circuits, an electronic fuse (200) may be formed such that an increased sensitivity to electromigration may be accomplished by including at least one region of increased current density. This may be accomplished by forming a corresponding fuse region (203) as a non-linear configuration, wherein at corresponding connection portions of linear segments, the desired enhanced current crowding may occur during the application of the programming voltage. Hence, increased reliability and more space- efficient layout of the electronic fuses may be accomplished.
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
45.
MULTIPLE GATE TRANSISTOR HAVING HOMOGENOUSLY SILICIDED FIN END PORTIONS
In a multiple gate transistor, the plurality of fins of the drain or source (211) of the transistor (200) are electrically connected to each other by means of a common contact element (243), wherein enhanced uniformity of the corresponding contact regions (235) may be accomplished by an enhanced silicidation process sequence. For this purpose, the fins may be embedded into a dielectric material (230) in which an appropriate contact opening (230A) may be formed to expose end faces (210F) of the fins (210), which may then act as silicidation surface areas.
In a CMOS manufacturing process flow, a cap layer (151C) formed on top of a gate electrode material (151 A) may be maintained throughout the entire implantation sequence for defining the drain and source regions (154) and may be removed during an etch process in which the width of a sidewall spacer structure (155) may be reduced so as to reduce a lateral offset of metal suicide regions (156) and of a stressed dielectric material. Thus, overall enhanced transistor performance may be obtained while nevertheless providing a high degree of compatibility with existing CMOS process strategies.
A device that includes an electronic device referred to as an integrated circuit interposer (110, 310, 810, 910) is disclosed. The integrated circuit includes a voltage regulator module (140, 340, 600, 700, 940). The interposer is attached to an electronic device (120, 850, 950), such as another integrated circuit, and facilitates control and distribution of power to the electronic device. The integrated circuit interposer (110, 210, 810, 910) can also conduct signaling between the attached electronic device (120, 850, 950) and another electronic device. The voltage regulator module (140, 340, 600, 700, 940) at the integrated circuit interposer can be configured to provide a voltage reference signal to the attached electronic device (120, 850, 950). Generation of the voltage reference signal by the integrated circuit interposer (110, 310, 810, 910) can be enabled or disabled and the value of the voltage reference signal can be adjusted, depending on operating requirements of the electronic device (120, 850, 950).
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
G06F 1/26 - Alimentation en énergie électrique, p.ex. régulation à cet effet
G06F 1/18 - Installation ou distribution d'énergie
H05K 1/14 - Association structurale de plusieurs circuits imprimés
48.
ENHANCED WIRE BOND STABILITY ON REACTIVE METAL SURFACES OF A SEMICONDUCTOR DEVICE BY ENCAPSULATION OF THE BOND STRUCTURE
The wire bond structure of sophisticated metallization systems, for instance based on copper, may be provided without a terminal aluminum layer and without any passivation layers for exposed copper surfaces (212S) by providing a fill material (250) after the wire bonding process in order to encapsulate at least the sensitive metal surfaces (212S) and a portion of the bond wire (230). Hence, significant cost reduction, reduced cycle times and a reduction of the required process steps may be accomplished independently from the wire bond materials used. Thus, integrated circuits requiring a sophisticated metallization system may be connected by wire bonding to the corresponding package (260) or carrier substrate with a required degree of reliability based on a corresponding fill material (250) for encapsulating at least the sensitive metal surfaces (212S).
H01L 23/24 - Matériaux de remplissage caractérisés par le matériau ou par ses propriétes physiques ou chimiques, ou par sa disposition à l'intérieur du dispositif complet solide ou à l'état de gel, à la température normale de fonctionnement du dispositif
H01L 23/485 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées formées de structures en couches comprenant des couches conductrices et isolantes, p.ex. contacts planaires
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
49.
METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED STRESSOR AND EXTENSION REGIONS
Methods are provided for fabricating a MOS transistor having self-aligned stressor and extension regions. A method comprises forming a gate stack overlying a layer of semiconductor material and forming a spacer about sidewalls of the gate stack. The method further comprises forming cavities in the layer of semiconductor material, wherein the cavities are substantially aligned with the spacer. The method further comprises forming a stress-inducing semiconductor material in the cavities, and implanting ions of a conductivity- determining impurity type into the stress-inducing semiconductor material using the gate stack and the spacer as an implantation mask.
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
50.
PERFORMANCE ENHANCEMENT IN PMOS AND NMOS TRANSISTORS ON THE BASIS OF SILICON/CARBON MATERIAL
A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type (150P, 150N) on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities (103P, 103N) prior to forming the corresponding strained semiconductor alloy (153), thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor (150P) and an N-channel transistor (150N), while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished.
Semiconductor devices and methods for fabricating semiconductor devices are provided. One exemplary method comprises providing a silicon-comprising substrate having a first surface, etching a recess into the first surface, the recess having a side surface and a bottom surface, implanting carbon ions into the side surface and the bottom surface, and forming an impurity-doped, silicon-comprising region overlying the side surface and the bottom surface.
A method for fabricating a gated lateral thyristor-based memory device (gltram) is provided. A semiconductor layer (406) is provided that includes first, second, third and fourth well regions (463, 471, 486, 493) of a first conductivity type in the semiconductor layer 406. A first gate structure (465/408) overlies the first well region (463), a second gate structure (475/408) overlies the second well region (471), a third gate structure (485/408) overlies the third well region (486) and is integral with the second gate structure (475/408), and a fourth gate structure (495/408) overlies the fourth well region (493). Sidewall spacers (467) are formed adjacent a first sidewall (414) of the first gate structure (465/408) and sidewalls (412, 413, 416, 417, 418, 419) of the second through fourth gate structures (475/408, 485/408, 495/408). In addition, an insulating spacer block (469) is formed overlying a portion (468) of the first well region (463) and a portion of the first gate structure (465/408). The insulating spacer block (.469) is adjacent a second sidewall (415) of the first gate structure (465/408). A first source region (472) is formed adjacent the first gate structure (465/408), a common drain/cathode region (474/464) is formed between the first and second gate structures (465/408, 475/408), a second source region (482) is formed adjacent the third gate structure (485/408), a common drain/source region (484/492) is formed between the third and fourth gate structures (485/408, 495/408), and a drain region (494) is formed adjacent the fourth gate structure (495/408). A first base region (468) is formed that extends into the first well region (463) under the insulating spacer block (467) adjacent the first gate structure (465/408), and an anode region (466) is formed in the first well region (463) that extends into the first well region (463) adjacent the first base region (468).
H01L 27/102 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants bipolaires
G11C 11/39 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des thyristors
H01L 29/74 - Dispositifs du type thyristor, p.ex. avec un fonctionnement par régénération à quatre zones
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
53.
SEMICONDUCTOR DEVICE COMPRISING A CHIP INTERNAL ELECTRICAL TEST STRUCTURE ALLOWING ELECTRICAL MEASUREMENTS DURING THE FABRICATION PROCESS
A test structure or a circuit element acting temporarily as a test structure may be provided within the die region (210) of sophisticated semiconductor devices, while probe pads (241A, 241B) may be located in the frame (230) in order to not unduly consume valuable die area. The electrical connection between the test structure and the probe pads (241A, 241B) may be established by a conductive path (245, 246) including a buried portion (245A, 246A), which extends from the die region (210) into the frame below a die seal (220), thereby maintaining the electrical and mechanical characteristics of the die seal (220).
In an embodiment, a system memory (20) stores a set of input/output (I/O) translation tables (36). One or more I/O devices (22) initiate direct memory access (DMA) requests including virtual addresses. An I/O memory management unit (IOMMU) (26) is coupled to the I/O devices (22) and the system memory (20), wherein the IOMMU (26) is configured to translate the virtual addresses in the DMA requests to physical addresses to access the system memory (20) according to an I/O translation mechanism implemented by the IOMMU (26). The IOMMU (26) comprises one or more caches (30), and is configured to read translation data from the I/O translation tables (36) responsive to a prefetch command (148) that specifies a first virtual address. The reads are responsive to the first virtual address and the I/O translation mechanism, and the IOMMU (26) is configured to store data in the caches (30) responsive to the read translation data.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
A method is disclosed which includes implanting an inert species in a layer of a gate electrode material (205A), the gate electrode material being formed above a substrate (201) and having a P-doped layer portion and an N-doped layer portion, forming a first gate electrode (205P) from the P-doped layer portion and a second gate electrode (205N) from the N-doped layer portion, performing a wet chemical cleaning process, and forming a first transistor (200B) on the basis of the first gate electrode (205P) and a second transistor (200A) on the basis of the second gate electrode (205N).
Processor overclocking techniques are disclosed. Upon automatically determining (310) that overclocking entry criteria are satisfied, one or more cores (230) are clocked (320) above their standard operation frequencies. The cores (230) may be overclocked until one or more exit criteria are satisfied (330). At that point, an exit procedure is performed (340), with the one or more overclocked cores (230) return to their normal operating frequency.
By providing a CMP stop layer in a metal gate stack (160), the initial height thereof may be efficiently reduced after the definition of the deep drain and source areas (152), thereby providing enhanced process conditions for forming highly stressed dielectric materials. Consequently, the dielectric material (161) may be positioned more closely to the channel region substantially without deteriorating gate conductivity.
In a dual stress liner approach, an intermediate etch stop material (234) may be provided on the basis of a plasma-assisted oxidation process (250) rather than by deposition so the corresponding thickness (234T) of the etch stop material (234) may be reduced. Consequently, the resulting aspect ratio may be less pronounced compared to conventional strategies, thereby reducing deposition-related irregularities which may translate into a significant reduction of yield loss, in particular for highly scaled semiconductor devices (200).
By providing a body controlled double channel transistor (200, 400, 500P, 500N), increased functionality in combination with enhanced stability may be accomplished. For instance, flip flop circuits (550) usable for static RAM cells (560) may be formed on the basis of the body controlled double channel transistor (200, 400, 500P, 500N), thereby reducing the number of transistors required per cell, which may result in increased information density.
A computer system (100) includes a main processor (10) and a security control processor (20) that is coupled to the main processor and configured to control and monitor an operational state of the main processor. To ensure the computer system may be trusted, the security control processor may be configured to hold the main processor in a slave mode during initialization of the security control processor such that the main processor is not operable to fetch and execute instructions from an instruction source external to the main processor, for example. In addition, the security control processor may be configured to initialize the operational state of the main processor to a predetermined state by transferring to the main processor via a control interface (26) one or more instructions and to cause the main processor to execute the one or more instructions while the main processor is held in the slave mode.
G06F 21/00 - Dispositions de sécurité pour protéger les calculateurs, leurs composants, les programmes ou les données contre une activité non autorisée
61.
ALTERNATE ADDRESS SPACE TO PERMIT VIRTUAL MACHINE MONITOR ACCESS TO GUEST VIRTUAL ADDRESS SPACE
In one embodiment, a processor (30) supports an alternate address space during execution of non-guest code (such as a minivisor (172) or a virtual machine monitor (VMM) (18)). The alternate address space may be the guest address space. An instruction in the minivisor ( 172)/VMM (18) may specify the alternate address space for a data access, permitting the minivisor (172) /VMM (18) to read guest memory state via the alternate address space. In another embodiment, a processor (30) may implement a page table base address register (mCR3) dedicated for the minivisor's (172) use. In still another embodiment, the minivisor (172) may be implemented as a specified entry point in the VMM address space (220).
A processor core (100) includes an instruction decode unit (140) that may dispatch a same integer instruction stream to a plurality of integer execution units (154a, 154b) and may consecutively dispatch a same floating-point instruction stream to a floating-point unit (160). The integer execution units may operate in lock-step such that during each clock cycle, each respective integer execution unit executes the same integer instruction. The floating-point unit may execute the same floating-point instruction stream twice. Prior to the integer instructions retiring, compare logic (158a, 158b, 163) may detect a mismatch between execution results from each of the integer execution units. In addition, prior to the results of the floating-point instruction stream transferring out of the floating-point unit, the compare logic may also detect a mismatch between results of execution of each consecutive floating-point instruction stream. Further, in response to detecting any mismatch, the compare logic may cause instructions causing the mismatch to be re-executed.
G06F 11/16 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p.ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
63.
TEMPERATURE MONITORING IN A SEMICONDUCTOR DEVICE BY THERMOCOUPLES DISTRIBUTED IN THE CONTACT STRUCTURE
By forming thermocouples in a contact structure of a semiconductor device, respective extension lines of the thermocouples may be routed to any desired location within the die, without consuming valuable semiconductor area in the device layer. Thus, an appropriate network of measurement points of interest may be provided, while at the same time allowing the application of well-established process techniques and materials. Hence, temperature-dependent signals may be obtained from hot spots substantially without being affected by design constraints in the device layer.
G01K 7/02 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments thermo-électriques, p.ex. des thermocouples
G01K 1/14 - Supports; Dispositifs de fixation; Dispositions pour le montage de thermomètres en des endroits particuliers
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
G01K 1/02 - Moyens d’indication ou d’enregistrement spécialement adaptés aux thermomètres
64.
MECHANISM FOR PROFILING PROGRAM SOFTWARE RUNNING ON A PROCESSOR
A processor (12) having one or more processor cores (15) includes execution logic that may execute instructions including one or more processes (Pl, P2). Each process may include one or more execution threads (Tl, T2). The processor also includes a profiling mechanism that includes monitor logic (18) and a monitor process (monitor code). The monitor logic may monitor the one or more processes and provide access to performance data associated with the one or more processes without interrupting a flow of control of the one or more processes being monitored. The monitor process may gather the performance data. In addition, the monitor process may include program instructions executable by the one more processor cores while operating in user mode.
A processor comprising one or more control units, a plurality of first execution units, and one or more second execution units. Fetched instructions that conform to a processor instruction set are dispatched to the first execution units. Fetched instructions that conform to a second instruction set (different from the processor instruction set) are dispatched to the second execution units. The second execution units may be configured to performing graphics operations, or other specialized functions such as executing Java bytecode, managed code, video/audio processing operations, encryption/decryption operations etc. The second execution units may be configured to operate in a coprocessor- like fashion. A single control unit may handle the fetch, decode and scheduling for all the executions units. Alternatively, multiple control units may handle different subsets of the executions units.
Various sockets (20, 320) for multiple sizes of chip package substrates (40, 335) (50, 337) are disclosed. In one aspect, an apparatus is provided that includes a socket (20, 320) that has a peripheral wall (120, 340) defining an interior space (140, 350) adapted to receive either of a first semiconductor chip package substrate (40, 335) and a second semiconductor chip package substrate (50, 337). The first semiconductor chip package substrate (40, 335) has a first size and a first plurality of structural features (160a, 420a) and the second semiconductor chip package substrate (50, 337) has a second size different than the first size and a second plurality of structural features(180a, 490a). The socket (20, 320) has a third plurality of structural features (130a, 130b, 390a) operable to engage the structural features of either of semiconductor chip package substrates to selectively enable the first semiconductor chip package substrate (40, 335) to be located at a first preselected position in the interior space (140, 350) and the second semiconductor chip package substrate (50, 337) to be located at a second preselected position in the interior space (140, 350).
A system and method are set forth which combine an ability to view video with an ability to access computer programs. In certain embodiments, the media system provides access to movies, music and photos in a visually appealing three dimensional environment. Also, in certain environment, the media system presents a three dimensional navigation tool (such as a three dimensional wheel) on which multiple media files are presented. Also, in certain embodiments, a user may access both local and remote media files via the media system. Also, in certain embodiments, the media system provides on demand integration (such as Orb integration) while providing a consistent user interface such that access to local and remote content is seamless.
By providing an implantation blocking material (258) on the gate electrode structures (252) of advanced semiconductor devices (200) during high energy implantation processes (203), the required shielding effect with respect to the channel regions (255) of the transistors (250A, 250B) may be accomplished. In a later manufacturing stage, the implantation blocking portion (258) may be removed to reduce the gate electrode height (253H) to a desired level in order to enhance the process conditions during the deposition of an interlayer dielectric material (210), thereby significantly reducing the risk of creating irregularities, such as voids, in the interlayer dielectric material (210), even in densely packed device regions.
A system and method for obtaining coherence permission for speculative prefetched data. A memory controller stores an address of a prefetch memory line in a prefetch buffer. Upon allocation of an entry in the prefetch buffer a snoop of all the caches in the system occurs. Coherency permission information is stored in the prefetch buffer. The corresponding prefetch data may be stored elsewhere. During a subsequent memory access request for a memory address stored in the prefetch buffer, both the coherency information and prefetched data may be already available and the memory access latency is reduced.
A first DRAM device (11) comprises a first input connected to a first trace line (21) to receive an address signal and a second input is connected to receive an operating voltage, such as Vdd. A second DRAM device comprises a first input connected to the first trace line (21) to receive the address signal and a second input to receive the operating voltage. A first signal termination structure (20) is connected to the first trace line, wherein the first signal termination structure is to terminate the first trace line to the operating voltage.
A semiconductor structure (300) comprises a semiconductor substrate (301). A layer of an electrically insulating material (304) is formed over the semiconductor substrate (301). An electrically conductive feature (312) is formed in the layer of electrically insulating material (304). A first layer of a semiconductor material (320) is formed between the electrically conductive feature (312) and the layer of electrically insulating material (304).
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
72.
METHOD AND APPARATUS FOR DYNAMICALLY DETERMINING TESTER RECIPES
A method includes retrieving a group test parameter determined based on test results associated with a plurality of integrated circuit devices (140). A particular integrated circuit device (140) is tested using a test program and the group test parameter.
A method for producing a plurality of clock signals. The method includes generating a reference clock signal using a phase locked loop (PLL). The reference clock signal is then provided to each of a plurality of clock divider units which each divide the received reference clock signal to produce a corresponding divided clock signal. The method then removes one or more clock cycles (per a given number of cycles) in order to produce a plurality of domain clock signals each having an effective frequency based on a frequency and a number of cycles removed from the correspondingly received divided clock signal.
In the process sequence for replacing conventional gate electrode structures (310) by high-k metal gate structures (310N, 310B, 310P), the number of additional masking steps may be maintained at a low level, for instance by using highly selective etch steps (322, 325, 327, 331), thereby maintaining a high degree of compatibility with conventional CMOS techniques. Furthermore, the techniques disclosed herein enable compatibility to front-end process techniques and back-end process techniques, thereby allowing the integration of well-established strain- inducing mechanisms in the transistor level as well as in the contact level.
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
A DRAM controller (103) may comprise two sub-controllers (406, 404), each capable of handling a respective N-bit interface (e.g. 64-bit interface). Each sub-controller may also be configurable to be (2*N)-bit (e.g. 128-bit) capable with respect to control logic, for controlling a logical 128-bit data path. In ganged mode, each sub-controller may logically operate as if it were handling data in 128-bit chunks, (i.e. handling the entire 128- bit data path), while actual full bandwidth may be achieved by having one of the sub-controllers operate on commands and a first N-bit portion of each (2*N)-bit chunk of data, and having the other sub-controller operate on a 'copy' of the commands with a corresponding remaining N-bit portion of each (2*N)-bit chunk of data. Once the BIOS has configured and initialized the two DRAM controllers to operate in ganged mode, the BIOS and all software may no longer need to be aware that two memory controllers are used to access a single (2*N)-bit wide channel.
MOS structures (100, 200) that exhibit lower contact resistance and methods for fabricating such MOS structures are provided. In one method, a semiconductor substrate (106) is provided and a gate stack (146) is fabricated on the semiconductor substrate. An impurity-doped region (116) within the semiconductor substrate aligned with the gate stack is formed. Adjacent contact fins (186) extending from the impurity-doped region are fabricated and a metal suicide layer (126) is formed on the contact fins. A contact (122) to at least a portion of the metal suicide layer on at least one of the contact fins is fabricated.
H01L 21/285 - Dépôt de matériaux conducteurs ou isolants pour les électrodes à partir d'un gaz ou d'une vapeur, p.ex. condensation
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 23/485 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées formées de structures en couches comprenant des couches conductrices et isolantes, p.ex. contacts planaires
77.
CONNECTIVITY MANAGER TO MANAGE CONNECTIVITY SERVICES
A system and method are disclosed for managing the service connectivity of a mobile device to a plurality of connectivity services. A mobile device comprising a service connectivity manager accesses a repository of service connectivity management information. The service connectivity manager uses a first subset of the service connectivity management information to determine the connectivity services supported by a mobile device. A second subset of the service connectivity management information is then used by the service connectivity manager to determine the connectivity services supported by a predetermined network. The service connectivity manager then manages the service connectivity between the mobile device and the connectivity services supported by the predetermined network.
A mechanism for superscalar decode of variable length instructions. A length decode unit may obtain a plurality of instruction bytes based on a scan window of a predetermined size. The instruction bytes may be associated with a plurality of variable length instructions, which are scheduled to be executed by a processing unit. The length decode unit may, for each instruction byte, estimate the start of a next variable length instruction following a current variable length instruction, and store a first pointer. A pre- pick unit may, for each instruction byte, use the first pointer to estimate the start of a subsequent variable length instruction following the next variable length instruction within the scan window, and store a second pointer. A pick unit may use a start pointer and related first and second pointers to determine the actual start of the variable length instructions within the scan window, and generate instruction pointers.
A processor cache memory subsystem (30) includes a cache memory (60) having a configurable associativity. The cache memory may operate in a fully associative addressing mode and a direct addressing mode with reduced associativity. The cache memory includes a data storage array (265) including a plurality of independently accessible sub-blocks (0, 1, 2, 3) for storing blocks of data. For example each of the sub-blocks implements an n-way set associative cache. The cache memory subsystem also includes a cache controller (21) that may programmably select a number of ways of associativity of the cache memory. When programmed to operate in the fully associative addressing mode, the cache controller may disable independent access to each of the independently accessible sub-blocks and enable concurrent tag lookup of all independently accessible sub-blocks, and when programmed to operate in the direct addressing mode, the cache controller may enable independent access to one or more subsets of the independently accessible sub- blocks.
A technique is presented which provides for a selective pre-amorphization of source/drain regions of a transistor while preventing pre-amorphization of a gate electrode of the transistor. Illustrative embodiments include the formation of a pre-amorphization implant blocking material over the gate electrode. Further illustrative embodiments include inducing a strain in a channel region by use of various stressors.
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 21/266 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions en utilisant des masques
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
81.
IMMEDIATE AND DISPLACEMENT EXTRACTION AND DECODE MECHANISM
An extraction and decode mechanism for acquiring and processing instructions and the corresponding constant(s) embedded within the instructions. The extraction and decode mechanism may be included within a processing unit, and may comprise an instruction decode unit and at least one constant steer network. During operation, the instruction decode unit may obtain and decode instructions which are to be executed by the processing unit. For each instruction, the instruction decode unit may also determine the location of one or more constants embedded within the instruction. The constant steer network may receive the location information from the instruction decode unit. While the instruction decode unit decodes the instruction, the constant steer network may obtain the constant(s) embedded within the instruction based on the location information and store the constant(s). The constant(s) embedded within the instruction may be immediate or displacement (imm/disp) constant(s).
In one disclosed embodiment, the present method for preventing void formation in a solder joint formed between two metallic surfaces includes forming (410) at least one slit (218) in a layer of solder to form a slit solder layer (214), positioning (440) the slit solder layer between the two metallic surfaces, and heating (450) the slit solder layer to form the solder joint, wherein the at least one slit forms an outgas alley to prevent void formation in the solder joint. Where solder joint width is a concern, the present method includes applying (450) external pressure concurrently with heating (450). The outgas alley is formed to provide a ready avenue of escape for flux gasses produced during formation of the solder joint.
B23K 1/20 - Traitement préalable des pièces ou des surfaces destinées à être brasées, p.ex. en vue d'un revêtement galvanique
B23K 35/02 - Baguettes, électrodes, matériaux ou environnements utilisés pour le brasage, le soudage ou le découpage caractérisés par des propriétés mécaniques, p.ex. par la forme
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 23/42 - Choix ou disposition de matériaux de remplissage ou de pièces auxiliaires dans le conteneur pour faciliter le chauffage ou le refroidissement
In one embodiment, a node (10A) comprises a plurality of interface circuits (12A- 12D) coupled to a node controller (42). Each of the plurality of interface circuits (12A-12D) is configured to couple to a respective link of a plurality of links. The node controller (42) is configured to select a first link from two or more of the plurality of links to transmit a first packet, wherein the first link is selected responsive to a relative amount of traffic transmitted via each of the two or more of the plurality of links.
By forming an additional dielectric material (260), such as silicon nitride, after patterning dielectric liners (230, 240) of different intrinsic stress, a significant increase of performance of N-channel transistors (220A) may be obtained while substantially not contributing to a performance loss of the P-channel transistor (220B).
Various methods and apparatus for semiconductor packing are disclosed. In one aspect, a method of manufacturing is provided that includes coupling first ends (237a) of plural conductor pins (183a, 183b, 183c) to a first surface (175) of a semiconductor chip package substrate (105). A layer (170) is formed on the first surface (175) that engages and resists lateral movement of the conductor pins (183a, 183b, 183c) while leaving second ends (237b) of the conductor pins (183a, 183b, 183c) exposed.
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 23/498 - Connexions électriques sur des substrats isolants
86.
TECHNIQUES FOR INTEGRATED CIRCUIT CLOCK MANAGEMENT
A clock generator (622) includes a first circuit (812) and a second circuit (814). The first circuit (812) includes a first clock input configured to receive a first clock signal at a first frequency, a second clock input configured to receive a second clock signal at the first frequency, and an output. The second clock signal is out-of-phase with the first clock signal. The second circuit (814) is coupled to the first circuit (812) and includes a mode signal input configured to receive a mode signal. The output of the first circuit (812) is configured to provide a generated clock signal whose effective frequency is based on the first and second clock signals and the mode signal.
G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p.ex. des signaux d'horloge
H03L 7/22 - Synthèse de fréquence indirecte, c. à d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant plus d'une boucle
87.
METHOD AND APPARATUS FOR IDENTIFYING BROKEN PINS IN A TEST SOCKET
A method includes scanning a test socket (120) after removal of a device under test (170) to generate scan data. The scan data is compared to reference data. A presence of at least a portion of a pin (210) in the test socket (120) is identified based on the comparison. A test system (100) includes a test socket (120), a scanner (140), and a control unit (150). The test socket (120) is operable to receive devices under test (170). The scanner (140) is operable to scan the test socket (120) after removal of a device under test (170) to generate scan data. The control unit (150) is operable to compare the scan data to reference data and identify a presence of at least a portion of a pin (210) in the test socket (120) based on the comparison.
By locally adapting the size and/or density of a contact structure (230A, 230B), for instance, within individual transistors (210, 210A, 210B) or in a more global manner, the overall performance of advanced semiconductor devices (200) may be increased. Hence, the mutual interaction between the contact structure (230A, 230B) and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 23/528 - Configuration de la structure d'interconnexion
brevets
