Methods for operating a communications device that communicates via inductive coupling, methods for operating an NFC device, and a communications device that communicates via inductive coupling are disclosed. In an embodiment, a method involves at the communications device, shifting a first transmission phase to obtain an updated transmission phase in response to information from a corresponding reader device, which indicates that active load modulation (ALM) communications between the communications device and the corresponding reader device under the first transmission phase fail, at the communications device, conducting subsequent ALM communications with the corresponding reader device under the updated transmission phase, in response to that the subsequent ALM communications under the updated transmission phase are successfully conducted between the communications device and the corresponding reader device, obtaining a new training data point based on the updated transmission phase, and training the communications device in response to the new training data point.
Various embodiments relate to a data processing system comprising instructions embodied in a non-transitory computer readable medium, the instructions for a cryptographic operation including matrix multiplication for lattice-based cryptography in a processor, the instructions, including: applying a first function to the rows of a matrix of polynomials to generate first outputs, wherein the first function excludes the identity function; adding an additional row to the matrix of polynomials to produce a modified matrix, wherein each element in the additional row is generated by a second function applied to a column of outputs associated with each element in the additional row; multiplying the modified matrix with a vector of polynomials to produce an output vector of polynomials; applying a verification function to the output vector that produces an indication of whether a fault occurred in the multiplication of the modified matrix with the vector of polynomials; and carrying out a cryptographic operation using output vector when the verification function indicates that no fault occurred in the multiplication of the modified matrix with the vector of polynomials.
H04L 9/30 - Clé publique, c. à d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
3.
SEMICONDUCTOR DEVICE WITH THERMAL DISSIPATION AND METHOD THEREFOR
A method of manufacturing a semiconductor device is provided. The method includes attaching a first die pad of a semiconductor die to a central pad of a package leadframe. The first die pad is located in a central region on an active side of the semiconductor die. A second die pad of the semiconductor die is connected a lead of the package lead frame. The second die pad is located in a periphery region on the active side of the semiconductor die. An encapsulant encapsulates a portion of the semiconductor die and a portion of the package leadframe. A backside surface of the semiconductor die is exposed at a top major surface of the encapsulant, and a backside surface of the central pad exposed at a bottom major surface of the encapsulant.
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p.ex. dissipateurs de chaleur
H01L 23/498 - Connexions électriques sur des substrats isolants
A method of processing radar data comprising: receiving a mask that identifies a set of samples in received radar signalling that are detected as including interference, and comprises a matrix of data having a fast-time dimension and a slow-time dimension; receiving radar data comprising a matrix of samples of received radar signalling having a fast-time dimension and a slow-time dimension wherein the set of samples identified by the mask have been set to a predetermined value to remove said samples including interference; determining a reconstruction of the radar data in which at least the set of samples of the radar data are replaced with estimated samples, wherein said determining a reconstruction of the radar data comprises formulating an optimization problem based on the radar data and the mask, and applying an iterative method to solve the optimization problem at least in part in the range-Doppler domain.
G01S 7/02 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe
G01S 7/35 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe - Détails de systèmes non impulsionnels
G06F 17/11 - Opérations mathématiques complexes pour la résolution d'équations
A time-interleaved analog to digital converter (ADC) circuit includes an input signal amplitude detector configured to determine an input signal amplitude of an analog input signal, a multi-tone signal generator configured to generate a plurality of analog and digital sinusoidal signals having an amplitude dependent on the determined input signal amplitude, and an analog input summing module configured to provide a summed output analog signal from the analog input signal and the analog sinusoidal signals. A time-interleaved ADC has an input coupled to receive the summed output analog signal from the analog input summing module and configured to provide a timing skew-calibrated digital output signal from the summed output analog signal. A digital output subtractor module is configured to provide a digital output signal at an output of the circuit from the digital output signal from the time-interleaved ADC and the digital sinusoidal signals from the multi-tone signal generator.
A circuit arrangement for detecting a glitch on a supply voltage comprising a low pass filter arrangement coupled to a supply terminal and configured provide a filtered supply voltage. The circuit arrangement comprises a first and second detector circuit each configured to receive the supply voltage and the filtered supply voltage and configured to provide a first and second detection signal indicative of a glitch comprising a transient, positive and a transient negative change in the supply voltage at a first detector output terminal and second detector output terminal respectively. The circuit arrangement further comprises a circuit-arrangement output terminal configured to provide an output signal indicative of the detection of a glitch in the supply voltage based on the first detection signal and the second detection signal.
G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
One example discloses an on-chip shielded device, including: a planar structure including a substrate and a passivation layer; an electrical component formed within the substrate and coupled to an input signal path and an output signal path; a first shielding element positioned above the electrical component and the passivation layer; and a second shielding element positioned above the electrical component, the passivation layer and the first shielding element.
A method of forming a semiconductor device is provided. The method includes forming a first cavity at a first major surface of a first encapsulant. A first semiconductor die is affixed on the first major surface of the first encapsulant and a second semiconductor die is affixed on a bottom surface of the first cavity. A second encapsulant encapsulates the first semiconductor die, the second semiconductor die, and at least exposed portions of the first major surface of the first encapsulant. A package substrate is formed on a first major surface of the second encapsulant. The package substrate includes conductive traces interconnected to the first semiconductor die and the second semiconductor die.
H01L 23/04 - Conteneurs; Scellements caractérisés par la forme
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
9.
SYSTEM AND METHOD OF DIGITAL TO ANALOG CONVERSION USING DYNAMIC ELEMENT MATCHING
A dynamic element matching system including sequential register groups, decode circuitry, and pointer control circuitry. Each register group includes at least two registers. The decode circuitry controls a state of each register group based on a level of a digital input signal, a relative position with respect to a begin pointer and an end pointer, and a corresponding one of multiple pseudo random probability values. The pointer control circuitry cyclically advances the end pointer among the register groups causing decode circuitry to add one or more register groups and enable a register within each added register group in response to the level of the digital input signal increasing, and also cyclically advances the begin pointer among the register groups causing the decode circuitry to remove one or more register groups and disable a register within each removed register group in response to the level of the digital input signal decreasing.
Various embodiments relate to a data processing system comprising instructions embodied in a non-transitory computer readable medium, the instructions for a cryptographic operation using masked compressing of coefficients of a polynomial having ns arithmetic shares for lattice-based cryptography in a processor, the instructions, including: shifting a first arithmetic share of the ns arithmetic shares by an input mask λ1; scaling the shifted first arithmetic share by a value based on a first compression factor δ and a masking scaling factor φ1; shifting the scaled first arithmetic share by a value based on the masking scaling factor φ1; scaling a second to ns shares of the ns arithmetic shares by a value based on the first compression factor δ and the masking scaling factor φ1; converting the ns scaled arithmetic shares to ns Boolean shares; right shifting the ns Boolean shares based upon the masking scaling factor φ1 and a second compression factor φ2; XORing an output mask λ2 with the shifted first Boolean share to produce ns compressed Boolean shares; and carrying out a cryptographic operation using the ns arithmetic shares when the ns compressed Boolean shares indicates that the coefficients of the polynomial are within boundary values.
G06F 7/72 - Méthodes ou dispositions pour effectuer des calculs en utilisant une représentation numérique non codée, c. à d. une représentation de nombres sans base; Dispositifs de calcul utilisant une combinaison de représentations de nombres codées et non codées utilisant l'arithmétique des résidus
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
In accordance with a first aspect of the present disclosure, a communication system is provided, comprising: a plurality of communication nodes which are operatively coupled to each other, wherein each of said communication nodes comprises a first radio frequency (RF) communication unit configured to perform ranging sessions with an external communication device; a controller configured to create a logical subset of said communication nodes based on an indication of a channel quality between the communication nodes and the external communicationdevice,whereinsaidindicationofthechannelqualityhasbeenobtained using a second RF communication unit comprised in each of said communication nodes; the controller further being configured to cause that only the communication nodes included in said logical subset perform said ranging sessions with the external communication device. In accordance with a second aspect of the present disclosure, a corresponding method of operating a communication system is conceived. In accordance with a third aspect of the present disclosure, a computer program is provided for carrying out said method.
Joint communication and sensing by a joint communication and sensing system in a wireless network is disclosed. A transmitter is arranged to transmit a first beam in a direction selected from a plurality of directions stored in a memory, where each direction corresponds to a direction of a respective remote device. The first beam comprises communication symbols to be communicated to the remote device in the direction during a communication session with the remote device. A reflection of the transmitted first beam is received via a receive antenna during the communication session, where the reflected first beam comprises the communication symbols. A position of one or more objects is identified based on a timing of transmission and receipt of the communication symbols in the transmitted first beam and the reflected first beam respectively and the sense symbols in the transmitted second beam and the reflected second beam respectively.
G01S 13/87 - Combinaisons de plusieurs systèmes radar, p.ex. d'un radar primaire et d'un radar secondaire
H04B 7/06 - Systèmes de diversité; Systèmes à plusieurs antennes, c. à d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p.ex. réseaux de mise en forme adaptatifs
A semiconductor device comprising a substrate having a first conductivity type, the substrate having a top surface and a bottom surface, a first buried layer disposed in the substrate at a first depth from the top surface, wherein the first buried layer has a second conductivity type and a first doping concentration, a second buried layer adjacent and surrounding the first buried layer at the first depth, wherein the second buried layer has the second conductivity type and a second doping concentration, wherein the second doping concentration is less than the first doping concentration, and an isolation trench disposed in the substrate and surrounding the second buried layer, wherein the isolation trench extends from the top surface of the substrate to a second depth, the second depth exceeding the first depth.
An integrated circuit (IC) includes circuitry in a plurality of power domains for transmitting and/or receiving radar chirp frames and first and second monitoring systems for monitoring supply voltages of a first and a second subset of the plurality of power domains, respectively. The first subset is monitored outside of a time window during which a chirp frame is transmitted and/or received utilizing circuitry of the IC, and the second subset is monitored during the time window. The first monitoring system includes an output for an error signal indicating a supply voltage in the first subset does not comply with a first voltage parameter. The second monitoring system includes a unique monitoring circuit for each power domain in the second subset, and each unique monitoring circuit includes an output for an error signal indicating a supply voltage in the second subset does not comply with a second voltage parameter.
G01S 7/03 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe - Détails de sous-ensembles HF spécialement adaptés à ceux-ci, p.ex. communs à l'émetteur et au récepteur
One example discloses a voltage converter, including: a power stage configured to generate an output voltage (Vo) and an output current (Jo) based on a switching frequency (fs); a primary control loop configured to vary the switching frequency (fs) in response to an on-time value code (Ton_code) and/or a peak output current code (iLpeak_code); and a secondary control loop configured to generate the Ton_code and/or the iLpeak_code.
H02M 3/156 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation
H02M 1/00 - APPAREILS POUR LA TRANSFORMATION DE COURANT ALTERNATIF EN COURANT ALTERNATIF, DE COURANT ALTERNATIF EN COURANT CONTINU OU VICE VERSA OU DE COURANT CONTINU EN COURANT CONTINU ET EMPLOYÉS AVEC LES RÉSEAUX DE DISTRIBUTION D'ÉNERGIE OU DES SYSTÈMES D'ALI; TRANSFORMATION D'UNE PUISSANCE D'ENTRÉE EN COURANT CONTINU OU COURANT ALTERNATIF EN UNE PUISSANCE DE SORTIE DE CHOC; LEUR COMMANDE OU RÉGULATION - Détails d'appareils pour transformation
Systems and methods for providing voltage regulators with sliced pole tracking are discussed. In some embodiments, a voltage regulator may include: an error amplifier, a voltage-to-current converter coupled to the error amplifier, and a current-to-current converter coupled to the voltage-to-current converter, where the current-to-current converter comprises a sliced pole tracking circuit coupled to a power device, and where the power device is configured to provide an output voltage to a load.
A plurality of chained clock dividers provides a plurality of generated clocks generated from a root clock. Each clock divider provides a generated clock having a lower frequency that its corresponding input clock and which transitions at falling edges of its corresponding input clock. Clock gating circuitry selectively gates the generated clocks based on a clock ready signal and provides the generated clocks as a corresponding plurality of safe clocks when the clock ready indicator indicates the generated clocks are ready. A delay circuit has an inverted clock input configured to receive a final generated clock. The delay circuit provides a trigger output in response to a falling edge of the final generated clock. A set of synchronization flip flops receives a clock enable signal and the trigger output and provides the clock ready indicator based on the clock enable signal and the trigger output.
A method is provided for protecting a machine learning (ML) model from a side channel attack (SCA). A permutation is performed of weights and biases for a first layer of the ML model. The permutated weights and biases of the first layer are scaled using a scaling factor greater than zero to generate scaled and permutated weights and biases for a first plurality of nodes of the first layer. The weights for a second layer immediately following the first layer are modified to compensate for the permutation and scaling of the weights and biases of the first layer. The modified weights and biases of the first and second layers are substituted for corresponding original weights and biases of the ML model. An inference engine of the ML model is executed using the modified weights and biases of the first and second layers for an inference operation.
G06F 21/75 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par inhibition de l’analyse de circuit ou du fonctionnement, p.ex. pour empêcher l'ingénierie inverse
A transmitter circuit including an impedance setting circuit having first and second legs, wherein each leg includes an adjustable pull-up resistance and an adjustable pull-down resistance connected in series between a supply terminal and a reference terminal. A first-leg-node, between the adjustable resistances of the first leg, is connected to a first bus terminal. A second-leg-node, between the adjustable resistances of the second leg, is connected to a second bus terminal. The controller detects a transition in a transmission data signal, and in response to a dominant to recessive transition the controller controls a voltage setting circuit to set the differential driver voltage on the bus to a recessive value; adjusts each of the adjustable pull-up resistances and the adjustable pull-down resistances with the same target impedance profile such that the transmitter circuit drives the bus with a target driver impedance for an active recessive period of a bit time.
An apparatus configured to:
receive an input dataset indicative of radar signals, reflected from targets, received at an antenna;
determine an objective function for evaluation over a plurality of points of a search space representing possible direction-of-arrival angles;
evaluate the objective function for a first candidate number of targets;
perform a first evaluation of a branch metric function based on a second candidate number of targets, wherein the branch metric function is indicative of a change in the objective function; and
if the branch metric function is greater than a predetermined threshold, then evaluate the objective function for the second candidate number of targets;
if the branch metric function is less than the predetermined threshold, then evaluate the objective function for the first candidate number of targets, wherein the evaluation is based on at least one of the first candidate number of targets having a different, second candidate direction-of-arrival angle.
G01S 13/42 - Mesure simultanée de la distance et d'autres coordonnées
G01S 7/35 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe - Détails de systèmes non impulsionnels
G01S 13/00 - Systèmes utilisant la réflexion ou la reradiation d'ondes radio, p.ex. systèmes radar; Systèmes analogues utilisant la réflexion ou la reradiation d'ondes dont la nature ou la longueur d'onde sont sans importance ou non spécifiées
21.
NETWORK DEVICE, COMMUNICATION SYSTEM AND METHOD FOR THE NETWORK DEVICE
The present invention relates to a network device comprising: a first input interface, a first output interface, and a second output interface, wherein the network device is configured to change from a first state, referred to as a time state, to a second state, referred to as a spatial state, and vice versa, wherein the network device is configured to generate each of a first output message and a second output message based on a first input message, wherein the network device is configured to transmit, in the time state, both, the first output message and the second output message, offset in time either via the first output interface or second output interface, and wherein the network device is configured to transmit, in the spatial state, the first output message via the first output interface and the second output message via the second output interface. The present invention also relates to a communication system comprising the network device and to a method for the network device.
A semiconductor die includes a transformer with terminals of a first winding electrically coupled to external die terminals of the semiconductor die. The terminals of a second winding of the transformer are coupled to internal circuitry of the semiconductor die. An ESD clamp circuit is electrically coupled to the center tap of the second winding of the transformer. When made conductive during and ESD event, the ESD clamp circuit discharges ESD current between the center tap and a supply rail.
A method is provided for detecting interference in a radar system. The method includes transmitting, by a transmitter of the radar system, a sequence of radar pulses at a regular interval with a rest period following each radar pulse of the sequence of radar pulses. The transmitter is disabled during each rest period. A receiver is enabled to receive reflected radar pulses from a target during the rest period following each radar pulse of the sequence of radar pulses. Some of the radar pulses are selected to be omitted and not transmitted. The receiver is still enabled during the rest periods following the omitted transmission pulses. Any reflected pulses received during the rest periods following the omitted transmission pulses may be an indication of a targeted interference of the radar system. In another embodiment, a radar system is provided.
G01S 7/02 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe
In accordance with a first aspect of the present disclosure, a radio frequency (RF) communication device is provided, comprising: a receiver unit configured to receive at least one radio frequency signal, wherein the receiver unit has a variable initial phase; a controller configured to change said initial phase; a measurement unit configured to measure a plurality of amplitudes and/or phases of the radio frequency signal, wherein each of said amplitudes and/or phases of the radio frequency signal corresponds to a different initial phase of the receiver unit. In accordance with a second aspect of the present disclosure, a corresponding method of operating an RF communication device is conceived.
There is provided a phase shifting device and method of manufacturing the same. The device comprises an auto-transformer comprising a primary winding configured to receive an input signal; and two secondary windings, wherein a first one of the two secondary windings is in phase with the primary winding and a second one of the two secondary windings is out of phase with the primary winding. The device also comprises a first switch coupled to an output signal of the first one of the two secondary windings of the auto-transformer; and a second switch coupled to an output signal of the second one of the two secondary windings of the auto-transformer. Output signals of the first and second switches are couplable to an output of the phase shifting device.
An apparatus includes a printed circuit board (PCB), a solder pad, a signal via, a plurality of metalized vias, and a waveguide. The PCB has a first surface opposite a second surface and includes a first metal layer, a second metal layer having a waveguide opening, and a PCB channel region from the waveguide opening in the second metal layer to the second surface. The solder pad is positioned on the first surface of the PCB over the channel region, and the signal via is coupled to the solder pad and a via pad in the second metal layer within the waveguide opening. The plurality of metalized vias extend from the first surface to the second surface of the PCB and form a boundary around the channel region. The waveguide is affixed to the waveguide opening in the second metal layer.
H05K 1/11 - Eléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
H01Q 13/00 - Cornets ou embouchures de guide d'onde; Antennes à fentes; Antennes guide d'onde à ondes de fuite; Structures équivalentes produisant un rayonnement le long du trajet de l'onde guidée
H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
H05K 3/00 - Appareils ou procédés pour la fabrication de circuits imprimés
27.
NEAR-RANGE INTERFERENCE MITIGATION FOR AUTOMOTIVE RADAR SYSTEM
A signal processing system and method includes a first input configured to receive an input signal range profile. The input signal range profile includes near-range interference signals. A second input is configured to receive a reference signal range profile; and a processor is configured to perform steps including: executing a recursive least squares operation to determine coefficient values of a finite impulse response (FIR) filter, wherein the coefficient values are selected to minimize a difference between the input signal range profile and the reference signal range profile when the reference signal range profile is filtered through the FIR filter to generate a filtered reference signal range profile, and subtracting the filtered reference signal range profile from the input signal range profile to remove the near-range interference signals from the input signal range profile.
G01S 7/35 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe - Détails de systèmes non impulsionnels
G01S 13/931 - Radar ou systèmes analogues, spécialement adaptés pour des applications spécifiques pour prévenir les collisions de véhicules terrestres
28.
METHOD AND INTEGRATED CIRCUIT FOR CLOCK RECOVERY IN AN RFID TAG
There is provided, a method for clock recovery in a RFID tag, the method includes receiving a RF field from a RFID reader. A field clock is generated from the received RF field, from which a clock recovery signal is generated. The RF field is modulated to produce a RF modulation. Generation of the clock recovery signal is paused while the RF field is being modulated. A modulation envelope signal is generated and used for load modulation. Generation of the clock recovery signal at the end of the RF modulation is resumed after a delay of one clock cycle from a falling edge of the modulation envelope signal. In another embodiment of the method, instead of adding the delay, a differential amplifier is used to increase RF field detection sensitivity. The method and the RFID tag ensures synchronized resumption of a PLL clock and the clock recovery signal.
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p.ex. en utilisant une boucle verrouillée en phase
G06K 19/07 - Supports d'enregistrement avec des marques conductrices, des circuits imprimés ou des éléments de circuit à semi-conducteurs, p.ex. cartes d'identité ou cartes de crédit avec des puces à circuit intégré
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
A low drop-out (LDO) regulator, includes an NMOS transistor having one of a source and drain terminal configured to be coupled to a voltage supply and the other of the source and drain terminal coupled to the low drop out voltage regulator output. A gate driver for the LDO regulator includes a boost converter having a boost converter input configured to be coupled to a boost converter reference voltage, a boost converter output configured to output a boosted voltage greater than the boost converter reference voltage and the voltage supply; and a boost converter clock input configured to receive a clock signal. The gate driver further includes a notch filter having a notch filter input coupled to the boost converter output and a notch filter output coupled to the gate driver output.
H02M 1/00 - APPAREILS POUR LA TRANSFORMATION DE COURANT ALTERNATIF EN COURANT ALTERNATIF, DE COURANT ALTERNATIF EN COURANT CONTINU OU VICE VERSA OU DE COURANT CONTINU EN COURANT CONTINU ET EMPLOYÉS AVEC LES RÉSEAUX DE DISTRIBUTION D'ÉNERGIE OU DES SYSTÈMES D'ALI; TRANSFORMATION D'UNE PUISSANCE D'ENTRÉE EN COURANT CONTINU OU COURANT ALTERNATIF EN UNE PUISSANCE DE SORTIE DE CHOC; LEUR COMMANDE OU RÉGULATION - Détails d'appareils pour transformation
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p.ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
30.
METHOD AND APPARATUS FOR DETERMINATION OF DIRECTION OF ARRIVAL ANGLE
An apparatus configured to:
receive an input dataset indicative of the amplitude and phase of radar signals received at a plurality of antenna elements;
determine an objective function;
determine a beam forming spectrum, the beam forming spectrum comprising a correlation of the input dataset with a set of beamsteering vectors;
perform a first determination process for evaluation of the objective function comprising the processor being configured to:
identify two or more peaks in the beam forming spectrum based on a predetermined threshold level, determine candidate direction-of-arrival angles therefrom for definition of a first-reduced search space;
perform a second determination process for evaluation of the objective function comprising the processor being configured to:
determine a peak direction-of-arrival angle comprising the direction-of-arrival angle that corresponds to a peak in the beam forming spectrum:
evaluate the objective function over the first reduced search space and using the peak direction-of-arrival angle.
G01S 3/12 - Moyens pour déterminer le sens d'une direction, p.ex. en combinant des signaux provenant d'une antenne directionnelle ou d'une bobine exploratrice de goniomètre avec ceux venant d'une antenne non directionnelle
G01S 3/04 - Radiogoniomètres pour déterminer la direction d'où proviennent des ondes infrasonores, sonores, ultrasonores ou électromagnétiques ou des émissions de particules sans caractéristiques de direction utilisant des ondes radio - Détails
G01S 7/35 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe - Détails de systèmes non impulsionnels
31.
METHOD AND DEVICE FOR PERFORMING A PRESENCE CHECK FOR WIRELESS CHARGING LISTENER DEVICES
A wireless charging (WLC) poller device and WLC listener device are provided. A method for performing a presence check of the WLC listener device includes providing a radio frequency (RF) presence check signal. An input signal from the antenna by the poller device is received concurrently with the transmission of the RF presence check signal. A rate of change of a magnitude of the input signal is measured during the transmission of the presence check signal. A difference between the input signal and an expected input signal is determined. A presence of the listener device is detected if an absolute value of the measured rate of change of the input signal is above a threshold rate of change, and the difference between the input signal and the expected input signal is within a predetermined distance. Prior to the presence check, a capacitor of the WLC listener device may be discharged.
H02J 50/80 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique mettant en œuvre l’échange de données, concernant l’alimentation ou la distribution d’énergie électrique, entre les dispositifs de transmission et les dispositifs de réception
H02J 50/20 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant des micro-ondes ou des ondes radio fréquence
32.
More secure data reading with error correction codes
Various embodiments relate to a memory controller configured to read data from a memory array, including: an error correction codes (ECC) encoder configured to encode data stored in the memory array; an ECC decoder configured to decode first data read from the memory array based upon a first read request and detect errors in the first data read from the memory array; and a fault controller configured to: command the memory controller to read other data from the memory array when the ECC detects an error; command the memory controller to re-read the first data from the memory array; when the ECC detects an error; compare the re-read first data to the read first data; and signal a fault attack when the re-read first data is different from the read first data.
G06F 11/00 - Détection d'erreurs; Correction d'erreurs; Contrôle de fonctionnement
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G06F 21/56 - Détection ou gestion de programmes malveillants, p.ex. dispositions anti-virus
One example discloses a first wireless network device, including: a far-field transceiver; a near-field transceiver; wherein the first wireless network device is configured to be wirelessly near-field coupled to a second wireless network device that also includes a far-field transceiver and a near-field transceiver; wherein the first wireless network device is further configured to be wirelessly near-field coupled to a set of near-field wireless network devices using only the near-field transceiver; wherein first wireless network device, the second wireless network device, and the set of near-field wireless network devices are configured to be in physical contact with a body; and wherein the first wireless network device is configured to be wirelessly far-field coupled to a third wireless network device only if the second wireless network device is not wirelessly far-field coupled to the third wireless network device.
A bias circuit for generating a virtual reference voltage is described. The bias circuit may bias a switching device configured to switch a switching device output between a first and second supply voltage. The bias circuit includes a bias stage coupled between the first supply voltage rail and the second supply voltage rail. The bias stage has a bias stage output configured to output a virtual reference voltage value having a value between the first and second supply voltage. The bias circuit further includes a voltage follower coupled to the bias stage. The voltage follower is configured to output the virtual reference voltage. The bias circuit further includes a first charge pump coupled to the voltage follower output; and at least one of a second charge pump coupled to the bias stage voltage output, and a switchable buffer coupled to the bias stage voltage output and the voltage follower output.
H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
H03K 19/0175 - Dispositions pour le couplage; Dispositions pour l'interface
35.
ESD CLAMP CIRCUIT WITH VERTICAL BIPOLAR TRANSISTOR
A semiconductor die has ESD clamp circuits that include vertical PNP transistors. The vertical PNP transistors include at least one region in a semiconductor substrate that is substrate isolated from a biased portion of the substrate. The ESD clamp circuits include a resistive element that is electrically coupled in a conductive path between the emitter and base of the vertical PNP transistor. The PNP transistor is conductive during certain ESD events to discharge ESD charge from the emitter to the collector.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
A method of manufacturing a semiconductor device is provided. The method includes attaching a first end of a first bond wire to a first conductive lead and a second end of the first bond wire to a first bond pad of a first semiconductor die. A conductive lead extender is affixed to the first conductive lead by way of a conductive adhesive, the lead extender overlapping the first end of the first bond wire. A first end of a second bond wire is attached to the lead extender, the first end of the second bond wire conductively connected to the first end of the first bond wire.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
37.
System and Methods for Vehicle Localization Using Infrastructure Sensing
Radar localization systems and methods are provided to determine the location of an object. The radar localization systems and methods can determine the location of an object based on data obtained from at least two radar measurements made by the radar localization device. In some embodiments, a radar localization system can be included in a wireless communications system that conducts both wireless communications and radar sensing. Radar localization systems include at least a computing unit that performs a radar localization method. Radar localization methods may use map data in object localization to eliminate non-feasible locations of the object.
Embodiments of sigma-delta analog-to-digital converter (ADC) circuits and a microphone circuit are disclosed. In an embodiment, a sigma-delta ADC circuit includes a pair of operational transconductance amplifiers (OTAs), a filter connected to the pair of OTAs, a quantizer connected to the filter, a differential digital-to-analog converter (DAC) connected to the quantizer, and a bias compensation circuit configured to measure a biasing condition of a first OTA of the pair of OTAs and to apply the biasing condition of the first OTA to a second OTA of the pair of OTAs to reduce Total Harmonic Distortion Plus Noise (THD+N) in the sigma-delta ADC circuit. An output of a microphone and a differential output of the differential DAC are inputted into input terminals of the pair of OTAs.
A circuit comprising: a common terminal, first terminal and second terminal, wherein the common terminal is coupled to a first and second circuit branch at a branch node; wherein the first/second circuit branches include a respective first/second quarter wavelength transmission line having a first end coupled to the branch node and a second end respectively coupled to the first/second terminal; wherein the first and second terminals are coupled together via a branch-interconnection arrangement; wherein the circuit comprises: a first switched arrangement comprising a first switch having a first and second switch-terminal, wherein the first switch-terminal is coupled to the common terminal, and wherein a first resistor and a first capacitor are arranged in parallel and coupled between the second switch-terminal and a reference terminal; and a second switched arrangement coupled to the first terminal, wherein the first quarter wavelength transmission line is coupled between the first and second switched arrangements.
In accordance with a first aspect of the present disclosure, an antenna unit is provided, comprising: an integrated circuit package containing an integrated circuit die and an antenna structure coupled to the integrated circuit die; a dielectric layer separated from the integrated circuit package, wherein the dielectric layer is placed at a predefined distance above an upper surface of the integrated circuit package. In accordance with a second aspect of the present disclosure, a corresponding method of producing an antenna unit is conceived.
A method of manufacturing a semiconductor device is provided. The method includes forming a redistribution layer (RDL) over a semiconductor die, a portion of the RDL contacting a die pad of the semiconductor die. A non-conductive layer is formed over the RDL. An opening in the non-conductive layer is formed exposing a portion of the RDL. A plurality of plateau regions is formed in the non-conductive layer. A cavity region in the non-conductive layer separates each plateau region of the plurality of plateau regions. A metal layer is deposited over the non-conductive layer and exposed portion of the RDL and etched to expose the plurality of plateau regions through the metal layer. The cavity region remains substantially filled by a portion of the metal layer.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
42.
SEMICONDUCTOR DEVICE WITH REDISTRIBUTION METALLIZATION AND METHOD THEREFOR
A method of manufacturing a semiconductor device is provided. The method includes forming a redistribution layer (RDL) over a semiconductor die. A portion of the RDL contacts a die pad of the semiconductor die. A metal layer is formed on a top surface and sidewalls of the RDL and configured to encase the RDL. A non-conductive layer is formed over the metal layer and underlying RDL. An opening in the non-conductive layer is formed exposing a portion of the metal layer formed on the RDL. An under-bump metallization (UBM) is formed in the opening and conductively connected to the die pad by way of the metal layer and RDL.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
43.
MULTI-MODE SIGMA-DELTA ADC CIRCUIT AND MICROPHONE CIRCUIT HAVING A MULTI-MODE SIGMA-DELTA ADC CIRCUIT
Embodiments of multi-mode sigma-delta analog-to-digital converter (ADC) circuits and a microphone circuit are disclosed. In an embodiment, a multi-mode sigma-delta ADC circuit includes a pair of operational transconductance amplifiers (OTAs), a filter connected to the pair of OTAs, a quantizer connected to the filter, a differential digital-to-analog converter (DAC) connected to the quantizer, and a controller configured to switch the multi-mode sigma-delta ADC circuit between a single-ended operational mode, a pseudo differential operational mode, and a full differential operational mode to improve common mode rejection (CMR) performance by controlling the pair of OTAs. An output of a microphone and a differential output of the differential DAC are inputted into input terminals of the pair of OTAs.
A wireless communication system includes: a transceiver configured to modulate desired transmission data onto a band of frequencies, thereby generating a transmission signal, and to demodulate a reception signal within the same frequencies in order to obtain received data; and an antenna module that includes a first radiative element, coupled to the transceiver and configured to receive and broadcast the transmission signal, and a second radiative element, also coupled to the transceiver and configured to receive the reception signal, simultaneous with the broadcast of the transmission signal. The first radiative element and the second radiative element have a common centroid. The transceiver and the antenna module are part of a single wireless device that is configured for full-duplex wireless communication, at a data rate of at least 100 megabits per second (Mb/s) over a distance that is not more than 100 millimeters from the antenna module.
H04L 5/14 - Fonctionnement à double voie utilisant le même type de signal, c. à d. duplex
H04B 1/38 - TRANSMISSION - Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission Émetteurs-récepteurs, c. à d. dispositifs dans lesquels l'émetteur et le récepteur forment un ensemble structural et dans lesquels au moins une partie est utilisée pour des fonctions d'émission et de réception
45.
SYSTEM FOR SCAN MODE EXIT AND METHODS FOR SCAN MODE EXIT
Resetting an integrated circuit (IC) by reset circuit of the IC comprises receiving a clock signal and a data signal. A sequence of bits of the data signal is stored in a memory based on the clock signal. A test mode signal is received and the sequence of bits is decoded in response to receiving the test mode signal. One of adjusting a counter value of a counter of the reset circuitry and outputting a reset signal corresponding to the counter value is performed based on the decoded sequence of bits.
An error amplifier including a differential pair circuit, a resistive device, a low voltage capacitor, and a protection device. The differential pair circuit is coupled between an upper supply node and a lower supply node with first and second intermediate nodes and is responsive to a difference between a reference voltage and a feedback voltage for driving a control voltage developed on the second intermediate node. The resistive device is coupled between the second intermediate node and a low voltage node, and the low voltage capacitor and the protection device are coupled between the low voltage node and the lower supply node. The protection device is dynamically controlled by the first intermediate node to prevent the low voltage node from exceeding a predetermined maximum level. The protection device may be a transistor having size parameters based on voltage characteristics of the first intermediate node during expected operating conditions.
A circuit comprising: a digital attenuator part comprising: a first and second attenuator terminal; a first inductor having a first terminal coupled to the first attenuator terminal and a second terminal coupled to the second attenuator terminal; a first switched arrangement comprising a first switch having a first switch-terminal and a second switch-terminal, wherein the first switch-terminal is coupled to the first terminal of the first inductor, and a first resistor and a first capacitor are arranged in parallel, coupled between the second switch-terminal and a reference voltage; and a second switched arrangement comprising a second switch having a first switch-terminal and a second switch-terminal, wherein the first switch-terminal is coupled to the second terminal of the first inductor, and wherein a second resistor and a second capacitor are arranged in parallel and coupled between the second switch-terminal and the reference voltage.
The present disclosure relates to a Controller Area Network (CAN) system including: a CAN device and a monitoring device. The CAN device includes a transmit data (TXD) interface, a transmitter, a CAN BUS interface, and a control unit. The control unit reads out an identifier from a TXD message and compares the identifier with a reference tag. The CAN device generates a CAN BUS signal based on the TXD message at the CAN BUS interface. The control unit, if the comparison indicates that the identifier does not correspond to the reference tag, invalidates a representation of the TXD message by the CAN BUS signal and temporarily prevents another CAN BUS signal from being generated by the CAN device at the CAN BUS interface. The monitoring device receives an instruction message over a CAN BUS network and, in response, tests for reachability other CAN devices on the CAN BUS network.
A system includes a phase-shift to duty-cycle converter and a low pass filter. The phase-shift to duty-cycle converter has a first input for a reference clock and a second input for a phase-shifted clock that is phase-shifted relative to the reference clock. The low pass filter has an input coupled to an output of the phase-shift to duty-cycle converter and an output for an output signal. In some implementations, the phase-shift to duty-cycle converter includes a simple logic gate and a reset-set flip flop. The simple logic gate has a third input coupled to the first input and a fourth input coupled to the second input, and the reset-set flip flop has a fifth input coupled to the first input and a sixth input coupled to the second input. The low pass filter is coupled to the output of one of the simple logic gate and the reset-set flip flop.
A system and method for a radar system are provided. The radar system includes a leader radar device that includes a first clock generation circuit configured to generate a first clock signal, and a first transmitter and receiver configured to transmit and receive radar signals using a first local oscillator signal. The system includes a follower radar device. The follower radar device is configured to receive the first clock signal and the first local oscillator signal from the leader radar device. The follower radar device includes a second clock generation circuit configured to generate a second clock signal, wherein, in a default operational mode of the radar system at least a portion of the second clock generation circuit is disabled, and a second transmitter and receiver configured to transmit and receive first radar signals.
G01S 7/03 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe - Détails de sous-ensembles HF spécialement adaptés à ceux-ci, p.ex. communs à l'émetteur et au récepteur
G01S 13/02 - Systèmes utilisant la réflexion d'ondes radio, p.ex. systèmes du type radar primaire; Systèmes analogues
G01S 13/536 - Discrimination entre objets fixes et mobiles ou entre objets se déplaçant à différentes vitesses utilisant la transmission d'ondes continues non modulées, ou modulées en amplitude, en fréquence ou en phase
51.
SYSTEM AND METHOD FOR SECURING INDIRECT MEMORY ACCESSES
An integrated circuit (IC), including a functional circuit and a security system, is disclosed. The functional circuit generates a request packet for an indirect memory access of a memory. The security system validates the functional circuit based on a security attribute and a functional identifier of the functional circuit. Based on the request packet and the validation of the functional circuit, the security system identifies an instruction sequence associated with the indirect memory access. Further, the security system determines a type of the indirect memory access based on the instruction sequence, and validates the type of the indirect memory access based on the security attribute and the request packet. Based on the validation of the type of the indirect memory access, the instruction sequence is executed, thereby facilitating the indirect memory access for the functional circuit.
A method of controlling a frequency-modulated oscillator 110 of a phase-locked loop circuit 100 is described, wherein the oscillator 110 comprises a bank of capacitors 413. The method comprises the steps of (i) switching a capacitor 414 of the bank of capacitors 413 to change an output frequency 1050 of an output signal 112 of the oscillator 110 from a first frequency 1051 to a second frequency 1052, (ii) determining a frequency information associated with the capacitor 414 and based on at least one of the first frequency 1051 and the second frequency 1052; and (iii) writing the frequency information to a look-up table 224, 225, 226 stored in a control unit 120 of the oscillator 110. A corresponding frequency-modulated oscillator 110 and phase-locked loop circuit 100 are also described.
H03L 7/099 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03B 5/08 - Eléments déterminant la fréquence comportant des inductances ou des capacités localisées
H03L 7/093 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
A power down signal generator generates a power down signal. The power down signal generator includes a detection transistor, a resistor coupled in series with the detection transistor, and a compensation transistor coupled in parallel to the resistor. The detection transistor receives a first supply voltage in a first voltage domain and a current. A control voltage is generated across the resistor based on a first part of the current. The compensation transistor receives a bias voltage derived from a second supply voltage in a second voltage domain and sinks, based on the bias voltage, a second part of the current to maintain the control voltage within a predefined range. The generation of the power down signal is controlled based on the first supply voltage and the control voltage.
G06F 1/24 - Moyens pour la remise à l'état initial
G06F 1/28 - Surveillance, p.ex. détection des pannes d'alimentation par franchissement de seuils
H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
H03K 19/0185 - Dispositions pour le couplage; Dispositions pour l'interface utilisant uniquement des transistors à effet de champ
54.
END-TO-END TRANSACTION INTEGRITY THROUGH STANDARD INTERCONNECT
A system-on-chip (SoC) method and apparatus are disclosed for checking end-to-end integrity of communications over an network interconnect, where the SoC includes an initiator subsystem connected over the network interconnect to a target subsystem, wherein a first integrity module is configured to compute a first integrity value based on regular transaction messages sent or received by the initiator subsystem and to send a protecting information transaction (PIT) message over the network interconnect to the target subsystem, wherein a second integrity module is configured to compute a second integrity value based on regular transaction messages sent or received by the destination subsystem and to send a PIT response message over the network interconnect to the initiator subsystem, and wherein a compatibility module compares the first and second integrity values to verify the end-to-end integrity of the regular transaction messages sent or received over the network interconnect.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
The present invention relates to a Controller Area Network, CAN, transceiver, comprising: a CAN BUS interface, a transmit data, TXD, interface, a receive data, RXD, interface, a receiver, and a transmitter, wherein the transceiver is configured to receive, via the TXD interface, from a CAN controller, a digital TXD transmit signal representing a frame comprising a plurality of bits, wherein the transmitter is configured to generate, at the CAN BUS interface, a BUS signal representing the bits of the frame in a sequence, wherein the transceiver is configured to measure an electrical current of the transmitter, to detect each dominant bit represented by the BUS signal based on the transmitter current, to detect an error sequence of at least six consecutive dominant bits being detected based on the transmitter current, and to generate a control signal representing a fault of the transmitter in response to a detected error sequence. The present invention relates to a method for the CAN transceiver.
In accordance with a first aspect of the present disclosure, a near field communication (NFC) device is provided, comprising: an NFC transceiver configured to communicate with an external NFC device and to apply at least one transceiver parameter when communicating with the external NFC device; a calibration unit operatively coupled to the NFC transceiver and configured to calibrate the NFC transceiver; wherein the calibration unit is configured to calibrate the NFC transceiver by causing the NFC transceiver to apply different values of the transceiver parameter, measuring a noise level in the NFC transceiver for each applied value of the transceiver parameter, and selecting an optimal value from the applied values of the transceiver parameter in dependence on the noise level measured for each applied value. In accordance with a second aspect of the present disclosure, a corresponding method of operating an NFC device is conceived.
A memory includes a supply voltage generation circuit for providing a supply voltage to a plurality of SRAM cells of the memory during at least one mode of memory operation. The supply voltage generation circuit includes a first reference generation circuit that includes at least one SRAM cell with a replica SRAM latch. The first reference generation circuit provides a first voltage during an at least one mode of memory operation. The supply voltage generation circuit includes a second reference generation circuit that includes at least one SRAM cell with a replica SRAM latch. The second reference generation circuit provides a second voltage during the at least one mode of memory operation. The voltage generation circuit includes an output for providing a supply voltage to the plurality of cells during the at least one mode of memory operation.
H03K 19/094 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des dispositifs à semi-conducteurs utilisant des transistors à effet de champ
58.
CIRCUIT AND METHOD FOR DETECTING A FAULT INJECTION ATTACK IN AN INTEGRATED CIRCUIT
A fault detection circuit includes a plurality of conductors, a plurality of logic gates coupled to the conductors, a storage circuit, and a checker circuit. The conductors are arranged in parallel. Each logic gate is coupled to a first end of each conductor. The storage circuit is coupled to a second end of each conductor. The checker circuit is coupled to the storage circuit. A known initial bit pattern is provided to an input of the logic gates, and an output of the logic gates is provided to the storage circuit via the conductors. The checker circuit determines if the output of the logic gates stored in the storage circuit is an expected result. If the output is not the expected result, then the checker circuit provides an indication that a fault injection attack is occurring. In another embodiment, a method for detecting a fault injection attack is provided.
G06F 21/52 - Contrôle des usagers, programmes ou dispositifs de préservation de l’intégrité des plates-formes, p.ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p.ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données
G06F 21/71 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information
In accordance with a first aspect of the present disclosure, a tunable attenuator is provided, comprising: one or more transformer windings configured to facilitate attenuating a signal; one or more conductive loops provided underneath the transforming windings; a controller configured to control an amount of current flowing through the conductive loops, thereby providing a tunable attenuation of said signal. In accordance with a second aspect of the present disclosure, a corresponding method of producing a tunable attenuator is conceived.
H03H 11/24 - Atténuateurs indépendants de la fréquence
H03F 3/193 - Amplificateurs à haute fréquence, p.ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs comportant des dispositifs à effet de champ
In accordance with a first aspect of the present disclosure, a method of detecting a target is conceived, comprising: performing, by a first detection unit, at least one ultra-wideband (UWB) radar operation; generating, by the first detection unit, a first detection output based on a result of the UWB radar operation, wherein said first detection output is indicative of a first target movement; performing, by a second detection unit, at least one UWB ranging operation; generating, by the second detection unit, a second detection output based on a result of the UWB ranging operation, wherein said second detection output is indicative of a second target movement; accepting or rejecting, by a processing unit, the first detection output based on the second detection output. In accordance with further aspects of the present disclosure, a corresponding computer program and a corresponding target detection system are provided.
A transistor formed in a semiconductor substrate is provided with a cooling trench. The cooling trench is elongated and extends laterally from a first end of an elongated gate electrode disposed above a channel region of the transistor to a second end of the gate electrode in a first direction that is parallel to a top surface of the semiconductor substrate. The cooling trench is coupled to the first current terminal and extends laterally from a first end to a second end of the first elongated cooling trench along the first direction and extends vertically from the first current terminal and through the top surface into the semiconductor substrate. The cooling trench is filled throughout with a thermally-conductive material configured to dissipate heat from the channel region into the semiconductor substrate.
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
62.
CIRCUIT WITH TWO DIGITAL-TO-ANALOG CONVERTERS AND METHOD OF OPERATING SUCH THE CIRCUIT
A circuit 100 is described comprising (i) a first digital-to-analog converter 110, (ii) a second digital-to-analog converter 111, (iii) a plurality of unit elements 120, and (iv) switching circuitry 130. The switching circuitry 130 is adapted so that in a first switching state 231, a set of unit elements 221 of the plurality of unit elements 120 forms part of the first digital-to-analog converter 110, and in a second switching state 232, the set of unit elements 221 forms part of the second digital-to-analog converter 111. Furthermore, a corresponding method of operating a circuit 100 is described.
A digitally controlled DC-DC converter has a power stage coupled to an input voltage and to a control signal to generate an output voltage in response to the control signal. A controller generates the control signal and has an adjustment block to compare the output voltage to a reference voltage to generate a comparison signal, a logic circuit coupled to the adjustment block to receive the comparison signal and to generate the control signal in response to the comparison signal using a control word, and a digital-to analog converter coupled to the adjustment block, the power stage input voltage and the logic circuit to receive the control word from the logic circuit and to generate a converter voltage representing the control word using another voltage, the converter voltage being applied to the adjustment block to adjust the comparison signal.
H02M 3/157 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation avec commande numérique
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
H02M 1/088 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques pour la commande simultanée de dispositifs à semi-conducteurs connectés en série ou en parallèle
64.
Dynamic Configuration Of Reaction Policies In Virtualized Fault Management System
A method of dynamic configuration of reaction policies in virtualized fault management system includes disabling a fault handler circuit comprising a reaction core in response to receiving a request to modify a respective first reaction policy including a plurality of first recovery actions of the reaction core, wherein each of the first recovery actions is responsive to a respective fault indication. At least one event status is cleared from an event table of the fault handler circuit. The at least one event status is set in response to the fault handler circuit receiving the respective fault indication. The reaction core is configured with a second reaction policy including a plurality of second recovery actions.
A delta-sigma modulator including force circuitry that receives an output digital signal and provides a forced digital signal with a predetermined force state based on a force control signal, a combiner that subtracts the forced digital signal from the output digital signal for providing a digital error signal, and force correction circuitry that converts the digital error signal into one or more analog error correction signals applied to corresponding inputs of loop filter circuitry. The digital error signal and the force control signal may each be used to develop corresponding analog feedback signals used to adjust an analog input signal. The digital error signal may also be converted to one or more correction signals applied to corresponding inputs of the loop filter circuitry to correct the output digital signal. The digital error signal may also be used by a digital noise cancellation filter to further correct the output digital signal.
A method of manufacturing a semiconductor device is provided. The method includes placing a package substrate on a carrier substrate, forming a frame on the package substrate, and affixing an active side of a semiconductor die on the package substrate. The semiconductor die together with the frame and the package substrate form a cavity between the semiconductor die and the package substrate. At least a portion of the semiconductor die and the package substrate are encapsulated with an encapsulant. The frame is configured to prevent the encapsulant from entering the cavity.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
The disclosure relates to switching SIMs in a mobile telecommunications device based on geographic location. Example embodiments disclosed include a method of operating a mobile telecommunications device having a first SIM and a second SIM, the method comprising: identifying a geographic location of the device; operating the device using the first SIM to connect to a first network if the device is within a first geographic location; and operating the device using the second SIM to connect to a second network if the device is within a second geographic location and if a received signal strength indicator, RSSI, of the second network is greater than a predefined threshold value.
H04W 48/04 - Restriction d'accès effectuée dans des conditions spécifiques sur la base des données de localisation ou de mobilité de l'utilisateur ou du terminal, p.ex. du sens ou de la vitesse de déplacement
H04W 48/18 - Sélection d'un réseau ou d'un service de télécommunications
68.
SEMICONDUCTOR DEVICE WITH EXTRINSIC BASE REGION AND METHOD OF FABRICATION THEREFOR
A semiconductor device, such as a heterojunction bipolar transistor (HBT), may include an extrinsic base region that is connected to a collector region via semiconductor material formed in an opening in one or more dielectric layers interposed between the extrinsic base region and the collector region. The extrinsic base region may be formed from monocrystalline semiconductor material, such as silicon or silicon germanium, via selective epitaxial growth. An intrinsic base region may be formed adjacent to the extrinsic base region and may be interposed directly between the collector region and an intrinsic emitter region. A HBT with such an arrangement may have reduced base-collector capacitance and reduced base resistance compared to some conventional HBTs.
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
69.
SENSOR NODE WITH WIRELESS ENERGY HARVESTING AND METHOD FOR OPERATING THE SENSOR NODE
A sensor node is provided having a radio frequency (RF) circuit and a sensor interface circuit. The RF circuit wirelessly harvests energy from an external device such as a smart phone to produce a voltage at an output to charge a storage capacitor. The sensor interface circuit is configured to communicate with a sensor. In response to a request from the external device, the sensor node provides a voltage level of the capacitive element to the external device. The external device uses the voltage level to determine capabilities of the sensor node and to control sensing functions of the sensor node. In another embodiment, a method is provided to operate the sensor node.
G01R 19/25 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant une méthode de mesure numérique
70.
UBM-FREE METAL SKELETON FRAME WITH SUPPORT STUDS AND METHOD FOR FABRICATION THEREOF
An IC package includes one or more microelectronic devices, a plurality of package bumps disposed at a first side, and a metal structure electrically connecting at least a first device contact pad of a first microelectronic device and at least a first package bump of the plurality of package bumps. The metal structure includes an RDL trace extending between a first region aligned with the first device contact pad and a second region aligned with the first package bump, wherein the first package bump is mechanically and electrically connected directly to the second region of the RDL trace. The metal structure further includes a first via extending between the first region of the RDL trace and the first device contact pad and further includes a set of one or more support studs extending from the second region to a support surface facing the first side.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
71.
CONTINUOUS-TIME DELTA-SIGMA MODULATOR, INTEGRATED CIRCUIT AND METHOD THEREFOR
A continuous-time delta-sigma modulator, CTDSM (400, 500, 700, 800) is described that comprises: an operational transconductance amplifier, OTA, (406, 506, 706, 806) having an input port (404, 504, 719, 739, 819, 839) configured to receive an analog input signal and an output port (408, 508, 707, 708, 807, 808); an input low pass filter network comprising at least one input resistor, R1, (402, 502, 702, 722, 802, 822) at least one first shunt capacitor, C1, (403, 503, 703, 803) and at least one feedback resistor, Rdac (410, 510, 710, 810, 730, 830) connected to the input port of the OTA; an output filter network comprising a shunt second resistor, R2, (415, 515, 715, 815) in parallel to a second shunt capacitor, C2, (414, 514, 714, 814), and coupled to the output port (408, 508, 707, 708, 807, 808) of the OTA; a quantizer (413, 513, 713, 813) connected to the output filter network and having at least one output connected to the input port of the OTA via the at least one feedback resistor, Rdac; and wherein the input and output port of the OTA connected by a third feedforward-feedback capacitor, C3, (409, 509, 709, 729, 809, 829) arranged to provide a positive feedback around the OTA.
In one example, a circuit includes a secure chip storing one of an enclave of key values linked to an update code; a memory to store an updatable data set including the update value which corresponds to and is revised with the update code; and a logic circuit. The logic circuit is to: provide a key value, based to a revision to the update code, from among the enclave of key values, generate an authentication tag as a function of the provided key value, use the authentication tag to verify that the updatable data set is valid and up to date before using the updatable data set in an application specified for the updatable data set, and update the data set by storing a replacement updatable data set in the memory circuit and including, in the replacement updatable data set, a revised update value which corresponds to a revised update code that is used to provide another key value from among the enclave of key values.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
A coding module for a transceiver, the coding module comprising circuitry configured to:
receive transmit-data comprising a bitstream for transmission by the transceiver;
provide for 4B5B mapping of groups of four bits of the transmit-data to five bit codewords, comprising groups of five bits, for said transmission, wherein said codewords selected to represent the groups of four bits of the transmit-data comprise a predetermined mapping and are only selected from:
a) five bit codewords that comprise two zeros and three ones; and
b) five bit codewords that comprise three zeros and two ones.
A layered architecture for managing health of the electronic system comprises a plurality of health subsystems. Health subsystems receive health information from health monitors coupled to respective components of the electronic system and provide the health information to another health subsystem. Based on the received health information, the other health subsystem uses predictive data analytics to determine a health condition of the electronic system and update a health policy based on the predictive data analytics to improve prediction of the health condition of the electronic system.
The disclosure relates to an oscillator control system with dynamic control for power saving. Example embodiments include an oscillator control system comprising: an oscillator configured to provide an oscillator clock signal (osc_clk) in response to receiving an oscillator enable signal (en_osc); a system clock signal generator configured to generate a system clock signal (sys_clk); a system controller connected to receive a system clock signal (sys_clk) from the clock signal generator and an oscillator controller configured to provide the oscillator enable signal (en_osc) to the oscillator and receive the oscillator clock signal (osc_clk), to receive the system clock signal (sys_clk) from the clock signal generator and a system mode signal (sys_mode) from the system controller, and to receive a first change of state signal from an input of the oscillator control system, wherein the oscillator controller on receiving the first change of state signal, is configured to transition the oscillator control system from a first mode in which the oscillator clock signal and system clock signal are enabled to a second mode in which the oscillator clock signal and system clock signal are disabled by disabling the system clock signal (clk_enable) after a first set time period from receiving the change of state signal and to disable the oscillator enable signal (en_osc) after a second set time period following the first set time period.
An event manager for filtering safety and security events of a system including an event sequence list including predetermined event sequences in which each sequence includes at least one event identifier identifying a corresponding one of multiple monitored events, an event sequence array that stores a received event sequence in response to received event notifications, and a controller that stores an event identifier into the event sequence array and that determines whether the received event sequence matches at least one of the predetermined event sequences for determining a composite event and a response for each received event notification. The matching determination may be made with or without consideration of chronological order. A suspected composite event may be identified when multiple possible matches may exist, and a final composite event is ratified when only one match is found. An exception may be generated upon timeout of a timer.
A radio detection and ranging (radar) system includes various antennas and a controller. The antennas receive an interfering radio wave in an operating beamwidth of the radar system. The operating beamwidth is divided into a plurality of sectors. The controller determines a direction-of-arrival and a power level of the interfering radio wave. Further, the controller determines a power level of received signal energy within each sector of the plurality of sectors, and selects, from the plurality of sectors, a set of sectors such that a power level of received signal energy within each sector of the set of sectors is less than a threshold value of the corresponding sector. The controller then broadcasts another radio wave within the selected set of sectors to mitigate the interference of the interfering radio wave.
G01S 7/02 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe
G01S 13/58 - Systèmes de détermination de la vitesse ou de la trajectoire; Systèmes de détermination du sens d'un mouvement
G01S 13/931 - Radar ou systèmes analogues, spécialement adaptés pour des applications spécifiques pour prévenir les collisions de véhicules terrestres
78.
METHOD AND CIRCUIT FOR PROTECTING AN ELECTRONIC DEVICE FROM A SIDE-CHANNEL ATTACK
A method is provided for protecting an electronic device from a side-channel attack (SCA). The method includes providing a plurality of countermeasures that are for protecting the electronic device from the SCA. A set of countermeasures of the plurality of countermeasures is randomly enabled from the plurality of countermeasures to provide the protection during operation of the electronic device, such as for example, during an encryption operation. The method makes it more difficult for an attacker to construct a template of the electronic device that could be used in the SCA. In another embodiment, an electronic device is provided that incorporates the method.
One example discloses a power controller configured to modulate a load current sent to a load, including: a first chip including a set of higher-power circuits configured to directly modulate the load current sent to the load; a second chip electrically coupled to the first chip and including a set of lower-power circuits; wherein the set of higher-power circuits are electrically isolated from the set of lower-power circuits; a power control path distributed between the first chip and the second chip, and configured to modulate the load current sent to the load; a diagnostics path distributed between the first chip and the second chip, and configured to monitor the higher-power circuits in the first chip and the lower-power circuits in the second chip for a set of fault conditions; wherein a portion of the diagnostics path in the second chip includes a plausibility circuit configured to compare a load current commanded by a first portion of the power control path in the second chip to the load current sent to the load by a second portion of the power control path in the first chip; and wherein the plausibility circuit is configured to transmit a safe-state request if the load current sent to the load is not equivalent to the load current commanded; and wherein the safe-state request is transmitted in parallel to the load current commanded by the first portion of the power control path in the second chip.
H02H 7/20 - Circuits de protection de sécurité spécialement adaptés pour des machines ou appareils électriques de types particuliers ou pour la protection sectionnelle de systèmes de câble ou ligne, et effectuant une commutation automatique dans le cas d'un chan pour équipement électronique
H02H 1/00 - CIRCUITS DE PROTECTION DE SÉCURITÉ - Détails de circuits de protection de sécurité
A low power crystal oscillator is provided. The crystal oscillator includes a gain stage circuit having a first gain stage input coupled at a first oscillator terminal and configured to receive a first oscillator signal of a crystal. A first bias circuit is configured to generate a first bias voltage based on the first oscillator signal. A reference circuit is configured to generate a reference current based on the first bias voltage. A comparator circuit is configured to generate a clock signal based on the first oscillator signal and the first bias voltage. The comparator circuit includes a second bias circuit configured to generate a second bias voltage. The gain stage circuit includes a second gain stage input coupled to receive the second bias voltage.
H03B 5/36 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique l'élément actif de l'amplificateur comportant un dispositif semi-conducteur
H03B 5/06 - Modifications du générateur pour assurer l'amorçage des oscillations
81.
SEMICONDUCTOR DEVICE WITH LEAD-ON-CHIP INTERCONNECT AND METHOD THEREFOR
A method of forming a semiconductor device is provided. The method includes placing a semiconductor die and a leadframe on a carrier substrate. The semiconductor die includes a plurality of bond pads and the leadframe includes a plurality of leads. A first lead of the plurality of leads has a proximal end affixed to a first bond pad of the plurality of bond pads and a distal end placed on the carrier substrate. At least a portion of the semiconductor die and the leadframe is encapsulated with an encapsulant. The carrier substrate is separated from a first major side of the encapsulated semiconductor die and leadframe exposing a distal end portion of the first lead. A package substrate is applied on the first major side.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 23/367 - Refroidissement facilité par la forme du dispositif
82.
SEMICONDUCTOR DEVICE WITH UNDER-BUMP METALLIZATION AND METHOD THEREFOR
A method of manufacturing a semiconductor device is provided. The method includes forming a non-conductive layer over an active side of a semiconductor die partially encapsulated with an encapsulant. An opening in the non-conductive layer is formed exposing a portion of a bond pad of the semiconductor die. A laser ablated trench is formed at a surface of the non-conductive layer proximate to a perimeter of the opening. A bottom surface of the laser ablated trench is substantially roughened. An under-bump metallization (UBM) structure is formed over the bond pad and laser ablated trench.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
83.
TIME-CONTINUOUS POWER MONITORING FOR RADAR APPLICATIONS
A first input signal that corresponds to an output transmitted signal of an amplifier of a vehicle radar system is received and a digital threshold signal is transmitted to an input terminal of a digital-to-analog converter. The digital-to-analog converter is configured to generate an analog threshold value that is at least partially determined by a digital threshold value encoded into the digital threshold signal. If it is determined that a magnitude of the first input signal is less than a magnitude of the analog threshold value, a flag signal is transmitted to a system controller. The flag signal is indicative that a power level of the first output signal has fallen below a safety threshold value.
G01S 13/931 - Radar ou systèmes analogues, spécialement adaptés pour des applications spécifiques pour prévenir les collisions de véhicules terrestres
G01S 7/03 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe - Détails de sous-ensembles HF spécialement adaptés à ceux-ci, p.ex. communs à l'émetteur et au récepteur
A circuit arrangement for a touch sensor comprising:
a plurality of capacitive sensors configured to measure over a respective sampling period for detecting a touch event on a surface and provide an output;
an ADC to receive the output of the capacitive sensors and determine a digital value over a conversion period;
a first switch arrangement configured to selectively provide the output from the capacitive sensors to the ADC;
a controller configured to:
activate a first capacitive sensor to measure the capacitance for detecting a touch event and activate a second capacitive sensor for detecting a touch event such that the respective sampling periods are at least partly concurrent, and configured to control the first switch arrangement to cause the ADC to receive the output of the first capacitive sensor after its sampling time and receive the output of the second capacitive sensor after its sampling time.
A semiconductor device and methods of forming the same include a semiconductive fin protruding vertically from a body region and extending along a first direction, an insulator material above the body region and surrounding a lower portion of the fin, and a gap region between first and second ends of the semiconductive fin where at least a top portion of the semiconductive fin is absent. The device includes current terminals coupled to first and second ends of the fin, and a gate electrode and a gate extension coupled to the fin. The gate electrode surrounds the top portion of the semiconductive fin and is separated from the semiconductive by a gate insulator material. The gate extension has a first end adjacent to the gate electrode and a second end above the body region within the gap region.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 21/84 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant autre chose qu'un corps semi-conducteur, p.ex. étant un corps isolant
Various embodiments relate to a data processing system including instructions embodied in a non-transitory computer readable medium, the instructions for a cryptographic operation using masked coefficients of a polynomial having d arithmetic shares for lattice-based cryptography in a processor, the instructions, including: shifting an arithmetic share of the d arithmetic shares by a first bound λ0; converting the d shifted arithmetic shares to d Boolean shares; securely subtracting the first bound λ0 and a second bound λ1 from the Boolean shares to obtain z′B,k+1 having d shares, wherein k is the number of bits in the masked coefficients of the polynomial; setting the shares of a boundary check bit to a sign bit of z′B,k+1; and carrying out a cryptographic operation using the d arithmetic shares of the polynomial when the d shares of the boundary check bit indicate that the coefficients of the polynomial are within the first bound λ0 and second bound λ1.
H04L 9/30 - Clé publique, c. à d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
87.
WIRELESS CHARGING TRANSMITTER AND METHOD OF OPERATING THE SAME
A wireless charging transmitter, controller and system are disclosed. The transmitter has a full-bridge inverter having two full-bridge output nodes, a resonant circuit comprising a series arrangement of a transmitter inductor and a first capacitor, and a second capacitor in parallel with the series arrangement, a PI-filter coupled between the second capacitor and the full-bridge inverter; wherein the controller is configured to measure a Q-factor of the resonant circuit by: controlling the full-bridge inverter to connect an input voltage supply to the PI-filter to supply an excitation pulse to the resonant circuit; controlling the full-bridge inverter to disconnect the input voltage supply and initiate a resonance in the resonant circuit; controlling a switch in the full-bridge inverter to provide an reference ground to a first terminal of the transmitter inductor; and measuring a decay of the voltage at a second terminal of the transmitter inductor.
H02J 50/12 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage inductif du type couplage à résonance
H02J 50/60 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique sensibles à la présence d’objets étrangers, p.ex. détection d'êtres vivants
88.
METHOD FOR PROTECTING A MACHINE LEARNING MODEL FROM A SIDE CHANNEL ATTACK
A method is provided for protecting a machine learning (ML) model from a side channel attack (SCA). The method is executed by a processor in a data processing system. The method includes generating a first random bit. A first weighted sum is computed for a first connection between a node of a first layer and a node of a second layer of the ML model. The first weighted sum for the first connection is equal to a multiplication of the weight of the first connection multiplied by an input to the selected node. In the multiplication, one of the weight or the input is negated conditioned on a value of the random bit. A first output including the computed first weighted sum is provided to one or more nodes of a second layer of the plurality of layers.
The present invention relates to a CAN node being configured to predict, based on the at least one response message and a reference response, a fault of the CAN network and to determine a fault location of the predicted fault of the CAN network. The present disclosure also relates to a CAN system and a method for the CAN node.
A method is provided for protecting a machine learning model from a side channel attack. A weighted sum vector having first and second elements is initialized. A weight vector for a connection between a node of a first layer and a node of a second layer is multiplied with an input vector to the node of the first layer. A first element of the weight vector includes a weight, and a first element of the input vector includes the input. A second element of the weight vector is a negation of the first element of the weight vector and the second element of the input vector equals the first element of the input vector. A multiplication result is added to the weighted sum vector to produce a computed weighted sum vector. An output vector including the computed weighted sum vector is provided to the node of the second layer.
In accordance with a first aspect of the present disclosure, a communication device is provided, comprising: a plurality of antennas configured to receive an ultra-wideband signal; a processing unit configured to determine an angle of arrival, AoA, of the ultra-wideband signal, wherein said AoA is based on a phase difference of arrival, PDoA, derived from the ultra-wideband signal; a polarization angle estimation unit configured to estimate a polarization angle of the ultra-wideband signal; wherein the processing unit is further configured to determine the AoA of the ultra-wideband signal using the polarization angle estimated by the polarization angle estimation unit. In accordance with a second aspect of the present disclosure, a corresponding method of operating a communication device is conceived. In accordance with a third aspect of the present disclosure, a computer program is provided for carrying out said method.
RF signal is received (1006). The received RF signal includes a first RF signal encoding a first orthogonal frequency-division multiplexing (OFDM) symbol of a first long-term evolution (LTE) V2X data packet. A channel estimation in the time domain is determined (1012) using the received signal and an as-transmitted time domain version of an L-LTF symbol is determined (1014). The channel estimation in the time domain is applied to the as-transmitted time domain version of the L-LTF symbol to determine an as-transmitted version of the L-LTF symbol that exhibits channel fading (1018). A first portion of the as-transmitted version of the L-LTF symbol that exhibits channel fading is subtracted from a second portion of the received RF signal (1022) to remove inter-symbol interference from the received signal to generate a second received RF signal.
An object detection system that includes a transceiver and processing circuitry is disclosed. The transceiver receives a chirp wave reflected from a real object that is in the vicinity of the object detection system, and generates echo data based on the received chirp wave. The processing circuitry generates detection data that includes the echo data and target data associated with a virtual object. The target data is generated to identify a fault in the object detection system while the object detection system is operating in-field. Further, the target data is indicative of predefined parameters of the virtual object. The processing circuitry then processes the detection data to detect the virtual object and extract various parameters of the detected virtual object. Further, the processing circuitry identifies the fault in the object detection system based on a comparison of the extracted parameters with the predefined parameters.
G01S 7/52 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe
G01S 15/42 - Mesure simultanée de la distance et d'autres coordonnées
G01S 15/931 - Systèmes sonar, spécialement adaptés à des applications spécifiques pour prévenir les collisions de véhicules terrestres
94.
INTERFACE CIRCUIT AND METHOD FOR PROVIDING DC BIAS VOLTAGE CORRECTION
An interface circuit includes an analogue to digital converter having an input configured to receive an input signal having an unknown DC bias voltage via an input resistance and provide an output signal to an ADC feedback loop. The ADC feedback loop includes a digital filter arranged to digitally filter the fedback output signal. A digital to analogue converter (DAC) forming a DC feedback loop with the ADC and arranged to convert the digitally filtered fedback output signal to an analogue signal that is provided to the input of the ADC, wherein the analogue signal that is provided to the input of the ADC is arranged to include a DC bias component that is comparable to a DC bias component of a current of the input signal passing through the input resistor.
Tweakable block cipher encryption is described using a buffer identifier and a memory address. A method includes receiving a data block from a buffer, the buffer having a buffer identifier, combining a memory address and the buffer identifier to generate a tweak, encrypting the data block using the tweak in a tweakable block cipher, and storing the encrypted data block in in a memory at a location corresponding to the memory address
The received RF signal includes a first RF signal encoding a first orthogonal frequency-division multiplexing (OFDM) symbol of a first long-term evolution (LTE) V2X data packet. A legacy long training field (L-LTF) symbol is determined using the received RF signal (608), a channel estimation is calculated (612) using the L-LTF symbol, and legacy signal (L-SIG) field control bits are determined (614) from the received RF signal, the L-SIG field control bits including a plurality of IQ samples. A plurality of candidate L-SIG decodings are generated (618) using the IQ samples and the channel estimation, wherein each candidate L-SIG decoding of the plurality of L-SIG decodings is generated by setting a different number of IQ samples in the L-SIG field control bits to zero values (616), and a first L-SIG decoding of the plurality of candidate L-SIG decodings is identified (624). A data field from the received RF signal is decoded using the first L-SIG decoding (626).
Performing a Fast Fourier Transformation (FFT) with increased resolution by applying an adaptive left shift to signed binary integers of an input of a radix kernel and adaptive right shift to signed binary integers of an output of a butterfly of the radix kernel which is based on a leading bit count of the input. The adaptive left shift increases a resolution of the radix kernel computation and the adaptive right shift determines a number of bits of the increased resolution preserved in an output of the radix kernel.
G06F 17/14 - Transformations de Fourier, de Walsh ou transformations d'espace analogues
G06F 7/74 - Sélection ou codage, à l'intérieur d'un mot, de la position d'un ou de plusieurs chiffres binaires ayant une valeur spécifiée, p.ex. détection du un ou du zéro le plus ou le moins significatif, codeurs de priorité
G06F 5/01 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour le décalage, p.ex. la justification, le changement d'échelle, la normalisation
98.
INJECTION CURRENT MODULATION FOR CHIRP SIGNAL TIMING CONTROL
A radar system injects a calibrated current at a signal generator during a reset portion and acquisition portion of each chirp period. The signal generator employs “gear-switching” to reduce PLL bandwidth during an acquisition phase and to increase the phase lock loop (PLL) bandwidth during a reset phase. By employing gear switching to change the bandwidth of the PLL circuit during the different portions of each chirp period, the length of the reset period is reduced, thus improving overall efficiency of the radar system while maintaining good performance.
H03L 7/099 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
A transceiver comprising:
a transmitter configured to transmit a signal comprising differential voltages to at least a first terminal and a second terminal;
at least one receiver;
a controller configured to provide control signals to the transmitter to cause the transmitter to transmit symbols, wherein each symbol comprises a predefined set of said differential voltages including at least a positive differential voltage and a negative differential voltage; and
a signal balance module configured, for one or more symbols, to:
determine a first duration of the positive differential voltage of said one or more symbols;
determine a second duration of the negative differential voltage of said one or more symbols;
based on determination of a difference between the first and second durations, provide for control of the controller or control of the transmitter to reduce the difference between the first and second durations in a further symbol relative to the one or more symbols.
H04B 1/52 - Dispositions hybrides, c. à d. dispositions pour la transition d’une transmission bilatérale sur une voie à une transmission unidirectionnelle sur chacune des deux voies ou vice versa
H04B 1/58 - Dispositions hybrides, c. à d. dispositions pour la transition d’une transmission bilatérale sur une voie à une transmission unidirectionnelle sur chacune des deux voies ou vice versa
100.
Signal shaping for compensation of metastable errors
A circuit that receives a series a digital signal values from a digital circuit output where the output has a propensity to produce digital values with a metastable error. The circuit produces an analog output signal having values over time corresponding to the digital signal values. The circuit includes two data paths that receive the digital signal values and produce a delayed analog signal. One data path includes an analog delay and the other data path includes a digital delay and a digital to analog converter. The circuit uses the output of the two data paths to adjust a later output analog signal value that is produced by the analog circuit output subsequent to a former output analog signal value produced by the analog circuit output that corresponds to a digital signal value of the series with a metastable error to compensate for the metastable error in the output signal.
