A device includes a hardware block to perform a hardware process and internal logic coupled between a processing device, which executes instructions, and the hardware block. The internal logic can one of measure execution time or count clock cycles of at least a portion of the hardware process. The internal logic can further, in response to the measured execution time or the counted clock cycles satisfying a predetermined condition, provide data associated with the one of the execution time measurement or the clock cycles count to the processing device, the data being statistically indicative of a latency of data packets sent by the hardware process over a total time the hardware process executes.
A system includes a data processing unit (DPU) and DPU resource management circuits. A DPU resource management circuit establishes an interface associated with managing resources of the DPU, where establishing the interface is based on another DPU resource management circuit of the system accessing the DPU. The DPU resource management circuit monitors usage of the resources of the DPU based on auditing data provided by the second DPU resource management circuit. In some cases, the DPU resource management circuit may allocate resources of the DPU to an application. The DPU resource management circuit generates a catalog data structure of the resources of the DPU. The catalog data structure includes entries corresponding to resources of the DPU and functions provided by the resources.
A vertical-cavity surface-emitting laser (VCSEL) is provided that includes a mesa structure disposed on a substrate. The mesa structure defines an emission axis of the VCSEL. The mesa structure includes a first reflector, a second reflector, and a cascaded active region structure disposed between the first reflector and the second reflector. The cascaded active region structure includes a plurality of cascaded active region layers disposed along the emission axis, where each of the cascade active region layers includes an active region having multi-quantum well and/or dots layers (MQLs), a tunnel junction aligned with the emission axis, and an oxide confinement layer. The oxide confinement layer is disposed between the tunnel junction and MQLs, and has an electrical current aperture defined therein. The mesa structure defines an optical window through which the VCSEL is configured to emit light.
H01S 5/183 - Lasers à émission de surface [lasers SE], p.ex. comportant à la fois des cavités horizontales et verticales comportant uniquement des cavités verticales, p.ex. lasers à émission de surface à cavité verticale [VCSEL]
H01S 5/30 - Structure ou forme de la région active; Matériaux pour la région active
H01S 5/34 - Structure ou forme de la région active; Matériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p.ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH]
H01S 5/42 - Réseaux de lasers à émission de surface
4.
METHOD FOR IMPROVING PROCESSOR UTILIZATION IN AN EVENT-DRIVEN COOPERATIVELY SCHEDULED ENVIRONMENT
Techniques described herein include managing scheduling of interrupts by receiving a data packet comprising an indication of an interrupt to be delivered, determining an availability status of a processing thread, and managing an interrupt status indicator in response to determining the availability status. A value of the interrupt status indicator corresponds to a quantity of pending interrupts. An event handling circuit processes the interrupt or one or more pending interrupts using the processing thread.
An Integrated Circuit (IC) includes one or more functional hardware circuits, one or more processor cores, a cause-tree circuit, a memory buffer, and an analysis circuit. The processor cores are to handle events occurring in the functional hardware circuits. The cause-tree circuit includes leaf nodes, middle nodes and a root node. The leaf nodes are to collect the events from the one or more functional hardware circuits. The middle nodes are to coalesce the collected events and to deliver the events to the root node. The memory buffer is to buffer a plurality of the events delivered to the root node, so as to trigger the processor cores to handle the buffered events. The buffer analysis circuit is to analyze a performance of the cause-tree circuit based on the events buffered in the memory buffer.
Devices, apparatuses, systems, and methods are provided for improved thermal management in networking computing devices. An example thermal management apparatus includes a housing defining a first end and a second end opposite the first end. The apparatus further includes an electronic component supported within the housing, such as a GPU. The apparatus includes a primary inlet that receives a primary airflow having a first temperature and a secondary inlet that receives a secondary airflow having a second temperature where the second temperature is different than the first temperature. The primary airflow and the secondary airflow are collectively configured to dissipate heat generated by the electronic component.
Technologies for duty cycle distortion (DCD) estimation are described. A transmitter includes a first output driver comprising a first complementary metal-oxide semiconductor (CMOS) amplifier and a first attenuator coupled to an output of the first CMOS amplifier. The first CMOS amplifier receives an input signal and outputs an intermediate signal to the first attenuator. The first attenuator receives the intermediate signal and outputs an output signal having a signal swing that is less than a signal swing of the input signal. A first duty cycle correction (DCC) loop is coupled to the first output driver. The first DCC loop estimates first DCD in the intermediate signal output by the first CMOS amplifier.
H03K 3/017 - Réglage de la largeur ou du rapport durée période des impulsions
H03K 19/0185 - Dispositions pour le couplage; Dispositions pour l'interface utilisant uniquement des transistors à effet de champ
H03K 19/17784 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels pour l'adaptation des paramètres physiques pour la tension d'alimentation
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p.ex. réseaux de mise en forme adaptatifs
8.
Mechanical thermal interface for improved heat dissipation in network transceivers
A transceiver includes, (a) a communication circuit, which is configured to exchange signals between a cable and a communication unit when the transceiver is connected to the communication unit, and (b) a housing, including: (i) a first shell including a substrate having the communication circuit disposed thereon, (ii) a second shell, which is configured to connect with the first shell for encapsulating the communication circuit, the second shell has an opening facing the communication circuit, and (iii) a base plate, which is fitted in the opening and including a first surface having one or more cooling fins formed thereon, and a second surface, opposite the first surface that is facing the communication circuit, the base plate is configured to transfer heat between the communication circuit and the cooling fins.
G02B 6/42 - Couplage de guides de lumière avec des éléments opto-électroniques
H04B 10/40 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs-récepteurs
9.
SYSTEMS AND METHODS OF FLOW SIZE CLASSIFICATION USING MACHINE LEARNING
A network device, system-on-a-chip, and method of performing packet handling are described. A packet is received, and data associated with the packet is processed, using a configurable artificial intelligence engine, to generate a size classification for a flow associated with the packet. An action is performed based, at least in part, on the size classification for the flow associated with the packet.
H04L 41/16 - Dispositions pour la maintenance, l’administration ou la gestion des réseaux de commutation de données, p.ex. des réseaux de commutation de paquets en utilisant l'apprentissage automatique ou l'intelligence artificielle
G06N 5/02 - Représentation de la connaissance; Représentation symbolique
H04L 47/2441 - Trafic caractérisé par des attributs spécifiques, p.ex. la priorité ou QoS en s'appuyant sur la classification des flux, p.ex. en utilisant des services intégrés [IntServ]
Apparatuses, systems, and methods are provided for scalable networking systems. An example system includes a plurality of core switches and a first stage patch panel associated with operation of a first set of network ports. In an operational configuration in which the first stage patch panel is coupled with the plurality of core switches, the first stage patch panel is configured to operatively couple the first set of network ports and a first portion of the plurality of core switches such that signals may pass therebetween. Furthermore, the first stage patch panel may preclude communication to a remaining portion of the plurality of core switches. The system may include a second stage patch panel associated with a second set of network ports that is operatively coupled with the plurality of core switches in the absence of the first stage patch panel so as to scale the networking system.
A method for collective communications includes invoking a collective operation over a group of computing processes in which the processes concurrently transmit and receive data to and from other processes in the group via a communication medium. Messages are composed for transmission by source processes including metadata indicating how the data to be transmitted by the source processes in the collective operation are to be handled by destination processes that are to receive the data and also including in at least some of the messages the data to be transmitted by one or more of the source processes to one or more of the destination processes. The composed messages are transmitted concurrently from the source processes to the destination processes in the group over the communication medium. The data are processed by the destination processes in response to the metadata included in the messages received by the destination processes.
A system including an array of functional units connected via a two-dimensional mesh network is described. A first functional unit in the array of function units includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including generating a node identifier identifying a second functional unit in the array of functional units, and transmitting, over the two-dimensional mesh network, the node identifier identifying the second functional unit in the array of functional units. The node identifier may include a mesh interface component and a port identifier, and one or more information elements selected from the group consisting of a payload, a target node identifier, a target type identifier, an information type identifier, a linear identifier, and a protocol identifier.
Systems, computer program products, and methods are described herein for dynamic reconfiguration of network communications. An example system includes a first network pod including a first set of network ports, a second network pod including a second set of network ports, a set of network cores, and a first intermediate network switch. The first intermediate switch operatively couples the first network pod, the second network pod, and the set of network cores. The first intermediate network switch is configured to selectively establish full bisectional bandwidth data communication between a subset of the set of network cores, a subset of the first set of network ports, and a subset of the second set of network ports.
A virtual wire system includes a source device, a target device, and a mesh interface connecting the source device and the target device. One or more mesh messages are transmitted over the mesh interface from the source device to the target device, and the one or more mesh messages indicate a change in a value of a signal level at the source device. The source device may include a plurality of virtual wire sources, a virtual wire encoder, and a virtual wire arbiter operatively coupled to the plurality of virtual wire sources and the virtual wire encoder. The virtual wire arbiter is configured to determine whether information from a virtual wire source should be transmitted to the virtual wire encoder. The virtual wire encoder is configured to receive information from the virtual wire arbiter, combine the information into a single virtual wire message, and transmit the single virtual wire message to a first mesh interface component in the source device.
Various embodiments of the present disclosure are directed to accessing a quantum communication channel undetected and/or characterizing this communication channel based upon attempted access. An example method includes accessing a quantum communication channel transmitting one or more qubits. The method includes the introduction of a noise signal to the quantum communication channel and then applying in its absence one or more weak or variable-strength measurements to the quantum communication channel. A strength of at least one measurement of the one or more measurements is based at least in part upon the current noise signal. The method further includes obtaining information associated with the one or more qubits based on the one or more measurements.
A computing device which may include a programmable hardware device and a microcontroller to, based on a policy and parameters of a packet received by the programmable hardware device, program a rule in the programmable hardware device, the rule indicating how to process the packet.
YISSUM RESEARCH DEVELOPMENT COMPANY OF THE HERREW UNIVERSITY LTD. (Israël)
Inventeur(s)
Patronas, Ioannis (giannis)
Zahavi, Eitan
Bakopoulos, Paraskevas
Schapira, Michael
Mentovich, Elad
Abrégé
A method for distributed allocation of data paths in an optical network (100) including optical switches (30, 32, 130) connected by optical links (44, 140), includes receiving a request for a data path for connecting a source node (10) and a destination node (20). In in response to the request, one or more queries are sent, the queries corresponding to one or more candidate optical circuits that connect the source node and the destination node, the queries requesting one or more processors (230) to configure the optical switches along the candidate optical circuits to reserve optical channels on the optical links of the candidate optical circuits for the requested data path. An optical circuit is identified from among the candidate optical circuits, in which all the optical channels for the requested data path have been reserved successfully. The requested data path is established over the identified optical circuit.
In one embodiment, a communication apparatus, including a network interface configured to receive over a network a sequence of data packets of a network flow having a defined packet order, wherein the network interface is configured to receive an out-of-order data packet instead of multiple missing data packets according to the defined packet order, a timer, and packet processing circuitry configured to activate the timer responsively to receiving the out-of-order data packet, and set the time period over which the timer is activated responsively to a quantity of the multiple missing data packets.
Systems, computer program products, and methods are described herein for machine learning (ML) based system for network resilience and steering. An example system monitors data movement across one or more network ports; extracts network performance indicators associated with the data movement; determines, via a machine learning (ML) subsystem, that a status of a first network port is indicative of operational failure based on at least the network performance indicators; determines that the first network port is associated with a first network port cluster; determines a redundant network port and an intermediate network switch associated with the first network port cluster; and triggers the intermediate network switch to reroute a portion of network traffic from the first network port to the redundant network port in response to the status of the first network port.
H04L 43/065 - Génération de rapports liés aux appareils du réseau
H04L 41/16 - Dispositions pour la maintenance, l’administration ou la gestion des réseaux de commutation de données, p.ex. des réseaux de commutation de paquets en utilisant l'apprentissage automatique ou l'intelligence artificielle
H04L 43/0817 - Surveillance ou test en fonction de métriques spécifiques, p.ex. la qualité du service [QoS], la consommation d’énergie ou les paramètres environnementaux en vérifiant la disponibilité en vérifiant le fonctionnement
H04L 45/28 - Routage ou recherche de routes de paquets dans les réseaux de commutation de données en utilisant la reprise sur incident de routes
20.
MACHINE LEARNING (ML) BASED SYSTEMS FOR AIR GAPPING NETWORK PORTS
Systems, computer program products, and methods are described herein for machine learning (ML) based network resilience and steering. An example system monitors data traffic across one or more network ports and determines a first data traffic pattern from the data traffic. The system further determines, via a ML subsystem, that the first data traffic pattern is indicative of a security threat to a first network port. In response to determining that the first data traffic pattern is indicative of the security threat to the first network port, the system further isolates the first network port from the one or more network ports.
H04L 41/16 - Dispositions pour la maintenance, l’administration ou la gestion des réseaux de commutation de données, p.ex. des réseaux de commutation de paquets en utilisant l'apprentissage automatique ou l'intelligence artificielle
H04L 47/17 - Interaction entre les nœuds intermédiaires, p.ex. nœud après nœud.
A system includes a bus interface and circuitry. The bus interface is configured to communicate with an external device over a peripheral bus. The circuitry is configured to support a plurality of widgets that perform primitive operations used in implementing peripheral-bus devices, to receive a user-defined configuration, which specifies a user-defined peripheral-bus device as a configuration of one or more of the widgets, and to implement the user-defined peripheral-bus device toward the external device over the peripheral bus, in accordance with the user-defined configuration.
Systems and methods for resilience in network communications are provided. An example system includes a first network port pair including a first input network port and a first output network port. The system further includes an intermediate switch configured to communicably connect the first input network port and the first output network port and a first redundant network port communicably connected with the intermediate switch. The intermediate switch establishes communication between the first input network port and the first redundant network port in an instance in which the intermediate switch receives an indication of a malfunction associated with the first output network port or establishes communication between the first output network port and the first redundant network port in an instance in which the intermediate switch receives an indication of a malfunction associated with the first input network port.
Systems, apparatuses, and methods are provided for resilience in network communications. An example system includes at least one first network port including a first plurality of subports and at least one second network port including a second plurality of subports. The system also includes an intermediate switch communicably connected to the at least one first network port and the at least one second network port. At least one of the first plurality of subports includes at least one first offline subport that is inoperable in an instance in which each of the remaining first plurality of subports are operable. The intermediate switch is configured to route communication from one of the second plurality of subports to the at least one first offline subport in an instance in which the intermediate switch receives an indication of a malfunction associated with the first plurality of subports.
A communication system includes at least one send queue, containing send queue entries pointing to packets to be transmitted over a network by packet sending circuitry. A clock work queue contains clock queue entries to synchronize sending times of the packets pointed to by the send queue entries. At least one arming queue contains arming queue entries to arm the clock work queue at selected time intervals.
Apparatuses, systems, and techniques of using one or more circuits (e.g., of a network interface) to obtain contents of at least one memory region usable, by one or more processes being performed by a host computing system, to store dynamic memory allocations, and determine whether any of the process(es) is performing at least one potentially harmful task based at least in part on the contents of the memory region(s).
Apparatuses, systems, and techniques of using one or more circuits (e.g., of a network interface) to obtain assembly code for one or more machine code segments loaded and/or injected into a process, and determine whether the assembly code is likely to perform at least one unauthorized task.
G06F 21/55 - Détection d’intrusion locale ou mise en œuvre de contre-mesures
G06F 21/52 - Contrôle des usagers, programmes ou dispositifs de préservation de l’intégrité des plates-formes, p.ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p.ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données
G06F 21/56 - Détection ou gestion de programmes malveillants, p.ex. dispositions anti-virus
27.
QUANTUM-CLASSICAL HYBRID SECURITY SYSTEMS AND METHODS
Embodiments are disclosed for providing quantum-classical hybrid security. An example system includes a hybrid quantum-classical transmitter device. The hybrid quantum-classical transmitter device includes a classical transmitter and a quantum transmitter. The classical transmitter is configured to generate data based on a cryptography technique. The classical transmitter is also configured to generate a classical bitstream representation of the data, where the classical bitstream is configured for transmission via an optical communication channel. The quantum transmitter is configured to embed one or more qubits into the classical bitstream to generate a hybrid quantum-classical bitstream for transmission via the optical communication channel.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p.ex. couplage ou commande de qubit
A relay device is provided that may identify a quantity of empty data byte locations in a data buffer of the relay device. The relay device may receive an indicator associated with transmitting data packets. The relay device may pause or enable a lossless flow of data between the relay device, a host device, and a peer device based on the quantity of empty data byte locations, the indicator, or both. The relay device may include a first data interface coupled with a peer device, a second data interface coupled with a host device, a data buffer configured to store data packets received from the host device, and a state machine that enables a lossless transmission of data between the host device and peer device. The state machine may transmit a pause frame to the host device based on a data buffer utilization reaching a data storage capacity.
H04L 47/32 - Commande de flux; Commande de la congestion en supprimant ou en retardant les unités de données, p.ex. les paquets ou les trames
H04L 47/30 - Commande de flux; Commande de la congestion en combinaison avec des informations sur l'occupation de mémoires tampon à chaque extrémité ou aux nœuds de transit
A method includes providing a plurality of processes interconnected by a network, each of the plurality of processes being configured to hold a block of data destined for others of the plurality of processes. A set of data for all-to-all data exchange is received from one or more of the processes. The set of data is configured as a plurality of blocks of data in a matrix as matrix data, the matrix being distributed among the plurality of processes. The matrix data is transposed by changing the position of selected blocks of data of the plurality of blocks of data relative to the other blocks of data of the plurality of the blocks of data, without changing the structure of each of the blocks of data. The transposed matrix data is over the network and is then received, repacked, and conveyed to destination processes.
A network interface device includes a local register and packet processing circuitry coupled to the local register. The packet processing circuitry is to: capture a network packet transmitted by a software application running on an integrated computing system; capture, at time of transmission of the network packet, a value of a physical clock as a receive timestamp for subscriber entities that are running on the integrated computing system; store the receive timestamp in the local register; associate the receive timestamp from the local register with a first packet copy of the network packet; insert the first packet copy to a first receive pipeline of a first subscriber entity; associate the receive timestamp from the local register with a second packet copy of the network packet; and insert the second packet copy to a second receive pipeline of a second subscriber entity.
A network adapter includes a port and one or more circuits. The port is to send packets to a network in accordance with a Remote Direct Memory Access over Converged Ethernet (RoCE) protocol. The one or more circuits are to decide whether a packet is permitted to undergo Adaptive Routing (AR) in being routed through the network, to mark the packet with an indication of whether the packet is permitted to undergo AR, and to send the marked packet to the network via the port.
H04L 45/00 - Routage ou recherche de routes de paquets dans les réseaux de commutation de données
H04L 67/1097 - Protocoles dans lesquels une application est distribuée parmi les nœuds du réseau pour le stockage distribué de données dans des réseaux, p.ex. dispositions de transport pour le système de fichiers réseau [NFS], réseaux de stockage [SAN] ou stockage en réseau [NAS]
H04L 69/22 - Analyse syntaxique ou évaluation d’en-têtes
32.
Selective aggregation of messages in collective operations
A method for collective communications includes invoking a collective operation over a group of computing processes in which the processes in the group concurrently transmit and receive data messages to and from other processes in the group via a communication medium. The processes detect respective sizes of the data messages and transmit the data messages for which the respective sizes are greater than a predefined threshold to respective destination processes in the group without aggregation. The data messages for which the respective sizes are less than the predefined threshold are aggregated, and the aggregated data messages are transmitted to the respective destination processes.
An electronic device may include a receptacle cage comprising a longitudinal aperture extending along a portion of a top surface of the receptacle cage, a cooling body disposed directly on the top surface of the receptacle cage, wherein a longitudinal portion of a bottom surface of the cooling body is disposed within the longitudinal aperture on the top surface of the receptacle cage, a first conduit to deliver a liquid coolant into an interior of the cooling body, and a second conduit to deliver the liquid coolant from the interior of the cooling body.
Apparatuses, systems, and techniques of using parallel processor(s), such as one or more graphics processing units, to process packets (e.g., in real time). In at least one embodiment, a processor (e.g., a parallel processing unit, a central processing unit, and/or the like) detects when packet data has been stored in a memory accessible by the parallel processing unit. Then, the parallel processing unit may process the packet data to produce output data.
Technologies for payload direct memory storing (PDMS) for out-of-order delivery of packets in remote direct memory access (RDMA) are described. A responder device includes an RDMA transport layer that can receive packets out of order and allow direct data placement of packet data in order. The responder device receives a first packet with a first packet number and first location information. The responder device stores first packet data to a first location according to the first location information. The responder device also receives a second packet and stores second packet data to a second location according to the second location information. A second packet number indicates that the first packet is received out of order. The first and second packet data are stored in order. The responder device can provide an indication that a message has arrived in response to determining that all packets of the message have arrived.
H04L 69/22 - Analyse syntaxique ou évaluation d’en-têtes
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
G06F 15/167 - Communication entre processeurs utilisant une mémoire commune, p.ex. boîte aux lettres électronique
A network adapter includes a port and one or more circuits. The port communicates packets over a network in which switches forward packets in accordance with tuples of the packets. The one or more circuits are to hold a user-programmable scheme specifying assignments of the packets of a given flow destined to a peer node to sub-flows having respective different tuples, assign first packets of the given flow to one or more of the sub-flows in accordance with the user-programmable scheme, by setting respective tuples of the first packets, transmit the first packets to the peer node via the port, monitor notifications received from the network, the notifications being indicative of respective states of the sub-flows, based on the notifications and on the user-programmable scheme determine an assignment of second packets of the given flow to the sub-flows, and transmit the second packets to the peer node via the port.
An electronic circuit may include at least two capacitors arranged in parallel; at least two resistors arranged in series; a positive supply voltage connected to the resistors; a negative supply voltage connected to the resistors, the resistors producing a reference signal; a source circuit producing a source signal and connected to the positive supply voltage and negative supply voltage; and a receiving circuit connected to the positive supply voltage and negative supply voltage, and receiving the source signal and reference signal.
H03K 5/24 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p.ex. la pente, l'intégrale la caractéristique étant l'amplitude
38.
APPARATUSES AND METHODS FOR REDUCING DATA PORT DELAY
Systems, methods, apparatuses, and computer program products for reducing data port downtime are provided. An example network interface device of the present disclosure includes a first data port and a second data port. The network interface device performs a first link training process associated with the first data port coupled to a first communication link to determine a first communication parameter set for the first communication link. The network interface device then deactivates the first data port and performs a second link training process associated the second data port coupled to a second communication link to determine a second communication parameter set. Based on a network usage parameter set associated with a data plane of the network interface device, the network interface device determines whether to activate the first data port concurrently with the second data port.
A method for collective communications includes invoking a collective operation over a group of computing processes in which the processes concurrently transmit and receive data to and from other processes in the group via a communication medium. Messages are composed for transmission by source processes including metadata indicating how the data to be transmitted by the source processes in the collective operation are to be handled by destination processes that are to receive the data and also including in at least some of the messages the data to be transmitted by one or more of the source processes to one or more of the destination processes. The composed messages are transmitted concurrently from the source processes to the destination processes in the group over the communication medium. The data are processed by the destination processes in response to the metadata included in the messages received by the destination processes.
Embodiments are disclosed for facilitating quantum computing over classical and quantum communication channels. An example system includes a network interface card (NIC) apparatus. The NIC apparatus includes an optical receiver, an embedded processor, and a network switch. The optical receiver is configured to receive qubit data via a first communication channel associated with quantum communication. The embedded processor is configured to convert the qubit data into binary bit data. The network switch is configured to output the binary bit data via a second communication channel associated with classical network communication.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p.ex. couplage ou commande de qubit
Methods, systems, and machine-readable mediums to predict signal conductor traffic and to transition between signal conductor states in accordance with the predictions. In at least one embodiment, a scoring system is used to select a prediction method, which is used to determine when to transition a signal conductor between active and inactive states.
H04L 43/08 - Surveillance ou test en fonction de métriques spécifiques, p.ex. la qualité du service [QoS], la consommation d’énergie ou les paramètres environnementaux
A networking device and system are described, among other things. An illustrative system is disclosed to include a shared buffer and at least a flow controller. In some embodiments, the system and/or flow controller may be configured to measure a packet flow's bandwidth consumption of the shared buffer, assign a flow-type attribute to the packet flow based on the packet flow's bandwidth consumption of the shared buffer, select a shared buffer schema for the packet flow based on the flow-type attribute assigned to the packet flow, and apply the selected shared buffer schema to the packet flow. For example, the flow-type attribute assigned to the packet flow may comprise a mice flow state or an elephant flow state, and a reserve attribute may be assigned to the flow based on the packet flow being assigned the mice flow state or the elephant flow state.
H04L 47/62 - Ordonnancement des files d’attente caractérisé par des critères d’ordonnancement
H04L 43/0882 - Utilisation de la capacité de la liaison
H04L 47/2441 - Trafic caractérisé par des attributs spécifiques, p.ex. la priorité ou QoS en s'appuyant sur la classification des flux, p.ex. en utilisant des services intégrés [IntServ]
H04L 47/80 - Actions liées au type d'utilisateur ou à la nature du flux
H04L 49/103 - TRANSMISSION D'INFORMATION NUMÉRIQUE, p.ex. COMMUNICATION TÉLÉGRAPHIQUE Éléments de commutation de paquets caractérisés par la construction de la matrice de commutation en utilisant une mémoire partagée
A network device includes multiple ports, a Shared Buffer (SB) and a SB controller. The ports to connect to a communication network. The SB to temporarily store packets received from the communication network via the ports, the packets belonging to multiple flows. The SB controller to allocate one or more flow-specific storage regions in the SB, a given flow-specific storage region being allocated to store the packets that (i) belong to respective one or more of the flows and (ii) are to be transmitted via a respective egress queue. In response to detecting that an occupancy level in the given flow-specific storage region exceeds a specified occupancy threshold, the SB controller to report the flows in the given flow-specific storage region as congested.
H04L 47/12 - Prévention de la congestion; Récupération de la congestion
H04L 47/30 - Commande de flux; Commande de la congestion en combinaison avec des informations sur l'occupation de mémoires tampon à chaque extrémité ou aux nœuds de transit
44.
C2C YIELD AND PERFORMANCE OPTIMIZATION IN A DIE STACKING PLATFORM
Technologies for chip-to-chip (C2C) yield and performance optimization in a die stacking platform are described. One apparatus includes a substrate, a first integrated circuit disposed on the substrate at a first location, a second integrated circuit disposed on the substrate at a second location, and a third integrated circuit disposed on the second integrated circuit. The second integrated circuit is coupled to the first integrated circuit using a first chip-to-chip (C2C) interface via a physical terminal. The third integrated circuit is coupled to the first integrated circuit using a second C2C interface via the physical terminal. Only one of the first C2C interface and the second C2C interface is active at a time.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
Methods, systems, and computer program products to modulate telemetry data as a function to represent the performance of a network and/or individual devices connected to the network. In embodiments, the method includes receiving telemetry data that has been sampled at a given point of time, wherein the telemetry data is associated with a performance metric of a device; processing the telemetry data as a function representing performance of the network device, wherein processing the telemetry data comprises modulating the telemetry data at the given point of time to previously sampled telemetry data based on the function; and demodulating the modulated telemetry data. In embodiments, the method also includes transferring the modulated telemetry data for reporting.
H04L 43/55 - Test de la qualité du niveau de service, p.ex. simulation de l’utilisation du service
H04L 41/5009 - Détermination des paramètres de rendement du niveau de service ou violations des contrats de niveau de service, p.ex. violations du temps de réponse convenu ou du temps moyen entre l’échec [MTBF]
H04L 67/12 - Protocoles spécialement adaptés aux environnements propriétaires ou de mise en réseau pour un usage spécial, p.ex. les réseaux médicaux, les réseaux de capteurs, les réseaux dans les véhicules ou les réseaux de mesure à distance
46.
SYSTEMS AND METHODS FOR CONTROLLING TEMPERATURE IN A SERVER
A system and method for controlling cooling in a server is provided. The method includes receiving one or more server indicators relating to a task to be executed by at least one component of the server. The method also includes determining an expected cooling demand for the at least one component based on the one or more server indicators. The method further includes adjusting a cooling amount provided by a cooling mechanism based on the expected cooling demand of the at least one component. Various embodiments are described herein.
A data compression system comprising computer memory to store plural compression algorithms and a hardware processor to apply compression algorithm/s to incoming data items, wherein the compression algorithm to be applied to individual data item/s from among the incoming data items is selected, from among the plural compression algorithms, by the hardware processor, depending at least on the individual data item.
Systems, devices, and methods are described herein for reducing a link bringup time period for optical switching between network devices. An example method of the present disclosure receives an indication of a reconfiguration condition associated with an optical switch communicatively coupled to an optical communication channel and based on the reconfiguration condition, selects first data associated with a storage device or second data associated with a pattern generator device for transmission to a first network device. Selecting the first or second data may be based on a digital logic signal that indicates whether data is actively received from the second network device via the optical communication channel or may be based on a defined schedule for reconfiguring the optical switch.
Technologies for spreading a single transport flow across multiple network paths in remote direct memory access (RDMA) over converged Ethernet (RoCE) and InfiniBand are described. A network interface controller receives a first packet and a second packet of a transport flow directed to a second node. The network interface controller assigns a first network routing identifier to the first packet and a second network routing identifier to the second packet, the first network routing identifier corresponding to a first network path between the first and second nodes, the second network routing identifier corresponding to a second network path between the first node and the second node. The network interface controller schedules a first packet of the transport flow to be sent via the first network path and a second packet of the transport flow to be sent via the second network path.
In one embodiment, a multi-segment communication network system includes nodes connected via links, a first node including a first receiver and transmitter, and a second node including a second receiver and transmitter, wherein the first transmitter is to transmit a link training frame including a training pattern to the second receiver, which is to receive the link training frame, the second node is to find a tuning factor to which to tune the first transmitter responsively to the training pattern, and generate a request indicative of the found tuning factor, the second transmitter is to send the request in the link training frame via a plurality of the links to the first receiver, the first receiver is to receive the request, and the first node is to tune at least one parameter of the first transmitter based on the tuning factor indicated in the request.
System, methods, and devices for providing an address resolution service are provided. In one example, an Address Resolution Service (ARS) node is described as being in communication with one or more endpoints. The ARS node may include one or more circuits that respond to an ARS query message issued by the one or more endpoints with a response message that translates a layer three address to a layer two address.
H04L 61/103 - Correspondance entre adresses de types différents à travers les couches réseau, p.ex. résolution d’adresse de la couche réseau dans la couche physique ou protocole de résolution d'adresse [ARP]
H04L 61/2503 - Traduction d'adresses de protocole Internet [IP]
H04L 61/10 - Correspondance entre adresses de types différents
Systems, methods, and devices that perform computing operations are provided. In one example, a system includes a least one node, the at least one node having one or more processors, each having associated memory, a clock, a scheduler, the scheduler monitoring one or more of rates, rates of lanes, rates at which packets are sent, times, latencies of packets, topology, communication states, nodes, and packets in the system, an attribute monitor that measures counters for one or more of congestion state, line rate, and communication attributes. A packet scheduler determines a destination node based on information from the scheduler and the attribute monitor, and sends at least a portion of a packet to the destination node.
Optical communication devices and associated methods of manufacturing are provided. An example optical communication device includes a substrate defining a first end and a second end. The optical communication device also includes a primary optical communication medium attached to the second end and a secondary optical communication medium attached to the second end. The optical communication device further includes a signal preclusion component supported by the substrate that selectively preclude signal transmission of optical signals received via the first end to either the primary optical communication medium or the secondary optical communication medium.
G02B 6/293 - Moyens de couplage optique ayant des bus de données, c. à d. plusieurs guides d'ondes interconnectés et assurant un système bidirectionnel par nature en mélangeant et divisant les signaux avec des moyens de sélection de la longueur d'onde
H04B 10/50 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs
Systems and methods enable session sharing for session-based remote direct memory access (RDMA). Multiple queue pairs (QPs) can be added to a single session and/or session group where each of the QPs has a common remote. Systems and methods may query a session ID for an existing session group and then use the session ID with an add QP request to join additional QPs to an existing session. Newly added QPs may share one or more features with existing QPs of the session group, such as encryption parameters. Additionally, newly added QPs may be configured with different performance or quality of service requirements, thereby isolating performance, and permitting true scaling for high performance computing applications.
G06F 15/167 - Communication entre processeurs utilisant une mémoire commune, p.ex. boîte aux lettres électronique
H04L 67/1097 - Protocoles dans lesquels une application est distribuée parmi les nœuds du réseau pour le stockage distribué de données dans des réseaux, p.ex. dispositions de transport pour le système de fichiers réseau [NFS], réseaux de stockage [SAN] ou stockage en réseau [NAS]
H04L 67/146 - Marqueurs pour l'identification sans ambiguïté d'une session particulière, p.ex. mouchard de session ou encodage d'URL
55.
DYNAMIC FABRIC REACTION FOR OPTIMIZED COLLECTIVE COMMUNICATION
A networking device and system are described, among other things. An illustrative system is disclosed to include a congestion controller that manages traffic across a network fabric using receiver-based packet scheduling and a networking device that employs the congestion controller for data flows qualified as a large data flow but bypasses the congestion controller for data flows qualified as a small data flow. For example, the networking device may receive information describing a data flow directed toward a processing network; determine, based on the information describing the data flow, a size of the data flow; determine the size of the data flow is below a predetermined flow threshold; and in response to determining that the size of the data flow is below a predetermined threshold, bypass the congestion controller.
H04L 47/12 - Prévention de la congestion; Récupération de la congestion
H04L 47/36 - Commande de flux; Commande de la congestion en déterminant la taille des paquets, p.ex. l’unité de transfert maximale [MTU]
H04L 47/10 - Commande de flux; Commande de la congestion
H04L 47/30 - Commande de flux; Commande de la congestion en combinaison avec des informations sur l'occupation de mémoires tampon à chaque extrémité ou aux nœuds de transit
56.
METHOD AND CONFIGURATION FOR STACKING MULTIPLE PRINTED CIRCUIT BOARDS
Electronic devices, electronic modules, and methods for manufacturing electronic devices and/or electronic modules are described herein. In some embodiments, the present invention may be directed to an electronic module that includes a pair of printed circuit boards (PCBs) and a capacitor positioned between the PCBs. Each of the PCBs may include a pair of vias configured to provide electrical connections through the PCB, and the capacitor may include a pair of pins. Each pin of the capacitor may be aligned with a via of one of the PCBs and a corresponding via of the other PCB such that each pin is configured to provide electrical connection between the two PCBs. Additionally, the pair of pins may be configured to support the PCBs with respect to each other.
Apparatuses, systems, and techniques to monitor health data from components and predict needs for maintenance. In at least one embodiment, monitoring health data of cables having one or more known characteristics ands analyzing the health data to determine the health metrics of the one or more cable to generate profiles of the cables used to predict future health metrics of the cables and related cables sharing known characteristics.
Processes for continuous compositional grading for realization of low charge carrier barriers in electro-optical heterostructure semiconductor devices are provided. An example process includes forming, onto one or more semiconductor layers of an electro-optical semiconductor device, a first semiconductor layer associated with a first bandgap value and forming, onto the first semiconductor layer, a grading layer associated with a continuous compositional grading. The example method further includes forming, onto the grading layer, a second semiconductor layer associated with a second bandgap value. The second bandgap value is different than the first bandgap value.
H01L 31/18 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives
H01L 31/109 - Dispositifs sensibles au rayonnement infrarouge, visible ou ultraviolet caractérisés par une seule barrière de potentiel ou de surface la barrière de potentiel étant du type PN à hétérojonction
H01L 31/0304 - Matériaux inorganiques comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
Photodetectors configured to detect light in a particular wavelength range and including a quaternary material are described herein. In some embodiments, the present invention may be directed to a photodetector that includes a collector material that is substantially transparent to the particular wavelength range and a quaternary material adjacent to the collector material, where the quaternary material functions as an absorber material and is lattice-matched to the collector material. A conduction band difference between the collector material and the quaternary material may be approximately zero. Additionally, or alternatively, the photodetector may include a peripheral layer adjacent to the quaternary material, where the peripheral layer is doped with carbon. In some embodiments, the photodetector may include an optical window configured for use with a multi-mode optical fiber.
H01L 31/105 - Dispositifs sensibles au rayonnement infrarouge, visible ou ultraviolet caractérisés par une seule barrière de potentiel ou de surface la barrière de potentiel étant du type PIN
H01L 31/0304 - Matériaux inorganiques comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
60.
Duty cycle distortion (DCD) sampling in a low-swing transmitter
Technologies for jitter extraction are described. A receiver device includes an analog-to-digital converter (ADC) and a signal processing circuit. The signal processing circuit includes an equalizer block to output current data based on samples from the ADC. A clock-recovery (CR) block includes a timing error detector (TED) or a phase detector to measure a sampling offset. The CR block can use the sampling offset to control sampling of subsequent data by the ADC. A jitter extraction block can use the sampling offset to re-sample the current data to obtain re-sampled data based on the sampling offset to remove jitter from the current data.
H03K 3/017 - Réglage de la largeur ou du rapport durée période des impulsions
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p.ex. réseaux de mise en forme adaptatifs
H03K 19/0185 - Dispositions pour le couplage; Dispositions pour l'interface utilisant uniquement des transistors à effet de champ
H03K 19/17784 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels pour l'adaptation des paramètres physiques pour la tension d'alimentation
Methods and systems include a hardware abstraction layer to provide control of two or more network switch controllers as a single network switch controller.
In one embodiment, a retimer device includes a receiver to receive data from a first device via a data link, retimer circuitry to recover a clock phase from the received data, and prepare a new copy of the received data sampled by a clean clock based on the recovered clock phase, a transmitter to transmit the new copy to a second device via the data link, wherein the receiver is configured to receive an in-band standby signal from the first device having a given pattern in a physical layer of the signal, activate a power saving mode of the retimer device responsively to the standby signal having the given pattern in the physical layer of the standby signal, receive an in-band wakeup signal from the first device, and initiate an exit from the power saving mode to power up the retimer device responsively to the wakeup signal.
H04L 7/02 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière
63.
METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR DYNAMIC LOAD BALANCING
Methods, systems, and computer program products for selecting packing processing cores are provided. An example system includes a plurality of packet processing cores and a load balancing unit communicatively connected to the plurality of packet processing cores. The load balancing unit is configured to receive a workflow packet including packet description data indicative of at least a packet structure and a packet priority and receive, from the plurality of packet processing cores, state data indicative of at least a utilization state and an operating state of each of the respective packet processing cores. The load balancing unit determines a selected packet processing core from amongst the plurality of packet processing cores based on the state data of the packet processing core and the packet description data of the workflow packet and transmits the workflow packet to the selected packet processing core.
Bi-directional quantum interconnects are provided that include a first communication module and a second communication module. The first communication module includes a first quantum transmitter and a first quantum receiver, and the second communication module includes a second quantum transmitter and a second quantum receiver. The example interconnect further includes a first communication medium communicably coupling the first communication module and the second communication module such that communication is provided between the first quantum transmitter and the second quantum receiver and between the second quantum transmitter and the first quantum receiver via the first communication medium. The first quantum transmitter and the second quantum transmitter generate qubits having first and second quantum characteristics, respectively, to allow for bi-directional quantum communication over a common channel.
Systems, computer program products, and methods are described herein for network discovery, port identification, and/or identifying fiber link failures in an optical network, in accordance with an embodiment of the invention. The present invention may be configured to sequentially connect each port of an optical switch to a network port of a server and generate, based on information associated with network devices connected to the ports, a network map. The network map may identify which network devices are connected to which ports of the optical switch and may permit dynamic port mapping for network installation, upgrades, repairs, and/or the like. The present invention may also be configured to determine a fiber link in which a failure occurred and reconfigure the optical switch to allow communication between an optical time-domain reflectometer and the fiber link to test the fiber link.
H04B 10/073 - Dispositions pour la surveillance ou le test de systèmes de transmission; Dispositions pour la mesure des défauts de systèmes de transmission utilisant un signal hors service
H04B 10/077 - Dispositions pour la surveillance ou le test de systèmes de transmission; Dispositions pour la mesure des défauts de systèmes de transmission utilisant un signal en service utilisant un signal de surveillance ou un signal supplémentaire
H04B 10/079 - Dispositions pour la surveillance ou le test de systèmes de transmission; Dispositions pour la mesure des défauts de systèmes de transmission utilisant un signal en service utilisant des mesures du signal de données
In one embodiment, a communication system includes network devices, each comprising a network interface to receive at least one data stream, a given network device being configured to recover a remote clock from the at least one data stream received by the given network device, a frequency synthesizer to generate a clock signal and output the clock signal to each of the network devices, wherein the given network device is configured to find a clock frequency differential between the clock signal and the recovered remote clock, and provide a control signal to the frequency synthesizer responsively to the clock frequency differential, the control signal causes the frequency synthesizer to adjust the clock signal so as to iteratively reduce an absolute value of the clock frequency differential between the clock signal and the recovered remote clock.
H03L 7/08 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase
G06F 1/12 - Synchronisation des différents signaux d'horloge
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
67.
SYNTONIZATION THROUGH PHYSICAL LAYER OF INTERCONNECTS
In one embodiment, a clock syntonization system includes a first compute node including a first physical hardware clock to operate at a first clock frequency, a second compute node, and an interconnect data bus to transfer data from the first compute node at a data rate indicative of the first clock frequency of the first physical hardware clock, and wherein the second compute node includes clock synchronization circuitry to derive a second clock frequency from the data rate of the transferred data, and provide a clock signal at the derived second clock frequency.
H04L 7/027 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en extrayant le signal d'horloge ou de synchronisation du spectre du signal reçu, p.ex. en utilisant un circuit résonnant ou passe-bande
A high performance mechanism for exporting peripheral services and offloads using Direct Memory Access (DMA) engine is presented. The DMA engine comprises a ring buffer, a DMA memory, and a DMA engine interface operatively coupled to the ring buffer and the DMA memory. The DMA engine interface is configured to retrieve, from the ring buffer, a first DMA request; extract first transfer instructions from the first DMA request; retrieve a first data corresponding to the first DMA request from the DMA memory; and execute the first DMA request using the first data based on at least the first transfer instructions.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
A vertical-cavity surface-emitting laser (VCSEL) is provided that includes a first reflector; a second reflector; and an active region disposed between the first reflector and the second reflector. The first reflector defines a first reflector characteristic dimension in a plane that is substantially perpendicular to an emission axis of the VCSEL, and the second reflector defines a second reflector characteristic dimension in a plane that is substantially perpendicular to the emission axis. The first reflector characteristic dimension is substantially equal to the second reflector characteristic dimension, which enables the VCSEL to exhibit improved heat dissipation compared to conventional VCSELs.
H01S 5/183 - Lasers à émission de surface [lasers SE], p.ex. comportant à la fois des cavités horizontales et verticales comportant uniquement des cavités verticales, p.ex. lasers à émission de surface à cavité verticale [VCSEL]
H01S 5/125 - Lasers à réflecteurs de Bragg répartis [lasers DBR]
70.
VERTICAL-CAVITY SURFACE-EMITTING LASER (VCSEL) HAVING SEPARATE ELECTRICAL AND OPTICAL CONFINEMENT
Vertical-cavity surface-emitting lasers (VCSELs) and associated methods of manufacturing are provided. An example VCSEL includes a first reflector, a second reflector, and an active region disposed between the first reflector and the second reflector. The VCSEL further includes an electrical aperture defining a current confinement region configured to direct current to the active region and an optical aperture defining a medium through which light produced by the active region is emitted from the VCSEL. At least one dimension of the optical aperture of the VCSEL is formed independent of the electrical aperture of the VCSEL. In some instances, the dimension of the optical aperture is a first diameter such that the first diameter of the optical aperture is formed independent of a second diameter defined by the electrical aperture.
H01S 5/183 - Lasers à émission de surface [lasers SE], p.ex. comportant à la fois des cavités horizontales et verticales comportant uniquement des cavités verticales, p.ex. lasers à émission de surface à cavité verticale [VCSEL]
H01S 5/34 - Structure ou forme de la région active; Matériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p.ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH]
H01S 5/125 - Lasers à réflecteurs de Bragg répartis [lasers DBR]
71.
SYSTEMS, METHODS, AND APPARATUSES FOR SECURING OWNERSHIP OF OBJECTS IN A DIGITAL LEDGER
Various embodiments of the present disclosure provide for generating and managing a digital ledger access system and its associated objects. An example method is configured for securing objects in a digital ledger of objects by identifying an object from amongst a plurality of objects in the digital ledger of objects and generating a quantum token for attachment with the object. The method includes deriving one or more classical public keys associated with the quantum token and determining an attempt to access the object. The method provides access to the object in response to a validation of the classical public key based on the quantum token, and the method precludes access to the object in response to an invalidation of the classical public key based on the quantum token.
An apparatuses, systems, and techniques of a fault resilient transaction handling device for a virtualized system. A request to initiate a transaction involving a direct memory access (DMA) operation to access data associated with one or more guests is received at a device connected to a computing system that hosts the one or more guests. A page fault associated with execution of the DMA operation of the transaction is detected. A transaction fault handling protocol that is to be initiated to address the detected page fault is selected from a set of transaction fault handling protocols. The selected transaction fault handling protocol is caused to be performed to address the detected page fault.
A Direct Memory Access (DMA) device includes an interface and a DMA engine. The interface is configured to communicate with a first memory and with a second memory. The DMA engine is configured to (i) receive a request to transfer data between the first memory and the second memory in accordance with a pattern of offsets to be accessed in the first memory or in the second memory, and (ii) transfer the data in accordance with the request.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
74.
COMPANION METADATA FOR PRECISION TIME PROTOCOL (PTP) HARDWARE CLOCK
System, methods, and devices for sharing time information between machines are provided. In one example, a system includes a Precision Time Protocol (PTP) Hardware Clock (PHC) and an application. The application receives time information from the PHC along with contextual metadata associated with the time information, analyzes the contextual metadata associated with the time information, and determines a context in which the PHC is disciplined. The context in which the PHC is disciplined may control a manner in which the application uses the time information.
An apparatus for interconnecting devices in a network comprises a connection interface with a first face and a second face opposite the first face. The apparatus includes a first 2D array of first connection points arranged on the first face of the connection interface. Each first connection point in each column of the first 2D array connects to a different host device from among a plurality of host devices, and each first connection point in each row of the first 2D array connects to a single host device from among the plurality of host devices. A second 2D array of second connection points is arranged on the second face of the connection interface. Each second connection point is connected to a respective first connection point, each second connection point in each column of the second 2D array connects to a single network switch from among a plurality of network switches, and each second connection point in each row of the second 2D array connects to a different network switch from among the plurality of network switches.
H04L 49/15 - Interconnexion de modules de commutation
H04L 49/253 - Routage ou recherche de route dans une matrice de commutation en utilisant l'établissement ou la libération de connexions entre les ports
H04L 49/00 - TRANSMISSION D'INFORMATION NUMÉRIQUE, p.ex. COMMUNICATION TÉLÉGRAPHIQUE Éléments de commutation de paquets
Network devices and associated methods are provided for synchronization in an optically switched network. The network device includes one or more ports in communication with a plurality of devices via an optical switch. The one or more ports receive a master clock signal having a first frequency from a first device of the plurality of devices. The network device includes a local clock in communication with the one or more ports and operating at a second frequency. The network device includes a synchronization manager in communication with the one or more ports and the local clock and configured to be enabled and disabled. When the synchronization manager is enabled, it receives the master clock signal via the one or more ports and transmits an instruction to the local clock to operate at the first frequency.
A network device includes a first interface, a second interface and circuitry. The first interface is configured to communicate at least with a first memory. The second interface is configured to communicate over a network with a peer network device coupled to a second memory. The circuitry is configured to (i) receive a request to transfer data over the network between the first memory and the second memory in accordance with a pattern of offsets to be accessed in the first memory or in the second memory, and (ii) transfer the data in accordance with the request.
H04L 67/1097 - Protocoles dans lesquels une application est distribuée parmi les nœuds du réseau pour le stockage distribué de données dans des réseaux, p.ex. dispositions de transport pour le système de fichiers réseau [NFS], réseaux de stockage [SAN] ou stockage en réseau [NAS]
A network device includes a first interface, a second interface, and circuitry. The first interface is configured to communicate at least with a memory. The second interface is configured to communicate over a network with a peer network device. The circuitry is configured to receive a request to transfer data over the network between the memory and the peer network device in accordance with (i) a pattern of offsets to be accessed in the memory and (ii) a memory key representing a memory space to be accessed using the pattern, and to transfer the data in accordance with the request.
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G06F 12/0831 - Protocoles de cohérence de mémoire cache à l’aide d’un schéma de bus, p.ex. avec moyen de contrôle ou de surveillance
G06F 15/173 - Communication entre processeurs utilisant un réseau d'interconnexion, p.ex. matriciel, de réarrangement, pyramidal, en étoile ou ramifié
A method for communication includes provisioning each node in a network with a respective set of two or more network addresses. Each node in succession is assigned a respective network address from the respective provisioned set that has not been assigned for use by any preceding node. Upon finding for a given node that all the network addresses in the respective provisioned set were assigned to preceding nodes, the preceding nodes are searched to identify a candidate node having an additional network address in the respective provisioned set, other than the assigned respective network address, that was not yet assigned to any of the nodes. The additional network address is assigned to the candidate node instead of the respective network address that was previously assigned to the candidate node, and the assigning of the network addresses to the nodes in the succession resumes following the candidate node.
H04L 61/106 - Correspondance entre adresses de types différents à travers les réseaux, p.ex. correspondance entre numéros de téléphone et adresses de réseaux de données
An apparatus for cache management includes an interface and a processor. The interface is for communicating with a cache memory configured to store data items. The cache controller is configured to obtain a classification of the data items into a plurality of groups, to obtain respective target capacities for at least some of the groups, each target capacity defining a respective required size of a portion of the cache memory that is permitted to be occupied by the data items belonging to the group, and to cache new data items in the cache memory, or evict cached data items from the cache memory, in accordance with a policy that complies with the target capacities specified for the groups.
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
Systems, methods, and devices for performing computing operations are provided. In one example, a system is described to include an endpoint that belongs to a collective, where the endpoint receives a Send Ready Notification (SRN) message from another endpoint in the collective and conditions a response to the SRN message based on whether the collective has begun an operation. For example, when the collective has not begun the operation at the same time the SRN message is received from the other endpoint, the endpoint may transmit a Not Ready To Receive (NRTR) message back to the other endpoint that transmitted the SRN message. Additionally, the endpoint may queue the SRN message for later processing. In some embodiments, the SRN message may not be counted against a threshold quota (Ns) based on the NRTR message being transmitted back to the other endpoint.
A networking device and system are described, among other things. An illustrative system is disclosed to include a packet parser and a state machine that includes a NULL header state. The packet parser references the state machine to enter the NULL header state automatically in response to parsing a packet header of a predetermined type and then, while in the NULL header state, analyzes a subsequent set of bytes without advancing a parser pointer.
H04L 69/22 - Analyse syntaxique ou évaluation d’en-têtes
H04L 45/50 - Routage ou recherche de routes de paquets dans les réseaux de commutation de données utilisant l'échange d'étiquettes, p.ex. des commutateurs d'étiquette multi protocole [MPLS]
A receiver including an equalization component to receive a signal comprising a sequence of samples corresponding to symbols and generate an equalized signal with an estimated sequence of symbols corresponding to the signal. The receiver further includes a decision generation component to receive the equalized signal and generate, based on the equalized signal, a decision comprising a sequence of one or more bits that represent each symbol of the sequence of symbols and a confidence level corresponding to the decision.
Networking devices, systems, and methods are provided. In one example, a method includes receiving a packet at a networking device; evaluating the packet; based on the evaluation of the packet, truncating the packet from a first size to a second size that is smaller than the first size; and storing the truncated packet in a buffer prior to transmitting the truncated packet with the networking device.
A method includes receiving a network packet into a hardware pipeline of a network device; parsing and retrieving information of the network packet; determining, by the hardware pipeline, a packet-processing action to be performed by matching the information to a data structure of a set of flow data structures; sending, by the hardware pipeline, an action request to a programmable core, the action request being populated with data to trigger the programmable core to execute a hardware thread to perform a job, which is associated with the packet-processing action and that generates contextual data; retrieving the contextual data updated by the programmable core; and integrating the contextual data into performing the packet-processing action.
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache
G06F 9/48 - Lancement de programmes; Commutation de programmes, p.ex. par interruption
Technologies for jitter extraction are described. A receiver device includes an analog-to-digital converter (ADC) and a signal processing circuit. The signal processing circuit includes an equalizer block to output current data based on samples from the ADC. A clock-recovery (CR) block includes a timing error detector (TED) or a phase detector to measure a sampling offset. The CR block can use the sampling offset to control sampling of subsequent data by the ADC. A jitter extraction block can use the sampling offset to re-sample the current data to obtain re-sampled data based on the sampling offset to remove jitter from the current data.
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p.ex. en utilisant une boucle verrouillée en phase
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p.ex. réseaux de mise en forme adaptatifs
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
87.
COMPONENT, ASSEMBLY, AND USAGE PERSPICACITY MODEL AND USES THEREOF
A computing entity obtains product information corresponding to a product and defines a multi-region metric space vector based on the product information. The multi-region metric space vector is a vector within a multi-region metric space that comprises a first region corresponding to supply chain/component information, a second region corresponding to assembly/fabrication information, and a third region corresponding to usage/usage environment information. Each of the first, second, and third regions are multi-dimensional. The computing entity processes the multi-region metric space vector using a component, assembly, and usage perspicacity model configured to define fuzzy clusters within the multi-region metric space; determines a parameter corresponding to the product based on at least one fuzzy cluster to which the perspicacity model assigned the multi-region space vector; and provides or causes providing of (a) a visual/audible representation of the parameter or (b) a machine-readable representation of the parameter as input to an application/program.
A device may include a printed circuit board (PCB), a plurality of surface-mount devices disposed on the PCB, wherein a thermal mass of each of the surface-mount devices ranges between a first thermal mass value and a second thermal mass value that is greater than the first thermal mass value, and a plurality of thermal capacitors disposed on the PCB, wherein a thermal mass of each of the thermal capacitors is equal to or greater than the first thermal mass value of the surface-mount devices.
A device, a switch, and a method of determining latency which exceeds a threshold are described. A task is enqueued and a time is determined based on two clocks. A time the task is dequeued is determined based on the two clocks. Based on the time of enqueue and the time of dequeue according to each of the two clocks, the task is identified as meeting or violating a service level agreement.
H04L 47/625 - Ordonnancement des files d’attente caractérisé par des critères d’ordonnancement pour des créneaux de service ou des commandes de service
Devices, methods, and systems are provided. In one example, a device is described to include circuitry that collects data received from a data source, references a descriptor that describes a data reformat operation to perform on the data received from the data source, reformats the data received from the data source according to the data reformat operation, and provides the reformatted data to the data target via the second device interface.
Disclosed are a testing unit, system, and method for testing and predicting failure of optical receivers. The testing unit and system are configured to apply different values of current, voltage, heat stress, and illumination load on the optical receivers during testing. The test methods are designed to check dark current, photo current, forward voltage, and drift over time of these parameters.
A transceiver module for providing operational resilience is presented. The transceiver module is configured to receive first data via a first optical module in a first configuration of operation and detect, using an adapter that is operationally connected to the first optical module, an operational failure of the first optical module. In response to detecting the operational failure, the transceiver module is configured to switch, via the adapter, from the first configuration of operation to a second configuration of operation by: automatically engaging a second optical module; triggering the first data that was initially directed into a first input port of the first optical module to be directed into a second input port of the second optical module; and receiving the first data from a second output port of the second optical module.
H04B 10/038 - Dispositions pour le rétablissement de communication après défaillance utilisant des contournements
H04B 10/112 - Transmission dans la ligne de visée sur une distance étendue
H04B 10/40 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs-récepteurs
93.
SYSTEM AND METHOD FOR RADIATIVE COOLING FOR DATA CENTERS
Methods, apparatuses, systems, computing devices, and/or the like are provided. An example system for heat dissipation may include a memory. The example system may also include a processor configured to receive at least one visual representation of at least a portion of the sky, determine, based on the at least one visual representation (e.g., using artificial intelligence), a mask distinguishing between clouded and cloudless portions of the sky, based on the mask, determine a direction in which to point a heat dissipation panel toward one or more aim portions of the sky, and generate a signal to cause one or more heat dissipation surfaces or panels to be moved (e.g., using a robotic arm) such that heat is radiated toward the one or more aim portions of the sky.
H05K 7/20 - Modifications en vue de faciliter la réfrigération, l'aération ou le chauffage
G05B 19/4155 - Commande numérique (CN), c.à d. machines fonctionnant automatiquement, en particulier machines-outils, p.ex. dans un milieu de fabrication industriel, afin d'effectuer un positionnement, un mouvement ou des actions coordonnées au moyen de données d'u caractérisée par le déroulement du programme, c.à d. le déroulement d'un programme de pièce ou le déroulement d'une fonction machine, p.ex. choix d'un programme
An apparatus, system, and method include, for each of two or more switches of a communication network, identifying a set of routing paths from the switch to a destination node based on a topology associated with the communication network. The set of routing paths include a first subset of routing paths and a second subset of routing paths. The topology includes an indication of a convergence of the first subset of routing paths at a node between the switch and the destination node. The apparatus, system, and method include allocating a data flow to a first routing path of the first subset of routing paths and a second routing path of the second subset of routing paths according to a target data flow rate common to the first routing path and the second routing path.
A computing device which may include a hardware-configurable device reconfigurable to perform a series of logical operations to determine, based on parameters related to execution of a job received by the hardware-configurable device, whether or not the job is permissible for execution.
Methods, systems, and computer program products to combine multiple telemetry data signals to generate a single higher resolution signal. In embodiments, the method includes: modulating a sampling of telemetry data by at least two network devices; receiving telemetry data from the at least two network devices; combining the received telemetry data; and determining a status of the network and/or network devices based on a processing of the combined telemetry data.
H04L 43/022 - Capture des données de surveillance par échantillonnage
H04L 43/028 - Capture des données de surveillance en filtrant
H04L 43/08 - Surveillance ou test en fonction de métriques spécifiques, p.ex. la qualité du service [QoS], la consommation d’énergie ou les paramètres environnementaux
97.
SYSTEMS AND METHODS FOR IMPLEMENTING QUANTUM WALKS IN DISTRIBUTED QUANTUM COMPUTING
A distributed quantum computing system formed of a plurality of quantum processing units (QPUs) is provided for performing quantum walks. An example first QPU includes a first plurality of physical qubits propagating across a first plurality of nodes where at least a portion of the first plurality of nodes are local nodes configured to perform the one or more quantum walks on the first QPU. The one or more quantum walks are conducted across the first plurality of nodes of at least the first QPU so as to form a graphical structure. Performance of the one or more quantum walks on the first QPU further includes propagation of at least a portion of the first plurality of physical qubits across the first plurality of nodes responsive to one or more inputs from evolution operators.
G06N 10/60 - Algorithmes quantiques, p.ex. fondés sur l'optimisation quantique ou les transformées quantiques de Fourier ou de Hadamard
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p.ex. couplage ou commande de qubit
In one embodiment, a secure challenge-response method includes requesting respective token challenges from devices, receiving the respective token challenges from the devices, providing the respective token challenges to a signing server, receiving from the signing server a signature of the respective token challenges signed with a private key of the signing server, and providing to a given device of the devices a request to perform an operation, the request including the signature and the respective token challenges.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
99.
SYSTEMS AND METHODS OF PACKET CLASSIFICATION USING ARTIFICIAL INTELLIGENCE
A network device, system-on-a-chip, and method of performing packet handling are described. A packet is received, and a lookup based on one or more packet header fields of the packet is performed using a lookup generator action handler. An artificial intelligence engine processes packet header data associated with the packet, and a smart indication is generated. A forwarding decision is made for the packet based on the lookup performed by the lookup generator action handler as well as based on the smart indication generated with the artificial intelligence engine.
A System-On-Chip (SoC) includes a set of registers, a processor, and Out-Of-Order Write (OOOW) circuitry. The processor is to execute instructions including write instructions. After issuing a first write instruction to any of the registers in the set, the processor is to await an acknowledgement for the first write instruction before issuing a second write instruction to any of the registers in the set. The OOOW circuitry is to identify the write instructions issued by the processor to the registers in the set, to perform the identified write instructions in the registers irrespective of acknowledgements from the registers, and to send to the processor imitated acknowledgements for the identified write instructions.
