An integrated circuit (IC) package includes a partial leadframe including (a) a shunt resistor leadframe element including a pair of shunt resistor contacts and a shunt resistor conductively connected between the pair of shunt resistor contacts and (b) at least one external contact leadframe element separate from the shunt resistor leadframe element, the at least one external contact leadframe element allowing external contact to the IC package. The IC package also a mold encapsulation formed over the shunt resistor leadframe element, wherein the pair of shunt resistor contacts are externally contactable through the mold encapsulation.
G01R 1/20 - Modifications des éléments électriques fondamentaux en vue de leur utilisation dans des appareils de mesures électriques; Combinaisons structurelles de ces éléments avec ces appareils
G01R 1/04 - Boîtiers; Organes de support; Agencements des bornes
G01R 1/30 - Combinaison structurelle d'appareils de mesures électriques avec des circuits électroniques fondamentaux, p.ex. avec amplificateur
G01R 19/32 - Compensation des variations de température
3.
ADAPTIVE BIAS DECODER FOR NON-VOLATILE MEMORY SYSTEM
In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to an erase gate line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the erase gate line in response to changes in a voltage of the source line.
A device comprising: a repository for an item, the repository having an item intake; a sensor that generates a signal corresponding to characteristics of an item in the repository; an artificial intelligence circuit that receives from the sensor the signal corresponding to characteristics of an item in the repository and that transmits an indicator signal indicative of the item in the repository; and an indicator that receives from the artificial intelligence circuit the indicator signal and that indicates the item in the repository based on the indicator signal.
G06Q 10/08 - Logistique, p.ex. entreposage, chargement ou distribution; Gestion d’inventaires ou de stocks
G06Q 10/087 - Gestion d’inventaires ou de stocks, p.ex. exécution des commandes, approvisionnement ou régularisation par rapport aux commandes
G06Q 10/0875 - Gestion d’inventaires ou de stocks, p.ex. exécution des commandes, approvisionnement ou régularisation par rapport aux commandes Énumération ou classification des pièces, des fournitures ou des services, p.ex. nomenclatures
5.
APPARATUS AND METHOD FOR PROCESSING RECEIVE DATA IN A RECEIVE DATA PATH INCLUDING PARALLEL FEC DECODING
An apparatus comprises a data width converter and a forward error correction (FEC) decoder. The data width converter includes an input to receive an input data stream having an input bit width, a first output to produce a first output data stream having a first output bit width, and a second output to produce a second output data stream having at least a second output bit width. The FEC decoder includes an input to receive the second output data stream having the at least second output bit width. The FEC decoder includes an error correction output to produce one or more error correction values at least partially based on one or more FEC code words in the second output data stream. The one or more error correction values are for correction of one or more symbols, one or more partial symbols, or both, in the first output data stream having the first output bit width. In one or more examples, the data width converter is in a receive data path, and at least a portion of the FEC decoder is in parallel with the receive data path.
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
6.
APPARATUS AND METHOD FOR PROCESSING TRANSMIT DATA IN A TRANSMIT DATA PATH INCLUDING PARALLEL FEC ENCODING
An apparatus comprises a data width converter and a forward error correction (FEC) encoder. The data width converter includes an input to receive an input data stream at an input bit width, a first output to produce a first output data stream at a first output bit width, and a second output to produce a second output data stream at a second output bit width. The FEC encoder includes an input to receive the second output data stream at the second output bit width. The FEC encoder includes an output to produce parity bits at least partially based on multiple received symbols of the second output data stream having the second output bit width. The parity7 bits for insertion in the first output data stream having the first output bit width. In one or more examples, the data width converter is in a transmit data path, and the FEC encoder is in parallel with the transmit data path.
An apparatus comprises a data width converter and a forward error correction (FEC) decoder. The data width converter includes an input to receive an input data stream having an input bit width, a first output to produce a first output data stream having a first output bit width, and a second output to produce a second output data stream having at least a second output bit width. The FEC decoder includes an input to receive the second output data stream having the at least second output bit width. The FEC decoder includes an error correction output to produce one or more error correction values at least partially based on one or more FEC code words in the second output data stream. The one or more error correction values are for correction of one or more symbols, one or more partial symbols, or both, in the first output data stream having the first output bit width. In one or more examples, the data width converter is in a receive data path, and at least a portion of the FEC decoder is in parallel with the receive data path.
A device comprising: a repository for an item, the repository having an item intake; a sensor that generates a signal corresponding to characteristics of an item in the repository; an artificial intelligence circuit that receives from the sensor the signal corresponding to characteristics of an item in the repository and that transmits an indicator signal indicative of the item in the repository; and an indicator that receives from the artificial intelligence circuit the indicator signal and that indicates the item in the repository based on the indicator signal.
B65G 1/137 - Dispositifs d'emmagasinage mécaniques avec des aménagements ou des moyens de commande automatique pour choisir les objets qui doivent être enlevés
An apparatus comprising: a pin to connect to a resistor and a power source; a measurement circuit to measure a voltage at the pin; a circuit to determine a mapped identification value of the apparatus based upon the voltage at the pin, the mapped identification value coding the apparatus as an instance of a product from a set of products; and an authentication circuit. The authentication circuit: calculates an authentication code using the mapped identification value; and provides the authentication code to an authentication host upon request from the authentication host.
G06Q 30/018 - Certification d’entreprises ou de produits
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
10.
APPARATUS AND METHOD FOR PROCESSING TRANSMIT DATA IN A TRANSMIT DATA PATH INCLUDING PARALLEL FEC ENCODING
An apparatus comprises a data width converter and a forward error correction (FEC) encoder. The data width converter includes an input to receive an input data stream at an input bit width, a first output to produce a first output data stream at a first output bit width, and a second output to produce a second output data stream at a second output bit width. The FEC encoder includes an input to receive the second output data stream at the second output bit width. The FEC encoder includes an output to produce parity bits at least partially based on multiple received symbols of the second output data stream having the second output bit width. The parity bits for insertion in the first output data stream having the first output bit width. In one or more examples, the data width converter is in a transmit data path, and the FEC encoder is in parallel with the transmit data path.
H03M 13/29 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes combinant plusieurs codes ou structures de codes, p.ex. codes de produits, codes de produits généralisés, codes concaténés, codes interne et externe
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
11.
Programming of a Selected Non-volatile Memory Cell by Changing Programming Pulse Characteristics
In one example, a method comprises applying a first programming pulse to a terminal of a selected non-volatile memory cell; and applying a second programming pulse to the terminal of the selected non-volatile memory cell, wherein a magnitude of a voltage the second programming pulse is equal to or lower than a magnitude of a voltage of the first programming pulse; wherein the selected non-volatile memory cell is programmed to a target value by the first programming pulse and the second programming pulse.
G06N 3/0442 - Réseaux récurrents, p.ex. réseaux de Hopfield caractérisés par la présence de mémoire ou de portes, p.ex. mémoire longue à court terme [LSTM] ou unités récurrentes à porte [GRU]
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G11C 11/54 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments simulateurs de cellules biologiques, p.ex. neurone
In one example, a system comprises an analog neural memory array comprising a plurality of non-volatile memory cells arranged into rows and columns; and a voltage generator to provide a voltage to one or more rows of the analog neural memory array, the voltage generator comprising a voltage ladder to generate a plurality of voltages according to a logarithmic formula.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
An apparatus comprising: a pin to connect to a resistor and a power source; a measurement circuit to measure a voltage at the pin; a circuit to determine a mapped identification value of the apparatus based upon the voltage at the pin, the mapped identification value coding the apparatus as an instance of a product from a set of products; and an authentication circuit. The authentication circuit: calculates an authentication code using the mapped identification value; and provides the authentication code to an authentication host upon request from the authentication host.
G06F 21/44 - Authentification de programme ou de dispositif
G06F 21/73 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par création ou détermination de l’identification de la machine, p.ex. numéros de série
14.
Multiple Row Programming Operation In Artificial Neural Network Array
Numerous examples are disclosed of programming multiple rows in an array in an artificial neural network as part of a single programming operation. In one example, a method comprises ramping up an output of a high voltage generator to a first voltage level; while maintaining the output of the high voltage generator at the first voltage level, programming a plurality of words of K rows of memory cells in an array of memory cells using the output of the high voltage generator, where K>1; and after the programming, ramping down the output of the high voltage generator to a second voltage level.
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to the source line of the array during operation.
Numerous examples are disclosed of output circuitry and associated methods in an artificial neural network. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, an output block to convert current from columns of the array into a first digital output during a first time period and a second digital output during a second time period, a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period, and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06F 5/01 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour le décalage, p.ex. la justification, le changement d'échelle, la normalisation
G06F 7/501 - Semi-additionneurs ou additionneurs complets, c. à d. cellules élémentaires d'addition pour une position
Numerous examples are disclosed of input circuitry and associated methods in an artificial neural network. In one example, a system comprises a plurality of address decoders to receive an address and output a plurality of row enabling signals in response to the address; a first plurality of registers to store, sequentially, activation data in response to the plurality of row enabling signals; and a second plurality of registers to store, in parallel, activation data received from the first plurality of registers.
In one example, a non-volatile memory system comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain of each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to a word line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the word line in response to changes in a voltage of the source line.
One or more examples relate to selectively line-based encoding pixels of an image via run-length encoding or gradient encoding. A method includes, for at least a portion of an image, determining a highest number of: a number of pixels in a run compressible via run-length encoding, and a number of pixels in a run compressible via gradient encoding; and selectively encoding at least some pixels of an image via the one of run-length encoding or gradient encoding corresponding to the determined highest number.
H04N 19/146 - Débit ou quantité de données codées à la sortie du codeur
H04N 19/182 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c. à d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant un pixel
H04N 19/593 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage prédictif mettant en œuvre des techniques de prédiction spatiale
Numerous examples are disclosed of input circuitry and associated methods in an artificial neural network. In one example, a system comprises a plurality of address decoders to receive an address and output a plurality of row enabling signals in response to the address; a first plurality of registers to store, sequentially, activation data in response to the plurality of row enabling signals; and a second plurality of registers to store, in parallel, activation data received from the first plurality of registers.
G11C 8/18 - Circuits de synchronisation ou d'horloge; Génération ou gestion de signaux de commande d'adresse, p.ex. pour des signaux d'échantillonnage d'adresse de ligne [RAS] ou d'échantillonnage d'adresse de colonne [CAS]
G11C 8/08 - Circuits de commande de lignes de mots, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, pour lignes de mots
G11C 8/04 - Dispositions pour sélectionner une adresse dans une mémoire numérique utilisant un dispositif d'adressage séquentiel, p.ex. registre à décalage, compteur
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G11C 11/54 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments simulateurs de cellules biologiques, p.ex. neurone
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
21.
MULTIPLE ROW PROGRAMMING OPERATION IN ARTIFICIAL NEURAL NETWORK ARRAY
Numerous examples are disclosed of programming multiple rows in an array in an artificial neural network as part of a single programming operation. In one example, a method comprises ramping up an output of a high voltage generator to a first voltage level; while maintaining the output of the high voltage generator at the first voltage level, programming a plurality of words of K rows of memory cells in an array of memory cells using the output of the high voltage generator, where K > 1; and after the programming, ramping down the output of the high voltage generator to a second voltage level.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
22.
OUTPUT CIRCUIT FOR ARTIFICIAL NEURAL NETWORK ARRAY
Numerous examples are disclosed of output circuitry and associated methods in an artificial neural network. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, an output block to convert current from columns of the array into a first digital output during a first time period and a second digital output during a second time period, a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period, and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06N 3/0442 - Réseaux récurrents, p.ex. réseaux de Hopfield caractérisés par la présence de mémoire ou de portes, p.ex. mémoire longue à court terme [LSTM] ou unités récurrentes à porte [GRU]
A method may include setting a data pattern status signal to indicate a data pattern status of a data pattern to be received by a data-dependent power consumer; and modulating power consumption from a power source that provides the data-dependent power consumer at least partially based on the set data pattern status signal.
H04L 7/04 - Commande de vitesse ou de phase au moyen de signaux de synchronisation
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p.ex. en utilisant une boucle verrouillée en phase
H04L 25/49 - Circuits d'émission; Circuits de réception à au moins trois niveaux d'amplitude
24.
VERIFICATION METHOD AND SYSTEM IN ARTIFICIAL NEURAL NETWORK ARRAY
Numerous examples are disclosed of verification circuitry and associated methods in an artificial neural network. In one example, a system comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells respectively capable of storing one of N possible levels corresponding to one of N possible currents, and a plurality of output blocks to receive current from respective columns of the vector-by-matrix multiplication array and generate voltages during a verify operation of the vector-by-matrix multiplication and generate digital outputs during a read operation of the vector-by-matrix multiplication.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
25.
MODULATING POWER CONSUMPTION FROM A POWER SOURCE THAT SUPPLIES A DATA-DEPENDENT POWER CONSUMER
A method may include setting a data pattern status signal to indicate a data pattern status of a data pattern to be received by a data-dependent power consumer; and modulating power consumption from a power source that provides the data-dependent power consumer at least partially based on the set data pattern status signal.
G06F 1/3203 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements
G06F 1/3206 - Surveillance d’événements, de dispositifs ou de paramètres initiant un changement de mode d’alimentation
G06F 1/3215 - Surveillance de dispositifs périphériques
G06F 1/3234 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise
G06F 1/3296 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par diminution de la tension d’alimentation ou de la tension de fonctionnement
G06F 1/30 - Moyens pour agir en cas de panne ou d'interruption d'alimentation
26.
VERIFICATION METHOD AND SYSTEM IN ARTIFICIAL NEURAL NETWORK ARRAY
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G11C 11/54 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments simulateurs de cellules biologiques, p.ex. neurone
27.
SCALABLE COMMON VIEW TIME TRANSFER AND RELATED APPARATUSES AND METHODS
Common view time transfer and related apparatuses and methods are disclosed. An apparatus includes a receiver oscillator to provide a local clock signal and one or more processors. The one or more processors are to perform, at least partially based on the local clock signal, event time tagging pre-processing at least partially responsive to satellite signals received from one or more satellites to generate a decimated precision correction state estimate; determine, per satellite signal pseudo range residuals; determine a navigation engine clock state; perform a precision clock state pre-processing operation at least partially responsive to the navigation engine clock state and the decimated precision correction state estimate to generate a precision navigation clock state; and generate a common view real time report at least partially responsive to the per satellite signal pseudo range residuals and the precision navigation clock state.
G01S 19/25 - Acquisition ou poursuite des signaux émis par le système faisant intervenir des données d'assistance reçues en provenance d'un élément coopérant, p.ex. un GPS assisté
G01S 19/23 - Test, contrôle, correction ou étalonnage d'un élément récepteur
G01S 19/39 - Détermination d'une solution de navigation au moyen des signaux émis par un système de positionnement satellitaire à radiophares le système de positionnement satellitaire à radiophares transmettant des messages horodatés, p.ex. GPS [Système de positionnement global], GLONASS [Système mondial de satellites de navigation] ou GALILEO
In one example, a neural network device comprises a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises a plurality of memory cells, each of the plurality of memory cells configured to store a weight value corresponding to a number of electrons on its floating gate and the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the stored weight values.
An integrated resistor includes a resistor tub, a resistive element, and a dielectric liner. The resistor tub is formed from a conformal metal, and includes a laterally-extending tub base and vertically-extending tub sidewalls extending upwardly from the laterally-extending tub base, wherein the laterally-extending tub base and vertically-extending tub sidewalls define in a resistor tub interior opening. The dielectric liner is formed in the resistor tub interior opening. The resistive element is formed over the dielectric liner in the resistor tub interior opening, and includes a pair of resistor heads connected by a laterally-extending resistor body. The dielectric liner electrically insulates the resistive element from the resistor tub.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H10N 97/00 - Dispositifs électriques à l’état solide à film mince ou à film épais, non prévus ailleurs
30.
DETERMINING A LOCKED STATUS OF A CLOCK TRACKING CIRCUIT
An example apparatus includes a phase detector, a digital discriminator, and a logic circuit. A status signal of the phase detector is at least partially based on a phase relationship between a reference clock and a feedback clock, the feedback clock generated by a clock tracking circuit to track the reference clock. The digital discriminator may sample the status signal of the phase detector. The logic circuit may determine a locked status of the clock tracking circuit at least partially based on samples of the status signal of the phase detector.
H03L 7/087 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie utilisant au moins deux détecteurs de phase ou un détecteur de fréquence et de phase dans la boucle
H03L 7/091 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence utilisant un dispositif d'échantillonnage
H03L 7/095 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie utilisant un détecteur de verrouillage
H03L 7/089 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence engendrant des impulsions d'augmentation ou de diminution
31.
WORD LINE DRIVER FOR VECTOR-BY-MATRIX MULTIPLICATION ARRAY
In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells organized into rows and columns; a plurality of word lines coupled respectively to rows of the vector-by-matrix multiplication array; and a word line driver coupled to the plurality of word lines, the word line driver comprising a plurality of select transistors coupled to a common control line and the plurality of word lines, and a plurality of bias transistors coupled to the plurality of select transistors and capable of providing a bias voltage to a single select transistor in the plurality of select transistors or to all of plurality of select transistors in response to control signals.
In one example, a system comprises an array comprising selected memory cells; an input block configured to apply, to each selected memory cell, a series of input signals to a terminal of the selected memory cell in response to a series of input bits; and an output block for generating an output of the selected memory cells, the output block comprising an analog-to-digital converter to convert current from the selected memory cells into a digital value, a shifter, an adder, and a register; wherein the shifter, adder, and register are configured to receive a series of digital values in response to the series of input bits, shift each digital value in the series of digital values based on a bit location of an input bit within the series of input bits, and add results of the shift operations to generate an output indicating values stored in the selected memory cells.
In one example, a circuit comprises an input transistor comprising a first terminal, a second terminal coupled to ground, and a gate; a capacitor comprising a first terminal and a second terminal; an output transistor comprising a first terminal providing an output current, a second terminal coupled to ground, and a gate; a first switch; and a second switch; wherein in a first mode, the first switch is closed and couples an input current to the first terminal of the input transistor and the gate of the input transistor and the second switch is closed and couples the first terminal of the input transistor to the first terminal of the capacitor and the gate of the output transistor, and in a second mode, the first switch is open and the second switch is open and the capacitor discharges into the gate of the output transistor.
A method of forming a partially silicided element is provided. A silicided structure including a silicide layer on a base structure is formed. A dielectric region is formed over the silicided structure. The dielectric region is etched to form a contact opening exposing a first area of the silicide layer and a tub opening exposing a second area of the silicide layer. A conformal metal is deposited to (a) fill the contact opening to define a contact and (b) form a cup-shaped metal structure in the tub opening. Another etch is performed to remove the cup-shaped metal structure in the tub opening, to remove the underlying silicide layer second area and to expose an underlying area of the base structure, wherein the silicide layer first area remains intact. The base structure with the intact silicide layer first area and removed silicide layer second area defines the partially silicided element.
An example apparatus includes a phase detector and a phase error detector. The phase detector may set a status signal to indicate status of phase difference between a reference clock and a feedback clock, the feedback clock generated by a clock tracking circuit to track the reference clock. The phase error detector may set an error signal to be proportional to a phase difference between the reference clock and the feedback clock. At least partially responsive to the status signal, the phase error detector to change from triggered only by edges of the reference clock and feedback clock having a first polarity to triggered by edges of the reference clock and feedback clock having the first polarity and by edges of the reference clock and feedback clock having a second polarity, the second polarity different than the first polarity.
H03L 7/087 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie utilisant au moins deux détecteurs de phase ou un détecteur de fréquence et de phase dans la boucle
H03L 7/091 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence utilisant un dispositif d'échantillonnage
H03L 7/095 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie utilisant un détecteur de verrouillage
H03L 7/089 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence engendrant des impulsions d'augmentation ou de diminution
A system for network data transactions, the system including an ingress port to receive data frames and timestamp received data frames, a frame analyzer to forward the data frames to a processor, the processor to extract timing information from the data frames and update the data frames based on updated timing calculations and output updated data frames via one or more egress ports. Data frames are timestamped at ingress and egress ports, and egress timestamps are saved in a timestamp memory. The system reduces overall network delays by using dedicated hardware and stored timestamp information.
A device for control of network traffic may include a plurality of edge interface circuit and internal interface circuits each coupled to one or more network components. The device may prepend frame identification information to received data frames and remove duplicate data frames when identification information is detected multiple times. The device may store frame identification information in a non-transitory memory device and perform a lookup operation to identify duplicate data frames and eliminate loops in the network.
A device includes a PWM circuit to generate a complementary PWM signal comprised of a positive polarity PWM signal and a negative polarity PWM signal. The positive polarity signal may drive a high-side switch. A trigger multiplexer may take as input the negative polarity PWM signal and may force an output based on a predetermined condition, the predetermined condition including but not limited to the maximum on-time of a low-side switch. The output of the trigger multiplexer may drive a low-side switch. The high-side switch and the low-side switch may drive a load.
H03K 17/693 - Dispositifs de commutation comportant plusieurs bornes d'entrée et de sortie, p.ex. multiplexeurs, distributeurs
H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
A device for control of network traffic may include a plurality of edge interface circuit and internal interface circuits each coupled to one or more network components. The device may prepend frame identification information to received data frames and remove duplicate data frames when identification information is detected multiple times. The device may store frame identification information in a non-transitory memory device and perform a lookup operation to identify duplicate data frames and eliminate loops in the network.
Teachings of the present disclosure include systems and/or methods for encoding digital data into a handwritten sample. An example method includes: accessing a predetermined vibration pattern stored in a memory corresponding to defined data; and vibrating a stylus based on the predetermined vibration pattern during creation of the handwritten sample to encode the defined data into the handwriting sample.
G06F 3/01 - Dispositions d'entrée ou dispositions d'entrée et de sortie combinées pour l'interaction entre l'utilisateur et le calculateur
G06F 3/0354 - Dispositifs de pointage déplacés ou positionnés par l'utilisateur; Leurs accessoires avec détection des mouvements relatifs en deux dimensions [2D] entre le dispositif de pointage ou une partie agissante dudit dispositif, et un plan ou une surface, p.ex. souris 2D, boules traçantes, crayons ou palets
G06V 40/30 - Reconnaissance d’auteur; Lecture et vérification des signatures
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
A device includes a PWM circuit to generate a complementary PWM signal comprised of a positive polarity PWM signal and a negative polarity PWM signal. The positive polarity signal may drive a high-side switch. A trigger multiplexer may take as input the negative polarity PWM signal and may force an output based on a predetermined condition, the predetermined condition including but not limited to the maximum on-time of a low-side switch. The output of the trigger multiplexer may drive a low-side switch. The high-side switch and the low-side switch may drive a load.
H03K 17/0812 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension sans réaction du circuit de sortie vers le circuit de commande par des dispositions prises dans le circuit de commande
H03K 17/082 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension par réaction du circuit de sortie vers le circuit de commande
A system for network data transactions, the system including an ingress port to receive data frames and timestamp received data frames, a frame analyzer to forward the data frames to a processor, the processor to extract timing information from the data frames and update the data frames based on updated timing calculations and output updated data frames via one or more egress ports. Data frames are timestamped at ingress and egress ports, and egress timestamps are saved in a timestamp memory. The system reduces overall network delays by using dedicated hardware and stored timestamp information.
An integrated resistor includes a resistor tub, a resistive element, and a dielectric liner. The resistor tub is formed from a conformal metal, and includes a laterally-extending tub base and vertically-extending tub sidewalls extending upwardly from the laterally-extending tub base, wherein the laterally-extending tub base and vertically-extending tub sidewalls define in a resistor tub interior opening. The dielectric liner is formed in the resistor tub interior opening. The resistive element is formed over the dielectric liner in the resistor tub interior opening, and includes a pair of resistor heads connected by a laterally-extending resistor body. The dielectric liner electrically insulates the resistive element from the resistor tub.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
A method of forming a partially silicided element is provided. A silicided structure including a silicide layer on a base structure is formed. A dielectric region is formed over the silicided structure. The dielectric region is etched to form a contact opening exposing a first area of the silicide layer and a tub opening exposing a second area of the silicide layer. A conformal metal is deposited to (a) fill the contact opening to define a contact and (b) form a cup-shaped metal structure in the tub opening. Another etch is performed to remove the cup-shaped metal structure in the tub opening, to remove the underlying silicide layer second area and to expose an underlying area of the base structure, wherein the silicide layer first area remains intact. The base structure with the intact silicide layer first area and removed silicide layer second area defines the partially silicided element.
H01L 21/3213 - Gravure physique ou chimique des couches, p.ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
Teachings of the present disclosure include systems and/or methods for encoding digital data into a handwritten sample. An example method includes: accessing a predetermined vibration pattern stored in a memory corresponding to defined data; and vibrating a stylus based on the predetermined vibration pattern during creation of the handwritten sample to encode the defined data into the handwriting sample.
G06V 30/224 - Reconnaissance de caractères caractérisés par le type d’écriture de caractères imprimés pourvus de marques de codage additionnelles ou de marques de codage
B43K 29/08 - Combinaisons d'instruments pour écrire avec d'autres objets avec des dispositifs de mesure, de calcul ou des dispositifs indicateurs
G06F 3/0346 - Dispositifs de pointage déplacés ou positionnés par l'utilisateur; Leurs accessoires avec détection de l’orientation ou du mouvement libre du dispositif dans un espace en trois dimensions [3D], p.ex. souris 3D, dispositifs de pointage à six degrés de liberté [6-DOF] utilisant des capteurs gyroscopiques, accéléromètres ou d’inclinaiso
G06F 3/0354 - Dispositifs de pointage déplacés ou positionnés par l'utilisateur; Leurs accessoires avec détection des mouvements relatifs en deux dimensions [2D] entre le dispositif de pointage ou une partie agissante dudit dispositif, et un plan ou une surface, p.ex. souris 2D, boules traçantes, crayons ou palets
G06F 3/038 - Dispositions de commande et d'interface à cet effet, p.ex. circuits d'attaque ou circuits de contrôle incorporés dans le dispositif
46.
DETERMINING A LOCKED STATUS OF A CLOCK TRACKING CIRCUIT
An example apparatus includes a phase detector, a digital discriminator, and a logic circuit. A status signal of the phase detector is at least partially based on a phase relationship between a reference clock and a feedback clock, the feedback clock generated by a clock tracking circuit to track the reference clock. The digital discriminator may sample the status signal of the phase detector. The logic circuit may determine a locked status of the clock tracking circuit at least partially based on samples of the status signal of the phase detector.
H03L 7/091 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence utilisant un dispositif d'échantillonnage
H03L 7/093 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
H03L 7/095 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie utilisant un détecteur de verrouillage
47.
SINGLE AND DUAL EDGE TRIGGERED PHASE ERROR DETECTION
An example apparatus includes a phase detector and a phase error detector. The phase detector may set a status signal to indicate status of phase difference between a reference clock and a feedback clock, the feedback clock generated by a clock tracking circuit to track the reference clock. The phase error detector may set an error signal to be proportional to a phase difference between the reference clock and the feedback clock. At least partially responsive to the status signal, the phase error detector to change from triggered only by edges of the reference clock and feedback clock having a first polarity to triggered by edges of the reference clock and feedback clock having the first polarity and by edges of the reference clock and feedback clock having a second polarity, the second polarity different than the first polarity.
H03L 7/087 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie utilisant au moins deux détecteurs de phase ou un détecteur de fréquence et de phase dans la boucle
H03L 7/091 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence utilisant un dispositif d'échantillonnage
48.
NEURAL NETWORK ARRAY COMPRISING ONE OR MORE COARSE CELLS AND ONE OR MORE FINE CELLS
In one example, a system comprises a neural network array of non-volatile memory cells arranged in rows and columns; and a logical cell comprising a first plurality of non-volatile memory cells in a first row of the array and a second plurality of non-volatile memory cells in a second row adjacent to the first row; wherein the first plurality of non-volatile memory cells and the second plurality of non-volatile memory cells are configured as one or more coarse cells and one or more fine cells.
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 16/14 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
49.
DEVICE AND METHODS FOR DIGITAL SWITCHED CAPACITOR DC-DC CONVERTERS
A switched-capacitor DC-DC converter circuit may convert an input voltage into a desired output voltage level. A comparator may compare a desired voltage level to a divided version of the output voltage. A fully digital control circuit comprising a frequency divider circuit, a counter circuit, a digital control logic circuit and a gain selection circuit may generate a gain value, and a phase generator may convert the gain value into clock phase signals and control settings to control a switch array to select capacitors to produce a desired output voltage.
H02M 1/00 - APPAREILS POUR LA TRANSFORMATION DE COURANT ALTERNATIF EN COURANT ALTERNATIF, DE COURANT ALTERNATIF EN COURANT CONTINU OU VICE VERSA OU DE COURANT CONTINU EN COURANT CONTINU ET EMPLOYÉS AVEC LES RÉSEAUX DE DISTRIBUTION D'ÉNERGIE OU DES SYSTÈMES D'ALI; TRANSFORMATION D'UNE PUISSANCE D'ENTRÉE EN COURANT CONTINU OU COURANT ALTERNATIF EN UNE PUISSANCE DE SORTIE DE CHOC; LEUR COMMANDE OU RÉGULATION - Détails d'appareils pour transformation
H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p.ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
50.
DEVICE AND METHODS FOR DIGITAL SWITCHED CAPACITOR DC-DC CONVERTERS
A switched-capacitor DC-DC converter circuit may convert an input voltage into a desired output voltage level. A comparator may compare a desired voltage level to a divided version of the output voltage. A fully digital control circuit comprising a frequency divider circuit, a counter circuit, a digital control logic circuit and a gain selection circuit may generate a gain value, and a phase generator may convert the gain value into clock phase signals and control settings to control a switch array to select capacitors to produce a desired output voltage.
H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p.ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
H02M 3/157 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation avec commande numérique
51.
SETTING A PERFORMANCE MODE OF AN RF RECEIVER FRONTEND
Examples relate to setting a performance mode of an RF receiver front end. An example method includes determining a power state of an input signal to an RF receiver front end; and setting a performance mode of the RF receiver front end to one of at least three distinct performance modes offered by the RF receiver front end at least partially responsive to the determined power state of the input signal.
A first example comprises programming a memory cell to store a value; applying a series of currents of increasing size to a bit line of the memory cell; and measuring a voltage of a control gate terminal of the memory cell to determine a bias. A second example comprises programming a memory cell to store a value; applying a predetermined current to a bit line of the memory cell; and measuring a voltage of a control gate terminal of the memory cell to determine a bias.
G11C 11/54 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments simulateurs de cellules biologiques, p.ex. neurone
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/24 - Circuits de commande de lignes de bits
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
53.
DETERMINATION OF A BIAS VOLTAGE TO APPLY TO ONE OR MORE MEMORY CELLS
In one example, a method comprises programming a memory cell capable of storing any of N values with 1 of the N values; applying a series of currents of increasing size to a bit line of the memory cell; comparing a voltage of the bit line to a reference voltage to generate a comparison output; and when the comparison output changes value, measuring a voltage of a control gate terminal of the memory cell and storing the voltage in a bias lookup table.
G11C 11/54 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments simulateurs de cellules biologiques, p.ex. neurone
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/24 - Circuits de commande de lignes de bits
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
54.
ANNULAR KNOB-ON-DISPLAY DEVICES AND RELATED APPARATUSES
Annular knob-on-display (KoD) devices and related apparatuses. An apparatus includes a frame having substantially annular shape, a dome switch, a plurality of actuator members, and a plurality of pivot members. Respective pivot members of the plurality of pivot members secures an actuator member of the plurality of actuator members to the frame and transfers force applied to the actuator member to the dome switch.
G06F 3/039 - Leurs accessoires, p.ex. tapis de souris
H01H 25/06 - Organe moteur à mouvement angulaire et à mouvement rectiligne, le mouvement rectiligne s'effectuant le long de l'axe du mouvement angulaire
55.
CAPACITIVELY DETERMINING QUANTITY OF PARTICULATE PRESENT IN A CHAMBER
An example relates to a method that includes capacitively determining a quantity of particulate present in an internal chamber of a housing structure while the housing structure receives a feed air stream to the internal chamber; and providing a value representing the measured quantity of particulate.
G01F 23/263 - Indication ou mesure du niveau des liquides ou des matériaux solides fluents, p.ex. indication en fonction du volume ou indication au moyen d'un signal d'alarme en mesurant des variables physiques autres que les dimensions linéaires, la pression ou le poids, selon le niveau à mesurer, p.ex. par la différence de transfert de chaleur de vapeur ou d'eau en mesurant les variations de capacité ou l'inductance de condensateurs ou de bobines produites par la présence d'un liquide ou d'un matériau solide fluent dans des champs électriques ou électromagnétiques en mesurant les variations de capacité de condensateurs
G01F 1/74 - Dispositifs pour la mesure du débit d'un matériau fluide ou du débit d'un matériau solide fluent en suspension dans un autre fluide
G01F 22/00 - Procédés ou appareils pour la mesure du volume des fluides ou des matériaux solides fluents, non prévus ailleurs
G01N 15/06 - Recherche de la concentration des suspensions de particules
A47L 9/28 - Montage de l'équipement électrique, p.ex. adaptation ou fixation à l'aspirateur; Commande des aspirateurs par des moyens électriques
56.
SYMBOL FILTERING AT A PHY-SIDE of PHY-MAC INTERFACE
Disclosed examples include a method. The method includes: conveying symbols from a PHY toward a MAC via a PHY-side of PHY-MAC interface; and filtering one or more symbols at an input of a PHY-side of an interface wrapper of the PHY-side of the PHY-MAC interface. Disclosed examples include an apparatus. The apparatus includes: a PHY-side of PHY-MAC interface; and a logic circuit provided at the PHY-side of PHY-MAC interface, the logic circuit comprising a symbol filter to filter one or more symbols conveyed via the PHY-side of PHY-MAC interface.
A method includes: observing that a digitally controlled oscillator (DCO) frequency is at a boundary of a DCO frequency overlap region; and bypassing at least a portion of the DCO frequency overlap region.
H03L 7/099 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03L 7/10 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase pour assurer la synchronisation initiale ou pour élargir le domaine d'accrochage
58.
REDUCE DCO FREQUENCY OVERLAP-INDUCED LIMIT CYCLE IN HYBRID AND DIGITAL PLLS
A method includes: observing that a digitally controlled oscillator (DCO) frequency is at a boundary of a DCO frequency overlap region; and bypassing at least a portion of the DCO frequency overlap region.
H03L 7/093 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
59.
SYSTEM FOR TRANSMITTING OBJECT RELATED DATA FROM A BASE UNIT TO A MOBILE UNIT THROUGH A PERSON'S BODY
A system includes a base unit associated with an object, and a mobile unit carriable by a person. The base unit includes a base unit capacitive coupling element providing a base unit-human capacitive coupling between the base unit and the person, and the mobile unit includes a mobile unit capacitive coupling element providing a mobile unit-human capacitive coupling between the mobile unit and the person. The base unit-human capacitive coupling and mobile unit-human capacitive coupling enable a data transmission connection between the base unit and mobile unit that passes through the person's body. Base unit transmitter circuitry of the base unit transmits object related data via the data transmission connection passing through the person's body, mobile unit receiver circuitry of the mobile unit receives the object related data, and an output device of the mobile unit outputs human-perceptible signals based on the received object related data.
G06F 3/0362 - Dispositifs de pointage déplacés ou positionnés par l'utilisateur; Leurs accessoires avec détection des translations ou des rotations unidimensionnelles [1D] d’une partie agissante du dispositif de pointage, p.ex. molettes de défilement, curseurs, boutons, rouleaux ou bandes
Disclosed examples include a method. The method includes: conveying symbols from a PHY toward a MAC via a PHY-side of PHY-MAC interface; and filtering one or more symbols at an input of a PHY-side of an interface wrapper of the PHY-side of the PHY-MAC interface. Disclosed examples include an apparatus. The apparatus includes: a PHY-side of PHY-MAC interface; and a logic circuit provided at the PHY-side of PHY-MAC interface, the logic circuit comprising a symbol filter to filter one or more symbols conveyed via the PHY-side of PHY-MAC interface.
G06F 13/36 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs
G06F 13/376 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès décentralisée utilisant une méthode de résolution des conflits d'utilisation, p.ex. détection de collision, évitement de collision
G06F 13/38 - Transfert d'informations, p.ex. sur un bus
G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation
H04L 12/413 - Réseaux à ligne bus avec commande décentralisée avec accès aléatoire, p.ex. accès multiple avec détection de porteuse et détection de collision (CSMA-CD)
A system includes a base unit associated with an object, and a mobile unit carriable by a person. The base unit includes a base unit capacitive coupling element providing a base unit-human capacitive coupling between the base unit and the person, and the mobile unit includes a mobile unit capacitive coupling element providing a mobile unit-human capacitive coupling between the mobile unit and the person. The base unit-human capacitive coupling and mobile unit-human capacitive coupling enable a data transmission connection between the base unit and mobile unit that passes through the person's body. Base unit transmitter circuitry of the base unit transmits object related data via the data transmission connection passing through the person's body, mobile unit receiver circuitry of the mobile unit receives the object related data, and an output device of the mobile unit outputs human-perceptible signals based on the received object related data.
A peripheral device for matrix multiplication including a weight memory, an input memory, a multiplier, an accumulator, an output memory and a sequencer to generate signals to drive the input memory and the output memory and to generate an interrupt signal. The weight memory may be loaded with weights and biases for a matrix multiplication operation, and the multiplier and accumulator may implement the multiply and accumulator operations for a matrix multiplication operation. Data may be swapped between the input memory and output memory to reduce the memory required for matrix multiplication operations.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
A peripheral device for matrix multiplication including a weight memory, an input memory, a multiplier, an accumulator, an output memory and a sequencer to generate signals to drive the input memory and the output memory and to generate an interrupt signal. The weight memory may be loaded with weights and biases for a matrix multiplication operation, and the multiplier and accumulator may implement the multiply and accumulator operations for a matrix multiplication operation. Data may be swapped between the input memory and output memory to reduce the memory required for matrix multiplication operations.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
An apparatus includes a power-over-Ethernet (POE) interface to be connected to a powered device (PD) over an Ethernet cable and a control circuit. The control circuit is to measure a voltage provided by the apparatus through the Ethernet cable, determine that the voltage has dropped by at least a given voltage change, based on a determination that the voltage has dropped by at least the given voltage change, determine whether or not a predetermined quantity of Maintain Power Signature (MPS) signals have been missed within a given time frame, and, based on a determination that the predetermined quantity of MPS signals has not been missed within the given time frame, determine that the PD is still connected to the apparatus.
An apparatus and method for determining electrical characteristics has an acquisition circuit and a control circuit. The control circuit causes a first modulation circuit to issue a first set of modulated signals to a first source of alternating current energy, wherein the first set of modulated signals has a first deadtime and wherein a high side switch and a low side switch of the first modulation circuit are turned off. The control circuit further causes the acquisition circuit to acquire a first electrical characteristic of the first source of alternating current energy from the first source of alternating current energy during the first deadtime.
H02P 6/182 - Dispositions de circuits pour détecter la position sans éléments séparés pour détecter la position utilisant la force contre-électromotrice dans les enroulements
H02P 6/10 - Dispositions pour commander l'ondulation du couple, p.ex. en assurant une ondulation réduite du couple
H02P 27/08 - Dispositions ou procédés pour la commande de moteurs à courant alternatif caractérisés par le type de tension d'alimentation utilisant une tension d’alimentation à fréquence variable, p.ex. tension d’alimentation d’onduleurs ou de convertisseurs utilisant des convertisseurs de courant continu en courant alternatif ou des onduleurs avec modulation de largeur d'impulsions
An apparatus includes a power-over-Ethernet (POE) interface to be connected to a powered device (PD) over an Ethernet cable and a control circuit. The control circuit is to measure a voltage provided by the apparatus through the Ethernet cable, determine that the voltage has dropped by at least a given voltage change, based on a determination that the voltage has dropped by at least the given voltage change, determine whether or not a predetermined quantity of Maintain Power Signature (MPS) signals have been missed within a given time frame, and, based on a determination that the predetermined quantity of MPS signals has not been missed within the given time frame, determine that the PD is still connected to the apparatus.
An apparatus and method for determining electrical characteristics has an acquisition circuit and a control circuit. The control circuit causes a first modulation circuit to issue a first set of modulated signals to a first source of alternating current energy, wherein the first set of modulated signals has a first deadtime and wherein a high side switch and a low side switch of the first modulation circuit are turned off. The control circuit further causes the acquisition circuit to acquire a first electrical characteristic of the first source of alternating current energy from the first source of alternating current energy during the first deadtime.
H02P 6/182 - Dispositions de circuits pour détecter la position sans éléments séparés pour détecter la position utilisant la force contre-électromotrice dans les enroulements
An apparatus may include a physical layer device, a detection circuitry and a power control circuitry. the physical layer device provides one or more functions of a physical layer to interface with a shared physical transmission medium. The detection circuitry detects an indication of power control signaling on the shared physical transmission medium, and detects an indication of Ethernet signaling on the shared physical transmission medium. The indication of power control signaling is different than the indication of Ethernet signaling. The power control circuitry manages a power state of the apparatus at least partially responsive to an output of the detection circuitry.
Motion detection apparatuses are disclosed. The motion detection may be performed using one or more of a sub-window of a predetermined time window, a predetermined threshold value that is settable responsive to changes in one or more environmental factors, or a detection trigger. An apparatus includes a processor and an analog-to-digital converter (ADC) circuitry to sample a reflected predetermined pattern signal to generate reflected predetermined pattern samples. The processor captures collections of the reflected predetermined pattern samples corresponding to a predetermined time window and determines a sum of the collections or sub-collections. The processor determines an average of magnitudes of the determined sum and determines that a moving object is detected responsive to a predetermined threshold value.
A device including an input to receive a clock signal, a ramp start program register, a ramp start active register, a ramp stop program register, a ramp stop active register, a ramp slope program register, a ramp slope active register, an update controller, the update controller to update, based on a programmable condition, respectively, the ramp start active register contents, the ramp stop active register contents and the ramp slope active register contents, and a ramp controller to generate a ramp signal, the ramp signal to begin at the value reflective of the ramp start active register contents, the ramp signal to change value at each cycle of the clock signal based on the value reflective of the ramp slope active register contents, and the ramp signal to stop at the value reflective of the ramp stop active register contents.
A device (104) including an input (210) to receive a clock signal (285), a ramp start program register (220), a ramp start active register (260), a ramp stop program register (221), a ramp stop active register (261), a ramp slope program register (222), a ramp slope active register (262), an update controller (240), the update controller to update, based on a programmable condition, respectively, the ramp start active register contents, the ramp stop active register contents and the ramp slope active register contents, and a ramp controller (280) to generate a ramp signal (290), the ramp signal to begin at the value reflective of the ramp start active register contents, the ramp signal to change value at each cycle of the clock signal based on the value reflective of the ramp slope active register contents, and the ramp signal to stop at the value reflective of the ramp stop active register contents.
H03K 4/02 - Génération d'impulsions ayant comme caractéristique essentielle une pente définie ou des parties en gradins avec parties en gradins, p.ex. en forme d'escalier
One or more examples relate to a method. The method may include: comparing a first value and a second value, the first value representing a duty cycle of a reference clock and the second value representing a duty cycle of an output clock generated by a clock tracking circuit to track the reference clock; setting a duty cycle of a changed clock to reduce duty cycle mismatch between the reference clock and the output clock indicated by the comparing; and providing the changed clock having set duty cycle in lieu of the one of the reference clock or the output clock.
H03L 7/081 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase avec un déphaseur commandé additionnel
H03K 5/156 - Dispositions dans lesquelles un train d'impulsions est transformé en un train ayant une caractéristique désirée
An inductor-inductor-capacitor (LLC) power converter includes a current input interface to receive a current input indication. The current input indication includes a voltage to represent a current passing through of a primary side of the LLC power converter. The LLC power converter includes voltage input interface to receive a voltage input. The voltage input is to include a representative voltage to be provided from a secondary side of the LLC power converter. The LLC power converter includes a control circuit to generate pulsed-width modulation (PWM) control signals for the LLC power converter. The control circuit is to match an on-time period of a first leg and a second leg of the LLC power converter and based upon the current input indication and the voltage input.
H02M 1/088 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques pour la commande simultanée de dispositifs à semi-conducteurs connectés en série ou en parallèle
H02M 3/00 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
75.
TRIGGERING AN ERROR DETECTOR ON RISING AND FALLING EDGES OF CLOCK SIGNALS, AND GENERATING AN ERROR SIGNAL THEREFROM
One or more examples relate to triggering a single error detector on rising and falling edges of clock signals, and generating an error signal therefrom. A method may include receiving a first clock signal and a second clock signal. The method may include generating, via a single error detector being triggered at least partially responsive to like respective edges of the first clock signal and the second clock signal, an error signal that represents a phase difference between the first clock signal and the second clock signal.
A multi-capacitor module includes a nested metal-insulator-metal (MIM) structure including a cup-shaped first electrode, a cup-shaped first insulator formed over the cup-shaped first electrode, a cup-shaped second electrode formed over the cup-shaped first insulator, a cup-shaped second insulator formed over the cup-shaped second electrode, and a third electrode formed over the cup-shaped second insulator. The cup-shaped first electrode, the cup-shaped second electrode, and the cup-shaped first insulator define a first capacitor, and the cup-shaped second electrode, the third electrode, and the cup-shaped second insulator define a second capacitor physically nested in the first capacitor.
H10N 97/00 - Dispositifs électriques à l’état solide à film mince ou à film épais, non prévus ailleurs
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
77.
REDUCING DUTY CYCLE MISMATCH OF CLOCKS FOR CLOCK TRACKING CIRCUITS
One or more examples relate to a method. The method may include: comparing a first value and a second value, the first value representing a duty cycle of a reference clock and the second value representing a duty cycle of an output clock generated by a clock tracking circuit to track the reference clock; setting a duty cycle of a changed clock to reduce duty cycle mismatch between the reference clock and the output clock indicated by the comparing; and providing the changed clock having set duty cycle in lieu of the one of the reference clock or the output clock.
H03L 7/081 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase avec un déphaseur commandé additionnel
H03K 5/156 - Dispositions dans lesquelles un train d'impulsions est transformé en un train ayant une caractéristique désirée
78.
TIMESTAMP AT A PARALLEL INTERFACE OF A SERDES COUPLING A PHY WITH A PHYSICAL TRANSMISSION MEDIUM
One or more examples relate, generally, to timestamp at a parallel interface of a SerDes for coupling a PHY with a physical transmission medium. In an example, an apparatus includes a SerDes to couple a PHY to a physical transmission medium; a hardware timestamp logic; a bit detector coupled to initiate the hardware timestamp logic at least partially responsive to observing an indicated bit at a parallel interface of the SerDes; and a logic circuit provided at a portion of the PHY, the logic circuit coupled to receive timestamps generated by hardware timestamp logic.
One or more examples relate to a method. The method includes: receiving up/down error signals indicative of duty cycle mismatch between a reference clock signal and a changed feedback clock signal that represents an output clock signal generated by a clock tracking circuit to track the reference clock signal; setting a duty cycle of a changed feedback clock signal to reduce duty cycle mismatch indicated by the up/down error signals; and providing the changed feedback clock having set duty cycle.
H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p.ex. des signaux d'horloge
80.
TIMESTAMP AT A PARALLEL INTERFACE OF A SERDES COUPLING A PHY WITH A PHYSICAL TRANSMISSION MEDIUM
One or more examples relate, generally, to timestamp at a parallel interface of a SerDes for coupling a PHY with a physical transmission medium. In an example, an apparatus includes a SerDes to couple a PHY to a physical transmission medium; a hardware timestamp logic; a bit detector coupled to initiate the hardware timestamp logic at least partially responsive to observing an indicated bit at a parallel interface of the SerDes; and a logic circuit provided at a portion of the PHY, the logic circuit coupled to receive timestamps generated by hardware timestamp logic.
A multi-capacitor module includes a stacked metal-insulator-metal (MIM) structure including a cup-shaped first electrode, a cup-shaped first insulator formed over the cup-shaped first electrode, a cup-shaped second electrode formed over the cup-shaped first insulator, a cup-shaped second insulator formed over the cup-shaped second electrode, a third electrode formed over the cup-shaped second insulator. The stacked MIM structure also includes a first sidewall spacer located between the cup-shaped first electrode and the cup-shaped second electrode, and a second sidewall spacer located between the cup-shaped second electrode and the third electrode. The cup-shaped first electrode, the cup-shaped second electrode, and the cup-shaped first insulator define a first capacitor, and the cup-shaped second electrode, the third electrode, and the cup-shaped second insulator define a second capacitor.
A multi-capacitor module includes a stacked metal-insulator-metal (MIM) structure including a cup-shaped first electrode, a cup-shaped first insulator formed over the cup-shaped first electrode, a cup-shaped second electrode formed over the cup-shaped first insulator, a cup-shaped second insulator formed over the cup-shaped second electrode, a third electrode formed over the cup-shaped second insulator. The stacked MIM structure also includes a first sidewall spacer located between the cup-shaped first electrode and the cup-shaped second electrode, and a second sidewall spacer located between the cup-shaped second electrode and the third electrode. The cup-shaped first electrode, the cup-shaped second electrode, and the cup-shaped first insulator define a first capacitor, and the cup-shaped second electrode, the third electrode, and the cup-shaped second insulator define a second capacitor.
H10N 97/00 - Dispositifs électriques à l’état solide à film mince ou à film épais, non prévus ailleurs
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
An inductor-inductor-capacitor (LLC) power converter includes a current input interface to receive a current input indication. The current input indication includes a voltage to represent a current passing through of a primary side of the LLC power converter. The LLC power converter includes voltage input interface to receive a voltage input. The voltage input is to include a representative voltage to be provided from a secondary side of the LLC power converter. The LLC power converter includes a control circuit to generate pulsed-width modulation (PWM) control signals for the LLC power converter. The control circuit is to match an on-time period of a first leg and a second leg of the LLC power converter and based upon the current input indication and the voltage input.
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
84.
REDUCING DUTY CYCLE MISMATCH OF CLOCK SIGNALS FOR CLOCK TRACKING CIRCUITS
One or more examples relate to a method. The method includes: receiving up/down error signals indicative of duty cycle mismatch between a reference clock signal and a changed feedback clock signal that represents an output clock signal generated by a clock tracking circuit to track the reference clock signal; setting a duty cycle of a changed feedback clock signal to reduce duty cycle mismatch indicated by the up/down error signals; and providing the changed feedback clock having set duty cycle.
H03L 7/081 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase avec un déphaseur commandé additionnel
H03K 5/156 - Dispositions dans lesquelles un train d'impulsions est transformé en un train ayant une caractéristique désirée
85.
TRIGGERING AN ERROR DETECTOR ON RISING AND FALLING EDGES OF CLOCK SIGNALS, AND GENERATING AN ERROR SIGNAL THEREFROM
One or more examples relate to triggering a single error detector on rising and falling edges of clock signals, and generating an error signal therefrom. A method may include receiving a first clock signal and a second clock signal. The method may include generating, via a single error detector being triggered at least partially responsive to like respective edges of the first clock signal and the second clock signal, an error signal that represents a phase difference between the first clock signal and the second clock signal.
H03L 7/089 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence engendrant des impulsions d'augmentation ou de diminution
H03L 7/081 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase avec un déphaseur commandé additionnel
Examples relate to generating sync signals. An example apparatus includes an output, an input and a circuit. The output provides a data-valid signal to a video source operative to provide video data to a video-data-processing pipeline. The input receives a delayed data-valid signal from the video-data-processing pipeline. The circuit to generate a delayed horizontal-sync signal and a delayed vertical-sync signal at least partially responsive to the received delayed data-valid signal.
H04N 21/43 - Traitement de contenu ou données additionnelles, p.ex. démultiplexage de données additionnelles d'un flux vidéo numérique; Opérations élémentaires de client, p.ex. surveillance du réseau domestique ou synchronisation de l'horloge du décodeur; Intergiciel de client
87.
IRREGULAR-SHAPED CAPACITIVE SENSORS AND LOCATIONS OF TOUCH EVENTS AT THE SAME
A method includes: changing a geometry of a capacitive sensor design from a first geometry to a second geometry, the second geometry different than the first geometry; and obtaining executable instructions to transform a location identifier of a touch event from a first location identifier associated with the first geometry to a second location identifier associated with the second geometry.
Vapor cells may include a body including a cavity within the body. A first substrate bonded to a second substrate at an interface within the body, at least one of the first substrate, the second substrate, or an interfacial material between the first and second substrates may define at least one recess or pore in a surface. A smallest dimension of the at least one recess or pore may be about 500 microns or less, as measured in a direction parallel to at least one surface of the first substrate partially defining the cavity.
H03L 7/26 - Commande automatique de fréquence ou de phase; Synchronisation utilisant comme référence de fréquence les niveaux d'énergie de molécules, d'atomes ou de particules subatomiques
89.
MULTI-CAPACITOR MODULE INCLUDING A NESTED METAL-INSULATOR-METAL (MIM) STRUCTURE
A multi-capacitor module includes a nested metal-insulator-metal (MIM) structure including a cup-shaped first electrode, a cup-shaped first insulator formed over the cup-shaped first electrode, a cup-shaped second electrode formed over the cup-shaped first insulator, a cup-shaped second insulator formed over the cup-shaped second electrode, and a third electrode formed over the cup-shaped second insulator. The cup-shaped first electrode, the cup-shaped second electrode, and the cup-shaped first insulator define a first capacitor, and the cup-shaped second electrode, the third electrode, and the cup-shaped second insulator define a second capacitor physically nested in the first capacitor.
H01L 49/02 - Dispositifs à film mince ou à film épais
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
Examples relate to generating sync signals. An example apparatus includes an output, an input and a circuit. The output provides a data-valid signal to a video source operative to provide video data to a video-data-processing pipeline. The input receives a delayed data-valid signal from the video-data-processing pipeline. The circuit to generate a delayed horizontal-sync signal and a delayed vertical-sync signal at least partially responsive to the received delayed data-valid signal.
G09G 5/00 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation
G09G 5/12 - Synchronisation entre l'unité d'affichage et d'autres unités, p.ex. d'autres unités d'affichage, des lecteurs de disques vidéo
G09G 5/18 - Circuits de synchronisation pour l'affichage à balayage par trame
91.
HIGH-LEVEL-SYNTHESIS FOR RISC-V SYSTEM-ON-CHIP GENERATION FOR FIELD PROGRAMMABLE GATE ARRAYS
An article of manufacture includes a medium with instructions that when read and executed by a processor, cause the processor to identify a code stream to be executed by a system-on-a-chip (SoC). The SoC is to include an open standard processor and hardware accelerators implemented in reprogrammable hardware. The processor is to, from the code stream, identify a first portion of the code stream to be executed as software by the open standard processor and a second portion to be executed in the accelerators, compile the first portion into a binary for execution by the open standard processor, and generate a hardware description for the second portion to be implemented by the hardware accelerators. The hardware description and the binary are to exchange data during execution of the code stream.
An article of manufacture includes a medium with instructions that when read and executed by a processor, cause the processor to identify a code stream to be executed by a system-on-a-chip (SoC). The SoC is to include an open standard processor and hardware accelerators implemented in reprogrammable hardware. The processor is to, from the code stream, identify a first portion of the code stream to be executed as software by the open standard processor and a second portion to be executed in the accelerators, compile the first portion into a binary for execution by the open standard processor, and generate a hardware description for the second portion to be implemented by the hardware accelerators. The hardware description and the binary are to exchange data during execution of the code stream.
A system includes a metal tub structure formed in an integrated circuit (IC) structure, a first metal component, and a second metal component. The first metal component is formed from a first metal. The first metal component is formed in an opening defined by the metal tub structure, and includes a first metal first junction element, a first metal second junction element, and a first metal bridge electrically connected to the first metal first junction element and the first metal second junction element. The second metal component is formed from a second metal different than the first metal, and includes a second metal first junction element electrically connected to the first metal first junction element to define a first thermocouple junction, and a second metal second junction element electrically connected to the first metal second junction element to define a second thermocouple junction.
G01K 7/02 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments thermo-électriques, p.ex. des thermocouples
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H10N 19/00 - Dispositifs intégrés ou ensembles de plusieurs dispositifs comprenant au moins un élément thermoélectrique ou thermomagnétique couvert par les groupes
H01L 23/34 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température
A metal-insulator-metal (MIM) capacitor includes a bottom electrode, an insulator cup formed on the bottom electrode, a top electrode formed in an opening defined by the insulator cup, a top electrode connection element electrically connected to the top electrode, a vertically-extending bottom electrode contact electrically connected to the bottom electrode, and a bottom electrode connection element electrically connected to the vertically-extending bottom electrode contact. The bottom electrode is formed in a lower metal layer. The insulator cup is formed in a tub opening in a dielectric region and includes a laterally extending insulator cup base formed on the bottom electrode and a vertically-extending insulator cup sidewall extending upwardly from the laterally extending insulator cup base. The top electrode connection element and bottom electrode connection element are formed in an upper metal layer.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H10N 97/00 - Dispositifs électriques à l’état solide à film mince ou à film épais, non prévus ailleurs
A metal-insulator-metal (MIM) capacitor includes a bottom electrode, an insulator cup formed on the bottom electrode, a top electrode formed in an opening defined by the insulator cup, a top electrode connection element electrically connected to the top electrode, a vertically-extending bottom electrode contact electrically connected to the bottom electrode, and a bottom electrode connection element electrically connected to the vertically-extending bottom electrode contact. The bottom electrode is formed in a lower metal layer. The insulator cup is formed in a tub opening in a dielectric region and includes a laterally extending insulator cup base formed on the bottom electrode and a vertically-extending insulator cup sidewall extending upwardly from the laterally extending insulator cup base. The top electrode connection element and bottom electrode connection element are formed in an upper metal layer.
H01L 49/02 - Dispositifs à film mince ou à film épais
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
A device for measuring phase noise, including a sampler to sample an input signal, an input filter to receive an input from the sampler, a noise generator to generate a noise signal, a combiner to receive input from, respectively, the input filter and the noise generator, the combiner to output an integrated noise output measurement. The input filter may operate in either the time domain or the frequency domain. The noise generate may generate a noise signal based on the sampler output, or may generate a noise estimate value based on the sampler output.
A fault event monitor and filter having a digital comparator receiving a digital input value, wherein the digital comparator generates a plurality of outputs based on programmable threshold input values, a first counter coupled to a first output of the plurality of outputs of the digital comparator, a second counter coupled to a second output of the plurality of outputs of the digital comparator, and an output controller with a first input coupled to an output of the first counter and with a second input coupled to an output of the second counter, wherein the output controller to generate a fault event signal based at least partially on signals received from the first and second counters.
A device for measuring phase noise, including a sampler to sample an input signal, an input filter to receive an input from the sampler, a noise generator to generate a noise signal, a combiner to receive input from, respectively, the input filter and the noise generator, the combiner to output an integrated noise output measurement. The input filter may operate in either the time domain or the frequency domain. The noise generate may generate a noise signal based on the sampler output, or may generate a noise estimate value based on the sampler output.
A fault event monitor and filter having a digital comparator receiving a digital input value, wherein the digital comparator generates a plurality of outputs based on programmable threshold input values, a first counter coupled to a first output of the plurality of outputs of the digital comparator, a second counter coupled to a second output of the plurality of outputs of the digital comparator, and an output controller with a first input coupled to an output of the first counter and with a second input coupled to an output of the second counter, wherein the output controller to generate a fault event signal based at least partially on signals received from the first and second counters.
A system includes a metal tub structure formed in an integrated circuit (IC) structure, a first metal component, and a second metal component. The first metal component is formed from a first metal. The first metal component is formed in an opening defined by the metal tub structure, and includes a first metal first junction element, a first metal second junction element, and a first metal bridge electrically connected to the first metal first junction element and the first metal second junction element. The second metal component is formed from a second metal different than the first metal, and includes a second metal first junction element electrically connected to the first metal first junction element to define a first thermocouple junction, and a second metal second junction element electrically connected to the first metal second junction element to define a second thermocouple junction.
G01K 7/06 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments thermo-électriques, p.ex. des thermocouples l'objet à mesurer ne formant pas l'un des matériaux thermo-électriques les matériaux thermo-électriques étant disposés l'un à l'intérieur de l'autre avec la jonction à une extrémité exposée à l'objet, p.ex. du genre à gaine
G01K 7/02 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments thermo-électriques, p.ex. des thermocouples
