An apparatus includes an apparatus input to receive a voltage input, an apparatus output to drive an output metal oxide semiconductor field effect transistor (MOSFET) at least partially based upon the voltage input, a current source circuit to provide a current source to the apparatus output when the voltage input rises above a first threshold and before the voltage input rises above a second threshold, a voltage clamp circuit to provide a clamped output voltage to the apparatus output when the voltage input rises above the second threshold, and a current sink circuit to provide a current sink to the apparatus output when the voltage input falls below the second threshold and before the voltage input reaches the first threshold.
H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
H03K 17/06 - Modifications pour assurer un état complètement conducteur
H03K 17/12 - Modifications pour augmenter le courant commuté maximal admissible
2.
VEHICLE SECURITY DEVICE WITH PRIMARY ALARM AND DISPLAY ALARM
A system having a theft event sensor; a primary alarm actuator; a display alarm actuator; and a vehicle security device to: receive a theft event signal from the theft event sensor, transmit a primary alarm signal to the primary alarm actuator, and transmit a display alarm signal to the display alarm actuator.
B60R 25/10 - VÉHICULES, ÉQUIPEMENTS OU PARTIES DE VÉHICULES, NON PRÉVUS AILLEURS Équipements ou systèmes pour interdire ou signaler l’usage non autorisé ou le vol de véhicules actionnant un dispositif d’alarme
B60R 25/104 - VÉHICULES, ÉQUIPEMENTS OU PARTIES DE VÉHICULES, NON PRÉVUS AILLEURS Équipements ou systèmes pour interdire ou signaler l’usage non autorisé ou le vol de véhicules actionnant un dispositif d’alarme caractérisé par le type de signal antivol, p.ex. signaux visuels ou audibles ayant des caractéristiques spéciales
An apparatus includes an adjustment circuit configured to receive a pulsed-width modulation (PWM) input, generate an adjusted PWM signal based upon the PWM input, and determine that a first pulse of the PWM input is shorter than a runt signal limit. The adjustment circuit is further configured to, in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit, and output the adjusted PWM signal to an electronic device.
A low dropout (LDO) regulator circuit is provided. The LDO regulator circuit may include a pre-regulator circuit to receive a high voltage input voltage and provide a low voltage supply voltage, and an LDO regulator to receive the low voltage supply voltage and provide a low voltage output voltage. The pre-regulator circuit may include an input stage, an output stage coupled to the input stage, and a first MOSFET coupled to the output stage to provide the low voltage supply voltage. The input stage and first MOSFET may receive the high voltage input voltage. The LDO regulator may include a second MOSFET coupled to the first MOSFET, and may receive the low voltage supply voltage and provide the low voltage output voltage.
G05F 1/563 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final comprenant deux niveaux de régulation, dont l'un au moins est sensible au niveau de sortie, p.ex. réglage grossier et fin
G05F 1/56 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final
G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
5.
Method and apparatus for carrying constant bit rate (CBR) client signals using CBR carrier streams comprising frames
A method and apparatus in which a data stream is received that includes constant bit rate (CBR) carrier streams, at least one of which comprises frames, a cumulative phase offset report (CPOR) and a client rate report (CRR). A counter accumulating a PHY-scaled stream clock (IPSCk) is sampled at a nominal sampling period (Tps) to obtain a cumulative PHY-scaled count (CPSC). A PHY-scaled stream phase offset (PSPO) is calculated that indicates phase difference between PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD). The data stream is demultiplexed to obtain CBR carrier streams. Respective CBR carrier streams include a previous network node CPOR (CPOR-P) and a previous network node CPO (CPO-P). A CPO is calculated that is a function of CPO-P and PSPO. CPO-P is replaced with the calculated CPO. The CBR carrier streams are multiplexed into intermediate-network-node data streams that are transmitted from the intermediate-network-node.
One or more examples relate to voltage level shifting. An example apparatus may include first and second inputs, an output, and a circuit. The first and second inputs may receive compliments of a signal represented by first voltage levels. The output may provide the signal represented by second voltage levels. The circuit may change voltage levels utilized to represent the signal from first voltage levels to second voltage levels. The circuit may include cross-coupled first high voltage switches, a pair of series coupled switches, and a pair of voltage clamping switches. The cross-coupled first high voltage switches may selectively couple the output to a high voltage node responsive to a high voltage level of the signal. The pair of series coupled switches may comprising respective second high voltage switches, and the pair of series coupled switches may selectively couple the output to a first voltage supply. The pair of voltage clamping switches may increase OFF-resistance of the respective second high voltage switches of the pair of series coupled switches responsive to a low voltage level at the respective input.
An apparatus having a substrate having first and second substrate contacts; a chip having a front-side chip contact and first and second back-side chip contacts, the front-side chip contact electrically connected to the first substrate contact; a chiplet having a chiplet contact electrically connected the first back-side chip contact; and a lead electrically connected to the second back-side chip contact and electrically connected to the second substrate contact.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
8.
SUPPLY VOLTAGE BASED OR TEMPERATURE BASED FINE CONTROL OF A TUNABLE OSCILLATOR OF A PLL
One or more examples relate, generally to supply voltage based or temperature based fine control of a tunable oscillator of a PLL. An associated method includes: receiving one or more values indicative of temperature or supply voltage of a phase-locked loop (PLL); setting a digital fine-tuning control code to an initialization code, the initialization code at least partially based on the received one or more values indicative of temperature or supply voltage of the PLL, wherein the digital fine-tuning control code for setting a number of tuning-elements within a fine bank of a tunable oscillator; and starting, with the set digital fine-tuning control code, a process to set an initial frequency of the oscillator at or close to a target frequency. The process may be a calibration process performed before initially acquiring lock or re-acquiring lock.
H03L 7/099 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
9.
EMI Reduction in PLCA-Based Networks Through Beacon Temporal Spreading
An apparatus may be communicatively coupled to other nodes in a network. The apparatus may include a control circuit configured to repeatedly issue transmission cycles to the other nodes. A given transmission cycle may include a least one send slot for each of the other nodes to send data. The control circuit may be configured to initiate transmission cycles by issuing beacon signals to the other nodes. The control circuit may be configured to determine when to issue a beacon signal in a given transmission cycle by determining that all of the other nodes have completed all associated send slots in an immediately previous transmission cycle and based upon a determination of the completion of the other nodes' transmission, delaying transmission of the beacon signal for the given transmission cycle.
H04L 12/413 - Réseaux à ligne bus avec commande décentralisée avec accès aléatoire, p.ex. accès multiple avec détection de porteuse et détection de collision (CSMA-CD)
10.
Automatic USB3 Hub for Detecting and Changing Link Speed
A USB control method comprising: counting errors encountered by a USB connection; comparing a number of counted errors to an error count threshold within a set time frame; identifying a port speed configuration for the USB connection; and changing the port speed configuration for the USB connection to a slower port speed configuration than the identified port speed configuration.
An active inductor modulator circuit is provided. The active inductor modulator circuit may include a circuit to receive an input signal and provide an output signal at an output terminal of the circuit based on a clock signal, a modulated active inductor coupled to the circuit to improve a time delay between the input signal and the provided output signal, and a modulation clock circuit to generate a delayed clock signal to enable the modulated active inductor prior to a transition of the output signal from a first logic state to a second logic state.
An apparatus includes two PHY circuits, each including a PHY transmitter circuit and connected to a universal serial bus (USB)-C connector. The apparatus includes a USB circuit to issue a receiver detect signal through one of the PHY transmitters circuit to the USB-C connector, issue another receiver detect signal through the other PHY transmitter circuit to the USB-C connector, determine which receiver detect signal resulted in a termination in a USB-C element, and consequently determine an orientation of a USB plug connected between the apparatus and the USB-C element.
A device with one-time-programmable (OTP) memory, boot code, volatile memory, and non-volatile memory. Boot code may use information in OTP to authenticate code of an implicit owner of the electronic device; receive a first create owner container request; create a first owner container comprising a first signed data image; store the first owner container; and use the first signed data image to authenticate first executable code associated with the first owner. Boot code may transfer ownership from the first owner to a second owner, including authenticating a signed transfer of ownership command using a key stored in the first owner container and creating a second owner container comprising a second signed data image associated with the second owner; storing the second owner container; revoking the first owner container; and using the second signed data image to authenticate second executable code associated with the second owner of the electronic device.
Disclosed are systems, methods, and devices for communicating a source of a 10SPE wake. Such a communication may be performed over a low-pin count hardware interface of a 10SPE physical layer (PHY) module having a split arrangement. A controller side of a 10SPE PHY may perform a local or remote 10SPE wake forward in response to a communicated source of a wake. Also disclosed is a digital interface for operatively coupling a PHY controller to PHY transceiver over a low-pin count connection, where the digital interface includes circuitry for checking the integrity of circuitry of the digital interface. Also disclosed is a PHY transceiver of a 10SPE PHY, where the transceiver includes a circuitry for controlling a starting polarity of frames.
H04L 69/28 - Minuteurs ou mécanismes de chronométrage utilisés dans les protocoles
H04L 69/323 - Protocoles de communication intra-couche entre entités paires ou définitions d'unité de données de protocole [PDU] dans la couche physique [couche OSI 1]
This description relates, generally, to protecting a circuit from an input voltage. Various examples include an apparatus including one or more circuits to draw current from, or provide current to, a pair of connectors for an input circuit. The connectors may be for electrical coupling to first and second terminals of a twisted pair. The one or more circuits may be at least partially responsive to positive and negative biasing signals. The apparatus may additionally include an operational amplifier to generate the positive and negative biasing signals. The operational amplifier may include: a first input terminal at least partially responsive to a reference voltage and a second input terminal at least partially responsive to a common-mode voltage of the input circuit. Related systems and methods are also disclosed.
A metal-insulator-metal (MIM) capacitor includes a bottom electrode cup, an insulator cup, and a top electrode. The bottom electrode cup includes a laterally-extending bottom electrode cup base, and a bottom electrode cup sidewall extending upwardly from the laterally-extending bottom electrode cup base. The insulator cup is formed in an opening defined by the bottom electrode cup, and includes a laterally-extending insulator cup base formed over the laterally-extending bottom electrode cup base, and an insulator cup sidewall extending upwardly from the laterally-extending insulator cup base. A dielectric sidewall spacer is located between the insulator cup sidewall and the bottom electrode cup sidewall. The top electrode is formed in an opening defined by the insulator cup.
A metal-insulator-metal (MIM) capacitor module includes an outer electrode, an insulator, an inner electrode, an outer electrode extension structure, an inner electrode contact element, and an outer electrode contact element. The outer electrode includes a plurality of vertically-extending outer electrode sidewalls. The insulator is formed in an opening defined by the vertically-extending outer electrode sidewalls, and includes a plurality of vertically-extending insulator sidewalls. The inner electrode formed in an interior opening defined by the insulator. The outer electrode extension structure extends laterally from a particular vertically-extending outer electrode sidewall. The inner electrode contact element and outer electrode contact element are formed in a metal layer. The inner electrode contact element is electrically connected to the inner electrode, and the outer electrode contact element is electrically connected to the outer electrode extension structure.
H01L 49/02 - Dispositifs à film mince ou à film épais
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
A low-resistance thick-wire integrated inductor may be formed in an integrated circuit (IC) device. The integrated inductor may include an elongated inductor wire defined by a metal layer stack including an upper metal layer, middle metal layer, and lower metal layer. The lower metal layer may be formed in a top copper interconnect layer, the upper metal layer may be formed in an aluminum bond pad layer, and the middle metal layer may comprise a copper tub region formed between the aluminum upper layer and copper lower layer. The wide copper region defining the middle layer of the metal layer stack may be formed concurrently with copper vias of interconnect structures in the IC device, e.g., by filling respective openings using copper electrochemical plating or other bottom-up fill process. The elongated inductor wire may be shaped in a spiral or other symmetrical or non-symmetrical shape.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01F 27/32 - Isolation des bobines, des enroulements, ou de leurs éléments
An electronic device may have a plurality of defined life cycle stages and a one-time-programmable (OTP) memory comprising a plurality of life cycle bits, wherein respective bit patterns of the life cycle bits may correspond with respective life cycle stages of the defined life cycle stages. The electronic device may also have a boot code stored in read only memory and executable by a processor to receive a request to transition from a current life cycle stage to a next life cycle stage and, in response to the received request, automatically generate a bit pattern corresponding to the next life cycle stage of the plurality of defined life cycle stages and program the bit pattern corresponding to the next life cycle stage of the plurality of defined life cycle stages in the OTP memory during a time when the OTP memory is not user-accessible.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
20.
INTEGRATED CIRCUIT BOND PAD WITH MULTI-MATERIAL TOOTHED STRUCTURE
An integrated circuit device may include a multi-material toothed bond pad including (a) an array of vertically-extending teeth formed from a first material, e.g., aluminum, and (b) a fill material, e.g., silver, at least partially filling voids between the array of teeth. The teeth may be formed by depositing and etching aluminum or other suitable material, and the fill material may be deposited over the array of teeth and extending down into the voids between the teeth, and etched to expose top surfaces of the teeth. The array of teeth may collectively define an abrasive structure. The multi-material toothed bond pad may be bonded to another bond pad, e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad surfaces, to thereby create a direct and/or eutectic bonding between the bond pads.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
21.
DIGITAL-TO-ANALOG CONVERTER (DAC) DATA GENERATOR CIRCUIT
A device having a digital-to-analog converter (DAC) data generator circuit to perform a function upon an event and generate digital DAC data based on the function and the event, and a DAC circuit to generate an analog waveform signal from the digital DAC data.
A system and method of testing an integrated circuit provide a first clock signal to a first flip-flop with an output to a functional circuit, provide a second clock signal to a second flip-flop with an input from the functional circuit, wherein the second flip-flip has a minimum hold time, provide a test input to the first flip-flop, observe a signal propagation time through the functional circuit, determine the signal propagation time is less than the minimum hold time of the second flip-flop, and increasing a timing separation by adding a unit of delay to the first clock signal or subtracting a unit of delay from the second clock signal.
An apparatus includes a database with device profiles, and a device programmer. The device programmer includes instructions. The instructions, when read and executed by a processor, cause the device programmer to identify a device identifier of an electronic device. The device programmer is further caused to, based upon the device identifier, access device data from the database. The device programmer is further caused to, based upon the device data, determine an area of memory of the electronic device that can be written. The device programmer is further caused to, based on the determination of the area of memory of the electronic device that can be written, write data to the area of memory.
One or more examples relate to a method, which includes sending, from a provisioner WiFi device to a provisionee WiFi device in an idle mode, a probe request frame including a random data in a custom data field; powering up the provisionee WiFi device in a SoftAp mode at least partially responsive to receiving the probe request frame; sending, from the provisioner WiFi device to the provisionee WiFi device in the SoftAp mode, a further probe request frame including the random data in a custom data field; sending, from the provisionee WiFi device in the SoftAp mode to the provisioner WiFi device, a probe response frame; establishing a secure WiFi connection between the provisioner WiFi device and the provisionee WiFi device utilizing passphrases respectively generated by the provisioner WiFi device and the provisionee WiFi device; and sending provisioning data, from the provisioner WiFi device to the provisionee WiFi device in SoftAp mode, via the secure WiFi connection.
H04L 9/06 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p.ex. système DES
25.
SWITCHING DATA BASED ON A BUS IDENTIFIER AND A DEVICE IDENTIFIER
One or more examples relate to an apparatus to switch data based on a bus identifier and a device identifier. Such an apparatus may include an upstream port for a respective peripheral component interconnect express (PCIe)-compliant communicative connection with a host; a downstream port for a respective PCIe-compliant communicative connection with an endpoint; and a switching logic. The switching logic may store a bus identifier and a device identifier for the endpoint; and switch data at least partially responsive to the bus identifier and the device identifier of the endpoint.
An electronic device includes a transaction host, first and second peripherals, memory, an access control register, and first and second access controllers. The memory stores access control identifier management instructions, a first task related to the first peripheral, and a first bitmask indicating respective access settings for the first and second peripherals for performing the first task. The access control register includes a first access control identifier for the first peripheral and a second access control identifier for the second peripheral. The transaction host executes the access control identifier management instructions to program the first and second access control identifiers based on the first bitmask, and subsequently executes the first task. The first and second access controllers control access to the first and second peripherals, respectively, based on the respective first and second access control identifiers programmed based on the first bitmask.
G06F 21/62 - Protection de l’accès à des données via une plate-forme, p.ex. par clés ou règles de contrôle de l’accès
G06F 13/10 - Commande par programme pour dispositifs périphériques
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
27.
Calibration of Sine-Cosine Coil Mismatches in Inductive Sensors
An apparatus includes a sampling circuit to sample input from a sensor circuit. The input includes a cosine coil waveform and a sine coil waveform. The sampling circuit is to generate a cosine coil sampled data stream and a sine coil sampled data stream. The apparatus includes an adjustment circuit to, based upon a characterization of the sensor circuit, delay the cosine coil sampled data stream or the sine coil sampled data stream.
G01D 18/00 - Test ou étalonnage des appareils ou des dispositions prévus dans les groupes
G01D 5/20 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensible; Moyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminé; Transducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension en faisant varier l'inductance, p.ex. une armature mobile
G01B 7/00 - Dispositions pour la mesure caractérisées par l'utilisation de techniques électriques ou magnétiques
28.
REDUCING ERROR IN ESTIMATED ANGULAR POSITION OF A ROTOR OF A MOTOR
An EtherCAT device is disclosed. The EtherCAT device comprises a data input port to receive a signal representing data, the signal representing one of a plurality of possible logical values; and a degradation calculation circuit. The degradation calculation circuit is to read, demodulate, and convert the received signal into a digital domain representation; process the digital domain representation into slices, where the value of the received signal at a respective time is represented in a respective one of the slices; determine differences between the respective slices and reference slices; identify an intended logical value of the received signal responsive to the determined differences; determine a quantification of error at the respective time responsive to the identified logical value and the determined differences; and determine a signal quality index responsive to the determined quantification of error.
Object detection for wireless power transmitters and related systems, methods, and devices are disclosed. A controller for a wireless power transmitter is configured to receive a measurement voltage potential responsive to a tank circuit signal at a tank circuit, provide an alternating current (AC) signal to each of the plurality of transmit coils one at a time, and determine at least one of a resonant frequency and a quality factor (Q-factor) of the tank circuit responsive to each selected transmit coil of the plurality of transmit coils. The controller is also configured to select a transmit coil to use to transmit wireless power to a receive coil of a wireless power receiver responsive to the determined at least one of the resonant frequency and the Q-factor for each transmit coil of the plurality of transmit coils.
H02J 50/60 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique sensibles à la présence d’objets étrangers, p.ex. détection d'êtres vivants
H02J 50/12 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage inductif du type couplage à résonance
H02J 50/40 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant plusieurs dispositifs de transmission ou de réception
G01R 27/26 - Mesure de l'inductance ou de la capacitance; Mesure du facteur de qualité, p.ex. en utilisant la méthode par résonance; Mesure de facteur de pertes; Mesure des constantes diélectriques
31.
EtherCAT Device with Clock Generation Mode and Clock Propagation Mode
An EtherCAT device with a node for use in an EtherCAT network is disclosed. The EtherCAT device includes: a clock circuit; a clock input to receive an input clock signal; a clock output to send an output clock signal; and control logic. The control logic is to determine whether to operate the EtherCAT device in a clock generation mode or a clock propagation mode, wherein in the clock generation mode, the clock circuit is to drive an oscillator to generate the input clock signal; and in the clock propagation mode, the clock circuit is to receive the input clock signal from another node in the EtherCAT network. The control logic is further to control the clock circuit to output the output clock signal for a subsequent node in the EtherCAT network based upon the input clock signal.
A charge pump cell for a charge pump is disclosed that may exhibit improved latch-up immunity. A circuit may be arranged at the charge pump cell to apply a voltage to a bulk contact of a charge transfer transistor of such a charge pump cell at least partially responsive to a relationship between a voltage at a first terminal of the charge transfer transistor and a voltage at a second terminal of the charge transfer transistor. A charge pump including one or more such charge pump cells may include a control loop that is configured to control a pumping signal at least partially responsive to a state of an output voltage of the charge pump.
H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p.ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
33.
PARALLELED TRANSISTOR CELLS OF POWER SEMICONDUCTOR DEVICES
An apparatus is disclosed that includes a common drain, a common source, and a common gate, respectively, of the power semiconductor device, and paralleled transistor cells of the power semiconductor device. In various examples, a configuration of a gate structure of a first respective transistor cell coupled with the common gate is different than a configuration of a gate structure of a second respective transistor cell coupled with the common gate. Alternatively or additionally, in various examples, a configuration of a structure coupled between a first portion of the paralleled transistor cells and the common gate is different than a configuration of a structure coupled between the second portion of the paralleled transistor cells and the common gate.
H03K 3/012 - Modifications du générateur pour améliorer le temps de réponse ou pour diminuer la consommation d'énergie
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
34.
ELECTRONIC DEVICE INCLUDING ACCESS CONTROL IDENTIFIERS FOR CONTROLLING ACCESS TO PERIPHERALS
An electronic device includes a transaction host, a first peripheral, a second peripheral, a first access controller connected to the first peripheral, a second access controller connected to the second peripheral, and an access control register storing a first access control identifier for the first peripheral and a second access control identifier for the second peripheral. The first access controller to receive an access request for access to the first peripheral by the transaction host, perform an access determination for the first peripheral based at least on the first access control identifier for the first peripheral, and allow or prevent the transaction host access to the first peripheral based on the access determination.
An apparatus and method including a command input to receive a command with a macro identifier from a channel processor, a macro memory storing a plurality of flash control commands, each comprising a duration and a plurality of target control values to control a flash target; and a second finite state machine comprising a plurality of control outputs each corresponding control inputs on the flash target, wherein in response to a received command, the first finite state machine locates in the macro memory a sequence of flash control commands associated with the macro identifier and sequentially outputs the flash control commands to the second finite state machine; and wherein the second finite state machine drives each of the plurality of control outputs based on corresponding values in the first flash control command for the duration specified in the current flash control command.
Some examples may relate to an object-recognition system. The object-recognition system may generate an object identifier when an object having detectable elements in a predetermined spatial pattern is in proximity to a capacitive sensor. The object-recognition system may include a capacitive sensor and a reader to capture channel-capacitance measurements at least partially responsive to the capacitive sensor in proximity of the detectable elements. The object-recognition system may include a recognizer to generate an object identifier at least partially responsive the captured channel-capacitance measurements.
G06F 3/044 - Numériseurs, p.ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction par des moyens capacitifs
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
G06F 3/041 - Numériseurs, p.ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction
37.
METAL-INSULATOR-METAL (MIM) CAPACITOR MODULE INCLUDING A CUP-SHAPED STRUCTURE WITH A ROUNDED CORNER REGION
A metal-insulator-metal (MIM) capacitor includes a bottom electrode cup, an insulator, and a top electrode. The bottom electrode cup includes a laterally-extending bottom electrode cup base and a bottom electrode cup sidewall extending upwardly from the laterally-extending bottom electrode cup base. The insulator includes an insulator cup formed in an opening defined by the bottom electrode cup, and a rounded insulator flange extending laterally outwardly and curving upwardly from the insulator cup, the rounded insulator flange covering an upper surface of the bottom electrode cup sidewall. The top electrode is formed in an opening defined by the insulator cup. The top electrode is insulated from the upper surface of the bottom electrode cup sidewall by the rounded insulator flange.
H01L 49/02 - Dispositifs à film mince ou à film épais
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
38.
METAL-INSULATOR-METAL (MIM) CAPACITOR INCLUDING AN INSULATOR CUP AND LATERALLY-EXTENDING INSULATOR FLANGE
A metal-insulator-metal (MIM) capacitor includes a bottom electrode cup, an insulator, and a top electrode. The bottom electrode cup includes a laterally-extending bottom electrode cup base and a bottom electrode cup sidewall extending upwardly from the laterally-extending bottom electrode cup base. The insulator includes an insulator cup formed in an opening defined by the bottom electrode cup, and an insulator flange extending laterally outwardly from the insulator cup sidewall and extending laterally over an upper surface of the bottom electrode cup sidewall. The top electrode is formed in an opening defined by the insulator cup. The top electrode is insulated from the upper surface of the bottom electrode cup sidewall by the insulator flange.
H01L 49/02 - Dispositifs à film mince ou à film épais
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
Examples may include an apparatus including a circuit coupled between a supply line, a return line, and a terminal. The circuit may provide an oscillating signal to the terminal. The circuit may include a first switch to couple the supply line with the terminal. The circuit may also include a second switch to couple the return line with the terminal. The circuit may also include a first inductor coupled between the first switch and the terminal. The circuit may also include a second inductor coupled between the second switch and the terminal. The circuit may also include a first diode coupled between the return line and an internal node of the first switch and the first inductor. The circuit may also include a second diode coupled between the supply line and an internal node of the second switch and the second inductor. Related systems and methods are also disclosed.
H02P 27/06 - Dispositions ou procédés pour la commande de moteurs à courant alternatif caractérisés par le type de tension d'alimentation utilisant une tension d’alimentation à fréquence variable, p.ex. tension d’alimentation d’onduleurs ou de convertisseurs utilisant des convertisseurs de courant continu en courant alternatif ou des onduleurs
H02M 7/537 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs, p.ex. onduleurs à impulsions à un seul commutateur
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
40.
CIRCUITRY FOR AUTONOMOUSLY MEASURING ANALOG SIGNALS AND RELATED SYSTEMS, METHODS, AND DEVICES
Analog signal measurement and related apparatus, systems, and methods are disclosed. Such an apparatus may include a signal analyzing circuitry to enable responsive to the assertion of the first enable signal, compare the amplified analog input signal to one or more threshold values responsive to the assertion of the second enable signal, and generate an alert signal responsive to a determination that the amplified analog input signal falls outside of the one or more threshold values.
An apparatus may comprise an off-chip data storage device and a semiconductor device package including processing circuitry and an on-chip memory device, the off-chip data storage device including master data and portions of the computer-readable instructions. The processing circuitry may retrieve a master data that includes a digital signature that may be used to verify the master data and a hash table that may include hash information for others of the portions. The processing circuitry may also verify the master instructions responsive to the digital signature, retrieve a portion, calculate a hash value of the retrieved portion, and determine whether the calculated hash value correlates to hash information of the hash table.
A computer system includes a non-transitory computer-readable memory to store (a) a vector table including an exception vector pointing to an exception handler and (b) a vector fail address of a vector fetch bus error handler, and a processor to identify an exception, initiate an exception vector fetch in response to the identified exception to read the exception vector from the vector table, identify a vector fetch bus error associated with the exception vector fetch, access the vector fail address of the vector fetch bus error handler in response to the vector fetch bus error, and execute the vector fetch bus error handler.
An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.
An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions. The instructions, when read and executed by a processor, cause the processor to determine that a first input instruction in a code stream to be executed is to perform a read-modify-write operation, determine that the first input instruction is to target a memory location, and, based on a determination that the first input instruction is to perform the read-modify-write operation and the determination that the first input instruction is to target the memory location, convert the first input instruction to a second input instruction to target the memory location with a mask to cause an atomic operation to implement the read-modify-write operation.
One or more examples relate, generally, to an apparatus. The apparatus includes a charged particle source and a charged particle pointer. The charged particle pointer urges charged particles emitted by the charged particle source in a predetermined direction. The charged particle pointer comprises a repeller, and an isolator positioned along a path extending from the repeller in the predetermined direction.
A system includes non-transitory computer readable memory and a processor. The non-transitory computer readable memory stores a current processor interrupt priority level and a current disable interrupt control (DISICTL) interrupt priority level. The processor to update the current processor interrupt priority level based on respective interrupt priority levels associated with respective exceptions, and update the current DISICTL interrupt priority level based on a respective DISICTL instruction, wherein the respective DISICTL instruction specifies a respective user-definable DISICTL interrupt priority level. The processor determines a highest interrupt priority level between the current processor interrupt priority level and the current DISICTL interrupt priority level, and apply the highest interrupt priority level during execution of respective code.
One or more examples relate to an apparatus includes an error detector, an oscillator, an analog proportional path, and a digital integral path. The oscillator includes an analog proportional input, a digital integral input, and an analog integral input. The analog proportional path to provide a control signal for the analog proportional input of the oscillator. The digital integral path to provide a control for the digital integral input and the analog integral input of the oscillator. A first signal path of an interface includes a direct coupling between the digital phase detector and integrator and the digital integral input of the oscillator. A second signal path of the interface includes a digital-to-analog converter (DAC) with a filtered delta-sigma modulator (DSM) input between the digital phase detector and integrator and the analog integral input of the oscillator.
H03L 7/099 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03L 7/091 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence utilisant un dispositif d'échantillonnage
An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.
A computer-implemented method is provided including instantiating an object of an analog information model object class definition defining a net interface to a digital circuit simulator, and a plurality of analog circuit properties. The method includes connecting the net interface of the data structure to a first net defined in a digital circuit simulation and identifying all other instances of the AIM object class definition connected to the first net defined in the digital circuit simulation of a simulated digital circuit and determining an analog voltage at and current through the first net based on the analog circuit properties of all instances connected to the first net.
G06F 30/367 - Vérification de la conception, p.ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
50.
Method and apparatus for carrying constant bit rate (CBR) client signals
A method and apparatus in which a data stream generated by a previous network node, a cumulative phase offset report (CPOR) and a client rate report (CRR) are received. A counter accumulating a PHY-scaled stream clock (IPSCk) is sampled at a nominal sampling period (Tps) to obtain a cumulative PHY-scaled count (CPSC). A PHY-scaled stream phase offset (PSPO) is calculated that indicates phase difference between a PHY-scaled stream nominal bit count (LPSD) and an incoming PHY-scaled count delta (IPSD), where IPSD indicates CPSC increment between successive CPSC samples. The data stream is demultiplexed to obtain CBR carrier streams that include a previous network node CPOR (CPOR-P) and a previous network node CPO (CPO-P). A CPO is calculated that is a function of CPO-P and the PSPO. CPO-P is replaced with the calculated CPO. The CBR carrier streams are multiplexed into intermediate-network-node data streams that are transmitted from the intermediate-network-node.
Systems and methods for monitoring copper corrosion in an integrated circuit (IC) device are disclosed. A corrosion-sensitive structure formed in the IC device may include a p-type active region adjacent an n-type active region to define a p-n junction space charge region. A copper region formed over the silicon may be connected to both the p-region and n-region by respective contacts, to thereby define a short circuit. Light incident on the p-n junction space charge region, e.g., during a CMP process, creates a current flow through the metal region via the short circuit, which drives chemical reactions that cause corrosion in the copper region. Due to the short circuit configuration, the copper region is highly sensitive to corrosion. The corrosion-sensitive structure may be arranged with less corrosion-sensitive copper structures in the IC device, with the corrosion-sensitive structure used as a proxy to monitor for copper corrosion in the IC device.
G01N 21/95 - Recherche de la présence de criques, de défauts ou de souillures caractérisée par le matériau ou la forme de l'objet à analyser
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 31/103 - Dispositifs sensibles au rayonnement infrarouge, visible ou ultraviolet caractérisés par une seule barrière de potentiel ou de surface la barrière de potentiel étant du type PN à homojonction
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
G01N 21/47 - Dispersion, c. à d. réflexion diffuse
G01N 21/88 - Recherche de la présence de criques, de défauts ou de souillures
H01L 31/02 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails - Détails
G01N 17/02 - Systèmes de mesure électro-chimique de l'action due aux intempéries, de la corrosion ou de la protection contre la corrosion
52.
SIMPLIFIED CURVATURE COMPENSATED BANDGAP USING ONLY RATIOED COMPONENTS
A curvature compensated bandgap circuit that is capable of matching best-in-class two (2) parts-per-million performance without over-temperature trimming. This improves performance metrics for precision voltage reference products without requiring individual device tuning during production thereof. A core bandgap circuit comprises a main operational amplifier having a second order bowed voltage response over temperature. A ptat circuit is coupled to the core bandgap circuit to provide a sigmoidal third order shape for the bandgap voltage.
G05F 3/22 - Régulation de la tension ou du courant là où la tension ou le courant sont continus utilisant des dispositifs non commandés à caractéristiques non linéaires consistant en des dispositifs à semi-conducteurs en utilisant des combinaisons diode-transistor dans lesquelles les transistors sont uniquement du type bipolaire
G05F 1/46 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu
53.
System and Method for a Storage Controller Card with Redundant Boot Storage
An storage controller and method for providing a respective first and a second solid-state memory interface to control a first and a second flash memory, a RAID controller coupled to the first and second solid-state memory interface, the RAID controller presenting a single boot device to a CPU and synchronizing writes to made to the boot device to both of the first and second solid-state memories, the RAID controller providing a plurality of data storage ports to be coupled to at least three data storage drives wherein the RAID controller is to present a unified data device to the CPU.
A flyback converter to receive an input voltage and provide an output voltage is provided, and may include a transformer having a primary winding and secondary winding, a primary switch coupled to the primary winding, a synchronous rectifier device coupled to the secondary winding, and a secondary side control circuit to turn on the synchronous rectifier device by outputting a control signal at a first amplitude, subsequently modify the control signal to maintain a voltage across the synchronous rectifier device substantially constant until a predicted time that precedes a current in the synchronous rectifier device reaching substantially zero, subsequently turn off the synchronous rectifier device based on the voltage across the synchronous rectifier device reaching substantially zero, and subsequently turn on the synchronous rectifier device by outputting the control signal at a second amplitude, before the primary switch is turned on. The second amplitude is less than the first amplitude.
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
H02M 1/00 - APPAREILS POUR LA TRANSFORMATION DE COURANT ALTERNATIF EN COURANT ALTERNATIF, DE COURANT ALTERNATIF EN COURANT CONTINU OU VICE VERSA OU DE COURANT CONTINU EN COURANT CONTINU ET EMPLOYÉS AVEC LES RÉSEAUX DE DISTRIBUTION D'ÉNERGIE OU DES SYSTÈMES D'ALI; TRANSFORMATION D'UNE PUISSANCE D'ENTRÉE EN COURANT CONTINU OU COURANT ALTERNATIF EN UNE PUISSANCE DE SORTIE DE CHOC; LEUR COMMANDE OU RÉGULATION - Détails d'appareils pour transformation
Vapor cells may include a body including a cavity within the body. A first substrate bonded to a second substrate at an interface within the body, at least one of the first substrate, the second substrate, or an interfacial material between the first and second substrates may define at least one recess or pore in a surface. A smallest dimension of the at least one recess or pore may be about 500 microns or less, as measured in a direction parallel to at least one surface of the first substrate partially defining the cavity.
G04F 5/14 - Appareils pour la production d'intervalles de temps prédéterminés, utilisés comme étalons utilisant des horloges atomiques
H03L 7/26 - Commande automatique de fréquence ou de phase; Synchronisation utilisant comme référence de fréquence les niveaux d'énergie de molécules, d'atomes ou de particules subatomiques
56.
System and Method for Enhancing Flash Channel Utilization
An apparatus and method for dispatching flash commands. The apparatus includes a plurality of queues, wherein each queue comprises an input to receive a flash command, an output to send a flash command, and an empty signal output to signal when the queue is empty, wherein each queue is assigned a unique, ordered priority. The apparatus includes a selector comprising a plurality of flash command inputs, a flash command output to a flash target, and a selection input, wherein each flash command input is coupled to a corresponding queue output. The apparatus includes an arbiter comprising inputs receiving each queue empty signal and receiving a lock bit from the flash command output of the selector and comprising a selection output coupled to the selection input of the selector. The flash command comprises a lock bit and a plurality of control bits to output to control inputs on a flash target.
G06F 12/02 - Adressage ou affectation; Réadressage
G06F 12/126 - Commande de remplacement utilisant des algorithmes de remplacement avec maniement spécial des données, p.ex. priorité des données ou des instructions, erreurs de maniement ou repérage
57.
System and Method for Flexibly Crossing Packets of Different Protocols
An apparatus and method coupling a first and a second data bus comprising selectors for routing first bus egress lanes to egress memories, each egress memory coupled to one second bus egress lane, where the second bus has more egress lanes than the first. Each egress memory corresponds to one second bus egress lane. A first FSM selecting which first bus egress lane to load into each egress memory synchronous with the first bus clock. A second FSM outputting egress memory values to the second bus synchronous with the second bus clock. A set of ingress memories, each memory coupled to one second bus ingress lane and to an input of each ingress selector. A third FSM loading the ingress memories synchronous with the second bus clock. A fourth FSM selecting which ingress memory to route to each first bus ingress lane synchronous with the first bus clock.
A system (e.g., NVMe controller) for managing access to a memory resource by multiple users may include memory storing function queue categorizations for function queues associated with each user, and circuitry to store and execute a multi-user arbitration algorithm that arbitrates access to the memory resource by the multiple users. The function queue categorizations assign a function category to each function queue associated with each user. The multi-user arbitration algorithm includes (a) selecting an intra-user winning function queue for each respective user by performing an intra-user function queue arbitration of the function queues associated with the respective user based on the function queue categorizations associated with the arbitrated function queues, (b) selecting an inter-user winning function queue by performing an inter-user function queue arbitration of the intra-user winning function queues selected for the multiple users, and (c) serving a function from the inter-user winning function queue to the memory resource.
A device includes an integrated inductor and metal interconnect formed in an integrated circuit (IC) structure. The integrated inductor includes an inductor wire having a portion defined by an inductor element stack including (a) a metal layer inductor element formed in a metal layer in the IC structure and (b) a multi-component via layer inductor element formed in a via layer in the IC structure vertically adjacent the metal layer, and conductively connected to the metal layer inductor element. The multi-component via layer inductor element includes a via layer inductor element cup-shaped component formed from a first metal, and a via layer inductor element fill component formed from a second metal in an opening defined by the via layer inductor element cup-shaped component. The metal interconnect includes a metal layer interconnect element formed in the metal layer, and an interconnect via formed in the via layer from the first metal.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01F 17/00 - Inductances fixes du type pour signaux
H01L 49/02 - Dispositifs à film mince ou à film épais
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
One or more examples relate, generally, to an orientation of a rotor. Some examples relate to an apparatus. The apparatus may include sample-accumulation logic to generate, over a time duration, a value indicative of inductance at least partially responsive to a probe signal provided to a stator of a motor. The apparatus may also include a probe-current discriminator to generate a further value indicative of an orientation of a rotor of the motor at least partially responsive to the generated value. The apparatus may also include update logic to update a process variable of a control loop at least partially responsive to a state of the further value.
A device includes (a) an integrated inductor having an inductor wire and (b) a metal interconnect arrangement, both formed in an integrated circuit layer stack of alternating metal layers and via layers. At least a portion of the inductor wire is defined by an inductor element stack including multiple metal layer inductor elements formed in multiple respective metal layers, and multiple via layer inductor elements formed in multiple respective via layers and conductively connected to the metal layer inductor elements. Each via layer inductor element has a length of at least 1 μm in each of two lateral directions orthogonal to each other and perpendicular to the vertical direction. The metal interconnect arrangement includes metal layer interconnect elements formed in the respective metal layers, and interconnect vias formed in the respective via layers.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01F 17/00 - Inductances fixes du type pour signaux
H01L 49/02 - Dispositifs à film mince ou à film épais
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
Examples disclosed herein relate generally to providing frames at a network port. Some examples relate to an apparatus. The apparatus may include a network port to directly couple the apparatus to a switch. The apparatus may also include a transmission logic to provide a frame at the network port at a time slot of a switch-associated cycle time. The transmission logic may provide the frame at the time slot at least partially responsive to an offset value and a port number. Related devices, systems and methods are also disclosed.
H04L 49/253 - Routage ou recherche de route dans une matrice de commutation en utilisant l'établissement ou la libération de connexions entre les ports
H04L 49/104 - Matrices de commutation pour mode de transfert asynchrone [ATM]
63.
DEVICES INCLUDING CAPACITOR COUPLING POWER PATH TO GROUND PATH AND ASSOCIATED COMPONENTS AND SYSTEMS
The device may include a core. The device may include built-up layers arranged over the core. The device may also include a ground path disposed in a first built-up layer of the built-up layers. The device may also include a power path disposed in a second built-up layer of the built-up layers. The device may also include a multi-terminal capacitor on a top layer of the built-up layers. The multi-terminal capacitor may be coupled to the ground path and the power path through respective vias passing through the built-up layers. The respective vias may be arranged to alternate such that respective vias coupled to the power path neighbor a respective via coupled to the ground path.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 49/02 - Dispositifs à film mince ou à film épais
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
A state machine motor controller (SMMC) interface comprises a plurality of states which defines a unique set of poles/motor phase/phases energized. Digital sensors capture the start of overlap of rotor poles with stator poles. The state change occurs when a rotor pole starts overlapping with a stator pole. The number of states depends on the number of phases and the design of the motor. The SMMC has up to four inputs to accept rotational information from digital sensors and can control motors having up to 16 states. A sequencer is used to keep track of state changes and provides a next state depending on forward/reverse direction setting and braking setting. A counter provides rotational speed based upon the number of clock pulses per time period for a state change. The sequencer checks for a faulty sensor(s) and generates a fault interrupt therefrom.
G05B 19/4155 - Commande numérique (CN), c.à d. machines fonctionnant automatiquement, en particulier machines-outils, p.ex. dans un milieu de fabrication industriel, afin d'effectuer un positionnement, un mouvement ou des actions coordonnées au moyen de données d'u caractérisée par le déroulement du programme, c.à d. le déroulement d'un programme de pièce ou le déroulement d'une fonction machine, p.ex. choix d'un programme
65.
COMUNICATION DEVICE AND SYSTEM WITH GROUND POTENTIAL DIFFERENCE COMPENSATION
A communication device for connection with a power source and a host device is provided. The communication device comprises a device controller and a converter circuit. The device controller is adapted for data communication with the host device and the converter circuit is configured to provide a virtual device ground at least to the device controller, so as to compensate a ground potential difference between the host device and the communication device.
A method and apparatus for embedding a microprocessor in a programmable logic device (PLD), where the microprocessor has a logic unit that can operate in two modes. A first mode is a general purpose mode running at least one general purpose process related to the PLD, and a second mode is a fixed function mode emulating a fixed function for use by logic configured into a fabric of the PLD (fabric). A memory unit is coupled to the logic unit and to the fabric, and the fabric is operable for transferring signals with the logic unit in relation to the fixed function.
A timing device includes an oven having a chamber, a crystal oscillator disposed in the chamber that generates a clock signal, and one or more sensors to generate operational characteristic signals indicative of respective operational characteristics of the crystal oscillator or the oven. The timing device includes a plurality of I/O connections and an IC device. The IC device includes processing logic to generate information that indicates how the generated clock signal is to be modified and a modulator coupled to the processing logic and the crystal oscillator. The modulator modulates the generated clock signal in relation to the information to generate a modulated clock signal indicative of the one or more operational characteristics of the crystal oscillator or the oven. The modulator outputs the modulated clock signal over a single one of the plurality of I/O connections.
H03B 5/36 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique l'élément actif de l'amplificateur comportant un dispositif semi-conducteur
H03K 19/173 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants
H03K 3/017 - Réglage de la largeur ou du rapport durée période des impulsions
H03B 5/04 - Modifications du générateur pour compenser des variations dans les grandeurs physiques, p.ex. alimentation, charge, température
68.
System and Method for Centralized Management of Workload and Parallel Service of Prioritized Requests
An apparatus and method for scheduling memory requests including receiving a plurality of requests having a type and associating each request of the received plurality of requests with a corresponding target, which is associated with one channel of a plurality of channels. The method assigning a priority to each request, assigning a utilization cost to each request based on the request’s target and request type, and queueing each request of the plurality of requests for scheduling. The method selecting a first request of the received plurality of requests to be scheduled based on its priority, scheduling the first request for processing at a time when the first request utilization cost is less than or equal to a current value of a dynamic utilization counter, and debiting the dynamic utilization counter by the first request utilization cost.
An electronic device includes a first interposer, a first integrated circuit (IC) device affixed to the first interposer, a second interposer, and a second IC device affixed to the second interposer. he second interposer is bonded to the first interposer. The first interposer includes first interposer circuitry and a first connection element electrically connected to the first interposer circuitry. The second interposer includes second interposer circuitry and a second connection element electrically connected to the second interposer circuitry. The second connection element is bonded to the first connection element to define a connection element pair. The connection element pair provides an electrical connection between the first interposer circuitry and the second interposer circuitry.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/10 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs ayant des conteneurs séparés
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
An apparatus comprising: a support structure; and a first electrically-conductive material arranged at the support structure to define a first continuous path for first electrical current to flow between a first location and a second location, the first continuous path comprising: a first path portion defining a first generally-clockwise path for the first electrical current to flow around a first axis, the first path portion including a first inner-circumferential portion and a first outer-circumferential portion, the first inner-circumferential portion located closer to a central axis than the first outer-circumferential portion, a radius of curvature of the first inner-circumferential portion being greater than a radius of curvature of the first outer-circumferential portion; and a second path portion defining a first generally-counter-clockwise path for the first electrical current to flow around a second axis, the first path portion and the second path portion circumferentially arranged around the central axis. Related devices, systems and methods are also disclosed.
G01D 5/22 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensible; Moyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminé; Transducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension en faisant varier l'inductance, p.ex. une armature mobile influençant deux bobines par une action différentielle
A three-dimensional metal-insulator-metal (MIM) capacitor is formed in an integrated circuit structure. The 3D MIM capacitor may include a bottom conductor including a bottom plate portion (e.g., formed in a metal interconnect layer) and vertically-extending sidewall portions extending from the bottom plate portion. An insulator layer is formed on the bottom plate portion and the vertically extending sidewall portions of the bottom conductor. A top conductor is formed over the insulating layer, such that the top conductor is capacitively coupled to both the bottom plate portion and the vertically extending sidewall portions of the bottom conductor, to thereby define an increased area of capacitive coupling between the top and bottom conductors. The vertically extending sidewall portions of the bottom conductor may be formed in a single metal layer or by components of multiple metal layers.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/52 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 49/02 - Dispositifs à film mince ou à film épais
72.
Method and Apparatus for Decoding with Trapped-Block Management
A method and apparatus for decoding in which a first failed decode operation is performed on raw bit values of a FEC block by a LDPC decoder. When the FEC block is determined to be a trapped block an updated LLR map is generated; the updated LLR map and either the raw bit values of the FEC block or a failed-decode-output-block from a previous failed decode operation on the trapped block are provided to the LDPC decoder; a decode operation of the LDPC decoder is performed using the updated LLR map on the bit values of the FEC block or the failed-decode-output-block from the previous failed decode operation; and the generating, the providing and the performing are repeated until the decode operation is successful or until a predetermined number of trapped-block-decoding iterations have been performed. When the decode operation is successful in decoding the FEC block the codeword is output.
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
73.
INTEGRATED CIRCUIT PACKAGE MODULE INCLUDING A BONDING SYSTEM
An integrated circuit package module includes an integrated circuit package device including a contact element, and a bonding system formed on the integrated circuit package device. The bonding system includes a bonding system substrate and a bonding element formed in the bonding system substrate and conductively coupled to the contact element of the integrated circuit package device. The bonding element includes (a) a conduction component conductively connected to the contact element, the conduction component formed from a first metal having a first melting point, and (b) a bonding component formed from a second metal having a second melting point lower than the first melting point of the first metal.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
74.
Introduction and Detection of Erroneous Stop Condition in a Single UART
A universal asynchronous receiver/transmitter includes a transmission register to include information to be transmitted, a receive register to include information received, a frame error checking circuit to evaluate contents of the receive register for a frame error, and control logic. The control logic is to route the contents of the transmission register to the receive register. The control logic is to, during transmission of the contents of the transmission register through the reprogrammable pin to the receive register, modify a bit inversion register to yield modified contents to be provided to the receive register. The modified contents are to cause a frame error. The control logic is to determine whether the frame error checking circuit detected the frame error.
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
75.
CHANGING CARRIER SENSE SIGNAL GENERATED BY A RECONCILIATION SUBLAYER OF A PHYSICAL LAYER THAT MAY CAUSE UNINTENDED SIGNALING AT A REDUCED MEDIA INDEPENDENT INTERFACE (RMII)
On or more examples relate, generally, to an apparatus that includes a reconciliation sublayer of a physical layer, a reduced media independent interface (RMII) of the physical layer, and a logic circuit. Such a logic circuit may operate to receive a changed carrier sense signal provided by the reconciliation sublayer, generate a further changed carrier sense signal at least partially responsive to a prediction that the changed carrier sense signal would cause unintended signaling at the RMII, and provide the further changed carrier sense signal to the RMII.
H04W 74/08 - Accès non planifié, p.ex. accès aléatoire, ALOHA ou accès multiple par détection de porteuse [CSMA Carrier Sense Multiple Access]
H04L 7/02 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière
H04L 69/324 - Protocoles de communication intra-couche entre entités paires ou définitions d'unité de données de protocole [PDU] dans la couche liaison de données [couche OSI 2], p.ex. HDLC
H04L 47/62 - Ordonnancement des files d’attente caractérisé par des critères d’ordonnancement
H04L 69/32 - Architecture des piles de protocoles du type interconnexion de systèmes ouverts en 7 couches, p.ex. interfaces entre le niveau liaison et le niveau physique
76.
WAKE SOURCE COMMUNICATION ACCORDING TO 10SPE LOCAL AND REMOTE WAKE AND RELATED SYSTEMS, METHODS, AND DEVICES
One or more examples relate, generally, to an apparatus. Such an apparatus includes a digital interface, a wake detect logic, and a power management connection. The digital interface may define a physical layer transceiver side of a connection between a physical layer transceiver and a physical layer controller, respectively of a 10SPE physical layer. The wake detect logic may communicate a source of detected wake from the physical layer transceiver to the physical layer controller via the digital interface. The power management connection may operatively couple to an enable connection of a switched voltage regulator.
An integrated circuit structure including a metal-insulator-metal (MIM) capacitor module and a thin-film resistor (TFR) module is provided. The MIM capacitor module includes a bottom electrode base formed in a lower metal layer, a bottom electrode formed in a dielectric region between the lower metal layer and an upper metal layer, an insulator formed over the bottom electrode, and a top electrode formed in the upper metal layer over the insulator. The bottom electrode includes a cup-shaped bottom electrode component and a bottom electrode fill component formed in an interior opening defined by the cup-shaped bottom electrode component. The TFR module includes a pair of metal heads formed in the dielectric region and a resistor element connected across the pair of metal heads. Each metal head includes a cup-shaped head component and a head fill component formed in an interior opening defined by the cup-shaped head component.
H01L 27/01 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant uniquement des éléments à film mince ou à film épais formés sur un substrat isolant commun
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
78.
Method of forming a metal-insulator-metal (MIM) capacitor
A method of forming a metal-insulator-metal (MIM) capacitor with copper top and bottom plates may begin with a copper interconnect layer (e.g., Cu MTOP) including a copper structure defining the capacitor bottom plate. A passivation region is formed over the bottom plate, and a wide top plate opening is etched in the passivation region, to expose the bottom plate. A dielectric layer is deposited into the top plate opening and onto the exposed bottom plate. Narrow via opening(s) are then etched in the passivation region. The wide top plate opening and narrow via opening(s) are concurrently filled with copper to define a copper top plate and copper via(s) in contact with the bottom plate. A first aluminum bond pad is formed on the copper top plate, and a second aluminum bond pad is formed in contact with the copper via(s) to provide a conductive coupling to the bottom plate.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 49/02 - Dispositifs à film mince ou à film épais
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
A metal-insulator-metal (MIM) capacitor module is provided. The MIM capacitor module includes a bottom electrode base formed in a lower metal layer, a bottom electrode conductively coupled to the bottom electrode base, a planar insulator formed over the bottom electrode, and a top electrode formed in an upper metal layer over the insulator. The bottom electrode includes a cup-shaped bottom electrode component and a bottom electrode fill component formed in an interior opening defined by the cup-shaped bottom electrode component.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 49/02 - Dispositifs à film mince ou à film épais
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
80.
INTEGRATED CIRCUIT PACKAGE WITH HEAT TRANSFER CHIMNEY INCLUDING THERMALLY CONDUCTIVE NANOPARTICLES
An electronic device includes an integrated circuit package including a die mounted on a die carrier, a mold structure at least partially encapsulating the mounted die, and a heat transfer chimney formed on the die. The heat transfer chimney extends at least partially through the mold structure to transfer heat away from the die. The heat transfer chimney is formed from a thermally conductive compound including thermally conductive nanoparticles.
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/552 - Protection contre les radiations, p.ex. la lumière
H01L 23/29 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par le matériau
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
Some examples disclosed herein include a method. The method may include determining a relationship between a property of a position, navigation, and timing (PNT)-based timing signal and a property of a virtual time source. The method may also include determining a state of the PNT-based timing signal at least partially responsive to the determined relationship. The method may also include one or more of: providing the PNT-based timing signal at least partially responsive to determining that the state of the PNT-based timing signal corresponds to a first state, disregarding the PNT-based timing signal at least partially responsive to determining that the state of the timing signal corresponds to a second state, and providing an indication of the state of the PNT-based timing signal at least partially responsive to determining that the state of the timing signal corresponds to a second state. Related devices, systems and methods are also disclosed.
G01S 19/05 - Systèmes de positionnement par satellite à radiophares émettant des messages horodatés, p.ex. GPS [Système de positionnement global], GLONASS [Système global de navigation par satellite] ou GALILEO Éléments coopérants; Interaction ou communication entre les différents éléments coopérants ou entre les éléments coopérants et les récepteurs fournissant des données d'assistance
G01S 19/25 - Acquisition ou poursuite des signaux émis par le système faisant intervenir des données d'assistance reçues en provenance d'un élément coopérant, p.ex. un GPS assisté
A method of forming a via is provided. A lower metal element is formed, and a first patterned photoresist is used to form a sacrificial element over the lower metal element. A dielectric region including a dielectric element projection extending upwardly above the sacrificial element is formed. A second patterned photoresist including a second photoresist opening is formed, wherein the dielectric element projection is at least partially located in the second photoresist opening. A dielectric region trench opening is etched in the dielectric region. The sacrificial element is removed to define a via opening extending downwardly from the dielectric region trench opening. The dielectric region trench opening and the via opening are filled to define (a) an upper metal element in the dielectric region trench opening and (b) a via in the via opening, wherein the via extends downwardly from the upper metal element.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
83.
INDUCTIVE ANGULAR-POSITION SENSORS, AND RELATED DEVICES, SYSTEMS, AND METHODS
Examples disclosed herein relate generally to inductive angular-position sensors. An example apparatus may include a support structure, a first inductive angular-position sensor, a second inductive angular-position sensor, and a shield. The first inductive angular-position sensor may include a respective first sense coil arranged at a first portion of the support structure. The respective first sense coil may at least partially circumscribe an axis. The second inductive angular-position sensor may include a respective first sense coil arranged opposite the first sense coil of the first inductive angular-position sensor at a second portion of the support structure. The first sense coil of the first inductive angular-position sensor may at least partially circumscribe the axis. The shield may be arranged between the first sense coil of the first inductive angular-position sensor and the first sense coil of the second inductive angular-position sensor.
G01B 7/30 - Dispositions pour la mesure caractérisées par l'utilisation de techniques électriques ou magnétiques pour tester l'alignement des axes
G01D 5/20 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensible; Moyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminé; Transducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension en faisant varier l'inductance, p.ex. une armature mobile
84.
DETERMINING ALLOCATION OF LANES OF A PERIPHERAL-COMPONENT INTERCONNECT-EXPRESS PORT TO LINKS
Examples disclosed herein include a method including transmitting, via respective lanes of a number of lanes of a peripheral component interconnect express (PCIe) port, a respective lane identifier. The method may also include receiving, via the respective lanes of the number of lanes of the PCIe port, respective further lane identifiers. The method may also include determining which of the number of lanes to allocate to a link for communicating with a device coupled to the PCIe port at least partially responsive to the respective further lane identifiers. The method may also include allocating the determined lanes of the number of lanes to the link. Related devices and systems are also disclosed.
G06F 13/22 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le balayage successif, p.ex. l'appel sélectif
A feedback mechanism about a state of a transmission of a packet over a wireless medium is disclosed. In one or more examples, a wireless stack determines a state of a transmission of wireless packets that correspond to the network packet and infers a state of transmission of the network packet based on such a determination. The wireless stack informs a network stack about the state of transmission of the network packet.
An operational amplifier includes a pre-amplifier circuit, a first trim circuit, and a second trim circuit. The pre-amplifier circuit is to include a differential pair and receive an input voltage. The first trim circuit is to produce an offset voltage correction current and provide the offset voltage correction current to the pre-amplifier circuit to correct an offset of the operational amplifier. The second trim circuit is to produce a common mode voltage (VCM) correction current, provide the VCM voltage correction current to the pre-amplifier circuit, and cause the VCM correction current to have a non-zero value to reduce a correction caused by the offset voltage correction current when the input voltage is within a mid voltage input range. The pre-amplifier circuit is to apply the offset correction current and the VCM correction current to output signals of the differential pair.
Various examples may include an apparatus including a memory to store ingressing data or egressing data, a timer to generate a timing signal responsive to a user-configurable time interval, and a circuit to move the ingressing data or the egressing data from the memory at least partially responsive to the timing signal generated by the timer. Various examples may include a method including receiving a data packet at a network-facing interface, writing data of the data packet into a memory, receiving a timing signal, and responsive to the timing signal, providing the data from the memory at a device-facing interface. Various examples may include a method including receiving data at a device-facing interface, writing the data to a memory, receiving a timing signal, and responsive to the timing signal, providing a data packet including the data at a network-facing interface. Related devices, systems and methods are also disclosed.
Foreign object detection for wireless power transmission and related systems, methods, and devices are disclosed. A controller for a wireless power transmitter is to determine a transmit coil voltage potential at a transmit coil of the wireless power transmitter, determine an input power provided to the wireless power transmitter, determine a transmitter power loss, and determine a transmitted power of the wireless power transmitted to the wireless power receiver based, at least in part, on the input power and the transmitter power loss. The controller is also to compute a power loss responsive to the transmitted power and a received power indicated by the wireless power receiver, and determine that a foreign object is detected responsive to a determination that the power loss is greater than a predetermined threshold.
H02J 50/60 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique sensibles à la présence d’objets étrangers, p.ex. détection d'êtres vivants
H02J 50/10 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage inductif
H02J 50/40 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant plusieurs dispositifs de transmission ou de réception
Various examples relate to adjustable light sources. An example may include an apparatus including a light source to adjustably emit light toward a region of interest at least partially responsive to a control signal. The apparatus may also include a sensor to generate a signal indicative of an intensity of light sensed by the sensor in the region of interest. The apparatus may also include a wireless-communication equipment to broadcast a value that represents the intensity of light received by the sensor. The wireless-communication equipment may also receive a broadcast of a further value that represents an intensity of light in a further region of interest. The apparatus may also include a processor to adjust the control signal at least partially responsive to the further value. Related devices, systems and methods are also disclosed.
A controller for a motor system includes an input terminal to receive a signal indicating a speed of an electric motor and a regenerative brake current interpolator to indicate a brake current to be applied to the electric motor responsive to the speed of the electric motor. Values of the brake current vary with variation of the speed of the electric motor.
A system for managing a virtual meeting (e.g., video conference) includes memory storing a video conference application and at least one processor to execute the video conference application to generate a virtual meeting view for a first attendee including multiple attendee video streams arranged according to a virtual attendee arrangement specifying positions of the attendee video streams relative to each other in the virtual meeting view, receive second attendee audio data associated with a second attendee video stream, identify a particular video stream position specified by the virtual attendee arrangement, determine differential stereo effect data corresponding with the particular video stream position, and apply the differential stereo effect data to the second attendee audio data to provide differential audio signals on different audio channels output to the first attendee to create a stereo sound effect corresponding with the particular video stream position.
H04L 12/18 - Dispositions pour la fourniture de services particuliers aux abonnés pour la diffusion ou les conférences
H04N 21/431 - Génération d'interfaces visuelles; Rendu de contenu ou données additionnelles
H04N 21/439 - Traitement de flux audio élémentaires
H04N 21/44 - Traitement de flux élémentaires vidéo, p.ex. raccordement d'un clip vidéo récupéré d'un stockage local avec un flux vidéo en entrée ou rendu de scènes selon des graphes de scène MPEG-4
H04N 21/4788 - Services additionnels, p.ex. affichage de l'identification d'un appelant téléphonique ou application d'achat communication avec d'autres utilisateurs, p.ex. discussion en ligne
92.
TEMPERATURE SENSOR INTEGRATED IN A TRANSISTOR ARRAY
A temperature sensor integrated in a transistor array, e.g., metal-oxide-semiconductor field-effect transistor (MOSFET) array, is provided. The integrated temperature sensor may include a doped well region formed in a substrate (e.g., SiC substrate), a resistor gate formed over the doped well region, first and second sensor terminals conductively coupled to the doped well region on opposite sides of the resistor gate. The integrated temperature sensor includes a gate driver to apply a voltage to the resistor gate that affects a resistance of the doped well region below the resistor gate, and temperature analysis circuitry to determine a resistance of a conductive path passing through the doped well region, and determine a temperature associated with the transistor array.
G01K 7/16 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments résistifs
G01K 7/01 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments semi-conducteurs à jonctions PN
An integrated circuit device includes an anti-fuse device. The anti-fuse device includes a cup-shaped bottom anti-fuse electrode, a cup-shaped anti-fuse insulator formed in an opening defined by the cup-shaped bottom anti-fuse electrode, and a top anti-fuse electrode formed in an opening defined by the cup-shaped anti-fuse insulator. A thickness of the cup-shaped anti-fuse insulator is less than 200 Å.
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
A damascene method for manufacturing a thin film resistor (TFR) module is provided. A pair of heads are formed spaced apart from each other. A dielectric region is deposited over the pair of heads, and an opening extending over both heads is formed in the dielectric region. A TFR layer is deposited over the dielectric region and extending into the opening to define a cup-shaped TFR layer structure including (a) a laterally-extending TFR element base conductively connected to both heads and (b) vertical ridges extending upwardly from the laterally-extending TFR element base. A high density plasma (HDP) ridge removal process is performed to remove or shorten the vertical ridges from the cup-shaped TFR layer structure, thereby defining a TFR element having removed or shorted vertical ridges. The removal or shortening of the vertical ridges may improve the temperature coefficient of resistance (TCR) characteristic of the TFR element.
H01C 7/00 - Résistances fixes constituées par une ou plusieurs couches ou revêtements; Résistances fixes constituées de matériau conducteur en poudre ou de matériau semi-conducteur en poudre avec ou sans matériau isolant
H01C 17/232 - Ajustement du coefficient de température; Ajustement de la valeur de la résistance par ajustement du coefficient de température
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01C 17/12 - Appareils ou procédés spécialement adaptés à la fabrication de résistances adaptés pour déposer en couche le matériau résistif sur un élément de base par des techniques de film mince par pulvérisation
H01L 49/02 - Dispositifs à film mince ou à film épais
95.
Techniques for controlling vapor pressure of subject materials in vapor cells and related methods
Methods of using vapor cells may involve providing a vapor cell including a body defining a cavity within the body. At least a portion of at least one surface of the vapor cell within the cavity may include at least one pore having an average dimension of about 500 microns or less, as measured in a direction parallel to the at least one surface. A vapor pressure of a subject material within the cavity may be controlled utilizing the at least one pore by inducing an exposed surface of a subject material in a liquid state within the at least one pore to have a shape different than a shape the exposed surface of the subject material in a liquid state would have on a flat, nonporous surface.
H03L 7/26 - Commande automatique de fréquence ou de phase; Synchronisation utilisant comme référence de fréquence les niveaux d'énergie de molécules, d'atomes ou de particules subatomiques
G04F 5/14 - Appareils pour la production d'intervalles de temps prédéterminés, utilisés comme étalons utilisant des horloges atomiques
G05D 16/04 - Commande de la pression d'un fluide sans source d'énergie auxiliaire
96.
SECURE BOOT ASSIST FOR DEVICES, AND RELATED SYSTEMS, METHODS AND DEVICES
Systems, methods, and devices of the disclosure relate, generally, to secure boot assist for devices. In one or more embodiments, a first device includes firmware that needs to be verified as secure as part of a secure boot process, and a second device assists the first device to secure the secure boot process. In some embodiments the second device verifies security of the firmware responsive to security data provided by the first device, or verifies security of a program provided by the first device, the program for verifying security of the firmware. In some embodiments the second device provides a program for verifying security of the firmware to the first device.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 21/34 - Authentification de l’utilisateur impliquant l’utilisation de dispositifs externes supplémentaires, p.ex. clés électroniques ou cartes à puce intelligentes
97.
Introduction and Detection of Parity Error in a UART
A UART includes a transmission register, a receive register, a virtual remappable pin, a parity error check circuit to evaluate contents of the receive register for a parity error, and control logic to determine contents of the transmission register. The contents include underlying data and a parity bit based thereupon. The control logic is to route the contents through the first virtual remappable pin to the receive register. The control logic is to, before reception of the entire contents at the receive register, cause modified contents to be provided to the receive register. The modified contents are to cause a parity error. The modified contents are to include different underlying data or a different parity bit than the contents of the transmission register. The control logic is to determine whether the parity error check circuit detected the parity error.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
98.
PROVIDING A DRIVEN SHIELD DURING CAPACITANCE MEASUREMENT
One or more examples of the present disclosure relate generally to systems and methods for canceling mutual capacitive effects in a capacitance measurement. Some examples relate to providing a driven shield during capacitance measurement. Some examples relate to providing such a driven shield using rail-to-rail voltage.
A CAN bus transmitter has an input to receive a transmit data signal, and CANH and CANL outputs coupled to a CAN bus. The CAN bus transmitter comprises a plurality of CAN driver circuits having inputs coupled through delay circuits with their CANH and CANL outputs in common and connected to the CAN bus. Matching of Cgs capacitances between devices of the CANH and CANL legs provides substantially synchronized changes in the CANH and CANL output logic levels upon a change in the input logic level. Variable delaying of the input logic level changes to each of the plurality of CAN driver circuits reduces emission of unwanted signals from the CAN bus.
H03K 19/003 - Modifications pour accroître la fiabilité
H03K 19/096 - Circuits synchrones, c. à d. circuits utilisant des signaux d'horloge
H03K 19/094 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des dispositifs à semi-conducteurs utilisant des transistors à effet de champ
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
H03K 19/17784 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels pour l'adaptation des paramètres physiques pour la tension d'alimentation
H03K 19/17736 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels des ressources de routage
100.
SYSTEM AND METHOD FOR PERFORMING RATE ADAPTATION OF CONSTANT BIT RATE (CBR) CLIENT DATA WITH A FIXED NUMBER OF IDLE BLOCKS FOR TRANSMISSION OVER A METRO TRANSPORT NETWORK (MTN)
A system and method for performing rate adaptation of constant bit rate (CBR) client data for transmission over a Metro Transport Network (MTN) by defining a plurality of pseudo-Ethernet packets at a source node, assembling a plurality of Generic Mapping Procedure (GMP) frames by mapping a plurality of blocks from a stream of encoded blocks of CBR client data, a plurality of pad blocks, and GMP overhead into consecutive pseudo-Ethernet packets of the plurality of pseudo-Ethernet packets, inserting a fixed number of idle blocks between one or more of the consecutive pseudo-Ethernet packets and inserting an MTN path overhead (POH) frame that is aligned to the plurality of GMP frames to generate a plurality of rate adapted GMP frames for transmission over the MTN to an intermediate node or a sink node.
H04J 3/16 - Systèmes multiplex à division de temps dans lesquels le temps attribué à chacun des canaux au cours d'un cycle de transmission est variable, p.ex. pour tenir compte de la complexité variable des signaux, pour adapter le nombre de canaux transmis
H04J 3/07 - Dispositions de synchronisation utilisant le bourrage d'impulsions pour les systèmes à débits d'informations différents ou variables
H04J 3/12 - Dispositions pour produire les signaux d'appel ou de surveillance
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