NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Huang, Tse-Yao
Abrégé
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including an array area and a peripheral area; and a peripheral gate structure including: a peripheral gate dielectric layer inwardly positioned in the peripheral area of the substrate and including a U-shaped cross-sectional profile; a peripheral gate conductor including a bottom portion positioned on the peripheral gate dielectric layer and a neck portion positioned on the bottom portion; and a peripheral gate capping layer positioned on the peripheral gate dielectric layer and the bottom portion, and surrounding the neck portion. A top surface of the peripheral gate capping layer and a top surface of the neck portion are substantially coplanar.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Huang, Tse-Yao
Abrégé
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including an array area and a peripheral area; and a peripheral gate structure including: a peripheral gate dielectric layer inwardly positioned in the peripheral area of the substrate and including a U-shaped cross-sectional profile; a peripheral gate conductor including a bottom portion positioned on the peripheral gate dielectric layer and a neck portion positioned on the bottom portion; and a peripheral gate capping layer positioned on the peripheral gate dielectric layer and the bottom portion, and surrounding the neck portion. A top surface of the peripheral gate capping layer and a top surface of the neck portion are substantially coplanar.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Chiu, Hsih-Yang
Abrégé
An electronic fuse device includes a substrate, an insulating layer on the substrate, a first fuse gate, a first pass gate, and a first readout electrode. The substrate includes a first doping region, a second doping region, and a third doping region having a first conductivity type, and a highly doped region having a second conductivity type different from the first conductivity type. The first doping region is between the second doping region and the highly doped region. The second doping region is between the first doping region and the third doping region. The first fuse gate is on the insulating layer and between the first doping region and the second doping region. The first pass gate is on the insulating layer and between the second doping region and the third doping region. The first readout electrode is electrically connected to the third doping region.
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
H01L 23/62 - Protection contre l'excès de courant ou la surcharge, p.ex. fusibles, shunts
4.
SEMICONDUCTOR DEVICE STRUCTURE WITH PATTERNS HAVING COPLANAR BOTTOM SURFACES AND METHOD FOR PREPARING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Chou, Liang-Pin
Abrégé
A semiconductor device structure includes a first hard mask pattern disposed over a metal layer. The semiconductor device structure also includes a second hard mask pattern disposed over the metal layer and spaced apart from the first hard mask pattern. A bottom surface of the first hard mask pattern is coplanar with a bottom surface of the second hard mask pattern.
H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
5.
SEMICONDUCTOR DEVICE STRUCTURE WITH PATTERNS HAVING COPLANAR BOTTOM SURFACES AND METHOD FOR PREPARING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Chou, Liang-Pin
Abrégé
A semiconductor device structure includes a first hard mask pattern disposed over a metal layer. The semiconductor device structure also includes a second hard mask pattern disposed over the metal layer and spaced apart from the first hard mask pattern. A bottom surface of the first hard mask pattern is coplanar with a bottom surface of the second hard mask pattern.
H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
6.
SEMICONDUCTOR DEVICE AND A METHOD FOR FILM DEPOSITION
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Liu, Ji-Feng
Abrégé
A semiconductor device and a method and tool for film deposition are provided. The method of film deposition includes holding a semiconductor device in a chamber by a holding component, wherein the chamber is defined by a showerhead and a pedestal, providing reacting gases by the showerhead from a bottom side of the chamber, and forming a first dielectric layer on a backside surface of the semiconductor device.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Yang, Wu-Der
Abrégé
An electronic device and a method of controlling an electronic device are provided. The electronic device includes a first transistor having a first resistor, second resistor, first transistor, and second transistor. The second resistor is connected to the first resistor. The first transistor is connected to the first resistor in parallel and has a first bulk. The second transistor is connected to the second resistor in parallel and has a second bulk. The first bulk of the first transistor receives a first voltage and the first bulk of the second transistor receives a second voltage. The first voltage and the second voltage are different.
G05F 1/46 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu
G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Liu, Ji-Feng
Abrégé
A method and a tool for film deposition are provided. The method of film deposition includes holding a semiconductor device in a chamber by a holding component, wherein the chamber is defined by a showerhead and a pedestal, providing reacting gases by the showerhead from a bottom side of the chamber, and forming a first dielectric layer on a backside surface of the semiconductor device.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Kuan, Shih-Fan
Fan, Hsu-Cheng
Wang, Jiann-Jong
Lin, Chung-Hsin
Lin, Yu-Ting
Abrégé
A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a substrate, a word line, a first capacitor, a second capacitor, a first bit line and a second bit line. The word line is disposed on the substrate and extends along a first direction. The first capacitor extends along a second direction different from the first direction and is located at a first level. The second capacitor extends along the second direction and is located at a second level different from the first level. The first bit line is electrically connected to the first capacitor and the word line. The second bit line is electrically connected to the second capacitor and the word line.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Kuan, Shih-Fan
Fan, Hsu-Cheng
Wang, Jiann-Jong
Lin, Chung-Hsin
Lin, Yu-Ting
Abrégé
A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a word line, a first capacitor, a second capacitor, a first bit line and a second bit line. The word line is disposed on the substrate and extends along a first direction. The first capacitor extends along a second direction different from the first direction and is located at a first level. The second capacitor extends along the second direction and is located at a second level different from the first level. The first bit line is electrically connected to the first capacitor and the word line. The second bit line is electrically connected to the second capacitor and the word line.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Chen, Chien Yu
Hsieh, Meng-Kai
Abrégé
A fault analysis device and a fault analysis method of the fault analysis device are provided. A sensing circuit senses a first distorted signal on a first signal transmission path of an abnormal signal device when the abnormal signal device performs a preset operation. A signal generating circuit provides a fault test signal to a second signal transmission path of a standard device corresponding to the first signal transmission path when the standard device performs the preset operation, so as to generate a second distorted signal on the second signal transmission path, where the first distorted signal and the second distorted signal have the same signal distortion characteristics.
G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
H04L 41/0631 - Gestion des fautes, des événements, des alarmes ou des notifications en utilisant l’analyse de la corrélation entre les notifications, les alarmes ou les événements en fonction de critères de décision, p.ex. la hiérarchie ou l’analyse temporelle ou arborescente
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Chiang, Chia Che
Abrégé
The present disclosure provides a method of manufacturing a semiconductor device. The method includes: forming a semiconductor layer stack on a metal layer, in which the semiconductor layer stack includes a first nitride layer, a first oxide layer, a second nitride layer, a second oxide layer, and a third nitride layer; forming a mask layer on the semiconductor layer stack, in which the mask layer includes a plurality of hollowed portions; depositing a thin silicon layer on inner walls of the hollowed portions; and forming a plurality of trenches in the semiconductor layer stack by the hollowed portions.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Huang, Tse-Yao
Abrégé
The present application discloses a contact structure, a semiconductor device, and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an impurity region positioned in the substrate; an intervening conductive layer positioned on the impurity region; a bottom conductive layer positioned on the bottom conductive layer; a conductive capping layer positioned on the bottom conductive layer; a top conductive layer positioned on the conductive capping layer. The intervening conductive layer, the bottom conductive layer, the conductive capping layer, and the top conductive layer configure a contact structure. The bottom conductive layer includes germanium or silicon germanium. The bottom conductive layer includes n-type dopants or p-type dopants.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Chen, Che-Wei
Liu, Kai-Li
Sung, Yulin
Abrégé
A test interface circuit includes N switches and N resistors, wherein N is a positive integer. A first end of each of the N switches is coupled to each of N test connection ends, a second end of each of the N switches receives a reference voltage. Each of the N first resistors is coupled to each of the N switches in series between each of the N test connection ends and the reference voltage. Wherein, each of the N switches is controlled by each of N control signals to be turned on or cut off.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Huang, Tse-Yao
Abrégé
The present application discloses a contact structure, a semiconductor device, and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an impurity region positioned in the substrate; an intervening conductive layer positioned on the impurity region; a bottom conductive layer positioned on the bottom conductive layer; a conductive capping layer positioned on the bottom conductive layer; a top conductive layer positioned on the conductive capping layer. The intervening conductive layer, the bottom conductive layer, the conductive capping layer, and the top conductive layer configure a contact structure. The bottom conductive layer includes germanium or silicon germanium. The bottom conductive layer includes n-type dopants or p-type dopants.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Chiu, Hsih-Yang
Abrégé
A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, a semiconductor layer, and a word line. The bit line is disposed over the substrate. The semiconductor layer is disposed over the bit line. The word line abuts the semiconductor layer. The word line has a lower surface facing the substrate and an upper surface opposite to the lower surface. The semiconductor layer includes a first doped region with a first conductive type, a second doped region with a second conductive type opposite to the first conductive type. The first doped region is disposed between the second doped region and the bit line. The first boundary between the first doped region and the second doped region is substantially aligned with the lower surface of the word line.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
17.
SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR CHANNEL LAYER AND METHOD OF MANUFACTURING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Chiu, Hsih-Yang
Abrégé
A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, a semiconductor layer, and a word line. The bit line is disposed over the substrate. The semiconductor layer is disposed over the bit line. The word line abuts the semiconductor layer. The word line has a lower surface facing the substrate and an upper surface opposite to the lower surface. The semiconductor layer includes a first doped region with a first conductive type, a second doped region with a second conductive type opposite to the first conductive type. The first doped region is disposed between the second doped region and the bit line. The first boundary between the first doped region and the second doped region is substantially aligned with the lower surface of the word line.
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
18.
SEMICONDUCTOR DEVICE INCLUDING VERTICAL SUPPORTING STRUCTURE
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Wang, Wen-Chieh
Abrégé
A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a lower horizontal supporting layer, an upper horizontal supporting layer, a vertical supporting structure, and a first capacitor electrode. The lower horizontal supporting layer is disposed on the substrate. The upper horizontal supporting layer is disposed on the lower horizontal supporting layer. The vertical supporting structure extends between the lower horizontal supporting layer and the upper horizontal supporting layer. The first capacitor electrode is disposed on the substrate and extends from the lower horizontal supporting layer to the upper horizontal supporting layer.
H01L 27/08 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type
H01G 4/012 - Forme des électrodes non autoporteuses
H01G 4/38 - Condensateurs multiples, c. à d. combinaisons structurales de condensateurs fixes
19.
SEMICONDUCTOR DEVICE INCLUDING VERTICAL SUPPORTING STRUCTURE
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Wang, Wen-Chieh
Abrégé
A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a lower horizontal supporting layer, an upper horizontal supporting layer, a vertical supporting structure, and a first capacitor electrode. The lower horizontal supporting layer is disposed on the substrate. The upper horizontal supporting layer is disposed on the lower horizontal supporting layer. The vertical supporting structure extends between the lower horizontal supporting layer and the upper horizontal supporting layer. The first capacitor electrode is disposed on the substrate and extends from the lower horizontal supporting layer to the upper horizontal supporting layer.
H01L 27/08 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type
H01G 4/012 - Forme des électrodes non autoporteuses
H01G 4/38 - Condensateurs multiples, c. à d. combinaisons structurales de condensateurs fixes
20.
ELECTRONIC DEVICE, ELECTRONIC STRUCTURE AND METHOD OF MANUFACTURING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Lo, Yi-Jen
Abrégé
An electronic device, an electronic structure and a manufacturing method are provided. The electronic device includes a substrate, a conductive structure and at least one external connector. The conductive structure is disposed on the substrate and includes a test pad configured to be contacted by a probe during a testing process. The external connector is electrically connected to the conductive structure and is exposed from a surface of the electronic device for an external electrical connection. A vertical projection of the at least one external connector overlaps a vertical projection of the test pad.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
21.
ELECTRONIC DEVICE, ELECTRONIC STRUCTURE AND METHOD OF MANUFACTURING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Lo, Yi-Jen
Abrégé
An electronic device, an electronic structure and a manufacturing method are provided. The electronic device includes a substrate, a conductive structure and at least one external connector. The conductive structure is disposed on the substrate and includes a test pad configured to be contacted by a probe during a testing process. The external connector is electrically connected to the conductive structure and is exposed from a surface of the electronic device for an external electrical connection. A vertical projection of the at least one external connector overlaps a vertical projection of the test pad.
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
22.
SEMICONDUCTOR STRUCTURE HAVING DUMMY CONDUCTIVE MEMBER AND MANUFACTURING METHOD THEREOF
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Lo, Yi-Jen
Abrégé
The present application provides a semiconductor structure having a dummy conductive member, and a manufacturing method of the semiconductor structure. The semiconductor structure includes a first wafer including a first substrate, a first dielectric layer over the first substrate, a first bonding layer over the first dielectric layer, a first via extending through the first bonding layer, and a first dummy conductive member disposed adjacent to the first via and extending partially through the first bonding layer; and a second wafer including a second bonding layer over the first bonding layer, a second via extending through the second bonding layer, a second dummy conductive member disposed adjacent to the second via and extending partially through the second bonding layer, a second dielectric layer over the second bonding layer, and a second substrate over the second dielectric layer.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Lin, Ya-Chin
Abrégé
A method of forming a semiconductor structure includes forming a dielectric stack over a substrate, in which forming the dielectric stack includes forming a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer and a third support layer in sequence. A first hard mask layer is formed over the dielectric stack. A second hard mask layer is formed over the first hard mask layer. A patterned mask is formed over the second hard mask layer. The first and second hard mask layers are etched using the patterned mask as an etch mask to form first and second hard masks, in which the first hard mask layer is etched faster than the second hard mask layer. An opening is formed in the dielectric stack to expose the substrate. A bottom electrode layer is formed in the opening of the dielectric stack.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Lo, Yi-Jen
Abrégé
The present application provides a semiconductor structure having a dummy conductive member, and a manufacturing method of the semiconductor structure. The semiconductor structure includes a first wafer including a first substrate, a first dielectric layer over the first substrate, a first bonding layer over the first dielectric layer, a first via extending through the first bonding layer, and a first dummy conductive member disposed adjacent to the first via and extending partially through the first bonding layer; and a second wafer including a second bonding layer over the first bonding layer, a second via extending through the second bonding layer, a second dummy conductive member disposed adjacent to the second via and extending partially through the second bonding layer, a second dielectric layer over the second bonding layer, and a second substrate over the second dielectric layer.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
25.
HARDMASK STRUCTURE AND METHOD OF FORMING SEMICONDUCTOR STRUCTURE
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Fang, Wei-Chuan
Abrégé
A hardmask structure and a method of forming a semiconductor structure are provided. The hardmask structure includes a first ashable hardmask, a first dielectric antireflective coating, and a second ashable hardmask. The first dielectric antireflective coating is disposed on the first ashable hardmask. The second ashable hardmask is disposed on the first dielectric antireflective coating. A stress of the first ashable hardmask is from about −100 MPa to about 100 MPa.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Tsai, Jhen-Yu
Abrégé
A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate having a trench and a gate structure in the trench. The gate structure includes a lower gate electrode, an upper gate electrode disposed over the lower gate electrode, and a silicide layer contacting the upper gate electrode.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Fang, Wei-Chuan
Abrégé
A hardmask structure and a method of forming a semiconductor structure are provided. The hardmask structure includes a first ashable hardmask, a first dielectric antireflective coating, and a second ashable hardmask. The first dielectric antireflective coating is disposed on the first ashable hardmask. The second ashable hardmask is disposed on the first dielectric antireflective coating. A stress of the first ashable hardmask is from about −100 MPa to about 100 MPa.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Tsai, Jhen-Yu
Abrégé
A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate having a trench and a gate structure in the trench. The gate structure includes a lower gate electrode, an upper gate electrode disposed over the lower gate electrode, and a silicide layer contacting the upper gate electrode.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Hao, Chung-Peng
Abrégé
A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a first bit-line extending in a first direction and a first word-line extending in a second direction substantially perpendicular to the first direction. The semiconductor device also includes a first channel. The first bit-line and the first word-line are electrically coupled to the first channel. The semiconductor device also includes a first gate line disposed between the first bit-line and the first word-line. The first gate line is electrically coupled to the first channel and configured to close the first channel once the first bit-line and the first word-line are shorted together through the first channel.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Chou, Liang-Pin
Abrégé
A semiconductor device includes a plurality of drain regions in a substrate; a plurality of capacitor plugs on the plurality of drain regions; a plurality of lower electrodes on the plurality of capacitor plugs and respectively including a U-shaped cross-sectional profile; a lower supporting layer above the substrate, against on outer surfaces of the plurality of lower electrodes, and including: a plurality of first openings along the lower supporting layer and between the plurality of lower electrodes; and a higher supporting layer above the lower supporting layer, against on the outer surfaces of the plurality of lower electrodes, and including: a plurality of second openings along the higher supporting layer and topographically aligned with the plurality of first openings. The widths of the plurality of first openings and the widths of the plurality of second openings are substantially the same.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Tsai, Tzu-Ching
Abrégé
A circuit device includes: a first substrate having a first barrier layer; a second substrate having a second barrier layer; a first conductive portion arranged over the first barrier layer; a second conductive portion arranged over the second barrier layer; a first expanding pad arranged on the first conductive portion and including a first contact area greater than that of the first conductive portion; and a second expanding pad bonded to the first expanding pad, arranged on the second conductive portion and including a second expanded contact area greater than that of the second conductive portion. The first barrier layer and the second barrier layer include aluminum fluoride.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
32.
SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR PREPARING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Fan, Cheng-Hsiang
Abrégé
The present disclosure provides a semiconductor device structure with fine patterns and a method for forming the semiconductor device structure, which can prevent the collapse of the fine patterns. The semiconductor device structure includes a first target structure and a second target structure disposed over a semiconductor substrate. The semiconductor device structure also includes a first spacer element disposed over the first target structure, wherein a topmost point of the first spacer element is between a central line of the first target structure and a central line of the second target structure in a cross-sectional view.
H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
H01L 21/308 - Traitement chimique ou électrique, p.ex. gravure électrolytique en utilisant des masques
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Huang, Tse-Yao
Abrégé
The present disclosure provide a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a first buried gate structure and a second buried gate structure disposed in a semiconductor substrate. The first buried gate structure includes a first gate dielectric layer, and a first lower semiconductor layer disposed over the first gate dielectric layer. The first lower semiconductor layer has a T-shaped profile in a cross-sectional view. The first buried gate structure also includes a first upper semiconductor layer disposed over the first lower semiconductor layer. The second buried gate structure includes a second gate dielectric layer, and a second lower semiconductor layer disposed over the second gate dielectric layer. The second lower semiconductor layer has a U-shaped profile in the cross-sectional view. The second buried gate structure also includes a second upper semiconductor layer disposed over the second lower semiconductor layer.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
34.
SEMICONDUCTOR DEVICE HAVING GATE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Hao, Chung-Peng
Abrégé
A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a first bit-line extending in a first direction and a first word-line extending in a second direction substantially perpendicular to the first direction. The semiconductor device also includes a first channel. The first bit-line and the first word-line are electrically coupled to the first channel. The semiconductor device also includes a first gate line disposed between the first bit-line and the first word-line. The first gate line is electrically coupled to the first channel and configured to close the first channel once the first bit-line and the first word-line are shorted together through the first channel.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Chou, Liang-Pin
Abrégé
A semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a plurality of drain regions in a substrate; a plurality of capacitor plugs on the plurality of drain regions; a plurality of lower electrodes on the plurality of capacitor plugs and respectively including a U-shaped cross-sectional profile; a lower supporting layer above the substrate, against on outer surfaces of the plurality of lower electrodes, and including: a plurality of first openings along the lower supporting layer and between the plurality of lower electrodes; and a higher supporting layer above the lower supporting layer, against on the outer surfaces of the plurality of lower electrodes, and including a plurality of second openings along the higher supporting layer and topographically aligned with the plurality of first openings. The widths of the first openings and the widths of the second openings are substantially the same.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Yang, Wu-Der
Abrégé
A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a decoupling capacitor structure, and an electronic component. The decoupling capacitor structure is disposed on the substrate. The electronic component is disposed on the decoupling capacitor structure and electrically connected to the decoupling capacitor structure. The electronic component is stacked over the decoupling capacitor structure.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des groupes principaux , ou dans une seule sous-classe de , , p.ex. circuit hybrides
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 49/02 - Dispositifs à film mince ou à film épais
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Huang, Tse-Yao
Abrégé
The present disclosure provide a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a first buried gate structure and a second buried gate structure disposed in a semiconductor substrate. The first buried gate structure includes a first gate dielectric layer, and a first lower semiconductor layer disposed over the first gate dielectric layer. The first lower semiconductor layer has a T-shaped profile in a cross-sectional view. The first buried gate structure also includes a first upper semiconductor layer disposed over the first lower semiconductor layer. The second buried gate structure includes a second gate dielectric layer, and a second lower semiconductor layer disposed over the second gate dielectric layer. The second lower semiconductor layer has a U-shaped profile in the cross-sectional view. The second buried gate structure also includes a second upper semiconductor layer disposed over the second lower semiconductor layer.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
38.
SEMICONDUCTOR DEVICE WITH DECOUPLING CAPACITOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Yang, Wu-Der
Abrégé
A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a decoupling capacitor structure, and an electronic component. The decoupling capacitor structure is disposed on the substrate. The electronic component is disposed on the decoupling capacitor structure and electrically connected to the decoupling capacitor structure. The electronic component is stacked over the decoupling capacitor structure.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des groupes principaux , ou dans une seule sous-classe de , , p.ex. circuit hybrides
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
39.
SEMICONDUCTOR DEVICE WITH CONDUCTIVE CAP LAYER OVER CONDUCTIVE PLUG AND METHOD FOR FORMING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Tsai, Hung-Chi
Abrégé
The present disclosure relates to a semiconductor device including a semiconductor substrate, word lines, mask layers, spacers, a conductive plug, a conductive cap layer, and a dielectric layer. The word lines are disposed over the semiconductor substrate. The mask layers are disposed over the plurality of word line, respectively. The spacers are disposed over opposite sidewalls of the word lines and opposite sidewalls of the mask layers, respectively. The conductive plug is disposed between the word lines. The conductive cap layer is disposed over the conductive plug. The dielectric layer is disposed over the word lines and the spacers. Each of the spacers includes an inner spacer, an outer spacer, and an air gap. The inner spacer is in contact with the respective word line and the respective mask layer. The air gap is disposed between the inner spacer and the outer spacer.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Li, Wei Zhong
Chiu, Hsih-Yang
Abrégé
A semiconductor structure includes a substrate, an anti-fuse, first and second transistors, a contact structure, and a dielectric layer. The substrate includes a well region and first and second conductivity type doped regions in the well region, in which the second conductivity type doped region surrounds the first conductivity type doped region and includes a first portion and a second portion perpendicular to the first portion in a top view. The anti-fuse is in an anti-fuse region of the first conductivity type doped region. The first and second transistors are in the well region. The anti-fuse is disposed between the first and second transistors, and the anti-fuse is electrically connected to the first and second transistors. The contact structure is above the anti-fuse. The dielectric layer is between the contact structure and the anti-fuse region of the first conductivity type doped region.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Yang, Shu-Wei
Abrégé
A memory control circuit and a refresh method for a dynamic random access memory (DRAM) array are provided. The memory control circuit includes a mode register circuit, a command decoder and a refresh circuit. The mode register circuit includes a plurality of mode registers. The command decoder receives a refresh command and sets a flag of a target mode register corresponding to the refresh command among the plurality of mode registers to a setting value. The refresh circuit refreshes the DRAM array in response to the refresh command through the command decoder and the setting value of the flag of the target mode register.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Chen, Jyun-Da
Abrégé
A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.
G11C 29/56 - Vérification du fonctionnement correct des mémoires; Test de mémoires lors d'opération en mode de veille ou hors-ligne Équipements externes pour test de mémoires statiques, p.ex. équipement de test automatique [ATE]; Interfaces correspondantes
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
43.
SEMICONDUCTOR DEVICE WITH METAL SPACERS AND METHOD FOR FABRICATING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Su, Kuo-Hui
Abrégé
The present application discloses a semiconductor device including a substrate, an active area in the substrate, a first plug positioned above the active area, second plugs positioned above the active area, metal spacers positioned above the first plug and the plurality of second plugs, and air gaps respectively positioned between the plurality of metal spacers. The active area includes a narrow portion having a first width and two side portions having a second width, wherein the narrow portion is disposed between the two side portions, and the first width is less than the second width from a top view.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p.ex. structures d'interconnexions enterrées
44.
METHOD OF MANUFACTURING TSEMICONDUCTOR DEVICE HAVING BONDING STRUCTURE
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Lo, Yi-Jen
Shih, Chiang-Lin
Chiu, Hsih-Yang
Abrégé
A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bonding structure, a bit line, and a word line. The bonding structure is disposed on the substrate. The bit line is disposed on the bonding structure. The channel layer is disposed on the bit line. The word line surrounds the channel layer. The bonding structure includes a dielectric material.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
45.
SEMICONDUCTOR DEVICE WITH SHALLOW CONTACTS AND METHOD FOR FABRICATING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Huang, Tse-Yao
Abrégé
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a word line structure positioned in the substrate; a plurality of impurity regions positioned in the substrate and adjacent to the word line structure; a plurality of bottom shallow contacts positioned on the word line structure; a first interconnect layer positioned on the plurality of bottom shallow contacts; a plurality of top shallow contacts positioned on the first interconnect layer; and a plurality of deep contacts positioned on the plurality of impurity regions. Top surfaces of the plurality of top shallow contacts and top surfaces of the plurality of deep contacts are substantially coplanar.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
46.
METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE WITH IMPROVED ETCHING PROCESS
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Huang, Zhi-Yi
Chuang, Ying-Cheng
Chen, Tsung-Cheng
Abrégé
The present disclosure provides a manufacturing method of a semiconductor structure. The method includes: forming a conformal layer over a first patterned layer over a substrate; forming a second layer over the conformal layer and between portions of the first patterned layer; performing a first etching to form a second patterned layer and a patterned conformal layer; performing a second etching to remove a portion of the first patterned layer to form a first inclined member of the first patterned layer tapered away from the substrate and lining a vertical portion of the patterned conformal layer, and to remove a portion of the second patterned layer to form a second inclined member of the second patterned layer tapered away from the substrate and lining the vertical portion of the patterned conformal layer; and performing a third etching to remove the vertical portions of the patterned conformal layer.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Shih, Chiang-Lin
Lin, Yu-Ting
Abrégé
A semiconductor structure includes a first dielectric layer, a second dielectric layer on the first dielectric layer, a capacitor structure in the first dielectric layer and the second dielectric layer, a third dielectric layer on the second dielectric layer, a word line, a channel structure, and a gate dielectric. The word line is located in the third dielectric layer and extends across the capacitor structure. The channel structure is located in the third dielectric layer and surrounds the word line and a portion of the third dielectric layer. The gate dielectric has a first portion and a second portion separated from the first portion, wherein the first portion is between a sidewall of the word line and the channel structure, and the second portion is between an inner sidewall of the third dielectric layer and the channel structure.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Chuang, Ying-Cheng
Abrégé
A semiconductor memory device manufacturing method includes: sequentially forming a lower oxide layer, a word line metal layer and an upper oxide layer over at least a portion of a memory cell; forming a through hole passing through the upper oxide layer, the word line metal layer and the lower oxide layer to expose the portion of the memory cell; forming a sacrificial pillar into the through hole; removing the upper oxide layer to expose a top portion of the sacrificial pillar; sequentially forming a first oxide spacer sidewall, a nitride spacer sidewall and a second oxide spacer sidewall on a sidewall of the top portion of the sacrificial pillar; removing the nitride spacer sidewall to form a void gap; etching the word line metal layer through the void gap to form separate word lines.
H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
49.
SEMICONDUCTOR DEVICE WITH SHALLOW CONTACTS AND METHOD FOR FABRICATING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Huang, Tse-Yao
Abrégé
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a word line structure positioned in the substrate; a plurality of impurity regions positioned in the substrate and adjacent to the word line structure; a plurality of bottom shallow contacts positioned on the word line structure; a first interconnect layer positioned on the plurality of bottom shallow contacts; a plurality of top shallow contacts positioned on the first interconnect layer; and a plurality of deep contacts positioned on the plurality of impurity regions. Top surfaces of the plurality of top shallow contacts and top surfaces of the plurality of deep contacts are substantially coplanar.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
50.
SEMICONDUCTOR STRUCTURE WITH OVERLAY MARK, METHOD OF MANUFACTURING THE SAME, AND SYSTEM FOR MANUFACTURING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Lin, Tsai-Wei
Abrégé
The present disclosure provides a semiconductor structure, a method of manufacturing the semiconductor structure and a system for manufacturing the semiconductor structure. The method includes several operations. A substrate including a device region and a scribe line region is provided. A first layer is formed over the substrate. A first photoluminescent layer is formed over the first layer in the scribe line region. The first layer and the first photoluminescent layer are patterned to form a first pattern in the scribe line region. A first patterned mask layer is formed over a second layer. An alignment of the first patterned mask layer with the first pattern is detected. A pattern of the first patterned mask layer is transferred to the second layer to form a second pattern in the scribe line region.
G03F 9/00 - Mise en registre ou positionnement d'originaux, de masques, de trames, de feuilles photographiques, de surfaces texturées, p.ex. automatique
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/544 - Marques appliquées sur le dispositif semi-conducteur, p.ex. marques de repérage, schémas de test
51.
SEMICONDUCTOR STRUCTURE WITH OVERLAY MARK AND SYSTEM FOR MANUFACTURING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Lin, Tsai-Wei
Abrégé
The present disclosure provides a semiconductor structure, a method of manufacturing the semiconductor structure and a system for manufacturing the semiconductor structure. The method includes several operations. A substrate including a device region and a scribe line region is provided. A first layer is formed over the substrate. A first photoluminescent layer is formed over the first layer in the scribe line region. The first layer and the first photoluminescent layer are patterned to form a first pattern in the scribe line region. A first patterned mask layer is formed over a second layer. An alignment of the first patterned mask layer with the first pattern is detected. A pattern of the first patterned mask layer is transferred to the second layer to form a second pattern in the scribe line region.
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
G03F 7/00 - Production par voie photomécanique, p.ex. photolithographique, de surfaces texturées, p.ex. surfaces imprimées; Matériaux à cet effet, p.ex. comportant des photoréserves; Appareillages spécialement adaptés à cet effet
G03F 9/00 - Mise en registre ou positionnement d'originaux, de masques, de trames, de feuilles photographiques, de surfaces texturées, p.ex. automatique
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/544 - Marques appliquées sur le dispositif semi-conducteur, p.ex. marques de repérage, schémas de test
52.
SEMICONDUCTOR DEVICE HAVING BONDING STRUCTURE AND METHOD OF MANUFACTURING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Lo, Yi-Jen
Shih, Chiang-Lin
Chiu, Hsih-Yang
Abrégé
A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bonding structure, a bit line, and a word line. The bonding structure is disposed on the substrate. The bit line is disposed on the bonding structure. The channel layer is disposed on the bit line. The word line surrounds the channel layer. The bonding structure includes a dielectric material.
H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
53.
METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE WITH IMPROVED ETCHING PROCESS
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Huang, Zhi-Yi
Chuang, Ying-Cheng
Chen, Tsung-Cheng
Abrégé
The present disclosure provides a manufacturing method of a semiconductor structure. The method includes: forming a conformal layer over a first patterned layer over a substrate; forming a second layer over the conformal layer and between portions of the first patterned layer; performing a first etching to form a second patterned layer and a patterned conformal layer; performing a second etching to remove a portion of the first patterned layer to form a first inclined member of the first patterned layer tapered away from the substrate and lining a vertical portion of the patterned conformal layer, and to remove a portion of the second patterned layer to form a second inclined member of the second patterned layer tapered away from the substrate and lining the vertical portion of the patterned conformal layer; and performing a third etching to remove the vertical portions of the patterned conformal layer.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Lo, Yi-Jen
Abrégé
The present application provides a semiconductor structure having a conductive pad with a protrusion, and a manufacturing method of the semiconductor structure. The semiconductor structure includes a first die including a first substrate, a first dielectric layer over the first substrate, a first conductive pad at least partially exposed through the first dielectric layer, a first bonding layer over the first dielectric layer, and a first via extending through the first bonding layer and coupled to the first conductive pad; and a second die including a second bonding layer bonded to the first bonding layer, a second substrate over the second bonding layer, and a second via extending through the second substrate and the second bonding layer, wherein a first contact surface area between the first bonding layer and the second via is substantially greater than a second contact surface area between the first via and the second via.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
55.
SEMICONDUCTOR DEVICE STRUCTURE HAVING CHANNEL LAYER WITH REDUCED APERTURE AND METHOD FOR MANUFACTURING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Xiao, Yu
Abrégé
A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a word line, a channel layer, and a bit line. The word line is disposed on the substrate. The channel layer is surrounded by the word line. The bit line is disposed on the channel layer. The channel layer has a first portion in the substrate and a second portion over the substrate. A first width of the first portion is greater than a second width of the second portion along a first direction.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Li, Wei-Zhong
Shih, Yi-Ting
Wang, Chien-Chung
Chiu, Hsih-Yang
Abrégé
A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Chou, Yi-Hsien
Abrégé
The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of bottom interconnectors positioned on the second side of the package structure, and respectively including: a bottom exterior layer positioned on the second side of the package structure; and a cavity enclosed by the bottom exterior layer.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Shih, Chiang-Lin
Lin, Yu-Ting
Abrégé
A dynamic random access memory includes an array region, a bottom capacitor array located in the array region, and a top capacitor array located in the array region and located on the bottom capacitor array. The bottom capacitor array is single-sided capacitor array. The top capacitor is a double-sided capacitor array.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Xiao, Yu
Abrégé
A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a word line, a channel layer, and a bit line. The word line is disposed on the substrate. The channel layer is surrounded by the word line. The bit line is disposed on the channel layer. The channel layer has a first portion in the substrate and a second portion over the substrate. A first width of the first portion is greater than a second width of the second portion along a first direction.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Li, Wei-Zhong
Chiu, Hsih-Yang
Abrégé
The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate; a transistor disposed over the substrate; and a trench fuse disposed in the substrate and penetrating a source/drain (S/D) region of the transistor. A method for manufacturing the semiconductor structure is also provided.
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Liu, Fang-Wen
Abrégé
An electrostatic discharge (ESD) protection circuit is provided. The protection circuit includes a MOS transistor and a resistor. The MOS transistor is electrically coupled to a core circuit. The resistor is electrically coupling to a gate of the MOS transistor for creating a bias on the gate to directing an ESD current to a ground when an ESD event occurs on the core circuit. A layout of the MOS transistor is spaced apart from a layout of the core circuit by a layout of a dummy structure. The resistor is formed by utilizing a portion of the dummy structure.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
62.
SEMICONDUCTOR STRUCTURE HAVING FUSE BELOW GATE STRUCTURE AND METHOD OF MANUFACTURING THEREOF
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Li, Wei-Zhong
Chiu, Hsih-Yang
Abrégé
The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate; a transistor disposed over the substrate; and a trench fuse disposed in the substrate and penetrating a source/drain (S/D) region of the transistor. A method for manufacturing the semiconductor structure is also provided.
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 23/528 - Configuration de la structure d'interconnexion
63.
SEMICONDUCTOR DEVICE WITH EPITAXIAL BOTTOM ASSISTANT LAYER
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Huang, Tse-Yao
Abrégé
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first impurity region positioned in the substrate; a first dielectric layer positioned on the substrate; a first contact including a buried portion positioned along the first dielectric layer and on the first impurity region, and a protruding portion positioned on the buried portion and protruding from the first dielectric layer; a first top assistant cap covering the protruding portion; and a first top conductive layer positioned on the first top assistant cap. The first top assistant cap includes germanium or silicon germanium.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Hou, Szu-Yu
Lin, Li-Han
Abrégé
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate having a first surface, a plurality of layers disposed on the first surface of the substrate. The plurality of layers includes a first nitride layer disposed on the first surface of the substrate, a first silicon-containing layer disposed on the first nitride layer, an intermediate nitride layer disposed on the first silicon-containing layer, a second silicon-containing layer disposed on the intermediate nitride layer, and a second nitride layer disposed on the second silicon-containing layer. In addition, the semiconductor structure includes a trench capacitor penetrating the plurality of layers and in contact with the substrate. The trench capacitor has a first portion having a first lateral surface and a second portion having a second lateral surface, and the first lateral surface has a slope different from that of the second lateral surface.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Kai, Wan Yu
Abrégé
A manufacturing method of a semiconductor device includes forming a contact opening in a wafer. The wafer includes a substrate, a gate structure over the substrate and a dielectric layer over the substrate and surrounding the gate structure, and the contact opening passes through the dielectric layer and exposes the substrate. A recess is formed in the substrate such that the recess is connected to the contact opening. An oxidation process is performed to convert a portion of the substrate exposed in the recess to form a protection layer lining a sidewall and a bottom surface of the recess. The protection layer is etched back to remove a first portion of the protection layer in contact with the bottom surface of the recess of the substrate. A metal alloy structure is formed at the bottom surface of the recess of the substrate.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
66.
SEMICONDUCTOR STRUCTURES HAVING DEEP TRENCH CAPACITOR AND METHODS FOR MANUFACTURING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Hou, Szu-Yu
Lin, Li-Han
Abrégé
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate having a first surface, a plurality of layers disposed on the first surface of the substrate. The plurality of layers includes a first nitride layer disposed on the first surface of the substrate, a first silicon-containing layer disposed on the first nitride layer, an intermediate nitride layer disposed on the first silicon-containing layer, a second silicon-containing layer disposed on the intermediate nitride layer, and a second nitride layer disposed on the second silicon-containing layer. In addition, the semiconductor structure includes a trench capacitor penetrating the plurality of layers and in contact with the substrate. The trench capacitor has a first portion having a first lateral surface and a second portion having a second lateral surface, and the first lateral surface has a slope different from that of the second lateral surface.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Lo, Yi-Jen
Abrégé
The present application provides a semiconductor structure having a conductive pad with a protrusion, and a manufacturing method of the semiconductor structure. The semiconductor structure includes a first die including a first substrate, a first dielectric layer over the first substrate, a first conductive pad at least partially exposed through the first dielectric layer, a first bonding layer over the first dielectric layer, and a first via extending through the first bonding layer and coupled to the first conductive pad; and a second die including a second bonding layer bonded to the first bonding layer, a second substrate over the second bonding layer, and a second via extending through the second substrate and the second bonding layer, wherein a first contact surface area between the first bonding layer and the second via is substantially greater than a second contact surface area between the first via and the second via.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Wen, Chih-Yuan
Abrégé
A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
69.
SEMICONDUCTOR DEVICE WITH ASSISTANT CAP AND METHOD FOR FABRICATING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Huang, Tse-Yao
Abrégé
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first impurity region positioned in the substrate; a first dielectric layer positioned on the substrate; a first contact including a buried portion positioned along the first dielectric layer and on the first impurity region, and a protruding portion positioned on the buried portion and protruding from the first dielectric layer; a first top assistant cap covering the protruding portion; and a first top conductive layer positioned on the first top assistant cap. The first top assistant cap includes germanium or silicon germanium.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Liu, Fang-Wen
Abrégé
An electrostatic discharge (ESD) protection circuit is provided. The protection circuit includes a MOS transistor and a resistor. The MOS transistor is electrically coupled to a core circuit. The resistor is electrically coupling to a gate of the MOS transistor for creating a bias on the gate to directing an ESD current to a ground when an ESD event occurs on the core circuit. A layout of the MOS transistor is spaced apart from a layout of the core circuit by a layout of a dummy structure. The resistor is formed by utilizing a portion of the dummy structure.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
71.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Tsai, Hung-Chi
Abrégé
The present application discloses semiconductor device, including a gate structure arranged on a substrate; a plurality of word lines arranged apart from the gate structure; two porous spacers arranged on two sides of the gate structure; and a first insulating layer arranged on the substrate laterally surrounding the gate structure and the porous spacers; and a second insulating layer arranged over the first insulating layer, wherein a top surface of the gate structure, top surfaces of the plurality of word lines and a top surface of the second insulating layer are level with each other, and wherein a porosity of the porous spacers is between about 25% and about 100%.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
72.
SEMICONDUCTOR STRUCTURE WITH AIR GAP IN PATTERN-DENSE REGION AND METHOD OF MANUFACTURING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Ho, Jar-Ming
Abrégé
The present disclosure provides a semiconductor structure, which includes: a first conductive layer arranged over a substrate; a dielectric layer arranged over the first conductive layer; a plurality of first conductive plugs penetrating through the dielectric layer; a plurality of spacers surrounding the respective first conductive plugs; a lining layer covering the dielectric layer, the spacer and the first conductive plugs, wherein the lining layer and the first conductive plugs include manganese (Mn); a second conductive plug penetrating through the lining layer; and a second conductive layer over the lining layer and the second conductive plug.
H01L 21/285 - Dépôt de matériaux conducteurs ou isolants pour les électrodes à partir d'un gaz ou d'une vapeur, p.ex. condensation
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 21/3213 - Gravure physique ou chimique des couches, p.ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
H01L 23/544 - Marques appliquées sur le dispositif semi-conducteur, p.ex. marques de repérage, schémas de test
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
73.
SEMICONDUCTOR STRUCTURE HAVING AIR GAP DIELECTRIC AND METHOD OF PREPARING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Lai, Chun-Chi
Abrégé
The present disclosure provides a semiconductor structure including a base layer, a first conductive line disposed on the base layer, a first dielectric pillar disposed on the base layer, a second dielectric pillar disposed on the base layer, a first liner, and a second liner. The first conductive line is disposed between the first dielectric pillar and the second dielectric pillar. The first liner encloses a first air gap, and is disposed between the first dielectric pillar and the first conductive line. The second liner encloses a second air gap, and is disposed between the second dielectric pillar and the first conductive line.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
74.
SEMICONDUCTOR MEMORY STRUCTURE HAVING DRAIN STRESSOR, SOURCE STRESSOR AND BURIED GATE AND METHOD OF MANUFACTURING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Fan, Cheng-Hsiang
Abrégé
The present disclosure provides a semiconductor memory structure, including a substrate, a gate structure, a first shallow trench isolation (STI), and a second STI. The gate structure, the first STI, and a second STI are disposed in the substrate. The gate structure is buried in the substrate. The gate structure is disposed between the first STI and the second STI.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Lin, Yu-Ying
Abrégé
A semiconductor device includes a substrate, a bitline, a bitline contact and a land pad. The bitline is over the substrate. The bitline contact is in contact with a bottom of the bitline and in the substrate. The bitline contact includes a first portion and a second portion below the first portion, and the first portion is wider than the second portion from a cross-section view. A word line is adjacent to the bitline contact. A land pad is on the substrate, and the land pad is adjacent to the word line, such that the word line is between the bitline contact and the land pad.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Lin, Shih-Ting
Abrégé
A semiconductor device can be applied to a memory device. The semiconductor device of the disclosure includes a voltage sensor, a convertor and a command/address on-die-termination (CA_ODT) circuit. The voltage sensor receives a voltage setting command, and sense a voltage level of the voltage setting command to generate a sensing signal. The convertor generates a setting signal in response to the sensing signal. The CA_ODT circuit generates a power voltage for the memory device in response to the setting signal, wherein a voltage level of the power voltage corresponds to the voltage level of the voltage setting command.
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p.ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Wu, Chang-Ting
Abrégé
An off-chip driver (OCD), including a pull-up driver and a pull-down driver, is provided. The pull-up driver and the pull-down driver are coupled to an output pad. One of the pull-up driver and the pull-down driver includes a main driving circuit, an auxiliary driving circuit, a connection circuit, and a common impedance. The main driving circuit is used to perform an output driving operation on the output pad, and the auxiliary driving circuit is used to selectively perform the output driving operation on the output pad. A first terminal of the common impedance is coupled to a driving terminal of the main driving circuit and a driving terminal of the auxiliary driving circuit through the connection circuit. A second terminal of the common impedance is coupled to the output pad.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Lin, Yuan-Yuan
Abrégé
The present disclosure provides a vertical memory structure including a semiconductor stack, a contact plug, gate electrodes and air gap structures. The semiconductor stack includes a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate. The contact plug is disposed over the lower semiconductor patterns structure. The contact plug includes a lower portion and a middle portion over the lower portion. A width of the middle portion is less than a width of the lower portion. The gate electrodes are surrounding a sidewall of the semiconductor stack. The air gap structures are disposed at outer sides of the plurality of gate electrode respectively.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Lo, Yi-Jen
Chiu, Hsih Yang
Chang, Ching Hung
Shih, Chiang-Lin
Abrégé
The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface is formed between the first device wafer and the second device wafer, wherein the second device wafer is electrically coupled to the first device wafer, and a function of the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
80.
SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR MANUFACTURING METHOD
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Lin, Yu-Ying
Huang, Chung-Lin
Abrégé
A semiconductor structure includes a semiconductor substrate; a spacer located in a trench of the semiconductor substrate, wherein the spacer includes two trench nitride layers and an empty gap sandwiched between the two trench nitride layers; a first nitride layer disposed to seal an exposed opening of the empty gap between the two trench nitride layers; a second nitride layer over the first nitride layer, wherein the second nitride layer has a higher density than the first nitride layer; and a third nitride layer having a first portion over the second nitride layer and a second portion disposed on sidewalls of the two trench nitride layers.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Lee, Chun-Lu
Abrégé
The disclosure provides a method for forming an electrostatic discharge (ESD) protection circuit. The method includes providing a circuit comprising a first voltage supply line, an internal circuit, an input/output (I/O) pad coupling to the internal circuit through a line, and a first ESD protection element between the I/O pad and the internal circuit, wherein the first ESD protection element includes a plurality of first ESD units; and forming a first connection circuit on the first ESD protection element, to couple a first group of the first ESD units to the first voltage supply line though a first node and couple the first group of the first ESD units to the line though a second node.
H01L 23/552 - Protection contre les radiations, p.ex. la lumière
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
82.
SEMICONDUCTOR DEVICE INCLUDING MARK STRUCTURE FOR MEASURING OVERLAY ERROR AND METHOD FOR MANUFACTURING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Yeh, Chih-Hsuan
Abrégé
A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a first pattern and a second pattern. The first pattern is disposed on the substrate. The first pattern includes a first segment and a second segment, each of which extends along a first direction. The second pattern is disposed on the first pattern. The second pattern includes a first part extending along a second direction different from the first direction. The first part of the second pattern overlaps the first segment and the second segment along a third direction different from the first direction and the second direction. The first pattern and the second pattern are associated with an overlay error.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Yang, Wu-Der
Abrégé
A WBGA package and a method of manufacturing a WBGA package are provided. The WBGA package includes a first substrate having a first through hole and a second substrate having a second through hole over the first through hole of the first substrate. The WBGA package also includes an electronic component having an active surface over the second through hole of the second substrate.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/13 - Supports, p.ex. substrats isolants non amovibles caractérisés par leur forme
84.
SEMICONDUCTOR DEVICE WITH CUSHION STRUCTURE AND METHOD FOR FABRICATING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Huang, Tse-Yao
Abrégé
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including a circuit area and a non-circuit area; a top dielectric layer positioned on the substrate; a top interconnector positioned along top dielectric layer and above the circuit area; a cushion structure positioned along the top dielectric layer and above the non-circuit area; a bottom passivation layer positioned on the top dielectric layer; a top conductive pad positioned in the bottom passivation layer and on the top interconnector; a redistribution layer positioned on the top conductive pad, on the bottom passivation layer, and extending from the circuit area to the non-circuit area; and an external connector positioned on the redistribution layer and above the cushion structure. The cushion structure includes a porous polymeric material.
H01L 23/18 - Matériaux de remplissage caractérisés par le matériau ou par ses propriétes physiques ou chimiques, ou par sa disposition à l'intérieur du dispositif complet
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Yang, Wu-Der
Abrégé
An electronic device and phase detector are provided. The phase detector includes a first input terminal, a second input terminal, a first input buffer, and a second input buffer. The first input buffer is electrically connected to the first input terminal. The second input buffer is electrically connected to the second input terminal.
G01R 25/00 - Dispositions pour procéder aux mesures de l'angle de phase entre une tension et un courant ou entre des tensions ou des courants
H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
86.
SEMICONDUCTOR DEVICE STRUCTURE WITH COMPOSITE INTERCONNECT STRUCTURE AND METHOD FOR PREPARING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Huang, Tse-Yao
Abrégé
A semiconductor device structure includes a first lower semiconductor structure disposed over a semiconductor substrate. The first lower semiconductor structure has a first sidewall and a second sidewall opposite to the first sidewall. The semiconductor device structure also includes a first upper semiconductor structure covering a top surface and the first sidewall of the first lower semiconductor structure. The first lower semiconductor structure and the first upper semiconductor structure include different materials. The semiconductor device structure further includes a first oxide portion disposed over the semiconductor substrate and extending along the second sidewall of the first lower semiconductor structure. The first oxide portion has an L-shape.
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Huang, Tse-Yao
Abrégé
A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, an interconnection structure, a first isolation feature, and a second isolation feature. The interconnection structure has a first lateral surface and a second lateral surface. The first isolation feature is disposed on the first lateral surface of the interconnection structure. The second isolation feature is disposed on the second lateral surface of the interconnection structure. The first isolation feature is different from the second isolation feature.
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
88.
SEMICONDUCTOR DEVICE WITH WIRE BOND AND METHOD FOR PREPARING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Huang, Tse-Yao
Abrégé
A semiconductor device includes a semiconductor substrate having a bonding pad, and a first dielectric layer disposed over the semiconductor substrate. A portion of the bonding pad is exposed by the first dielectric layer. The semiconductor device also includes a metal oxide layer disposed over the portion of the bonding pad, and a wire bond penetrating through the metal oxide layer to bond to the bonding pad. The portion of the bonding pad is entirely covered by the metal oxide layer and the wire bond.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 23/488 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes formées de structures soudées
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
89.
SEMICONDUCTOR DEVICE WITH REDISTRIBUTION STRUCTURE AND METHOD FOR FABRICATING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Huang, Tse-Yao
Abrégé
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first chip including: a first inter-dielectric layer positioned on a first substrate; a plug structure positioned in the first inter-dielectric layer and electrically coupled to a functional unit of the first chip; a first redistribution layer positioned on the first inter-dielectric layer and distant from the plug structure; a first lower bonding pad positioned on the first redistribution layer; and a second lower bonding pad positioned on the plug structure; and a second chip positioned on the first chip and including: a first upper bonding pad positioned on the first lower bonding pad; a second upper bonding pad positioned on the second lower bonding pad; and a plurality of storage units electrically coupled to the first upper bonding pad and the second upper bonding pad.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Wei, Meng-Liang
Chou, Sun-Fu
Abrégé
A gas purge device includes a first nozzle and a gas gate. The first nozzle is coupled to a front-opening unified pod (FOUP) through a first port of the FOUP. The gas gate is coupled to the first nozzle via a first pipe. The gas gate includes a first mass flow controller (MFC), a second MFC, and a first switch unit. The first MFC is configured to control a first flow of a first gas. The second MFC is configured to control a second flow of a second gas. The first switch unit is coupled to the first MFC and the second MFC, and is configured to provide the first gas to the first nozzle through the first pipe or receive the second gas from the first nozzle through the first pipe according to a process configuration.
H01L 21/673 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants utilisant des supports spécialement adaptés
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
91.
SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR PREPARING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Shih, Shing-Yih
Abrégé
A semiconductor package structure includes a first semiconductor wafer including a first bonding pad. The semiconductor package structure also includes a second semiconductor wafer including a second bonding pad and a third bonding pad. The second bonding pad and the third bonding pad are bonded to the first bonding pad of the first semiconductor wafer. The semiconductor package structure further includes a first via penetrating through the second semiconductor wafer to physically contact the first bonding pad of the first semiconductor wafer. A portion of the first via is disposed between the second bonding pad and the third bonding pad.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
92.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Ai, Tsu-Chieh
Abrégé
A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate and a conductive pad disposed on the substrate and having a first surface facing away from the substrate. The first surface of the conductive pad is recessed toward the substrate and defines a recessed portion. The semiconductor device also includes a capacitor structure at least partially disposed within the recessed portion of the conductive pad and electrically connected with the substrate through the conductive pad.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
93.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Chou, Liang-Pin
Abrégé
The present disclosure provides a semiconductor device. The semiconductor device includes a die stack, an intervening bonding layer, and a carrier structure. The intervening bonding layer is positioned on the die stack. The carrier structure is disposed on the intervening bonding layer opposite to the die stack. The carrier structure includes a heat dissipation unit configured to transfer heat generated from the die stack. The heat dissipation unit includes composite vias and conductive plates. Each of the composite vias includes a first through semiconductor via and a second through semiconductor via. The conductive plates are couple to the composite vias.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
94.
SEMICONDUCTOR DEVICE, SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STRUCTURE USING TILTED ETCH PROCESS
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Yeh, Huan-Yung
Abrégé
The present application discloses a semiconductor device including a first isolation structure, a second isolation structure, and a third isolation structure disposed in a semiconductor substrate. The semiconductor device further includes a transistor and a resistor. The transistor is disposed between the first isolation structure and the second isolation structure, and includes a gate electrode and a first source/drain (S/D) region. The resistor is disposed between the second isolation structure and the third isolation structure, and includes a resistor electrode. The first S/D region is disposed between the gate electrode and the second isolation structure, and is electrically connected to the resistor electrode.
H01L 21/308 - Traitement chimique ou électrique, p.ex. gravure électrolytique en utilisant des masques
H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
H01L 21/3213 - Gravure physique ou chimique des couches, p.ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
95.
SEMICONDUCTOR DEVICE WITH AIR GAP AND BORON NITRIDE CAP AND METHOD FOR PREPARING THE SAME
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Lin, Yuan-Yuan
Abrégé
The present disclosure provides a semiconductor device includes a semiconductor substrate, a first metal plug, a second metal plug, a third metal plug, a fourth metal plug, and a boron nitride layer. The first metal plug and the second metal plug are disposed over a pattern-dense region of the semiconductor substrate. The third metal plug and the fourth metal plug are disposed over a pattern-loose region of the semiconductor substrate. The boron nitride layer is disposed over the semiconductor substrate. Each of the first metal plug and the second metal plug includes a barrier layer and a conductive feature. The barrier layer is contact with the semiconductor substrate. The conductive feature is disposed over the barrier layer. The conductive feature is separated from the semiconductor substrate by the barrier layer.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Hsiao, Chuan-Lin
Liao, Wei-Ming
Abrégé
A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Shen, Zhi-Xuan
Abrégé
A method of manufacturing a semiconductor includes: providing a stacked structure comprising a first oxide layer, a second oxide layer, and a metal layer stacked between the first oxide layer and the second oxide layer; patterning the second oxide layer; forming a mask layer on the patterned second oxide layer; introducing a gas mixture to the stacked structure; and performing a pulsing plasma process to the stacked structure through the mask layer to form at least one via running through the first oxide layer, the metal layer, and the second oxide layer.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Huang, Shih-Ting
Abrégé
A method of forming a semiconductor structure includes following steps. A substrate is provided. The substrate has an active region, an isolation structure adjacent to the active region, and a contact on the active region. A dielectric stack is formed on the substrate. A poly layer is formed on the dielectric stack. The poly layer and the dielectric stack are etched to form an opening to expose the contact of the substrate. A conductive film is formed in the opening and an ALD oxide layer is deposited on a sidewall of the opening. In addition, a semiconductor structure is also disclosed herein.
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Lo, Yi-Jen
Abrégé
The present disclosure provides a method of manufacturing a semiconductor device. The method includes: forming a first via and a second via on a semiconductor structure, wherein the semiconductor structure includes a first dielectric layer, a first barrier layer, a first metal, a second barrier layer, a second dielectric layer, a substrate, and a second metal; forming a third dielectric layer on the substrate and a bottom and the inner sidewalls of the first via and the second via; punching through the third dielectric layer on the bottom of the first via and the second via; forming a third barrier layer on the substrate and in the first via and the second via; removing oxides formed from the first metal and the second metal; forming a fourth barrier layer; and forming a conductive material in the first via and the second via.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
NANYA TECHNOLOGY CORPORATION (Taïwan, Province de Chine)
Inventeur(s)
Huang, Sheng-Fu
Shih, Shing-Yih
Abrégé
A semiconductor structure includes a first chip and a second chip bonded to the first chip. The first chip includes a first semiconductor substrate, a first multi-level interconnect structure over the first semiconductor substrate, a first redistribution layer (RDL) over a conductive line of the first multi-level interconnect structure, a compact layer over the first RDL and the first multi-level interconnect structure, a cap layer over the compact layer, and a metal pad on the first RDL. The second chip includes a second semiconductor substrate, a second multi-level interconnect structure over the second semiconductor substrate, and conductive structure extending from the second multi-level interconnect structure to the metal pad.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe