Circuits are provided that generate from an input signal one or more output clock signals having reduced skew. The input signal has transitions derived from the transitions of an original clock signal having a frequency that differs from the frequency of the output clock signal. The frequency of the output clock signal is a product from multiplying the frequency for the input signal and an integer ratio. The circuit includes an accumulator, a fractional phase detector, and a loop filter. The accumulator periodically adds a numerical offset value to a numerical phase value. The output clock signal is generated from this numerical phase value. The fractional phase detector generates from the numerical phase value a respective numerical phase error for each of the transitions of the input signal. The loop filter generates the numerical offset value from a filtering of the respective numerical phase errors.
H03L 7/085 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie
2.
CONFIGURABLE TRANSACTIONAL MEMORY FOR SYNCHRONIZING TRANSACTIONS
A configurable transactional memory (102) synchronizes transactions from clients (104-110). The configurable transactional memory (102) includes a memory buffer (120) and a transactional buffer (128). The memory buffer (120) includes allocation control (124) and storage (126), and the allocation control (124) is configurable to selectively allocate the storage between a transactional buffer (128) and a data buffer (130) for the data words. The transactional buffer (128) stores states (132-134) indicating each combination of a data word and a client for which the data word is referenced by a write access in the transaction in progress from the client. The transactional arbiter (122) generates the completion status for the transaction in progress from each client. The completion status is either committed for no collision or aborted for a collision. A collision is an access that references a data word of the transaction from the client following a write access that references the data word of another transaction in progress from another client.
At least one MOS parameter of a MOS fuse (200) is characterized to provide at least one MOS parameter reference value. Then, the MOS fuse (200) is programmed by applying a programming signal to the fuse terminals (204, 206) so that programming current flows through the fuse link (202). The fuse resistance is measured to provide a measured fuse resistance associated with a first logic value. A MOS parameter of the programmed MOS fuse is measured to provide a measured MOS parameter value. The measured MOS parameter value is compared to the reference MOS parameter value to determine a second logic value of the MOS fuse, and a bit value is output based on the comparison.
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
G11C 17/16 - Mémoires mortes programmables une seule fois; Mémoires semi-permanentes, p.ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p.ex. mémoires PROM utilisant des liaisons électriquement fusibles
H01L 27/10 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive
4.
SEMICONDUCTOR STACK ASSEMBLY HAVING REDUCED THERMAL SPREADING RESISTANCE AND METHODS OF MAKING SAME
Semiconductor assemblies having reduced thermal spreading resistance and methods of making the same are described. In an example, a semiconductor device (101) includes a primary integrated circuit (IC) die (102) and at least one secondary IC die (104) mounted on the primary IC die (102). A heat extraction element (110) includes a base (109) mounted to the semiconductor device (101) such that each of the at least one secondary IC die (104) is between the primary IC die (102) and the heat extraction element (110). At least one dummy fill (106) is adjacent the at least one secondary IC die (104), and each thermally couples the primary IC die (102) to the heat extraction element (110).
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/433 - Pièces auxiliaires caractérisées par leur forme, p.ex. pistons
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des groupes principaux , ou dans une seule sous-classe de , , p.ex. circuit hybrides
5.
BLOCK BOUNDARY DETECTION FOR A WIRELESS COMMUNICATION SYSTEM
Method and apparatus for block boundary detection is described. A signal is received. The signal is quantized to provide a quantized signal to at least one correlator (310, 400, 500, 610) the quantized signal being a sequence of samples. The sequence of samples and a reference template including totaling partial results from the at least one correlator (310, 400, 500, 610) are cross-correlated to provide a result, the result being a symbol timing synchronization responsive to the cross-correlation also known as block boundary detection. The cross-correlation is provided in part by combining by exclusive-ORing a regression vector obtained from the sequence of samples and a coefficient term vector obtained from the reference template.
H04L 27/28 - Systèmes utilisant des codes à fréquences multiples à émission simultanée de fréquences différentes, chacune représentant un élément de code
A method of minimizing power consumption in an integrated device is disclosed. The method comprises providing a plurality of circuit blocks having circuits for performing logic functions, wherein each circuit block consumes power in a static state (1202); coupling one of a plurality of operating voltages to each circuit block of the plurality of circuit blocks (1204); enabling a reduction of power consumed by a first set of circuit blocks by way of a first power reduction signal (1206); and enabling a reduction of power consumed by a second set of circuit blocks by way of a second power reduction signal (1208). A circuit (100, 200) for minimizing power consumption in a device is also disclosed.
H03K 19/00 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion
H03K 19/1778 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels pour l'adaptation des paramètres physiques
7.
REDUCTION OF JITTER IN A SEMICONDUCTOR DEVICE BY CONTROLLING PRINTED CIRCUIT BOARD AND PACKAGE SUBSTRATE STACKUP
A model and method are provided for lowering device jitter by controlling the stackup of PCB planes (1-24) so as to minimize inductance between a FPGA (105) and PCB voltage planes (3, 8, 13, 17, 22) for critical core voltages within the FPGA (105). Furthermore, a model and method are provided for lowering jitter by controlling the stackup of package substrate planes so as to minimize inductance between a die and substrate voltage planes for critical core voltages within the die.
Formation of a hybrid integrated circuit device (400) is described. A design for the integrated circuit (100) is obtained and separated into at least two portions responsive to component sizes. A first die (200) is formed for a first portion of the hybrid integrated circuit device (400) using at least in part a first minimum dimension lithography. A second die (300) is formed for a second portion of the device using at least in part a second minimum dimension lithography, where the second die (300) has the second minimum dimension lithography as a smallest lithography used for the forming of the second die (300). The first die (200) and the second die (300) are attached to one another via coupling interconnects respectively thereof to provide the hybrid integrated circuit device (400).
H01L 21/58 - Montage des dispositifs à semi-conducteurs sur des supports
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
9.
A DOUBLE EXPOSURE SEMICONDUCTOR PROCESS FOR IMPROVED PROCESS MARGIN
A double exposure semiconductor process is provided for improved process margin at reduced feature sizes. During a first processing sequence, features defining non-critical dimensions of a polysilicon interconnect structure are formed, while other portions of the polysilicon layer are left un-processed. During a second processing sequence, features that define the critical dimensions of the polysilicon interconnect structure are formed without the need to execute a photoresist trimming procedure. Accordingly, only an etch process is executed, which provides higher resolution processing to create the critical dimensions needed during the second processing sequence.
G03F 7/00 - Production par voie photomécanique, p.ex. photolithographique, de surfaces texturées, p.ex. surfaces imprimées; Matériaux à cet effet, p.ex. comportant des photoréserves; Appareillages spécialement adaptés à cet effet
G03F 7/40 - Traitement après le dépouillement selon l'image, p.ex. émaillage
10.
METHOD OF AND CIRCUIT FOR SUPPRESSING NOISE IN A CIRCUIT
A method of suppressing noise in a circuit (302) is disclosed. The method comprises providing a supply voltage (Vcc) to a first terminal (312) of the circuit; (302) providing a ground voltage to a second terminal (314) of the circuit; providing a clock signal to the circuit; and actively decoupling noise from at least one of the first terminal (312) and the second terminal (314) of the circuit (302) by actively decoupling noise synchronously with the clock signal. A circuit for suppressing noise in a circuit (302) is also disclosed.
A contact pad in an integrated circuit is disclosed. The contact pad comprises a flat portion comprising a base (302) of the contact pad; a plurality of projections (304, 306, 308, 310, 312) extending from and substantially perpendicular to the flat portion; and a solder ball (108, 124) attached to the projections and the flat portion. A method of forming a contact pad is also disclosed.
H01L 23/485 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées formées de structures en couches comprenant des couches conductrices et isolantes, p.ex. contacts planaires
12.
ONE-TIME-PROGRAMMABLE LOGIC BIT WITH MULTIPLE LOGIC ELEMENTS
A memory cell with a logic bit has a first one-time-programmable ("OTP") memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operator coupled to the first OTP memory element output and to the second OTP memory element output and provides a binary memory output of the memory cell. In a particular embodiment, the first OTP memory element is a different type of OTP memory than the second OTP memory element. Examples of the memory elements are polysilicon fuses having necks of different width, metsl fuses, and antifuses.
H01L 21/8246 - Structures de mémoires mortes (ROM)
G11C 17/16 - Mémoires mortes programmables une seule fois; Mémoires semi-permanentes, p.ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p.ex. mémoires PROM utilisant des liaisons électriquement fusibles
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
A method and apparatus for capacitance multiplication using two charge pumps. A first charge pump (206) provides a current signal (I216) that is first conducted by a resistor (310) of an RC network and then split into three current paths prior to being conducted by a capacitor of the RC network. A first current path provides current to the capacitor (306) of the RC network from node (320). A second current path multiplies the current conducted by capacitor (306) by a first current multiplication factor. A third current path provides current to a second charge pump (208), which multiplies the current from the first charge pump (206) by a second current multiplication factor that has a fractional value with an inverse magnitude sign relative to the first current multiplication factor. The combination of the second and third current paths effectively multiplies the capacitance magnitude of capacitor (306).
H03L 7/093 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
Described is an integrated circuit (IC) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and logic resources. The operand ports receive operands for processing, and a slice output port conveys processed results. Each slice additionally includes a feedback port connected to the respective slice output port, to support accumulate functions in this embodiment, and a cascade input port connected to the output port of an upstream slice to support cascading.
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
H03K 19/17748 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels des ressources de configuration
An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.
A programmable logic device includes a plurality of programmable multi-gigabit transceivers, programmable logic fabric, and a control module. Each of the plurality of programmable multi-gigabit transceivers is individually programmed to a desired transceiving mode of operation in accordance with a plurality of transceiver settings. The programmable logic fabric is operably coupled to the plurality of programmable multi-gigabit transceivers and is configured to process at least a portion of the data being transceived via the multi-gigabit transceivers. The control module is operably coupled to produce the plurality of transceiver settings based on a desired mode of operation for the programmable logic device.
G06F 15/76 - Architectures de calculateurs universels à programmes enregistrés
H03K 19/177 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle
An analog front-end having built-in equalization includes a control module and a tunable gain stage. The control module is operably coupled to provide a frequency response setting based on a channel response of a channel providing high-speed serial data to the analog front-end. The tunable gain stage includes a frequency dependent load and an amplifier input section. The frequency dependent load is adjusted based on the frequency response setting. The amplifier input section is operably coupled to the frequency dependent load and receives the high-speed serial data. In conjunction with the frequency dependent load, the amplifier input section amplifies and equalizes the high-speed serial data to produce an amplified and equalized serial data.
A transmit line driver with selectable slew rates and a common mode idle state comprises a capacitor array (186) of selectable capacitors coupled between a line driver (184) and a pre-driver (182) wherein a slew rate may be selected by the selectable capacitors. A common mode idle state is provided by coupling a selectable switch (214, 215) (MOSFET in the described embodiment) to a mirror device (198) that provides a bias current to the pre-driver wherein, when the bias current is removed by the switch, the pre-driver produces an output signal that is equal to the supply voltage for the circuit. Accordingly, a differential pair (202, 204) of the line driver are both biased on and provide a common mode idle state. The common mode idle state is equal to one half of an output signal magnitude for a logic one.
A Transmit line driver with selectable pre-emphasis and driver signal magnitudes comprises a primary current driver for setting a primary current level and a pre-emphasis current driver that provides an additional amount of current that is superimposed with or added to the primary current level produced by the primary current driver. The pre-emphasis current has either negative or positive magnitude based upon a pre-emphasis signal logic state. A first current selection module defines a reference signal that is used to select the primary current driver output signal magnitude in a first current mirror, while a second current selection module is used to define a second reference signal that selects a pre-emphasis current driver signal magnitude in a second current mirror. Logic generates a binary signal to both the first and second current selection modules to select the current levels as well as the pre-emphasis signal.
A method for channel bonding begins when a master transceiver receives a channel bonding sequence. The process continues with the master transceiver generating a channel bonding request and transmitting it and channel bonding configuration information to the slave transceiver. The process continues with each slave receiving the channel bonding sequence, the channel bonding request and the channel bonding configuration information. The process continues as each slave processes the channel bonding request and the channel bonding sequence in accordance with the channel bonding configuration information to determine individual slave channel bonding start information. The process continues as the master processes the channel bonding sequence in accordance with the channel bonding configuration information and the channel bonding request to determine master channel bonding start information.
An integrated circuit (IC) is disclosed having circuitry arranged in a plurality of columns. A column in the IC is essentially a series of aligned circuit elements of the same type that extends from a first edge of the IC to a second edge. In addition there may be a center column having circuit elements of different types.
H01L 27/118 - Circuits intégrés à tranche maîtresse
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
Method and apparatus for simulating operations of a circuit design that includes high-level components and HDL components. The high-level components of the design are simulated in a high-level modeling system (HLMS), and the HDL components of the design are simulated with an HDL simulator. Data values are converted from a data type of the HLMS to a logic vector compatible with the HDL simulator for each data value to be input to the HDL simulator, and a logic vector is converted from the HDL simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL simulator. Events are scheduled for input to the HDL simulator as a function of the time of HLMS events and a maximum response time of the HDL components.
23.
FPGA ARCHITECTURE WITH MIXED INTERCONNECT RESOURCES
An FPGA includes a programmable interconnect structure in which the interconnect resources are divided into two groups. A first subset of the interconnect resources are optimized for high speed. A second subset of the interconnect resources are optimized for low power consumption. In some embodiments, the transistors of the first and second subsets have different threshold voltages. Transistors in the first subset, being optimized for speed, have a lower threshold voltage than transistors in the second subset, which are optimized for low power consumption. The difference in threshold voltages can be accomplished by using different doping levels, wells biased to different voltage levels, or using other well-known means. In some embodiments, the first subset of the interconnect resources includes buffers coupled to a higher voltage level than the second subset. In some embodiments, the first subset includes buffers manufactured using larger transistors than those in the second subset.
H03K 19/17758 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels des ressources de configuration pour accélérer la configuration ou la reconfiguration
24.
CLOCK AND DATA RECOVERY PHASE-LOCKED LOOP AND HIGH-SPEED PHASE DETECTOR ARCHITECTURE
A clock recovery circuit and a high speed phase detector circuit that operate at a clock speed equal to one-half the input data rate (i.e., a half-rate clock) are presented. The clock recovery circuit uses dual input latches to sample the incoming serial data an both the rising edge and falling edge of a half-rate clock signal to provide equivalent full data rate clock recovery. The clock recovery circuit functions to maintain the half-rate clock transitions in the center of the incoming serial data bits. The clock recovery circuit includes a phase detector, charge pump, controlled oscillation module and a feedback module. The phase detector produces information on the phase and data transitions in the incoming data signal to the charge pump. Generally, the circuit is delay insensitive and receives phase and transition information staggered relative to each other. The high speed phase detector circuit provides phase information and transition information from incoming serial data. The high speed phase detector circuit samples the incoming serial data on both the rising edge and falling edge of the half-rate clock to provide equivalent full high speed data rate sampling. The high speed phase detector circuit generates a delay between the phase information and the transition information. The phase information is produced in a first bit period and the transition information is produced in a second bit period relative to the first bit period.
H03L 7/085 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie
H03D 3/24 - Modifications de démodulateurs pour rejeter ou supprimer des variations d'amplitude au moyen de circuits oscillateurs verrouillés
H03D 13/00 - Circuits de comparaison de phase ou de fréquence de deux oscillations mutuellement indépendantes
H03L 7/087 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie utilisant au moins deux détecteurs de phase ou un détecteur de fréquence et de phase dans la boucle
H03L 7/089 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence engendrant des impulsions d'augmentation ou de diminution
H03L 7/091 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence utilisant un dispositif d'échantillonnage
H03L 7/10 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase pour assurer la synchronisation initiale ou pour élargir le domaine d'accrochage
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p.ex. en utilisant une boucle verrouillée en phase
25.
RECONFIGURATION OF THE PROGRAMMABLE LOGIC OF AN INTEGRATED CIRCUIT
A method of partially reconfiguring an IC having programmable modules that includes the steps of reading a frame of configuration information from the configuration memory array; modifying at least part of the configuration information, thereby creating a modified frame of configuration information; and overwriting the existing frame of configuration information in the configuration memory array with the modified frame, thereby partially reconfiguring the IC.
H03K 19/17728 - Blocs logiques reconfigurables, p.ex. tables de consultation
H03K 19/17748 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels des ressources de configuration
G11C 16/10 - Circuits de programmation ou d'entrée de données
An apparatus and method for adding input voltage signals. First 206 and second 208 input voltage signals are respectively sampled onto first 218 and second 228 capacitors during a first clock phase 202. In response to a second clock phase 204, the first sampled input voltage 206 that is held on the first capacitor 218 is coupled to the negative input terminal 236 of an amplifier 230, and the second sampled voltage 208 held on the second capacitor 228 is coupled to the positive terminal 240 of the amplifier 230. A feedback voltage is provided from the amplifier output 216 to the negative amplifier input 236 via the first capacitor 218 during the second clock phase 204. The first 206 and second 208 input voltage signals are added at the amplifier 230 during the second clock phase 204 to output 216 the sum in response to the sampled input voltage signals and the output feedback, whereby the resulting transfer function is independent of capacitor mismatch and non-linearity.
G06G 7/14 - Dispositions pour l'exécution d'opérations de calcul, p.ex. amplificateurs spécialement adaptés à cet effet pour l'addition ou la soustraction
brevets
