Embodiments herein describe a processor system that inciudes an integrated, adaptive accelerator. In one embodiment, the processor system includes multiple core complex chiplets that each contain one or processing cores for a host CPU. In addition the processor system inciudes an accelerator chiplet. The processor system can assign one or more of the core complex chiplets to the accelerator chiplet to form an IO device while the remaining core complex chiplets form the CPU for the host. In this manner, rather than the accelerator and the CPU having independent computer resources, the accelerator can be integrated into the processor system of the host so that hardware resources can be divided between the CPU and the accelerator depending on the needs of the particular application(s) executed by the host.
An integrated circuit device includes multiple heterogeneous functional circuit blocks and interface circuitry that permits the heterogeneous functional circuit blocks to exchange data with one another using communication protocols of the respective heterogeneous functional circuit blocks. The IC device includes fixed-function circuitry, user-configurable circuitry (e.g., programmable logic), and/or embedded processors/cores. A functional circuit block may be configured in fixed-function circuitry or in the user-configurable circuitry (i.e., as a plug-in). The interface circuitry includes a network-on-a-chip (NoC), an adaptor configured in the user-configurable circuitry, and/or memory. The memory may be accessible to the functional circuit blocks through an adaptor configured the user-configurable circuitry and/or through the NoC. The IC device may be configured as a SmartNIC, DPU, or other type of system-on-a-chip (SoC).
Embodiments herein describe creating tag bindings that can be used to assign tags to data corresponding to different tenants using a data processing unit (DPU) such as a SmartNIC, Artificial Intelligence Unit, Network Storage Unit, Database Acceleration Units, and the like. In one embodiment, the DPUs include tag gateways at the interface between a host and network element (e.g., a switch) that recognize and tag the data corresponding to the tenants. These tags are then recognized by data processing engines (DPEs) in the DPU such as Al engines, cryptographic engines, encryption engines, Direct Memory Access (DMA) engines, and the like. These DPEs can be configured to perform tag policies that provide security isolation and performance isolation between the tenants.
Embodiments herein describe a decentralized chip-to-chip (C2C) interface architecture to transport memory mapped traffic amongst heterogeneous IC devices in a packetized, scalable, and configurable manner. An IC chip may include functional circuitry that exchanges memory-mapped traffic with an off-chip device, a NoC that packetizes and de-packetizes memory-mapped traffic and routes the packetized memory-mapped traffic between the functional circuitry and the off-chip device, and NoC inter-chip bridge (NICE) circuitry that interfaces between the NoC and the off-chip device over C2C interconnections. The NICE circuitry may be configurable in a full mode to map packetized memory-mapped traffic to the C2C interconnections in a 1 :1 fashion and in a compressed to map packetized memory¬ mapped traffic to the C2C interconnections in a less-than 1 :1 fashion.
An integrated circuit includes a plurality of kernels and a virtual machine coupled to the plurality of kernels. The virtual machine is configured to interpret instructions directed to different ones of the plurality of kernels. The virtual machine is configured to control operation of the different ones of the plurality of kernels responsive to the instructions.
G06F 9/50 - Allocation de ressources, p.ex. de l'unité centrale de traitement [UCT]
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
Embodiments herein describe a distributed configuration system for a configurable device, instead of relying solely on a central configuration manager to distribute configuration information to various subsystems in the device, the embodiments herein include configuration interface managers (CIM) that are distributed in different regions of the device, whether those regions are in one integrated circuit or include multiple integrated circuits. The embodiments can still use a central configuration manager to distribute configuration information in a device image to the plurality of Cl Ms, which can then forward the configuration information to their assigned regions.
An integrated circuit (IC) can include a data processing array including a plurality of compute tiles arranged in a grid. The IC can include an array interface coupled to the data processing array. The array interface includes a plurality of interface tiles. Each interface tile includes a plurality of direct memory access circuits. The IC can include a network-on-chip (NoC) coupled to the array interface. Each direct memory access circuit is communicatively linked to the NoC via an independent communication channel.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p.ex. plusieurs processeurs de données à instruction unique
8.
NETWORK-ON-CHIP ARCHITECTURE FOR HANDLING DIFFERENT DATA SIZES
An integrated circuit (IC) includes a Network-on-Chip (NoC). The NoC includes a plurality of NoC master circuits, a plurality of NoC slave circuits, and a plurality of switches. The plurality of switches are interconnected and communicatively link the plurality of NoC master circuits with the plurality of NoC slave circuits. The plurality of switches are configured to receive data of different widths during operation and implement different operating modes for forwarding the data based on the different widths.
Embodiments herein describe a SoC with one or more untrusted islands that can host one or more roles or tenants in a data center environment (e.g., a cloud computing environment). In one embodiment, a secure shell encapsulates the untrusted islands with a secure application programming interface (API) to access other hardware resources in the SoC. Hardware resources in the SoC (e.g., HardIP, SoftIP, or both), can either be secure/trusted, or rely on the secure shell to ensure confidentiality.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 21/76 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits intégrés à application spécifique [ASIC] ou les dispositifs programmables, p.ex. les réseaux de portes programmables [FPGA] ou les circuits logiques programmables [PLD]
10.
EFFICIENCY AND QUALITY OF SERVICE IMPROVEMENTS FOR SYSTEMS WITH HIGHER BANDWIDTH CLIENTS MIXED WITH LOWER BANDWIDTH CLIENTS
Methods and apparatus relating to transmission on physical channels, such as in networks on chips (NoCs) or between chiplets, are provided. One example apparatus generally includes a higher bandwidth client; a lower bandwidth client; a first destination; a second destination; and multiple physical channels coupled between the higher bandwidth client, the lower bandwidth client, the first destination, and the second destination, wherein the higher bandwidth client is configured to send first traffic, aggregated across the multiple physical channels, to the first destination and wherein the lower bandwidth client is configured to send second traffic, concurrently with sending the first traffic, from the lower bandwidth client, dispersed over two or more of the multiple physical channels, to the second destination.
Embodiments herein describe wrapping non-safety compliant hardware resources with error detection checking to satisfy a safety standard. Doing so permits non-safety compliant hardware to be used to perform one or more tasks in a system that, as a whole, satisfies a particular safety standard (e.g., one of the ASIL QM, A, B, C, and D grades).
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G05B 19/042 - Commande à programme autre que la commande numérique, c.à d. dans des automatismes à séquence ou dans des automates à logique utilisant des processeurs numériques
G06F 21/64 - Protection de l’intégrité des données, p.ex. par sommes de contrôle, certificats ou signatures
G06F 21/72 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits de cryptographie
G06F 21/85 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs d’interconnexion, p.ex. les dispositifs connectés à un bus ou les dispositifs en ligne
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
H04W 4/48 - Services spécialement adaptés à des environnements, à des situations ou à des fins spécifiques pour les véhicules, p.ex. communication véhicule-piétons pour la communication dans le véhicule
H04W 12/106 - Intégrité des paquets ou des messages
Embodiments herein describe using an adaptive chip-to-chip (C2C) interface to interconnect two chips, wherein the adaptive C2C interface indudes circuitry for performing multiple different C2C protocois to communicate with the other chip. One or both of the chips in the C2C connection can include the adaptive C2C interface. During boot time, the adaptive C2C interface is configured to perform one of the different C2C protocois. During runtime, the chip then uses the selected C2C protocol to communicate with the other chip in the C2C connection.
Embodiments herein describe partitioning hardware and software in a system on a chip (SoC) into a hierarchy. In one embodiment, the hierarchy includes three levels of hardware-software configurations, enabling security and/or safety isolation across those three levels. The levels can cover the processor subsystem with compute, memory, acceleration, and peripheral resources shared or divided across those three levels.
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
An integrated circuit (IC) device for detecting errors within a register, the IC device includes registers and parity checking circuitry. The parity checking circuitry is coupled to the registers and comprises a first parity circuity, a second parity circuit, and error detection circuitry. The first parity circuit receives first register values from the registers and determine a first value from the first register values. The second parity circuit is receives second register values from the registers and determines a second value from the second register values. The error detection circuitry compares the first value and the second value to detect a first error within the registers, and output an error signal indicating the first error.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
Embodiments herein describe end-to-end bindings to create zones that extend between different components in a SoC, such as an I/O gateway, a processor subsystem, a NoC, storage and data accelerators, programmable logic, etc. Each zone can be assigned to a different domain that is controlled by a tenant such as an external host, or software executing on that host. Embodiments herein create end-to-end bindings between acceleration engines, I/O gateways, and embedded cores in SoCs. Instead of these components being treated as disparate monolithic components, the bindings divide up the hardware and memory resources across components that make up the SoC, into different zones. Those zones in turn can have unique bindings to multiple tenants. The bindings can be configured in bridges between components to divide resources into the zones to enable tenants of those zones to have dedicated available resources that are secure from the other tenants.
A network interface device (109) has data path circuitry (102,) configured to cause data to be moved into and/or out of the network interface device (109). The data path circuitry comprises: first circuitry (128) for providing one or more data processing operations; and interface circuitry (126) supporting channels. The channels comprises command channels receiving command information from a plurality of data path circuitry user instances (101), event channels providing respective command completion information to the plurality of data path user instances (101); and data channels providing the associated data.
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
G06F 12/0806 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement
H04L 49/00 - TRANSMISSION D'INFORMATION NUMÉRIQUE, p.ex. COMMUNICATION TÉLÉGRAPHIQUE Éléments de commutation de paquets
H04L 49/101 - TRANSMISSION D'INFORMATION NUMÉRIQUE, p.ex. COMMUNICATION TÉLÉGRAPHIQUE Éléments de commutation de paquets caractérisés par la construction de la matrice de commutation utilisant un crossbar ou une matrice
H04L 49/109 - TRANSMISSION D'INFORMATION NUMÉRIQUE, p.ex. COMMUNICATION TÉLÉGRAPHIQUE Éléments de commutation de paquets caractérisés par la construction de la matrice de commutation intégrés sur micropuce, p.ex. interrupteurs sur puce
G06F 9/50 - Allocation de ressources, p.ex. de l'unité centrale de traitement [UCT]
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 13/12 - Commande par programme pour dispositifs périphériques utilisant des matériels indépendants du processeur central, p.ex. canal ou processeur périphérique
17.
ADAPTIVE INTEGRITY LEVELS IN ELECTRONIC AND PROGRAMMABLE LOGIC SYSTEMS
Methods and apparatus for adaptive integrity levels in electronic and programmable logic systems. In one example, an interface for communication between a first component and a second component is provided. The interface includes logic configured to change an integrity level for a communication from the first component to the second component during operation of the first component and the second component.
G06F 21/85 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs d’interconnexion, p.ex. les dispositifs connectés à un bus ou les dispositifs en ligne
G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
G06F 11/08 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle
Clock generation circuitry includes quadrature locked loop circuitry having first injection locked oscillator circuitry, second injection locked oscillator circuitry, and XOR circuitry. The first injection locked oscillator circuitry receives a first input signal and a second input signal and outputs first clock signals. The first input signal and the second input signal correspond to a reference clock signal. The second injection locked oscillator circuitry is coupled to outputs of the first injection locked oscillator circuitry, and receives the first clock signals and generates second clock signals. The XOR circuitry receives the second clock signals and generates a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. The frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are greater than the frequency of the reference clock signal.
H03L 7/099 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03L 7/24 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence directement appliqué au générateur
Embodiments herein describe offloading encryption activities to a network interface controller/card (NIC) (e.g., a SmartNIC) which frees up server compute resources to focus on executing customer applications. In one embodiment, the smart NIC includes a system on a chip (SoC) implemented on an integrated circuit (IC) that includes an embedded processor. Instead of executing a transport layer security (TLS) stack entirely in the embedded processor, the embodiments herein offload certain TLS tasks to a Public Key Infrastructure (PKI) accelerator such as generating public-private key pairs.
G06F 21/72 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits de cryptographie
20.
TRANSMIT DRIVER ARCHITECTURE WITH A JTAG CONFIGURATION MODE, EXTENDED EQUALIZATION RANGE, AND MULTIPLE POWER SUPPLY DOMAINS
A transmit driver architecture with a test mode (e.g., a JTAG configuration mode), extended equalization range, and/or multiple power supply domains. One example transmit driver circuit generally includes one or more driver unit cells having a differential input node pair configured to receive an input data signal and having a differential output node pair configured to output an output data signal; a plurality of power switches coupled between the differential output node pair and one or more power supply rails; a first set of one or more drivers coupled between a first test node of a differential test data path and a first output node of the differential output node pair; and a second set of one or more drivers coupled between a second test node of the differential test data path and a second output node of the differential output node pair.
Synchronizing system resources of a multi-socket data processing system can include providing, from a primary System-on-Chip (SOC), a trigger event to a global synchronization circuit. The primary SOC is one of a plurality of SOCS and the trigger event is provided over a first sideband channel. In response to the trigger event, the global synchronization circuit is capable of broadcasting a synchronization event to the plurality of SOCS over a second sideband channel. In response to the synchronization event, the system resource of each SOC of the plurality of SOCS is programmed with a common value. The programming synchronizes the system resources of the plurality of SOCS.
Embodiments herein describe adapting a PIM model to compensate for changing PIM interference. A PIM model can include circuitry that generates a PIM compensation value that compensates for (i.e., mitigates or subtracts) PIM interference caused by transmitting two or more transmitter (TX) carriers in the same path. The disclosed adaptive scheme generates updated coefficients for the PIM model which are calculated after the RX signal has been removed from the RX channel. In this manner, as the PIM interference changes due to environmental conditions (e.g., temperature at the base station), the adaptive scheme can update the PIM model to generate a PIM compensation value that cancels the PIM interference.
H04B 1/10 - Dispositifs associés au récepteur pour limiter ou supprimer le bruit et les interférences
H04B 1/525 - Dispositions hybrides, c. à d. dispositions pour la transition d’une transmission bilatérale sur une voie à une transmission unidirectionnelle sur chacune des deux voies ou vice versa avec des moyens de réduction de la fuite du signal de l’émetteur vers le récepteur
23.
MULTIPATH MEMORY WITH STATIC OR DYNAMIC MAPPING TO COHERENT OR MMIO SPACE
Embodiments herein describe memories in a processor system in an integrated circuit (IC) that can be assigned to either a cache coherent domain or an I/O domain, rather than being statically assigned by a designer of the IC. That is, the user or customer can assign the memories to domain that best suits their desires. Further, the memories can be reassigned to a different domain if the user later changes her mind.
G06F 9/50 - Allocation de ressources, p.ex. de l'unité centrale de traitement [UCT]
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
Methods, systems, and apparatus described herein make a multi-level PAM signal (PAM-N signal) at a transmitter using CMOS-based components. By forming the PAM-N signal at the transmitter, receivers do not have to recombine and/or realign multiple signals and only employs a single transmission line channel (or two transmission line channels in differential implementations) to convey the data stream to the receiver from the transmitter.
Embodiments herein describe on-demand packetization where data (115) that is too large to be converted directly into data words (DWs) (130) for a chip-to-chip (C2C) interface (140) are packetized instead. When identifying a protocol word (115) that is larger than the DW (130) of the C2C interface (140), a protocol layer (120a) can perform packetization where a plurality of protocol words (115) are packetized and sent as a transfer. In one embodiment, the protocol layer (120a) removes some or all of the control data or signals in the protocol words (120a) so that the protocol words no longer exceed the size of the DW (130). These shortened protocol words (115) can then be mapped to DWs (130) and transmitted as separate packets on the C2C (140). The protocol layer (120a) can then collect the portion of the control data that was removed from the protocol words (115) and transmit this data as a separate packet on the C2C interface (140).
Transmitter circuitry includes inversion circuitry, first transform circuitry, and selection circuitry. The inversion circuitry generates a first transformed data word by inverting one or more of a plurality of bits of a first data word. The first transform circuitry generates a second transformed data word by performing a first invertible operation on the first data word and a second data word. The selection circuitry selects one of the first data word, the first transformed data word, and the second transformed data word based on a first number of bit inversions between the first data word and the second data word, a second number of bit inversions between the first transformed data word and the second data word, and a third number of bit inversions between the second transformed data word and the second data word. The selection circuitry further outputs the selected data word.
Using multiple overlays with a data processing array includes loading an application in a data processing array. The data processing array includes a plurality of compute tiles each having a processor. The application specifies kernels executable by the processors and implements stream channels that convey data to the plurality of compute tiles. During runtime of the application, a plurality of overlays are sequentially implemented in the data processing array. Each overlay implements a different mode of data movement in the data processing array via the stream channels. For each overlay implemented, a workload is performed by moving data to the plurality of compute tiles based on the respective mode of data movement.
Receiver circuitry (122) for a communication system includes signal processing circuitry (213), voltage digital-to-analog converter (DAC) circuitry (229), and slicer circuitry (218, 220). The signal processing circuitry receives a data signal (130) and generate a processed data signal. The voltage DAC circuitry generates a first threshold reference voltage (235). The slicer circuitry is coupled to an output of the signal processing circuitry. The slicer circuitry includes a capture flip-flop (CapFF) circuit that receives the processed data signal and the first threshold reference voltage (235). The CapFF circuit further generates a first data signal (218out, 220out). The first CapFF circuit includes a first offset compensation circuit (223 or 225) that adjusts a parasitic capacitance of the first CapFF circuit.
H03K 5/24 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p.ex. la pente, l'intégrale la caractéristique étant l'amplitude
H04L 25/06 - Moyens pour rétablir le niveau à courant continu; Correction de distorsion de polarisation
29.
IN-PACKAGE PASSIVE INDUCTIVE ELEMENT FOR REFLECTION MITIGATION
A package device comprises a first transceiver (110) comprising a first integrated circuit (IC) die and transmitter circuitry (112), and a second transceiver (120) comprising a second IC die and receiver circuitry (124). The receiver circuitry is coupled to the transmitter circuitry via a channel (140). The package device further comprises an interconnection device (130) connected to the first IC die and the second IC die. The interconnection device comprises the channel (140) connecting the transmitter circuitry with the receiver circuitry, and a passive inductive element (142) disposed external to the first IC die and the second IC die and along the channel.
H01F 17/00 - Inductances fixes du type pour signaux
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
A network interface device has a data source, a data sink and an interconnect configured to receive data from the data source and to output data to the data sink. The interconnect has a memory having memory cells. Each memory cell has a width which matches a bus segment width. The memory is configured to receive a first write output with a width corresponding to the bus segment width. The write output comprises first data to be written to a first memory cell of the memory, the first data being from the data source.
In one example, receiver circuitry for a communication system comprises signal processing circuitry configured to receive a data signal and generate a processed data signal, and error slicer circuitry. The error slicer circuitry is coupled to the output of the signal processing circuitry, and configured to receive the processed data signal. The error slicer circuitry comprises a first error slicer configured to receive a clock signal, and output a first error signal based on a first state of the clock signal and processed data signal. The first error slicer is further configured to output a second error signal based on a second state of the clock signal and the processed data signal.
Embodiments herein describe a describe an interface shell in a SmartNIC that reduces data-copy overhead in CPU-centric solutions that rely on hardware compute engine (which can include one or more accelerators). The interface shell offloads tag matching and address translation without CPU involvement. Moreover, the interface shell enables the compute engine to read messages directly from the network without extra data copy - i.e., without first copying the data into the CPU's memory.
Embodiments herein describe an integrated circuit that includes a NoC with at least two levels of switching: a sparse network and a non-blocking network. In one embodiment, the non-blocking network is a localized interconnect that provides an interface between the sparse network in the NoC and a memory system that requires additional bandwidth such as HBM2/3 or DDRS. Hardware elements connected to the NoC that do not need the additional benefits provided by the non-blocking network can connect solely to the sparse network. In this manner, the NoC provides a sparse network (which has a lower density of switching elements) for providing communication between lower bandwidth hardware elements and a localized non-blocking network for facilitating communication between the sparse network and higher bandwidth hardware elements.
Embodiments herein describe a multi-port memory system that includes one or more single port memories (e.g., a memory that can perform only one read or one write at any given time, referred to as a 1 W or 1 R memory). That is, the multi- port memory system can perform multiple read and writes in parallel (e.g., 1 R/1W, 1 R/3W, 2R/2W, 3R/1 W, etc.) even though the memory in the system can only perform one read or one write at any given time. The advantage of doing so is a reduction in area and power.
Embodiments herein describe an integrated circuit with a digital front end (DFE) that includes multiple hardened mixers that can be configured to support multiple different radio paths. The DFE provides the ability to distribute the processing across the multiple mixers, which can be combined and synchronized to create a larger mixer or may be used in other combinations to create multiple discrete mixers.
An integrated circuit can include a data processing engine (DPE) array having a plurality of tiles. The plurality of tiles can include a plurality of DPE tiles, wherein each DPE tile includes a stream switch, a core configured to perform operations, and a memory module. The plurality of tiles can include a plurality of memory tiles, wherein each memory tile includes a stream switch, a direct memory access (DMA) engine, and a random-access memory. The DMA engine of each memory tile may be configured to access the random-access memory within the same memory tile and the random-access memory of at least one other memory tile. Selected ones of the plurality of DPE tiles may be configured to access selected ones of the plurality of memory tiles via the stream switches.
A network interface device comprises an input configured to receive a storage response comprising a plurality of packets of data, one or more packets comprising a header part and data to be stored, the header part comprising a transport protocol header and a data storage application header. A first packet processor is configured to receive two or more of said plurality of packets and perform transport protocol processing of the received packets to provide transport protocol processed packets A second packet processor configured to receive the transport protocol processed packets from the first packet processor, to write the data to be stored of the received packets to memory and to provide the data storage application header and a pointer to a location in the memory to which the data has been written.
A network interface device comprises a streaming data processing path comprising a first data processing engine and hubs. A first scheduler associated with a first hub controls an output of data by the first hub to the first data processing engine and a second scheduler associated with a second hub controls an output of data by the second hub. The first hub is arranged upstream of the first data processing engine on the data processing path and is configured to receive data from a first upstream data path entity and from a first data processing entity implemented in programmable circuitry via a data ingress interface of the first hub. The first data processing engine is configured to receive data from the first hub, process the received data and output the processed data to the second hub arranged downstream of first data processing engine.
A network interface device comprises a first area of trust comprising a first part of the network interface device, the first part comprising one or more first kernels. A second area of trust comprising a second part of the network interface device different to said first part is provided, the second part comprising one or more second kernels. A communication link is provided between the first area of trust and the second area of trust. At least one of the first and second areas of trust is provided with isolation circuitry configured to control which data which is passed to the other of the first and second areas via the communication link.
The embodiments herein describe a 3D SmartNIC that spatially distributes compute, storage, or network functions in three dimensions using a plurality of layers. That is, unlike current SmartNIC that can perform acceleration functions in a 2D, a 3D Smart can distribute these functions across multiple stacked layers, where each layer can communicate directly or indirectly with the other layers.
Disclosed methods and systems involve, prior to mapping logic of the module to a target integrated circuit (1C) technology, estimating total delay of a module of a circuit design and determining whether or not the module is timing critical based on the total delay of the module and a timing constraint. Also prior to mapping, the module is restructured for timing optimization in response to determining that the module is timing critical. In response to determining that the module is not timing critical, and prior to mapping, the module is restructured for area optimization. The elements of the module are then mapped to the circuit elements of the target 1C technology, followed by place-and-route and generating implementation data for making an 1C that implements the circuit design.
G06F 119/12 - Analyse temporelle ou optimisation temporelle
G06F 30/34 - Conception de circuits pour circuits reconfigurables, p.ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
42.
A CIRCUIT FOR AND METHOD OF PROCESSING A DATA STREAM
A circuit for processing a data stream is described. The circuit comprises a burst phase detector configured to receive a data input signal; a clocking circuit coupled to the burst phase detector, wherein the clocking circuit is configured to receive a delayed data input signal and to receive a data stream phase signal and a data stream detect signal; and a programmable clock generator configured to receive a plurality of clock signals; wherein a selected clock signal of the plurality of clock signals is generated by the programmable clock generator and provided to the burst phase detector and the clocking circuit.
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
H03L 7/091 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence utilisant un dispositif d'échantillonnage
Examples described herein generally relate to clock tree routing in a chip stack. In an example, a multi-chip device includes a chip stack. The chip stack includes chips (102, 104, 106, 108). The chip stack includes a clock tree (902, 904). In-chip routing of the clock tree is contained within one logical chip of the chip stack. The chip stack includes leaf nodes disposed in respective chips. Each leaf node of the leaf nodes is electrically connected to the clock tree through a respective leaf-level connection bridge (922, 924). The respective leaf-level connection bridge extends in an out-of-chip direction through a plurality of the chips.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
44.
TEMPERATURE-LOCKED LOOP FOR OPTICAL ELEMENTS HAVING A TEMPERATURE-DEPENDENT RESPONSE
Examples described herein generally relate to a temperature-locked loop for optical elements. In an example, a device includes a controller and a digital-to- analog converter (DAC). The controller includes a DC-controllable transimpedance stage (DCTS), a sheer circuit, and a processor. The DCTS is configured to be coupled to a photodiode. An input node of the sheer circuit is coupled to an output node of the DCTS. The processor has an input node coupled to an output node of the sheer circuit. The DAC has an input node coupled to an output node of the processor and is configured to be coupled to a heater. The processor is configured to control (i) the DCTS to reduce a DC component of a signal on the output node of the DCTS and (ii) an output voltage on the output node of the DAC, both based on a signal output by the sheer circuit.
H04B 10/80 - Aspects optiques concernant l’utilisation de la transmission optique pour des applications spécifiques non prévues dans les groupes , p.ex. alimentation par faisceau optique ou transmission optique dans l’eau
H04B 10/69 - Dispositions électriques dans le récepteur
45.
MODEL-BASED DESIGN AND PARTITIONING FOR HETEROGENEOUS INTEGRATED CIRCUITS
Model-based implementation of a design for a heterogeneous integrated circuit can include converting a model, created as a data structure using a modeling system, into a data flow graph, wherein the model represents a design for implementation in an integrated circuit having a plurality of systems, the systems being heterogeneous, classifying nodes of the data flow graph for implementation in different ones of the plurality of systems of the integrated circuit, and partitioning the data flow graph into a plurality of sub-graphs based on the classifying, wherein each sub-graph corresponds to a different one of the plurality of systems. From each sub-graph, a portion of high-level language (HLL) program code can be generated. Each portion of HLL program code may be specific to the system corresponding to the sub-graph from which the portion of HLL program code was generated.
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
Embodiments herein describe a hardware accelerator (e.g., a network acceleration engine) for a blockchain machine or node. The hardware accelerator parses packets containing separate components of a block of transactions to generate data to perform a validation process. To avoid the latency that comes with using software, the embodiments herein describe a protocol processor in the hardware accelerator that parses the packets and prepares the data so it can be consumed by downstream components in the accelerator without software intervention. These downstream components can then perform a validation operation to validate one or more transactions before those transactions are committed (i.e., added) to a ledger of a permissioned blockchain.
G06F 21/76 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits intégrés à application spécifique [ASIC] ou les dispositifs programmables, p.ex. les réseaux de portes programmables [FPGA] ou les circuits logiques programmables [PLD]
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
47.
HIGH THROUGHPUT CIRCUIT ARCHITECTURE FOR HARDWARE ACCELERATION
A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.
Examples herein describe a programmable traffic management engine that includes both programmable and non-programmable hardware components. The non-programmable hardware components are used to generate features that can then be used to perform different traffic management algorithms. Depending on which traffic management algorithm the PTM engine is configured to do, the PTM engine may use a subset (or all) of the features to perform the algorithm. The programmable hardware components in the PTM engine are programmable (e.g., customizable) by the user to perform a selected algorithm using some or all of the features provided by the non-programmable hardware components.
Examples described herein generally relate to communication between integrated circuit (1C) dies in a wafer-level fan-out package. In an example, an electronic device includes a wafer-level fan-out package. The wafer-level fan-out package includes a first integrated circuit (1C) die, a second 1C die, and a redistribution structure. The first 1C die includes a transmitter circuit. The second 1C die includes a receiver circuit. The redistribution structure includes physical channels electrically connected to and between the transmitter circuit and the receiver circuit. The transmitter circuit is configured to transmit multiple single- ended data signals and a differential clock signal through the physical channels to the receiver circuit. The receiver circuit is configured to capture data from the multiple single-ended data signals using a first single-ended clock signal based on the differential clock signal.
H03K 19/17796 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels pour l'adaptation des paramètres physiques pour la disposition physique des blocs
H01L 23/552 - Protection contre les radiations, p.ex. la lumière
50.
VIRTUAL HOT PLUG SYSTEM AND METHOD FOR PCIE DEVICES
A method for managing a pool of physical functions in a PCIe integrated endpoint includes receiving a configuration instruction indicating a topology for a PCIe connected integrated endpoint (IE), and implementing the topology on the IE. The method further includes receiving a hot plug instruction, and, based at least in part, on the hot plug instruction, adding or removing a virtual endpoint (vEP) to or from a virtual downstream port (vDSP) on the IE.
Embodiments herein describe transferring ownership of data (e.g., cachelines or blocks of data comprising multiple cachelines) from a host to hardware in an I/O device. In one embodiment, the host and I/O device (e.g., an accelerator) are part of a cache-coherent system where ownership of data can be transferred from a home agent (HA) in the host to a local HA in the I/O device - e.g., a computational slave agent (CSA). That way, a function on the I/O device (e.g., an accelerator function) can request data from the local HA without these requests having to be sent to the host HA. Further, the accelerator function can indicate whether the local HA tracks the data on a cacheline-basis or by a data block (e.g., multiple cachelines). This provides flexibility that can reduce overhead from tracking the data, depending on the function's desired use of the data.
Examples described herein generally relate to integrated circuits that include a latch-based level shifter circuit with self-biasing. In an example, an integrated circuit includes first and second latches and an output stage circuit. Each of the first and second latches includes a bias circuit electrically connected to a respective latch node and configured to provide a bias voltage at the respective latch node, which is electrically coupled to a signal input node. The output stage circuit has first and second input nodes electrically connected to first and second output nodes of the first and second latches, respectively, and a third output node. The output stage circuit is configured to responsively pull up and pull down a voltage of the third output node in response to respective voltages of the first and second input nodes.
H03K 19/0185 - Dispositions pour le couplage; Dispositions pour l'interface utilisant uniquement des transistors à effet de champ
H04B 10/516 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs - Détails du codage ou de la modulation
H04B 17/18 - Surveillance en fonctionnement normal
53.
STATIC CONFIGURATION OF ACCELERATOR CARD SECURITY MODES
An accelerator card can include a read-only memory configured to store a security identifier in a designated field therein and a satellite controller configured to read the security identifier in response to a reset event. The satellite controller is configured to select, based on the security identifier, a security mode from a plurality of security modes and implement the selected security mode in the accelerator card.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 21/74 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information opérant en mode dual ou compartimenté, c. à d. avec au moins un mode sécurisé
54.
MULTI-DIE INTEGRATED CIRCUIT WITH DATA PROCESSING ENGINE ARRAY
A multi-die integrated circuit (IC) can include an interposer and a first die coupled to the interposer. The first die can include a data processing engine (DPE) array, wherein the DPE array includes a plurality of DPEs and a DPE interface coupled to the plurality of DPEs. The DPE interface has a logical interface and a physical interface. The multi-die IC also can include a second die coupled to the interposer. The second die can include a die interface. The DPE interface and the die interface are configured to communicate through the interposer.
Apparatus and associated methods relate to determining a natural exponent from a digital word input by splitting the digital word, and retrieving a precalculated and predetermined value from a data store at an address defined by the first word. In an illustrative example, the retrieved value may be a hyperbolic sum. The hyperbolic sum may be multiplied by the second word. The hyperbolic sum may be scaled, and summed with the multiplication result to generate a scaled exponential value. The scaled exponential value may be scaled to produce an exponential value representing ex. In various examples, the digital word input may be in a fixed point or a floating point format, or converted therebetween. In various embodiments, the data store may be a lookup table. Various examples may provide a compact and versatile architecture for determining a natural exponent with minimized hardware resources.
G06F 7/556 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul de fonctions logarithmiques ou exponentielles
e.g.e.g., a HIM) includes a wiring substrate, a first component, a second component, and a thermal management apparatus. The first component and the second component are communicatively coupled together via the wiring substrate. The thermal management apparatus is in thermal communication with the first component and the second component. The thermal management apparatus has a first thermal energy flow path for dissipating thermal energy generated by the first component and has a second thermal energy flow path for dissipating thermal energy generated by the second component. The first thermal energy flow path has a lower thermal resistivity than the second thermal energy flow path.
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/40 - Supports ou moyens de fixation pour les dispositifs de refroidissement ou de chauffage amovibles
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des groupes principaux , ou dans une seule sous-classe de , , p.ex. circuit hybrides
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
57.
DISAGGREGATED SWITCH CONTROL PATH WITH DIRECT-ATTACHED DISPATCH
Embodiments herein describe techniques for separating data transmitted between I/O functions in an integrated component and a host into separate data paths. In one embodiment, data packets are transmitted using a direct data path that bypasses a switch in the integrated component. In contrast, configuration packets (e.g., hot-swap, hot-add, hot-remove data, some types of descriptors, etc.) are transmitted to the switch which then forwards the configuration packets to their destination. The direct path for the data packets does not rely on switch connectivity (and its accompanying latency) to transport bandwidth sensitive traffic between the host and the I/O functions, and instead avoids (e.g., bypasses) the bandwidth, resource, store/forward, and latency properties of the switch. Meanwhile, the software compatibility attributes, such as hot plug attributes (which are not latency or bandwidth sensitive), continue to be supported by using the switch to provide a configuration data path.
A chip package assembly and method for fabricating the same are provided that provide a modular chip stack that can be matched with one or more chiplets. The use of chiplets enables the same modular stack to be utilized in a large number of different chip package assembly designs, resulting much faster development times at a fraction of the overall solution cost.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 23/433 - Pièces auxiliaires caractérisées par leur forme, p.ex. pistons
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication.
H03K 19/17736 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels des ressources de routage
60.
METHOD AND APPARATUS FOR TESTING MULTI-DIE INTEGRATED CIRCUITS
An example integrated circuit (1C) die in a multi-die 1C package, the multi-die 1C package having a test access port (TAP) comprising a test data input (TDI), test data output (TOO), test clock (TCK), and test mode select (TMS), is described. The 1C die includes a Joint Test Action Group (JTAG) controller having a JTAG interface that includes a TDI, a TDO, a TCK, and a TMS, a first output coupled to first routing in the multi-die 1C package, a first input coupled to the first routing or to second routing in the multi-die 1C package, a master return path coupled to the first input, and a wrapper circuit configured to couple the TDI of the TAP to the TDI of the JTAG controller, and selectively couple, in response to a first control signal, the TDO of the TAP to either the master return path or the TDO of the JTAG controller.
Embodiments herein describe a SoC that includes a NoC that supports both strict and relax ordering requests. That is, some applications may require strict ordering where requests transmitted from the same ingress logic to different egress logic blocks are performed sequentially. However, other applications may not require strict ordering, such as interleaved writes to memory. In those applications, relax ordering can be used were the same ingress logic block can transmit multiple requests to different egress logic blocks in parallel. For example, an ingress logic block may receive a first request that is indicated as being a relaxed ordered request. After transmitting the request to an egress logic block, the ingress logic block may receive a second request. The ingress logic block can transmit the second request to a different egress logic block without waiting for a response for the first request.
Electronic devices that include a continuous time linear equalizer, CTLE, are provided. An example of a CTLE includes a first inverter (402); a second inverter (404) having an input to receive an input signal (IN); a capacitor (408) coupled between an input of the first inverter (402) and the input of the second inverter (404); a resistor (410) coupled between a common-mode voltage (VCM) and the input of the first inverter; a third inverter (406) having an output to provide an output signal (Out); and a node (416) comprising an output of the first inverter (404), an output of the second inverter (402), an input of the third inverter (406), and the output of the third inverter.
A differential signal input buffer (200) is disclosed. The differential signal input buffer (200) may receive a differential signal that includes a first signal and a second signal and may be divided into a first section (260) and a second section (261). The first section (260) may buffer and/or amplify the first signal based on a first level-shifted second signal. The second section (261) may buffer and/or amplify the second signal based on a first level-shifted first signal. In some implementations, the first section (260) may buffer and/or amplify the first signal based on a second level-shifted second signal. Further, in some implementations, the second section (261) may buffer and/or amplify the second signal based on a second level-shifted first signal.
Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. Neighboring chips are connected to each other. Plural chips of the chips collectively include columns of broken via pillars and bridges. Each of the plural chips has a broken via pillar in each column. The broken via pillar has first and second continuous via pillar portions aligned in a direction normal to a side of a semiconductor substrate of the respective chip. The first continuous via pillar portion is not connected within the broken via pillar to the second continuous via pillar portion. Each of the plural chips has one or more of the bridges. Each bridge connects, within the respective chip, the first continuous via pillar portion in a column and the second continuous via pillar portion in another column.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
Examples described herein generally relate to multi-chip devices having stacked chips. In an example, a multi-chip device includes a chip stack that includes chips. One or more chips each includes a selection circuit and a broken via pillar that includes first and second continuous portions. The first continuous portion includes a through substrate via and a first metal line. The second continuous portion includes a second metal line. The first and second metal lines are disposed within dielectric layers disposed on a side of the semiconductor substrate of the respective chip. The first and second continuous portions are aligned in a direction normal to the side of the semiconductor substrate. An input node of the selection circuit is connected to one of the first or second metal line. An output node of the selection circuit is connected to the other of the first or second metal line.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
G06F 13/00 - Interconnexion ou transfert d'information ou d'autres signaux entre mémoires, dispositifs d'entrée/sortie ou unités de traitement
H03K 19/00 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
Some examples described herein relate to multi-chip devices. In an example, a multi-chip device includes first and second chips (102, 104). The first chip (102) includes a power supply circuit (508) and a logic circuit (506). The first and second chips are coupled together. The second chip (104) is configured to receive power from the power supply circuit (508). The second chip includes a programmable circuit (510), a pull-up circuit (PL), and a detector circuit (504). The detector circuit is configured to detect a presence of a power voltage on the second chip (104) and responsively output a presence signal (534-1). The power voltage on the second chip is based on the power from the power supply circuit. The logic circuit (506) is configured to generate a pull-up signal (540) based on the presence signal. The pull-up circuit is configured to receive the pull-up signal and configured to pull up a voltage of a node of the programmable circuit responsive to the pull- up signal.
H03K 19/17772 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels des ressources de configuration pour la mise sous ou hors tension
67.
DATA TRANSFERS BETWEEN A MEMORY AND A DISTRIBUTED COMPUTE ARRAY
An integrated circuit (IC) includes a plurality of dies. The IC includes a plurality of memory channel interfaces configured to communicate with a memory, wherein the plurality of memory channel interfaces are disposed within a first die of the plurality of dies. The IC may include a compute array distributed across the plurality of dies and a plurality of remote buffers distributed across the plurality of dies. The plurality of remote buffers are coupled to the plurality of memory channels and to the compute array. The IC further includes a controller configured to determine that each of the plurality of remote buffers has data stored therein and, in response, broadcast a read enable signal to each of the plurality of remote buffers initiating data transfers from the plurality of remote buffers to the compute array across the plurality of dies.
G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
Examples described herein provide for an isolation design for an inductor of a stacked integrated circuit device. An example is a multi-chip device comprising a chip stack comprising: a plurality of chips, neighboring pairs of the plurality of chips being bonded together, each chip comprising a semiconductor substrate, and a front side dielectric layer on a front side of the semiconductor substrate; an inductor disposed in a backside dielectric layer of a first chip of the plurality of chips, the backside dielectric layer being on a backside of the semiconductor substrate of the first chip opposite from the front side of the semiconductor substrate of the first chip; and an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer, the isolation wall comprising a through substrate via of the first chip, the isolation wall being disposed around the inductor.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 23/528 - Configuration de la structure d'interconnexion
A quadrature clock generator is disclosed. The quadrature clock generator may include a first injection-locked oscillator, a phase interpolator, and a second injection-locked oscillator. The first injection-locked oscillator may generate a first plurality clock signals from a first reference clock signal. The phase interpolator may generate a second reference clock signal from the first plurality of clock signals, and the second injection-locked oscillator may generate a second plurality of clock signals from the second reference clock signal. A first quadrature clock signal may be selected from the first plurality of clock signals and a second quadrature clock signal may be selected from the second plurality of reference clock signals.
Apparatus and associated methods relate to adapting a continuous time linear equalization circuit with minimum mean square error baud-rate clock and data recovery circuit to be able to lock to the center or near center of an eye diagram. In an illustrative example, a circuit may include an inter-symbol interference (ISI) detector configured to receive data and error samples, a summing circuit coupled to the output of the ISI detector, a moving average filter configured to receive the output of the summing circuit and generate an average output, a voter configured to generate a vote in response to the average output and a predetermined threshold, and, an accumulator and code generator configured to generate a code signal in response to the generated vote. By introducing the moving average filter and the voter, a quicker way to lock to the center or near center of an eye diagram may be obtained.
Creation of subsystems for a user design to be implemented in an integrated circuit (1C) includes generating, using computer hardware, a subsystem topology based on user provided subsystem data, wherein the subsystem topology specifies a plurality of subsystems of the user design where each subsystem includes a master circuit, and determining, using the computer hardware, a system management identifier for each master circuit of the subsystem topology. Programming data for programmable protection circuits of the 1C can be automatically generated using the computer hardware based on the subsystem topology and system management identifiers. The programmable protection circuits, when programmed with the programming data, form the plurality of subsystems and physically isolate the plurality of subsystems on the integrated circuit from one another.
G06F 21/76 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits intégrés à application spécifique [ASIC] ou les dispositifs programmables, p.ex. les réseaux de portes programmables [FPGA] ou les circuits logiques programmables [PLD]
G06F 21/73 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par création ou détermination de l’identification de la machine, p.ex. numéros de série
An example programmable device includes a configuration memory configured to store configuration data; a programmable logic having a configurable functionality based on the configuration data in the configuration memory; a signal conversion circuit; a digital processing circuit; an endpoint circuit coupled to the signal conversion circuit through the digital processing circuit; wherein the digital processing circuit includes a first one or more digital processing functions implemented as hardened circuits each having a predetermined functionality, and a second one or more processing functions implemented by the configurable functionality of the programmable logic.
H03K 19/1776 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels des ressources de configuration pour les mémoires
73.
EMBEDDED VARIABLE OUTPUT POWER (VOP) IN A CURRENT STEERING DIGITAL-TO-ANALOG CONVERTER
DACshuntshunt) may flow through a pair of cascode transistors (325, 330). In various examples, controlling the programmable shunt current sources (335b-335c) to compensate adjustments to the tail current source (335a) may, for example, permit controlled common mode voltage (Vcm) or operating point so as to reduce device voltage stress over a wider dynamic range of output voltages (Vop.Von).
An apparatus includes a first die including a first substrate with first TSVs running through it, a first top metal layer and first chimney stack vias (CSVs) connecting the first TSVs with the first top metal layer. The apparatus further includes an uppermost die including an uppermost substrate and an uppermost top metal layer, and uppermost CSVs connecting the uppermost substrate with the uppermost top metal layer. The first and uppermost dies are stacked face to face, the first TSVs and the first CSVs are mutually aligned, and the dies are configured such that current is delivered to the apparatus from the first TSVs up through the first CSVs, the first and uppermost top metal layers, and the uppermost CSVs.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/485 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées formées de structures en couches comprenant des couches conductrices et isolantes, p.ex. contacts planaires
Examples described herein generally related to multi-chip devices having vertically stacked chips. In an example, a multi-chip device includes a chip stack. The chip stack includes a base chip and a plurality of interchangeable chips. The base chip is directly bonded to a first one of the plurality of interchangeable chips. Each neighboring pair of the plurality of interchangeable chips is directly bonded together in an orientation with a front side of one chip of the respective neighboring pair directly bonded to a backside of the other chip of the respective neighboring pair. Each of the interchangeable chips has a same processing integrated circuit and a same hardware layout. The chip stack can include a distal chip, which can be directly bonded to a second one of the plurality of interchangeable chips.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 27/10 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
76.
SUBSYSTEM FOR CONFIGURATION, SECURITY, AND MANAGEMENT OF AN ADAPTIVE SYSTEM
An integrated circuit (IC) can include a processor system configured to execute program code, a programmable logic, and a platform management controller coupled to the processor system and the programmable logic. The platform management controller is adapted to configure and control the processor system and the programmable logic independently.
G06F 21/76 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits intégrés à application spécifique [ASIC] ou les dispositifs programmables, p.ex. les réseaux de portes programmables [FPGA] ou les circuits logiques programmables [PLD]
H03K 19/17768 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels des ressources de configuration pour la sécurité
An example configuration system for a programmable device includes: a configuration memory read/write unit configured to receive configuration data for storage in a configuration memory of the programmable device, the configuration memory comprising a plurality of frames; a plurality of configuration memory read/write controllers coupled to the configuration memory read/write unit; a plurality of fabric sub-regions (FSRs) respectively coupled to the plurality of configuration memory read/write controllers, each FSR including a pipeline of memory cells of the configuration memory disposed between buffers and a configuration memory read/write pipeline unit coupled between the pipeline and a next one of the plurality of FSRs.
H03K 19/17748 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels des ressources de configuration
Some examples described herein relate to redundancy in a multi-chip stacked device. An example described herein is a multi-chip device. The multi-chip device includes a chip stack including vertically stacked chips. Neighboring pairs of the chips are directly connected together. Each of two or more of the chips includes a processing integrated circuit. The chip stack is configurable to operate a subset of functionality of the processing integrated circuits of the two or more of the chips when any portion of the processing integrated circuits is defective.
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p.ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p.ex. essais de mise en route
G06F 11/20 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel en utilisant un masquage actif du défaut, p.ex. en déconnectant les éléments défaillants ou en insérant des éléments de rechange
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
Tracing status of a programmable device can include, in response to loading a device image for the programmable device, determining, using a processing unit on the programmable device, trace data for the device image, storing, by the processing unit, the trace data for the device image in a memory, and, in response to unloading the device image, recording the unloading of the device image in the trace data in the memory.
The embodiments herein creates DCT mechanisms that initiate a DCT at the time the updated data is being evicted from the producer cache (125). These DCT mechanisms are applied when the producer is replacing the updated contents in its cache because the producer has either moved on to working on a different data set (e.g., a different task) or moved on to working on a different function, or when the producer-consumer task manager (e.g., a management unit) enforces software coherency by sending Cache Maintenance Operations (CMO). One advantage of the DCT mechanism is that because the direct cache transfer takes place at the time the updated data is being evicted, by the time the consumer begins its task, the updated contents have already been placed in its own cache or another cache within the cache hierarchy.
G06F 12/0831 - Protocoles de cohérence de mémoire cache à l’aide d’un schéma de bus, p.ex. avec moyen de contrôle ou de surveillance
G06F 12/0804 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec mise à jour de la mémoire principale
81.
DYNAMICALLY RECONFIGURABLE NETWORKING USING A PROGRAMMABLE INTEGRATED CIRCUIT
An integrated circuit, IC, can include a platform (218) implemented, at least in part, in a static region (202) of programmable circuitry, wherein the platform includes a network interface card controller, NIC, coupled to a host interface (212) and a network interface (206), and a dynamic region (204) of programmable circuitry configured to implement user-specified circuitry (216) in communication with the platform, wherein the user-specified circuitry implements one or more packet processing functions. The NIC includes a plurality of communication interfaces connected to the dynamic region. The platform can establish and maintain a first communication link with a host data processing system using the host interface and a second communication link with a network using the network interface. The platform can continue to transfer data between the network and the host data processing system while at least a portion of the dynamic region of programmable circuitry is dynamically reconfigured to implement different user-specified circuitry therein.
H03K 19/17756 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels des ressources de configuration pour la configuration partielle ou la reconfiguration partielle
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
82.
PROGRAMMABLE NETWORK INTERFACE DEVICE COMPRISING A HOST COMPUTING DEVICE AND A NETWORK INTERFACE DEVICE
A network interface device (102) comprises a programmable interface (119) configured to provide a device interface with at least one bus between the network interface device (102) and a host device (101). The programmable interface (119) is programmable to support a plurality of different types of a device interface.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
G06F 13/12 - Commande par programme pour dispositifs périphériques utilisant des matériels indépendants du processeur central, p.ex. canal ou processeur périphérique
G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation
G06F 13/38 - Transfert d'informations, p.ex. sur un bus
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache
83.
CIRCUITS FOR AND METHODS OF CALIBRATING A CIRCUIT IN AN INTEGRATED CIRCUIT DEVICE
A circuit arrangement for calibrating a circuit in an integrated circuit device is described. The circuit arrangement may comprise a main circuit (1102) configured to receive input data at a first input (1106) and generate output data at a first output (1108), wherein the output data is based upon the input data and a function of the main circuit; a replica circuit (1104) configured to receive calibration data at a second input (1114) and generate calibration output data, based upon the calibration data, at a second output (1118), wherein the replica circuit provides a replica function of the function of the main circuit; and a calibration circuit (1120) configured to receive the output data from the main circuit during a foreground calibration mode, and the calibration output data from the replica circuit during a background calibration mode; wherein the calibration circuit provides control signals to the main circuit during the background calibration mode. A method of calibrating a circuit in an integrated circuit device is also described.
An integrated circuit device having a plurality of stacked dies is described. The integrated circuit device comprises a first die of the plurality of stacked dies having an input/output element configured to receive an input signal, the first die comprising a signal driver circuit configured to provide the input signal to each die of the plurality of stacked dies and a chip select circuit for generating a plurality of chip select signals for the plurality of stacked dies; and a second die of the plurality of stacked dies coupled to the first die, the second die having a function block configured to the receive the input signal; wherein the second die receives the input signal in response to a chip select signal of the plurality of chip select signals that corresponds to the second die. A method of implementing an integrated circuit device having a plurality of stacked dies is also described.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H03K 19/00 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion
H03K 19/173 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants
A system comprises one or more slice-aggregated cryptographic slices each configured to perform a plurality of operations on an incoming data transfer at a first processing rate by aggregating one or more individual cryptographic slices each configured to perform the plurality of operations on a portion of the incoming data transfer at a second processing rate. Each of the individual cryptographic slices comprises in a serial connection an ingress block configured to take the portion of the incoming data transfer at the second processing rate, a cryptographic engine configured to perform the operations on the portion of the incoming data transfer, an egress block configured to process a signature of the portion and output the portion of the incoming data transfer once the operations have completed. The first processing rate of each slice-aggregated cryptographic slices equals aggregated second processing rates of the individual cryptographic slices in the slice- aggregated cryptographic slice.
G06F 21/76 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits intégrés à application spécifique [ASIC] ou les dispositifs programmables, p.ex. les réseaux de portes programmables [FPGA] ou les circuits logiques programmables [PLD]
H04L 9/14 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité utilisant plusieurs clés ou algorithmes
G06F 30/34 - Conception de circuits pour circuits reconfigurables, p.ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuity configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect. The interconnect system may include one or more analog channels configured to distribute the reference voltage to each of the plurality of satellite monitors, and may include one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors to the root monitor as data packets.
H03K 19/003 - Modifications pour accroître la fiabilité
H03K 19/1778 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels pour l'adaptation des paramètres physiques
A device includes a physical medium attachment (PMA) (110), a physical coding sublayer (PCS) (120), a phase detector (140), and an oscillator (150). The PMA (110) receives data (102) at a first speed and overclocks the received data to a second speed (112), wherein the second speed is higher than the first speed. The PCS (120) receives the data (112) at the second speed. The phase detector (140) receives another data (122) from the PCS (120) wherein the another data (122) is based on the received data at the second speed (112) or the phase detector (140) is configured to receive the data at the second speed (112) from the PMA (110). The phase detector (140) adjusts a phase based on bit transitions. The oscillator (150) is coupled to the phase detector (140) and generates a reference clock signal wherein a phase of the reference clock is adjusted by the phase detector (150). The oscillator (150) clocks the PMA (110) based on the adjusted clock.
G06F 13/38 - Transfert d'informations, p.ex. sur un bus
G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation
H03L 7/08 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase
88.
REGULARITY OF FABRICS IN PROGRAMMABLE LOGIC DEVICES
A programmable logic device with fabric regularity is disclosed. For example, the programmable logic device may include a plurality of similar heterogeneous logic blocks. A user's design may be implemented within a first group of heterogeneous logic blocks. The user's design may be moved or copied to a second group of heterogeneous logic blocks. More specifically, routing, timing, and/or placement information associated with the implementation of the users design in the first group of heterogeneous logic blocks may be used to implement the user's design in the second group of heterogeneous logic blocks.
G06F 30/331 - Vérification de la conception, p.ex. simulation fonctionnelle ou vérification du modèle par simulation avec accélération matérielle, p.ex. en utilisant les réseaux de portes programmables [FPGA] ou une émulation
H03K 19/17728 - Blocs logiques reconfigurables, p.ex. tables de consultation
89.
DENSE WAVELENGTH-DIVISION AND MULTIPLEXING SCHEME FOR OPTICAL INTEGRATED CIRCUITS
An apparatus and method for generating a dense wavelength division and multiplexing (DWDM) optical stream in a photonic integrated circuit (PIC) is disclosed. An optical input source including a number (N) of optical channels (wavelengths) may be separated (de-interleaved) into multiple optical streams, each including a corresponding subset of the optical channels of the optical input source. Each of the multiple split optical streams may be modulated with an associated set of data streams by silicon-based micro-ring modulators to generate a corresponding modulated optical stream. A first pair of the modulated optical streams may be combined (interleaved) to generate a first optical output stream including N/2 modulated optical channels, and a second pair of the modulated optical streams may be combined (interleaved) to generate a second optical output stream including N/2 modulated optical channels. The channel spacing of the first and second optical output streams may be twice the channel spacing of the optical input source.
H04B 10/50 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs
H04J 14/02 - Systèmes multiplex à division de longueur d'onde
90.
LEARNING NEURAL NETWORKS OF PROGRAMMABLE DEVICE BLOCKS DIRECTLY WITH BACKPROPAGATION
An example method of training a neural network includes defining hardware building blocks (HBBs), neuron equivalents (NEQs), and conversion procedures from NEQs to HBBs; defining the neural network using the NEQs in a machine learning framework; training the neural network on a training platform; and converting the neural network as trained into a netlist of HBBs using the conversion procedures to convert the NEQs in the neural network to the HBBs of the netlist.
G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
An accelerator device (140) shares the same coherent domain as hardware elements in a host computing device (105). A mix of hardware and software coherency reduces the overhead of managing data when large chunks of data are moved from the host into the accelerator device. An accelerator application (125) executing on the host identifies a data set (130) it wishes to transfer to the accelerator device to be processed. The accelerator application transfers ownership from a home agent (135) in the host to the accelerator device. A slave agent (155) can then take ownership of the data. As a result, any memory operation requests received from a requesting agent (145) in the accelerator device can gain access to the data set in a local memory (160) via the slave agent without the slave agent obtaining permission from the home agent in the host.
Apparatus and associated methods relate to a consolidated power-on-reset system (PORS) at a system-on-chip (SoC) level. In an illustrative example, an integrated circuit (215) may include a first power domain (300a) and a second power region (300b). A level shifter circuit (300c) may be coupled to translate data from the first power domain to the second power domain. A PORS (270) including a voltage detection circuit (410, 470a, 470b), a glitch filter circuit (415, 475a, 475b), and logic gates (420a, 420b) may be configured to generate isolation signals (310, 320) between the first power domain (300a) and the second power domain (300b). The level shifter circuit (300c) may be enabled in response to the generated isolation signals. By using the isolation signals, multiple power domains on IC (215) may be managed comprehensively during power-up to avoid unstable operation.
H03K 19/0175 - Dispositions pour le couplage; Dispositions pour l'interface
H03K 19/0185 - Dispositions pour le couplage; Dispositions pour l'interface utilisant uniquement des transistors à effet de champ
H03K 19/17736 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels des ressources de routage
H03K 19/17772 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels des ressources de configuration pour la mise sous ou hors tension
H03K 19/1776 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels des ressources de configuration pour les mémoires
93.
FLOW CONVERGENCE DURING HARDWARE-SOFTWARE DESIGN FOR HETEROGENEOUS AND PROGRAMMABLE DEVICES
For an application having a software portion for implementation in a data processing engine (DPE) array of a device and a hardware portion for implementation in programmable logic (PL) of the device, an implementation flow is performed, using a processor executing a hardware compiler, on the hardware portion based on an interface block solution that maps logical resources used by the software portion to hardware of an interface block coupling the DPE array to the PL. In response to not meeting a design metric during the implementation flow, an interface block constraint is provided from the hardware compiler to a DPE compiler. In response to receiving the interface block constraint, an updated interface block solution is generated, using the processor executing the DPE compiler, and provided from the DPE compiler to the hardware compiler.
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
G06F 30/34 - Conception de circuits pour circuits reconfigurables, p.ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
94.
DATAFLOW GRAPH PROGRAMMING ENVIRONMENT FOR A HETEROGENOUS PROCESSING SYSTEM
Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the graph expressed in source code to determine where to assign the kernels in the heterogeneous processing system. Further, the compiler can select the specific communication techniques to establish the communication links between the kernels and whether synchronization should be used in a communication link. Thus, the programmer can express the dataflow graph at a high-level (using source code) without understanding about how the operator graph is implemented using the heterogeneous hardware in the SoC.
An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.
G06F 30/34 - Conception de circuits pour circuits reconfigurables, p.ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G06F 7/57 - Unités arithmétiques et logiques [UAL], c. à d. dispositions ou dispositifs pour accomplir plusieurs des opérations couvertes par les groupes ou pour accomplir des opérations logiques
G06F 30/34 - Conception de circuits pour circuits reconfigurables, p.ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
97.
HARDWARE-SOFTWARE DESIGN FLOW WITH HIGH-LEVEL SYNTHESIS FOR HETEROGENEOUS AND PROGRAMMABLE DEVICES
For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion having High-Level Synthesis (HLS) kernels for implementation within programmable logic (PL) of the device, a first interface solution is generated that maps logical resources used by the software portion to hardware resources of an interface block coupling the DPE array and the PL. A connection graph specifying connectivity among the HLS kernels and nodes of the software portion to be implemented in the DPE array; and, a block diagram based on the connection graph and the HLS kernels are generated. The block diagram is synthesizable. An implementation flow is performed on the block diagram based on the first interface solution. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.
G06F 30/34 - Conception de circuits pour circuits reconfigurables, p.ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
98.
CIRCUIT FOR AND METHOD OF TRANSMITTING A SIGNAL IN AN INTEGRATED CIRCUIT DEVICE
A circuit for transmitting signals in an integrated circuit device is described. The circuit comprises a first die (501); a second die (502) stacked on the first die (501); and a buffer (513) transmitting data between the first die (501) and the second die (502); wherein a first inverter (512) of the buffer (513) is on the first die (501), and a second inverter (514) of the buffer (513) is on the second die (502). A method of transmitting signals in an integrated circuit device is also described.
H03K 19/003 - Modifications pour accroître la fiabilité
H03K 19/0185 - Dispositions pour le couplage; Dispositions pour l'interface utilisant uniquement des transistors à effet de champ
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
99.
LOCK CIRCUIT FOR COMPETING KERNELS IN A HARDWARE ACCELERATOR
An example hardware accelerator in a computing system includes a bus interface coupled to a peripheral bus of the computing system; a lock circuit coupled to the bus interface; and a plurality of kernel circuits coupled to the lock circuit and the bus interface; wherein the plurality of kernel circuits provide lock requests to the lock circuit, the lock requests for data stored in system memory of the computing system; wherein the lock circuit is configured to process the lock requests from the plurality of kernel circuits and to issue atomic transactions over the peripheral bus through the bus interface based on the lock requests.
Examples herein describe a peripheral I/O device with a hybrid gateway that permits the device to have both I/O and coherent domains. As a result, the compute resources in the coherent domain of the peripheral I/O device can communicate with the host in a similar manner as CPU-to-CPU communication in the host. The dual domains in the peripheral I/O device can be leveraged for machine learning (ML) applications. While an I/O device can be used as an ML accelerator, these accelerators previously only used an I/O domain. In the embodiments herein, compute resources can be split between the I/O domain and the coherent domain where a ML engine is in the I/O domain and a ML model is in the coherent domain. An advantage of doing so is that the ML model can be coherently updated using a reference ML model stored in the host.
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