The invention provides a direct memory access (DMA) controller. The DMA controller has an address register, a data register and transfer circuitry for transferring data over a bus of a computing system. The DMA controller is configured to use the transfer circuitry to read data over the bus from a memory location having a first memory address, wherein the data comprises a second memory address, and store the second memory address in the address register, and use the transfer circuitry to transfer data over the bus between a memory location having the second memory address, or having a memory address derived from the second memory address, and the data register.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
G06F 12/14 - Protection contre l'utilisation non autorisée de mémoire
A configurable radio frequency receiver is provided. The receiver has at least one low noise amplifier; an oscillator arrangement for producing a plurality of signals having a first number or a second number of separate phases; and multiple mixer modules having inputs connected to an output of the low noise amplifier. The receiver has a configurable resistor network. The receiver is configured such that it can operate in a first mode with said plurality of signals having said first number of phases or a second mode with said plurality of signals having said second number of phases. The configurable resistor network enables the receiver to operate in the first mode in a first configuration, and the second mode in a second configuration. The mixer modules are employed during the operation of the first mode and the second mode.
A radio receiver device is disclosed. The radio receiver device is configured to receive a radio signal comprising a data packet, said data packet comprising a first portion comprising an encoded bit sequence and including information specific to the data packet and a second portion comprising an encoded bit sequence and comprising corresponding information specific to the data packet. The radio receiver device is configured to calculate a correlation metric using the first portion and the second portion; and to estimate a carrier frequency offset between the radio signal and the radio receiver device using the correlation metric.
A receiver apparatus for receiving an OFDM radio signal comprising a first plurality of subcarrier-symbols, modulated on a corresponding plurality of subcarriers, and a second plurality of subcarrier-symbols, modulated on the corresponding plurality of subcarriers, to generate first and second bit sequences, the first bit sequence being an interleaved version of the second bit sequence according to a predetermined interleave function. Soft-output decoder logic generates a first soft-bit sequence for the first plurality of subcarrier-symbols, and a second soft-bit sequence for the second plurality of subcarrier-symbols. Combiner logic combines the soft-bit sequences, with the soft-bit sequences either both in an interleaved state or both in a non-interleaved state, by combining a respective soft-bit having a bit position in the first soft-bit sequence with a respective soft-bit having a same bit position in the second soft-bit sequence. Hard-output decoder logic outputs a hard-bit sequence representing the transmitted bit sequence.
According to an aspect, there is provided a swing-boosted differential oscillator and a method for trimming the oscillator. The oscillator comprises a switch (110) for connecting a set of capacitors (C1, C2) alternately to power supply and ground (102, 112) based on a switching control (116A, 116B), a comparator (114) configured to produce the switching control (116A, 116B) by comparing a voltage of the capacitors (C1, C2) at the inputs (VC1, VC2) of the comparator to a preset threshold voltage, and a trimmable resistor (RCAL) connecting the inputs (VC1, VC2) of the comparator, the resistor controlling the frequency of the output (118) of the oscillator.
H03B 5/24 - Elément déterminant la fréquence comportant résistance, et soit capacité, soit inductance, p.ex. oscillateur à glissement de phase l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
H03K 3/012 - Modifications du générateur pour améliorer le temps de réponse ou pour diminuer la consommation d'énergie
H03K 3/013 - Modifications du générateur en vue d'éviter l'action du bruit ou des interférences
H03K 4/502 - Génération d'impulsions ayant comme caractéristique essentielle une pente définie ou des parties en gradins à forme triangulaire en dents de scie utilisant comme éléments actifs des dispositifs à semi-conducteurs dans laquelle la tension en dents de scie est produite à travers un condensateur le début de la période de retour étant déterminé par l'amplitude de la tension à travers le condensateur, p.ex. avec un comparateur le condensateur étant chargé à partir d'une source à courant constant
An integrated-circuit device comprises a resettable source register in a first reset domain. A destination circuit, outside the first reset domain, is arranged to sample an output of the resettable source register. A digital logic module causes a central reset controller to output a reset-warning signal in response to receiving a request to reset first reset domain, and to reset the first domain after a predetermined delay period from outputting the reset-warning signal.
A receiver apparatus is configured to receive a radio-frequency signal comprising a first subcarrier comprising first subcarrier symbols and a second subcarrier comprising second subcarrier symbols, wherein the first subcarrier symbols and the second subcarrier symbols both encode a same bit sequence in a respective first subcarrier symbol and a second subcarrier symbol. Soft-output decoder logic calculates respective log-likelihood ratios for each of the first subcarrier symbols and generates a first output sequence comprising the respective log-likelihood ratios calculated for the first subcarrier symbols and similarly generates a second output sequence. Combiner logic combines the output sequences by adding or subtracting a respective log-likelihood ratio with a respective log-likelihood ratio calculated for the respective second subcarrier symbol to obtain a combined log-likelihood ratio for a respective bit of the bit sequence, and outputs a combined output sequence comprising a respective combined log-likelihood ratio for each bit of the bit sequence.
According to an aspect, there is provided a swing-boosted differential oscillator (500) and a method for trimming the oscillator. The oscillator comprises a switch (110') for connecting a set of capacitors (C1, C2) alternately to power supply and ground (102', 112') based on a switching control (116A', 116B'), two comparators (502, 504) configured to produce an output signal of the oscillator (ck) and the switching control (116A', 116B') via a multiplexer (508) by comparing a voltage of the capacitors (C1, C2) at the inputs (VC1, VC2) of the comparators to a threshold voltage (VBB), where the comparators comprising back gate bias input (fig. 5: 804, fig. 8: Vbb, 804) for controlling the threshold voltage of the comparators, the threshold voltage trimming the frequency of the output signal of the oscillator.
H03K 4/502 - Génération d'impulsions ayant comme caractéristique essentielle une pente définie ou des parties en gradins à forme triangulaire en dents de scie utilisant comme éléments actifs des dispositifs à semi-conducteurs dans laquelle la tension en dents de scie est produite à travers un condensateur le début de la période de retour étant déterminé par l'amplitude de la tension à travers le condensateur, p.ex. avec un comparateur le condensateur étant chargé à partir d'une source à courant constant
H03K 19/00 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion
There is provided a method of testing an RF transceiver circuit and an RF transceiver circuit arranged to be operable in a test mode comprising a transmitter circuit portion and a receiver circuit portion, the receiver circuit portion including a mixer. The method involves the transmitter circuit portion generating a modulated signal and the receiver circuit portion receiving a continuous radio frequency wave. The mixer mixes the modulated signal with a signal derived from the continuous radio frequency wave to produce an output. A remainder of the receiver circuit portion processes the output of the mixer.
H04B 17/17 - Détection de contre-performance ou d’exécution défectueuse, p.ex. déviations de réponse
H04B 1/403 - Circuits utilisant le même oscillateur pour générer à la fois la fréquence de l’émetteur et la fréquence de l’oscillateur local du récepteur
A radio frequency device arranged to communicate with a radio network cell of a radio network is provided. The radio frequency device is arranged to operate in a first mode in which the radio frequency device communicates with a radio network cell using a standard communication protocol; to operate in a second mode in which the radio frequency device communicates with a radio network cell using a coverage enhancement communication protocol; to operate in a third mode in which the radio frequency device is restricted from communicating with a radio network cell using the coverage enhancement communication protocol; and to transition from operating in the third mode to operating in the second mode without operating in the first mode.
H04W 4/70 - Services pour la communication de machine à machine ou la communication de type machine
H04W 48/12 - Distribution d'informations relatives aux restrictions d'accès ou aux accès, p.ex. distribution de données d'exploration utilisant un canal de commande descendant
H04W 48/18 - Sélection d'un réseau ou d'un service de télécommunications
H04W 60/00 - Rattachement à un réseau, p.ex. enregistrement; Suppression du rattachement à un réseau, p.ex. annulation de l'enregistrement
H04W 60/04 - Rattachement à un réseau, p.ex. enregistrement; Suppression du rattachement à un réseau, p.ex. annulation de l'enregistrement utilisant des événements déclenchés
H04W 68/02 - Dispositions pour augmenter l'efficacité du canal d'avertissement ou de messagerie
H04W 88/06 - Dispositifs terminaux adapté au fonctionnement dans des réseaux multiples, p.ex. terminaux multi-mode
According to an aspect, there is provided a relaxation oscillator (100) comprising first (101, 11) and second (102, 12) current sources and a comparator (103) having a first input (103-) connected to the first current source, a second input (103+) connected to the second current source and an output. One of the first and second inputs is an inverting input and other one of the first and second inputs is a non- inverting input. The relaxation oscillator further comprises a resistive circuit (110) connected between the first input of the comparator and the ground. The resistive circuit comprises at least a first resistor (R) and a capacitor charging circuit (111) connected between the second input of the comparator and the ground. The capacitor charging circuit comprises a capacitor (105, C), a second resistor (107, R0) connected in series with the capacitor and a switch (106) connected in parallel with the capacitor. The switch is configured to be controlled based on the output of the comparator.
H03K 4/502 - Génération d'impulsions ayant comme caractéristique essentielle une pente définie ou des parties en gradins à forme triangulaire en dents de scie utilisant comme éléments actifs des dispositifs à semi-conducteurs dans laquelle la tension en dents de scie est produite à travers un condensateur le début de la période de retour étant déterminé par l'amplitude de la tension à travers le condensateur, p.ex. avec un comparateur le condensateur étant chargé à partir d'une source à courant constant
A control portion for controlling an amplifier portion of a transmitter device is provided. The amplifier portion is arranged to amplify a radio signal with a transmission gain based at least partially on a gain control signal and having a nominal gain relationship between the gain control signal and the transmission gain. The control portion is arranged to determine a desired transmission gain, to determine one or more operating conditions, to calculate a gain control signal for causing the amplifier portion to apply the desired transmission gain, taking into account the nominal gain relationship and the one or more operating conditions, and to output said gain control signal. The gain control signal is different to a gain control signal calculated based only on the nominal gain relationship.
A battery characterisation system for determining one or more characteristics of a battery is provided. The system comprises a controllable load arranged to be connected to a battery and a voltage sensor arranged to measure a voltage output from said battery. The battery characterisation system is arranged to receive information identifying one or more nominal properties of said battery; to select a discharge profile based on said one or more nominal properties; to control the controllable load to discharge said battery according to said discharge profile; to record the voltage output measured by the voltage sensor and a current output from the battery as the battery is being discharged; and to determine one or more characteristics of the battery using said recorded voltage output and current output.
G01R 31/36 - Dispositions pour le test, la mesure ou la surveillance de l’état électrique d’accumulateurs ou de batteries, p.ex. de la capacité ou de l’état de charge
G01R 31/3842 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p.ex. état de charge combinant des mesures de tension et de courant
A battery-powered device is disclosed comprising a battery and a voltage sensor arranged to measure a terminal voltage of the battery. The battery-powered device is arranged to: a) determine a current flowing into or out of the battery, b) predict a terminal voltage of the battery using the current and an estimated state of charge of the battery, c) measure an actual terminal voltage of the battery using the voltage sensor, d) compare the predicted terminal voltage with the actual terminal voltage and e) update the estimated state of charge of the battery based on said comparison. The battery-powered device is arranged to repeat steps (a)-(e) at one or more subsequent times, said one or more subsequent times being determined based on an operating state of the battery-powered device.
G01R 31/367 - Logiciels à cet effet, p.ex. pour le test des batteries en utilisant une modélisation ou des tables de correspondance
G01R 31/3842 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p.ex. état de charge combinant des mesures de tension et de courant
A boost converter circuit is disclosed comprising an input arranged to receive an input voltage from a battery; an output arranged to generate a higher, output voltage for powering a further circuit portion; and a switching arrangement arranged to control generation of the output voltage. The boost converter circuit compares the input voltage with a first reference input voltage and controls the switching arrangement to limit the output current of the boost converter circuit based on the comparison of the input voltage and the first reference input voltage. The boost converter circuit monitors a parameter indicative of a condition of the battery, determines a second, lower reference input voltage in response to the monitored parameter, compares the input voltage with the second reference input voltage and controls the switching arrangement to limit the output current of the boost converter circuit based on the comparison of the input voltage and the second reference input voltage.
H02M 1/00 - APPAREILS POUR LA TRANSFORMATION DE COURANT ALTERNATIF EN COURANT ALTERNATIF, DE COURANT ALTERNATIF EN COURANT CONTINU OU VICE VERSA OU DE COURANT CONTINU EN COURANT CONTINU ET EMPLOYÉS AVEC LES RÉSEAUX DE DISTRIBUTION D'ÉNERGIE OU DES SYSTÈMES D'ALI; TRANSFORMATION D'UNE PUISSANCE D'ENTRÉE EN COURANT CONTINU OU COURANT ALTERNATIF EN UNE PUISSANCE DE SORTIE DE CHOC; LEUR COMMANDE OU RÉGULATION - Détails d'appareils pour transformation
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
A radio transmitter is configured to operate in accordance with a first predetermined OFDM radio protocol. The transmitter reserves, within a timeslot with a predetermined timeslot duration, a reserved set of time-frequency resource units not available for an OFDM data channel defined by the first protocol. The transmitter allocates, within the timeslot, an allocated set of R time-frequency resource units for the OFDM data channel defined by the first protocol, wherein a number M of time-frequency resource units are included in both the allocated set and the reserved set, wherein the value R is such that R>N and R−M≤N, where N is a predetermined maximum number of time-frequency resource units that can be used to carry the data channel. The transmitter then transmits data indicative of the allocated set of R time-frequency resource units and data indicative of the reserved set of time-frequency resource units.
A digital radio transmitter device operates in accordance with a predetermined communication protocol that defines a default inter-frame spacing. The device has a minimum inter-frame spacing that is shorter than said default inter-frame spacing. The device is configured to: transmit a first data packet indicating that the device is able to support an inter-frame spacing shorter than said default inter-frame spacing; receive a second data packet from a peer device after said default inter-frame spacing; if said second data packet indicates that said peer device is able to support an inter-frame spacing shorter than said default inter-frame spacing, transmit a third data packet using an inter-frame spacing shorter than said default inter-frame spacing; and if said second data packet does not indicate that said peer device is able to support an inter-frame spacing shorter than said default inter-frame spacing, transmit said third packet using said default inter-frame spacing.
A receiver device is provided which is arranged to receive a data packet from a transmitter device comprising a control portion and a payload portion, said control portion comprising a feedback request indicator. The receiver device is arranged to detect the feedback request indicator, to attempt to decode the payload portion of the data packet, to transmit an acknowledgement to the transmitter device if said feedback request indicator indicates that an acknowledgement is requested for said data packet, and to process said data packet without transmitting an acknowledgement if said feedback request indicator indicates that an acknowledgement is not requested for said data packet.
H04L 1/1607 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue en utilisant un canal de retour dans lesquelles le canal de retour transporte des signaux de contrôle, p.ex. répétition de signaux de demande - Détails du signal de contrôle
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
H04L 1/1829 - Dispositions spécialement adaptées au point de réception
An integrated-circuit chip and method of operating said chip is provided. The integrated-circuit chip includes multiple processors, a system memory and a main system bus for carrying data between each of the processors and the system memory. The chip also has debug logic, a debug port for communicating with the debug logic from outside the chip and a debug connection that connects the debug logic to the main system bus. A power management system is also included for controlling the power supplied to each of a number of power domains on the chip. The debug logic and each of the processors are in different respective power domains. The debug logic is configured to send a debug instruction to any of the processors. The debug instruction is communicated over the debug connection and over the main system bus.
A receiver device comprises receiving circuitry configured to receive a radio signal modulated using frequency shift keying or phase shift keying, the radio signal comprising a plurality of successive symbol intervals, differential detector circuitry configured to multiply a signal for a current symbol interval with a first reference signal and output a first output signal for the current symbol interval, wherein the first reference signal corresponds to a conjugate of a signal for a first symbol interval preceding the current symbol interval and multiply the signal for the current symbol interval with a second reference signal and output a second output signal for the current symbol interval, wherein the second reference signal corresponds to a conjugate of a signal for a second symbol interval preceding the first symbol interval, in which the conjugate of the signal for the second symbol interval has been phase adjusted in dependence on a previous phase decision for the first symbol interval preceding the current symbol interval, combining circuitry configured to combine the first output signal for the current symbol interval and the second output signal for the current symbol interval to obtain a combined signal for the current symbol interval, and decision circuitry configured to output a phase decision for the current symbol interval in dependence upon the combined signal.
An amplitude regulator circuit portion is arranged to supply a current to an inverter in an oscillator circuit. The regulator monitors a voltage at the input terminal of the inverter and varies the current supplied to the inverter in response to the monitored voltage. The amplitude regulator comprises first, second, and third PMOS transistors, and first and second NMOS transistors and is arranged such that an input node is connected to the input terminal of the inverter, a respective gate terminal of each of the first and second NMOS transistors, and a respective drain terminal of the first NMOS and first PMOS transistors. The amplitude regulator also comprises a back-bias circuit portions arranged to vary a back-bias voltage at a back-gate terminal of the second NMOS transistor, to vary a threshold voltage, where the threshold voltage of the second NMOS transistor is lower than that of the first NMOS transistor.
H03B 5/36 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique l'élément actif de l'amplificateur comportant un dispositif semi-conducteur
H03B 5/04 - Modifications du générateur pour compenser des variations dans les grandeurs physiques, p.ex. alimentation, charge, température
According to an aspect, there is provided a first radio device for performing the following. The first radio device causes wireless transmission of one or more first advertising messages at one or more advertising radio frequencies using a connectionless mode of the first radio device. The radio device receives, for at least one first advertising message, a first scan request from a second radio device and transmits, for each first scan request, a first scan response to the second radio device. Based on one or more received first scan requests, the first radio device performs bi-directional channel sounding with the second radio device at one or more sounding radio frequencies. The first radio device receives, from the second radio device, at least one first message comprising information on second channel sounding measurements and transmits. to the second radio device, at least one second message comprising information on first channel sounding measurements performed by the first radio device.
H04W 4/80 - Services utilisant la communication de courte portée, p.ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
H04W 8/00 - Gestion de données relatives au réseau
There is disclosed an electronic device and a method of operating an electronic device. It has peripherals which each have one or more event outputs or task inputs, connected to a peripheral interconnect. The device also has a controller for configuring the peripheral interconnect and a memory, which are communicatively coupled to a bus system. The peripheral interconnect receives configuration data from the controller, which selectively connects peripheral event outputs and task inputs. The controller uses the bus system to access a sequence of instructions in a script stored in the memory. Each instruction in the sequence identifies a peripheral task input, event output and a second peripheral event output. Each subsequent instruction in the sequence is implemented in response to detecting an event signalled from the second peripheral event output identified by the preceding instruction in the sequence.
G06F 13/12 - Commande par programme pour dispositifs périphériques utilisant des matériels indépendants du processeur central, p.ex. canal ou processeur périphérique
An integrated circuit device includes an n-bit register comprising: a plurality of latches and at least one flip-flop, and clock gating circuitry, which includes a clock signal coupled to the latches and the flip-flop. Each latch comprises a latch gating terminal configured to receive a gating signal, wherein a respective latch is configured to receive the gating signal that either corresponds to the clock signal or is determined according to a logical operation including the clock signal such that a transparency for each respective latch is controlled in dependence upon a level of the gating signal. The integrated circuit device is configured to operate in a scan test mode, wherein during a scan shift operation, an input signal terminal of the flip-flop is configured to receive a test input signal and the flip-flop is configured to load the test input signal to an output signal terminal of the flip-flop.
An electronic device comprises an oscillator circuit portion comprising an inverter and a crystal oscillator connected between the input and output terminals of the inverter. An amplitude regulator circuit portion is arranged to supply a current to the inverter. The amplitude regulator monitors a voltage at the input of the inverter and varies the current supplied to the inverter in response to the monitored voltage. The amplitude regulator comprises a trimmable resistor arranged such that the voltage at the input of the inverter is set to an operating point when the supply current is equal to a threshold value, the operating point being at least partly determined by the selected resistance of the resistor. A current monitor is arranged to monitor the current supplied to the inverter during operation and to determine therefrom whether the voltage at the input terminal of the inverter is within a predetermined range.
H03B 5/36 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique l'élément actif de l'amplificateur comportant un dispositif semi-conducteur
A circuit portion comprises a DCDC converter that provides current to one of a plurality of loads at a time. A controller detects when a voltage across an under-supplied load of the plurality of loads is below a first threshold. Channel logic circuitry provides current from the converter to the under-supplied load in response to the controller detecting that the voltage is below the first threshold. A voltage regulator provides current to the under-supplied load when the voltage is below a second threshold.
H02M 3/157 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation avec commande numérique
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
H02M 1/00 - APPAREILS POUR LA TRANSFORMATION DE COURANT ALTERNATIF EN COURANT ALTERNATIF, DE COURANT ALTERNATIF EN COURANT CONTINU OU VICE VERSA OU DE COURANT CONTINU EN COURANT CONTINU ET EMPLOYÉS AVEC LES RÉSEAUX DE DISTRIBUTION D'ÉNERGIE OU DES SYSTÈMES D'ALI; TRANSFORMATION D'UNE PUISSANCE D'ENTRÉE EN COURANT CONTINU OU COURANT ALTERNATIF EN UNE PUISSANCE DE SORTIE DE CHOC; LEUR COMMANDE OU RÉGULATION - Détails d'appareils pour transformation
A common-mode feedback circuit for a fully differential amplifier comprises first (MB), second (MTP), and third (MTN) transistors, each having a respective drain, source, gate, and back-gate terminals. The drain terminal of the first transistor (MB) and the gate terminals of the first, second, and third transistors (MB, MTP, MTN) are connected together at a bias current terminal. The drain terminals of the second and third transistors are connected together at a tail current terminal. The source terminals of the first, second, and third transistors are connected together. The back-gate terminal of the first transistor (MB) is arranged to receive a common-mode reference voltage input (VCM), the back-gate terminal of the second transistor (MTP) is arranged to receive a positive output voltage (VP) from the fully differential amplifier, and the back-gate terminal of the third transistor (MTN) is arranged to receive a negative output voltage (VN) from the fully differential amplifier.
A constant-gm current source, arranged to generate a supply current for a Pierce oscillator. First and second transistors have source terminals connected to first and second supply rails, respectively, and drain terminals connected together and to the gate terminal of the first transistor. Third and fourth transistors have source terminals connected to the first and second supply rails, respectively, and drain terminals are connected together and to the gate terminal of the fourth transistor. An output portion varies the supply current in response to a voltage at the drain terminals of the third and fourth transistors. The gate terminals of the first and third transistors are connected together, and the gate terminals of the second and fourth transistors are connected together. An auto-calibration transistor has its source terminal connected to the first supply rail and its drain terminal connected to the source terminal of the first transistor.
H03B 5/04 - Modifications du générateur pour compenser des variations dans les grandeurs physiques, p.ex. alimentation, charge, température
H03B 5/36 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique l'élément actif de l'amplificateur comportant un dispositif semi-conducteur
A radio device for use in a DECT-2020 mesh network is configured to transmit DECT- 2020 radio beacons of a predetermined type periodically with a first beacon period. The radio device is further configured to determine that a predetermined condition is met, and, in response to determining that the predetermined condition is met, transmit DECT-2020 radio beacons of the predetermined type with a second beacon period, different from the first beacon period.
H04W 48/12 - Distribution d'informations relatives aux restrictions d'accès ou aux accès, p.ex. distribution de données d'exploration utilisant un canal de commande descendant
H04W 84/18 - Réseaux auto-organisés, p.ex. réseaux ad hoc ou réseaux de détection
A circuit portion is provided which includes an energy harvesting device producing a DC output; a DC-DC converter having an input connected to the DC output of the energy harvesting device; an output for connection to a load; and a monitoring module including a non-ohmic semiconductor element. The monitoring module is arranged to derive information relating to an output current flowing from the DC-DC converter by measuring a current through the non-ohmic semiconductor element. The monitoring module is arranged to adjust one or more parameters of the DC-DC converter based on the information relating to said output current flowing from the DC-DC converter.
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
H02M 1/00 - APPAREILS POUR LA TRANSFORMATION DE COURANT ALTERNATIF EN COURANT ALTERNATIF, DE COURANT ALTERNATIF EN COURANT CONTINU OU VICE VERSA OU DE COURANT CONTINU EN COURANT CONTINU ET EMPLOYÉS AVEC LES RÉSEAUX DE DISTRIBUTION D'ÉNERGIE OU DES SYSTÈMES D'ALI; TRANSFORMATION D'UNE PUISSANCE D'ENTRÉE EN COURANT CONTINU OU COURANT ALTERNATIF EN UNE PUISSANCE DE SORTIE DE CHOC; LEUR COMMANDE OU RÉGULATION - Détails d'appareils pour transformation
H02M 3/157 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation avec commande numérique
H02M 3/06 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p.ex. diviseur de tension
A radio communication system (100) comprises radio devices (200) configured as a radio mesh network (102). A source device transmits a message through the mesh network (102) for receipt by a destination device. The message encodes an identifier of the source device. Each of one or more intermediate devices, located sequentially along a path from the source to the destination, receives the message, encodes a respective identifier within the message, and transmits the message along the path towards the destination. The destination device receives the message and decodes the identifiers of the source and intermediate devices. It transmits a second message, for receipt by the source, that encodes the identifiers of the source and the intermediate devices. Each of the intermediate devices receives the second message, decodes an identifier of a next device along the communication path towards the source device, and uses the identifier to transmit the second message to the next device.
H04L 45/122 - Routage ou recherche de routes de paquets dans les réseaux de commutation de données Évaluation de la route la plus courte en minimisant les distances, p.ex. en sélectionnant une route avec un nombre minimal de sauts
H04W 40/22 - Sélection d'itinéraire ou de voie de communication, p.ex. routage basé sur l'énergie disponible ou le chemin le plus court utilisant la retransmission sélective en vue d'atteindre une station émettrice-réceptrice de base [BTS Base Transceiver Station] ou un point d'accès
H04W 40/24 - Gestion d'informations sur la connectabilité, p.ex. exploration de connectabilité ou mise à jour de connectabilité
A transmitter device includes a power supply, a power supply assessment module, a transmission power assessment module, and a data transmission module. The power assessment module assesses the present power delivery capability of the power supply. The transmission power assessment module assesses the power required for successful data transmission to an external communication party. The transmitter device compares the present power delivery capability to the power required for successful data transmission. If the comparison indicates that the present power delivery capability of the power supply is such that the power supply is able to supply sufficient power for successful data transmission, the transmitter device initiates data communication. If the comparison indicates that the present power delivery capability of the power supply is such that the power supply is not able to supply sufficient power for successful data transmission, the transmitter device does not initiate data communication.
A circuit portion is provided which includes an energy harvesting device producing a DC output; an inductor-less capacitor-based DC-DC converter, having an input connected to the DC output of the energy harvesting device; an output connected to a battery; and a voltage limiting module. The voltage limiting module includes a voltage sensor arranged to measure a voltage representative of a voltage at the battery and is arranged to limit a voltage provided by the DC-DC converter if the voltage representative of the voltage at the battery exceeds a threshold.
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p.ex. le niveau ou la densité de l'électrolyte
H01M 10/42 - Procédés ou dispositions pour assurer le fonctionnement ou l'entretien des éléments secondaires ou des demi-éléments secondaires
H02J 50/00 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique
A bootloader comprises software instructions for execution by a processor of an electronic processing device. The bootloader comprises an interpreter for interpreting a boot script stored in a memory of the processing device, and an integrity checker for checking the integrity of boot scripts stored in the memory. The bootloader comprises instructions for using the integrity checker to check the integrity of a first boot script of a plurality of boot scripts stored in the memory. The bootloader also comprises instructions for using the integrity checker to check the integrity of a second boot script of the plurality of boot scripts stored in the memory, independently of the integrity of the first boot script. The interpreter comprises instructions for interpreting a control-flow command in the first boot script, the control-flow command conditionally or unconditionally causing the bootloader to start interpreting commands from the second boot script.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
An electronic device comprises a synchronisation system that receives a signal clocked by a first clock signal having a first frequency and receives a second clock signal having said first frequency, but offset in phase from the first clock signal. The signal is delayed by an adjustable delay period. It is determined whether, following a logic transition in the delayed signal, the next clock edge received is an active edge or is a non-active edge. A calibration controller increases the delay period when the next clock edge is a non-active edge and maintains or decreases the delay period when the next clock edge is an active edge, or decreases the delay period when the next clock edge is an active edge and maintains or increases the delay period when the next clock edge is a non-active edge.
H03K 5/26 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p.ex. la pente, l'intégrale la caractéristique étant la durée, l'intervalle, la position, la fréquence ou la séquence
H03L 7/08 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase
A method of operating a digital radio receiver is provided as follows: a) receiving a radio signal comprising a symbol sequence; b) selecting a portion of the symbol sequence; c) determining a first error between the selected portion of the symbol sequence and a first predetermined symbol sequence using a difference metric; d) determining a set of second errors between the selected portion of the symbol sequence and a respective set of second predetermined symbol sequences, each formed by prepending different length portions of a predetermined preamble symbol sequence to a beginning of the first predetermined symbol sequence; and e) determining a minimum error from the first error and the set of second errors. If the first error is not the minimum error, a different portion of the symbol sequence is selected. Otherwise, a following portion of the symbol sequence is decoded to produce a data payload.
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H04L 27/144 - Circuits de démodulation; Circuits récepteurs avec démodulation utilisant les propriétés spectrales du signal reçu, p.ex. en utilisant des éléments sélectifs de la fréquence ou sensibles à la fréquence
H03M 13/41 - Estimation de séquence, c.à d. utilisant des méthodes statistiques pour la reconstitution des codes originaux utilisant l'algorithme de Viterbi ou des processeurs de Viterbi
A processing apparatus has a processor comprising a plurality of deferred-push processor registers and processor-register control circuitry. The processor-register control circuitry comprises a plurality of status registers, each status register corresponding to a different respective deferred-push register. The processor-register control circuitry is configured to: detect a write of a new value to a register of the deferred-push registers; and determine whether the status register for the deferred-push register has a first value, indicative of an unsaved status for the deferred-push register. The processor-control circuitry is configured, when the status register has the first value, to: read a current value from the deferred-push register before the writing of the new value to the deferred-push register completes; write the current value to a memory; and set the status register for the deferred-push register to a second value, indicative of a saved status for the deferred-push register.
An apparatus for demodulating a frequency-modulated signal comprises a joint frequency-offset & modulation-index estimator, and a signal demodulator. The joint estimator receives data representative of a preamble portion of the signal, modulated with predetermined preamble data. It jointly determines a frequency-offset estimate and a modulation-index estimate by using an optimization process that minimizes a cost function that is a function of the received data and that is parameterised by a frequency-offset parameter and by a modulation-index parameter. The signal demodulator receives data representative of a message portion of the signal, modulated with message data, and uses the frequency-offset estimate to demodulate the message.
H04L 27/144 - Circuits de démodulation; Circuits récepteurs avec démodulation utilisant les propriétés spectrales du signal reçu, p.ex. en utilisant des éléments sélectifs de la fréquence ou sensibles à la fréquence
39.
ADAPTATION OF DOWNLINK TO UPLINK SCHEDULING GAPS IN RADIO COMMUNICATIONS
A digital radio transceiver is configured to receive a downlink signal or channel addressed to the transceiver and begin transmission of an uplink signal or channel after a time gap following receipt of the downlink signal or channel. When the downlink signal or channel and the uplink signal or channel belong to a predetermined set of signals and channels, the time gap has a first value. When at least one of the downlink signal or channel and the uplink signal or channel do not belong to the predetermined set, the time gap has a second value, the second value being shorter than the first value.
A hardware accelerator comprises a direct memory access (DMA) system and an array of processing elements (PEs). Each PE comprises two data inputs and two data outputs and can perform a selectable logical or arithmetic operation. The array comprises configurable interconnects for selectively connecting outputs of the PEs to inputs of the PEs. A first data buffer comprises two or more first-edge cyclic registers, for connecting the DMA system to selected data inputs at a first edge of the PE array. A second data buffer comprises two or more second-edge linear or cyclic shift registers, for connecting selected data outputs of a second edge of the PE array to the DMA system.
A radio communication system, comprising a transmitter and a receiver wherein the transmitter is configured to transmit a multi-block request including control and timing information relating to a subsequent multi-block transmission, the receiver is configured to receive and decode said multi-block request, the transmitter is configured to subsequently transmit the multi-block transmission, wherein the multi-block transmission comprises a series of discrete blocks. Each block comprises a respective data payload and a synchronisation portion, and each synchronisation portion enables synchronisation between the transmitter and receiver when used in combination with the control and timing information, independently of receipt of other blocks in the multi-block transmission.
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H04W 4/80 - Services utilisant la communication de courte portée, p.ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
A method of, and apparatus for, demodulating a frequency-modulated signal. The method comprises: for each of a plurality of templates, performing a respective cross-correlation operation between the template and data representative of the frequency-modulated signal, each template comprising data representative of a signal that is frequency-modulated with predetermined preamble data using a different respective modulation index; generating frequency-offset data from one or more of the cross-correlation operations, the frequency-offset data being representative of a difference between a reference frequency and a carrier frequency of the frequency-modulated signal; determining a respective peak correlation-coefficient value from each of the cross-correlation operations; identifying a highest peak correlation-coefficient value in the determined peak correlation-coefficient values; determining a modulation index estimate in dependence on which template produced the highest peak correlation-coefficient value; and using the frequency-offset data and the modulation index estimate to demodulate at least a portion of the frequency-modulated signal.
H04L 27/156 - Circuits de démodulation; Circuits récepteurs avec démodulation utilisant les propriétés temporelles du signal reçu, p.ex. détectant la largeur de l'impulsion
A receiver comprises a matched filter bank, decision logic and a frequency offset estimator. The matched filter bank comprises an input for receiving data representative of a frequency- or phase-modulated signal. The decision logic generates a sequence of demodulated symbol values from outputs of the matched filter bank. The frequency offset estimator determines a first phase value from a first output and a second phase value from a second output of the matched filter bank, the second output being offset from the first by L symbol periods. It also determines a phase adjustment value from an L-symbol subsequence within the sequence of demodulated symbol values, each subsequence value being determined from values output by the matched filter bank between the first and second outputs. It estimates a frequency offset based on the difference between the first phase value plus the phase adjustment value, and the second phase value.
A system is provided which comprises a first circuit portion operating in a first clock domain with a first clock having a first frequency, a second circuit portion operating in a second clock domain with a second clock having a second, higher, frequency, and an interface circuit portion for transferring data from the first circuit portion to the second circuit portion. The interface circuit portion comprises a data input, a data output, a shared memory, a data storage portion, a signalling portion and a data access portion. The first circuit portion is arranged to assert data at the data input and to assert a data valid signal when asserting data at the data input. The data storage portion is configured to detect the data valid signal and to change an input data storage location of the shared memory in response to the data valid signal. The signalling portion is configured to generate an interface signal and to change a state of said interface signal in response to the data valid signal. The data access portion is configured to detect the change of state of the interface signal, to change an output data storage location of the shared memory in response to the change of state of the interface signal and to output a data ready signal to the second circuit portion in response to the change of state of the interface signal.
There is disclosed a radio system (100), and a method for operating a radio system. An orthogonal frequency-division multiple-access (OFDMA) radio signal (106) is transmitted, which has information digitally modulated onto it as OFDMA symbols on subcarriers in a first set of symbol periods. The radio signal (106) has a second set of symbol periods interleaved, with the first set of symbol periods in time, in which these subcarriers are unmodulated, so as to create a predetermined temporal pattern (221). The radio signal (106) is received on a first radio apparatus (101), which demodulates and uses information from the modulated symbol periods of the predetermined temporal pattern. A second radio apparatus (104) receives the same radio signal (106), detects the predetermined temporal pattern (221) of modulated and unmodulated symbol periods in the received radio signal, and, in response, activates its radio module (200) by generating an electrical wake-up signal.
A current limiting circuit portion for limiting an output current of an electronic device includes an input voltage line for receiving an input voltage and a trimming circuit portion. The trimming circuit portion includes a resistive part providing a first resistance that is configurable based on one or more resistance control signals applied thereto, and a condition-tracking part connected in series with the resistive part that includes a condition-tracking transistor, the condition-tracking part providing a second resistance that is dependent on temperature and the input voltage.
G05F 1/565 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final sensible à une condition du système ou de sa charge en plus des moyens sensibles aux écarts de la sortie du système, p.ex. courant, tension, facteur de puissance
G05F 1/595 - Dispositifs à semi-conducteurs connectés en série
G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
An asynchronous circuit portion for sampling an input signal is provided. The circuit portion comprises a sampling circuit portion arranged to sample the input signal to generate a sanitized output signal corresponding to the input signal; a comparison circuit portion arranged to compare the sanitized output signal with the input signal and to generate a change signal if the sanitized output signal does not correspond to the input signal; and a control circuit portion arranged to trigger the sampling circuit portion to sample the input signal to generate an updated sanitized output signal, in response to the change signal.
H03L 7/14 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase pour assurer une fréquence constante quand la tension d'alimentation ou la tension de correction fait défaut
H03L 7/085 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie
H03K 19/21 - Circuits OU EXCLUSIF, c. à d. donnant un signal de sortie si un signal n'existe qu'à une seule entrée; Circuits à COÏNCIDENCES, c. à d. ne donnant un signal de sortie que si tous les signaux d'entrée sont identiques
According to an aspect, there is provided a finite state machine repair circuitry comprising: at least one control unit, and at least one memory for storing instructions to be executed by the at least one control unit, wherein the at least one memory and the instructions are configured to, with the at least one control unit, cause the finite state machine repair circuitry at least to perform: causing overriding at least one of one or more input and/or output signals of a finite state machine circuit by corresponding one or more override signals generated by the finite state machine repair circuitry so as to a form a channel mimicking operation of said finite state machine circuit.
G06F 30/398 - Vérification ou optimisation de la conception, p.ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
A radio device comprises a radio transceiver, a resonator, a temperature measurement unit, a frequency synthesiser and a processing system. A temperature signal from the temperature measurement unit, representative of a measured temperature of the resonator, is used to determine an estimated frequency offset for the resonator at the measured temperature using a model stored in a memory of the processing system that relates frequency offset to temperature. A periodic signal from the resonator is provided to the frequency synthesizer, which, in dependence on the estimated frequency offset, is used to generate a periodic local signal. The radio transceiver receives a radio signal comprising a periodic component at a received signal frequency. An error value representative of a difference between the received signal frequency and a frequency of the periodic local signal is determined and used to update one or more parameters of the model stored in the memory.
H04B 1/38 - TRANSMISSION - Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission Émetteurs-récepteurs, c. à d. dispositifs dans lesquels l'émetteur et le récepteur forment un ensemble structural et dans lesquels au moins une partie est utilisée pour des fonctions d'émission et de réception
H03L 1/02 - Stabilisation du signal de sortie du générateur contre les variations de valeurs physiques, p.ex. de l'alimentation en énergie contre les variations de température uniquement
H03L 7/197 - Synthèse de fréquence indirecte, c. à d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle une différence de temps étant utilisée pour verrouiller la boucle, le compteur comptant entre des nombres variables dans le temps ou le diviseur de fréquence divisant par un facteur variable dans le temps, p.ex. pour obtenir une division de fréquence
09 - Appareils et instruments scientifiques et électriques
35 - Publicité; Affaires commerciales
38 - Services de télécommunications
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Semiconductors; semiconductor chips; semiconductor devices;
integrated circuits; power management integrated circuits;
electronic circuits; radio receivers and transmitters;
wireless transmitters and receivers; computer hardware;
computer hardware development tools; software development
kit (SDK); software development tools; downloadable computer
software and computer software platforms relating to
semiconductors, integrated circuits, Internet of Things
(IoT) devices and/or power management; downloadable computer
software and computer software platforms to enable users to
collect, view, monitor, retrieve, display, transmit,
process, analyse and/or manage data; downloadable computer
software and computer software platforms to enable users to
develop, test and manage prototype Internet of Things (IoT)
devices. Data management services; data collection services; business
data analysis services; data processing services;
computerised data verification. Electronic and wireless transmission of data; transmission
of data via satellite; electronic exchange of data;
electronic data transmission services for the dissemination
and exchange of profiles of IoT devices and systems;
providing access to, and interconnectivity with, data in
computer networks; providing access to, and
interconnectivity with, databases; providing access to, and
interconnectivity with, satellite data; providing access to,
and interconnectivity with, a global positioning system used
for monitoring, navigating, and locating objects and
persons; providing access to, and interconnectivity with,
online or offline computer database in the field of
satellite data and satellite data transmission; providing
access to, and interconnectivity with, Internet of Things
(IoT) systems and devices. Design and development of computer hardware, firmware and
software; installation, maintenance and updating of computer
software and firmware, including such services provided
over-the-air (OTA); user authentication services;
authentication services for computer security; technical
data analysis services; software as a service (SaaS)
relating to semiconductors, integrated circuits, Internet of
Things (IoT) devices and/or power management; providing
temporary use of non-downloadable computer software to
enable users to collect, view, monitor, retrieve, display,
transmit, process, analyse and/or manage data; providing
temporary use of non-downloadable computer software to
enable users to develop, test and manage prototype Internet
of Things (IoT) devices.
A method of operating a display system consisting of a plurality of light emitting diodes (LEDs) is disclosed. The LEDs are arranged in a plurality of groups and an integrated circuit provides power to the LEDs through a plurality of output pins connected to respective groups. The integrated circuit selectively determines the states of the output pins to illuminate the groups of LEDs in a repeating sequence such that each group is illuminated for a time dependent on a number of groups and a compensation factor. The compensation factor is dependent on at least a number of LEDs in the group.
09 - Appareils et instruments scientifiques et électriques
35 - Publicité; Affaires commerciales
38 - Services de télécommunications
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Semiconductors; semiconductor chips; semiconductor devices;
integrated circuits; power management integrated circuits;
electronic circuits; radio receivers and transmitters;
wireless transmitters and receivers; computer hardware;
computer hardware development tools; software development
kit (SDK); software development tools; downloadable computer
software and computer software platforms relating to
semiconductors, integrated circuits, internet of things
(IoT) devices and/or power management; downloadable computer
software and computer software platforms to enable users to
collect, view, monitor, retrieve, display, transmit,
process, analyse and/or manage data; downloadable computer
software and computer software platforms to enable users to
develop, test and manage prototype internet of things (IoT)
devices. Data management services; data collection services; business
data analysis services; data processing services;
computerised data verification. Electronic and wireless transmission of data; transmission
of data via satellite; electronic exchange of data;
electronic data transmission services for the dissemination
and exchange of profiles of IoT devices and systems;
providing access to, and interconnectivity with, data in
computer networks; providing access to, and
interconnectivity with, databases; providing access to, and
interconnectivity with, satellite data; providing access to,
and interconnectivity with, a global positioning system used
for monitoring, navigating, and locating objects and
persons; providing access to, and interconnectivity with,
online or offline computer database in the field of
satellite data and satellite data transmission; providing
access to, and interconnectivity with, internet of things
(IoT) systems and devices. Design and development of computer hardware, firmware and
software; installation, maintenance and updating of computer
software and firmware, including such services provided
over-the-air (OTA); cloud computing services; cloud hosting
provider services; cloud storage services for electronic
data; cloud repository services; cloud-based data protection
services; user authentication services; authentication
services for computer security; cloud provisioning services;
technical data analysis services; software as a service
(SaaS) relating to semiconductors, integrated circuits,
internet of things (IoT) devices and/or power management;
providing temporary use of non-downloadable computer
software to enable users to collect, view, monitor,
retrieve, display, transmit, process, analyse and/or manage
data; providing temporary use of non-downloadable computer
software to enable users to develop, test and manage
prototype internet of things (IoT) devices.
09 - Appareils et instruments scientifiques et électriques
35 - Publicité; Affaires commerciales
38 - Services de télécommunications
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Semiconductors; semiconductor chips; semiconductor devices;
integrated circuits; power management integrated circuits;
electronic circuits; radio receivers and transmitters;
wireless transmitters and receivers; computer hardware;
computer hardware development tools; software development
kit (SDK); software development tools; downloadable computer
software and computer software platforms relating to
semiconductors, integrated circuits, Internet of Things
(IoT) devices and/or power management; downloadable computer
software and computer software platforms to enable users to
collect, view, monitor, retrieve, display, transmit,
process, analyse and/or manage data; downloadable computer
software and computer software platforms to enable users to
develop, test and manage prototype Internet of Things (IoT)
devices. Data management services; data collection services; business
data analysis services; data processing services;
computerised data verification. Electronic and wireless transmission of data; transmission
of data via satellite; electronic exchange of data;
electronic data transmission services for the dissemination
and exchange of profiles of IoT devices and systems;
providing access to, and interconnectivity with, data in
computer networks; providing access to, and
interconnectivity with, databases; providing access to, and
interconnectivity with, satellite data; providing access to,
and interconnectivity with, a global positioning system used
for monitoring, navigating, and locating objects and
persons; providing access to, and interconnectivity with,
online or offline computer database in the field of
satellite data and satellite data transmission; providing
access to, and interconnectivity with, Internet of Things
(IoT) systems and devices. Design and development of computer hardware, firmware and
software; installation, maintenance and updating of computer
software and firmware, including such services provided
over-the-air (OTA); user authentication services;
authentication services for computer security; technical
data analysis services; software as a service (SaaS)
relating to semiconductors, integrated circuits, Internet of
Things (IoT) devices and/or power management; providing
temporary use of non-downloadable computer software to
enable users to collect, view, monitor, retrieve, display,
transmit, process, analyse and/or manage data; providing
temporary use of non-downloadable computer software to
enable users to develop, test and manage prototype Internet
of Things (IoT) devices.
A radio-frequency modulator apparatus comprises a baseband stage, a mixer stage and a radio-frequency stage. The baseband stage comprises: an input line for receiving an input current representative of a baseband input signal, a baseband transistor that passes some or all of the input current between a first and a second terminal thereof, an electrical connection between the input line and a control terminal of the baseband transistor, and an output line connected to said control terminal. The mixer stage receives a signal from the baseband stage and mixes it with a radio-frequency local-oscillator signal to generate a radio-frequency mixed signal. The radio-frequency stage receives the radio-frequency mixed signal, applies the radio-frequency mixed signal to a control terminal of a radio-frequency transistor causing it to pass a radio-frequency output current between a first and a second terminal thereof, and outputs the radio-frequency output current as an output signal.
H03D 7/12 - Transfert de modulation d'une porteuse à une autre, p.ex. changement de fréquence au moyen de dispositifs à semi-conducteurs ayant plus de deux électrodes
09 - Appareils et instruments scientifiques et électriques
35 - Publicité; Affaires commerciales
38 - Services de télécommunications
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Semiconductors; semiconductor chips; semiconductor devices;
integrated circuits; power management integrated circuits;
electronic circuits; radio receivers and transmitters;
wireless transmitters and receivers; computer hardware;
computer hardware development tools; software development
kit (SDK); software development tools; downloadable computer
software and computer software platforms relating to
semiconductors, integrated circuits, internet of things
(IoT) devices and/or power management; downloadable computer
software and computer software platforms to enable users to
collect, view, monitor, retrieve, display, transmit,
process, analyse and/or manage data; downloadable computer
software and computer software platforms to enable users to
develop, test and manage prototype internet of things (IoT)
devices. Data management services; data collection services; business
data analysis services; data processing services;
computerised data verification. Electronic and wireless transmission of data; transmission
of data via satellite; electronic exchange of data;
electronic data transmission services for the dissemination
and exchange of profiles of IoT devices and systems;
providing access to, and interconnectivity with, data in
computer networks; providing access to, and
interconnectivity with, databases; providing access to, and
interconnectivity with, satellite data; providing access to,
and interconnectivity with, a global positioning system used
for monitoring, navigating, and locating objects and
persons; providing access to, and interconnectivity with,
online or offline computer database in the field of
satellite data and satellite data transmission; providing
access to, and interconnectivity with, internet of things
(IoT) systems and devices. Design and development of computer hardware, firmware and
software; installation, maintenance and updating of computer
software and firmware, including such services provided
over-the-air (OTA); cloud computing services; cloud hosting
provider services; cloud storage services for electronic
data; cloud repository services; cloud-based data protection
services; user authentication services; authentication
services for computer security; cloud provisioning services;
technical data analysis services; software as a service
(SaaS) relating to semiconductors, integrated circuits,
internet of things (IoT) devices and/or power management;
providing temporary use of non-downloadable computer
software to enable users to collect, view, monitor,
retrieve, display, transmit, process, analyse and/or manage
data; providing temporary use of non-downloadable computer
software to enable users to develop, test and manage
prototype internet of things (IoT) devices.
09 - Appareils et instruments scientifiques et électriques
35 - Publicité; Affaires commerciales
38 - Services de télécommunications
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Semiconductors; semiconductor chips; semiconductor devices;
integrated circuits; power management integrated circuits;
electronic circuits; radio receivers and transmitters;
wireless transmitters and receivers; computer hardware;
computer hardware development tools; software development
kit (SDK); software development tools; downloadable computer
software and computer software platforms relating to
semiconductors, integrated circuits, internet of things
(IoT) devices and/or power management; downloadable computer
software and computer software platforms to enable users to
collect, view, monitor, retrieve, display, transmit,
process, analyse and/or manage data; downloadable computer
software and computer software platforms to enable users to
develop, test and manage prototype internet of things (IoT)
devices. Data management services; data collection services; business
data analysis services; data processing services;
computerised data verification. Electronic and wireless transmission of data; transmission
of data via satellite; electronic exchange of data;
electronic data transmission services for the dissemination
and exchange of profiles of IoT devices and systems;
providing access to, and interconnectivity with, data in
computer networks; providing access to, and
interconnectivity with, databases; providing access to, and
interconnectivity with, satellite data; providing access to,
and interconnectivity with, a global positioning system used
for monitoring, navigating, and locating objects and
persons; providing access to, and interconnectivity with,
online or offline computer database in the field of
satellite data and satellite data transmission; providing
access to, and interconnectivity with, internet of things
(IoT) systems and devices. Design and development of computer hardware, firmware and
software; installation, maintenance and updating of computer
software and firmware, including such services provided
over-the-air (OTA); cloud computing services; cloud hosting
provider services; cloud storage services for electronic
data; cloud repository services; cloud-based data protection
services; user authentication services; authentication
services for computer security; cloud provisioning services;
technical data analysis services; software as a service
(SaaS) relating to semiconductors, integrated circuits,
internet of things (IoT) devices and/or power management;
providing temporary use of non-downloadable computer
software to enable users to collect, view, monitor,
retrieve, display, transmit, process, analyse and/or manage
data; providing temporary use of non-downloadable computer
software to enable users to develop, test and manage
prototype internet of things (IoT) devices.
09 - Appareils et instruments scientifiques et électriques
35 - Publicité; Affaires commerciales
38 - Services de télécommunications
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Semiconductors; semiconductor chips; semiconductor devices;
integrated circuits; power management integrated circuits;
electronic circuits; radio receivers and transmitters;
wireless transmitters and receivers; computer hardware;
computer hardware development tools; software development
kit (SDK); software development tools; downloadable computer
software and computer software platforms relating to
semiconductors, integrated circuits, internet of things
(IoT) devices and/or power management; downloadable computer
software and computer software platforms to enable users to
collect, view, monitor, retrieve, display, transmit,
process, analyse and/or manage data; downloadable computer
software and computer software platforms to enable users to
develop, test and manage prototype internet of things (IoT)
devices. Data management services; data collection services; business
data analysis services; data processing services;
computerised data verification. Electronic and wireless transmission of data; transmission
of data via satellite; electronic exchange of data;
electronic data transmission services for the dissemination
and exchange of profiles of IoT devices and systems;
providing access to, and interconnectivity with, data in
computer networks; providing access to, and
interconnectivity with, databases; providing access to, and
interconnectivity with, satellite data; providing access to,
and interconnectivity with, a global positioning system used
for monitoring, navigating, and locating objects and
persons; providing access to, and interconnectivity with,
online or offline computer database in the field of
satellite data and satellite data transmission; providing
access to, and interconnectivity with, internet of things
(IoT) systems and devices. Design and development of computer hardware, firmware and
software; installation, maintenance and updating of computer
software and firmware, including such services provided
over-the-air (OTA); cloud computing services; cloud hosting
provider services; cloud storage services for electronic
data; cloud repository services; cloud-based data protection
services; user authentication services; authentication
services for computer security; cloud provisioning services;
technical data analysis services; software as a service
(SaaS) relating to semiconductors, integrated circuits,
internet of things (IoT) devices and/or power management;
providing temporary use of non-downloadable computer
software to enable users to collect, view, monitor,
retrieve, display, transmit, process, analyse and/or manage
data; providing temporary use of non-downloadable computer
software to enable users to develop, test and manage
prototype internet of things (IoT) devices.
An Orthogonal Frequency-Division Multiplexing digital radio transmitter is arranged to transmit a data packet comprising a plurality of Orthogonal Frequency-Division Multiplexing symbols. At least one of the symbols comprises a plurality of demodulation reference signals in a first plurality of frequency sub-carriers of the symbol. The transmitter is arranged to transmit a physical control channel at least partly distributed among a remainder of frequency sub-carriers of the symbol according to a calculated distribution. The transmitter calculates the distribution by arranging the remainder of frequency sub-carriers in a two-dimensional matrix such that said remainder of frequency sub-carriers have indices which are sequential in a first dimension and have a common increment in a second dimension, and allocating a second plurality of the remainder of frequency sub-carriers to the physical control channel sequentially in the second direction.
A method and device for phase-based ranging measurement between a first radio frequency transceiver and a second radio frequency transceiver. The method comprises the steps of:transmitting a radio frequency signal from the first radio frequency transceiver to the second radio frequency transceiver;receiving, on the first radio frequency transceiver, a radio frequency signal transmitted from the second radio frequency transceiver, the frequency being the same as the frequency transmitted from the first radio frequency transceiver; shifting the frequencies of the transmitted and the received radio signals of a transceiver to a same frequency, different from the transmitted and received frequencies, prior to being input to processing modules in the transmitter and receiver signal paths of the transceiver, where the modules in these signal paths are synchronized by sharing same clock domain; after an analogue to digital conversion module, converting the analogue transmitted and received radio frequency signals to digital signals, shifting the frequencies of the digital signals to the same frequency as the frequency of the transducer's transmitted and the received radio frequency signals, and measuring the frequency response between the transmitted and reflected radio frequency signals from the resulting digital signals. The device comprises means for performing said method.
G01S 13/10 - Systèmes pour mesurer la distance uniquement utilisant la transmission de trains discontinus d'ondes modulées par impulsions
G01S 13/30 - Systèmes pour mesurer la distance uniquement utilisant la transmission de trains discontinus d'ondes modulées par impulsions utilisant plus d'une impulsion par période radar
G01S 7/35 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe - Détails de systèmes non impulsionnels
H04B 1/408 - Circuits utilisant le même oscillateur pour générer à la fois la fréquence de l’émetteur et la fréquence de l’oscillateur local du récepteur la fréquence de l’oscillateur de l’émetteur étant identique à la fréquence de l’oscillateur local du récepteur
Radio transceiver device and method is provided. The method comprising sequentially transmitting, radio frequency signals on a plurality of radio channels, each channel being non-uniformly spaced and representing a distinct continuous tone, sequentially transmitting radio frequency signals with distinct continuous tones on same channels as those received from the first radio transceiver device, as well as measured phase difference of the radio frequency signals on each radio channel received from the first radio transceiver device, creating a first set of estimate candidates, repeatedly for the plurality radio channels, determining an optimal phase unwrapping vector candidate based on the first set of estimate candidates and the measured phase differences of signals received on the first and second transceiver devices to determine a second set of candidates, and calculating the distance between the first and second radio transceiver devices using the optimal phase unwrapping vector candidate and the second set.
A method for controlled phase adjustment and coherent modulation in a radio frequency transceiver is provided. The radio frequency transceiver comprises an analogue circuitry for transmitting and receiving radio frequency signals and an all-digital phase locked loop controlled by a Phase Locked Loop, PLL, Control unit (200). The method comprises: receiving a phase shift, and based thereon, deriving a corresponding digital control signal; inputting the digital control signal to the PLL Control unit (200), the control signal defining a temporary iteration pattern of delays to be used by a configurable delay block, DTC (240); locking a radio frequency oscillator signal of a Digital Controlled Oscillator (220) in the phase locked loop to the temporary iteration pattern of delays; adjusting the phase of the frequency signal in digital circuitry, until the signal phase matches the phase shift defined by the digital control signal.
H03L 7/085 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie
G01S 13/06 - Systèmes déterminant les données relatives à la position d'une cible
H04B 1/403 - Circuits utilisant le même oscillateur pour générer à la fois la fréquence de l’émetteur et la fréquence de l’oscillateur local du récepteur
09 - Appareils et instruments scientifiques et électriques
35 - Publicité; Affaires commerciales
38 - Services de télécommunications
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Semiconductors; semiconductor chips; semiconductor devices; integrated circuits; power management integrated circuits; electronic circuits; radio receivers and transmitters; wireless transmitters and receivers; computer hardware; computer hardware development tools; software development kit (SDK); software development tools; downloadable computer software and computer software platforms relating to semiconductors, integrated circuits, internet of things (IoT) devices and/or power management; downloadable computer software and computer software platforms to enable users to collect, view, monitor, retrieve, display, transmit, process, analyse and/or manage data; downloadable computer software and computer software platforms to enable users to develop, test and manage prototype internet of things (IoT) devices Data management services; data collection services; business data analysis services; data processing services; computerised data verification Electronic and wireless transmission of data; transmission of data via satellite; electronic exchange of data; electronic data transmission services for the dissemination and exchange of profiles of IoT devices and systems; providing access to, and interconnectivity with, data in computer networks; providing access to, and interconnectivity with, databases; providing access to, and interconnectivity with, satellite data; providing access to, and interconnectivity with, a global positioning system used for monitoring, navigating, and locating objects and persons; providing access to, and interconnectivity with, online or offline computer database in the field of satellite data and satellite data transmission; providing access to, and interconnectivity with, internet of things (IoT) systems and devices Design and development of computer hardware, firmware and software; installation, maintenance and updating of computer software and firmware, including such services provided over-the-air (OTA); cloud computing services; cloud hosting provider services; cloud storage services for electronic data; cloud repository services; cloud-based data protection services; user authentication services; authentication services for computer security; cloud provisioning services; technical data analysis services; software as a service (SaaS) relating to semiconductors, integrated circuits, internet of things (IoT) devices and/or power management; providing temporary use of non-downloadable computer software to enable users to collect, view, monitor, retrieve, display, transmit, process, analyse and/or manage data; providing temporary use of non-downloadable computer software to enable users to develop, test and manage prototype internet of things (IoT) devices
09 - Appareils et instruments scientifiques et électriques
35 - Publicité; Affaires commerciales
38 - Services de télécommunications
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Semiconductors; semiconductor chips; semiconductor devices; integrated circuits; power management integrated circuits; electronic circuits; radio receivers and transmitters; wireless transmitters and receivers; computer hardware; computer hardware development tools; software development kit (SDK); software development tools; downloadable computer software and computer software platforms relating to semiconductors, integrated circuits, Internet of Things (IoT) devices and/or power management; downloadable computer software and computer software platforms to enable users to collect, view, monitor, retrieve, display, transmit, process, analyse and/or manage data; downloadable computer software and computer software platforms to enable users to develop, test and manage prototype Internet of Things (IoT) devices Data management services; data collection services; business data analysis services; data processing services; computerised data verification Electronic and wireless transmission of data; transmission of data via satellite; electronic exchange of data; electronic data transmission services for the dissemination and exchange of profiles of IoT devices and systems; providing access to, and interconnectivity with, data in computer networks; providing access to, and interconnectivity with, databases; providing access to, and interconnectivity with, satellite data; providing access to, and interconnectivity with, a global positioning system used for monitoring, navigating, and locating objects and persons; providing access to, and interconnectivity with, online or offline computer database in the field of satellite data and satellite data transmission; providing access to, and interconnectivity with, Internet of Things (IoT) systems and devices Design and development of computer hardware, firmware and software; installation, maintenance and updating of computer software and firmware, including such services provided over-the-air (OTA); user authentication services; authentication services for computer security; technical data analysis services; software as a service (SaaS) relating to semiconductors, integrated circuits, Internet of Things (IoT) devices and/or power management; providing temporary use of non-downloadable computer software to enable users to collect, view, monitor, retrieve, display, transmit, process, analyse and/or manage data; providing temporary use of non-downloadable computer software to enable users to develop, test and manage prototype Internet of Things (IoT) devices
09 - Appareils et instruments scientifiques et électriques
35 - Publicité; Affaires commerciales
38 - Services de télécommunications
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Semiconductors; semiconductor chips; semiconductor devices; integrated circuits; power management integrated circuits; electronic circuits; radio receivers and transmitters; wireless transmitters and receivers; computer hardware; computer hardware development tools; software development kit (SDK); software development tools; downloadable computer software and computer software platforms relating to semiconductors, integrated circuits, internet of things (IoT) devices and/or power management; downloadable computer software and computer software platforms to enable users to collect, view, monitor, retrieve, display, transmit, process, analyse and/or manage data; downloadable computer software and computer software platforms to enable users to develop, test and manage prototype internet of things (IoT) devices Data management services; data collection services; business data analysis services; data processing services; computerised data verification Electronic and wireless transmission of data; transmission of data via satellite; electronic exchange of data; electronic data transmission services for the dissemination and exchange of profiles of IoT devices and systems; providing access to, and interconnectivity with, data in computer networks; providing access to, and interconnectivity with, databases; providing access to, and interconnectivity with, satellite data; providing access to, and interconnectivity with, a global positioning system used for monitoring, navigating, and locating objects and persons; providing access to, and interconnectivity with, online or offline computer database in the field of satellite data and satellite data transmission; providing access to, and interconnectivity with, internet of things (IoT) systems and devices Design and development of computer hardware, firmware and software; installation, maintenance and updating of computer software and firmware, including such services provided over-the-air (OTA); cloud computing services; cloud hosting provider services; cloud storage services for electronic data; cloud repository services; cloud-based data protection services; user authentication services; authentication services for computer security; cloud provisioning services; technical data analysis services; software as a service (SaaS) relating to semiconductors, integrated circuits, internet of things (IoT) devices and/or power management; providing temporary use of non-downloadable computer software to enable users to collect, view, monitor, retrieve, display, transmit, process, analyse and/or manage data; providing temporary use of non-downloadable computer software to enable users to develop, test and manage prototype internet of things (IoT) devices
09 - Appareils et instruments scientifiques et électriques
35 - Publicité; Affaires commerciales
38 - Services de télécommunications
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Semiconductors; semiconductor chips; semiconductor devices; integrated circuits; power management integrated circuits; electronic circuits; radio receivers and transmitters; wireless transmitters and receivers; computer hardware; computer hardware development tools; software development kit (SDK); software development tools; downloadable computer software and computer software platforms relating to semiconductors, integrated circuits, internet of things (IoT) devices and/or power management; downloadable computer software and computer software platforms to enable users to collect, view, monitor, retrieve, display, transmit, process, analyse and/or manage data; downloadable computer software and computer software platforms to enable users to develop, test and manage prototype internet of things (IoT) devices Data management services; data collection services; business data analysis services; data processing services; computerised data verification Electronic and wireless transmission of data; transmission of data via satellite; electronic exchange of data; electronic data transmission services for the dissemination and exchange of profiles of IoT devices and systems; providing access to, and interconnectivity with, data in computer networks; providing access to, and interconnectivity with, databases; providing access to, and interconnectivity with, satellite data; providing access to, and interconnectivity with, a global positioning system used for monitoring, navigating, and locating objects and persons; providing access to, and interconnectivity with, online or offline computer database in the field of satellite data and satellite data transmission; providing access to, and interconnectivity with, internet of things (IoT) systems and devices Design and development of computer hardware, firmware and software; installation, maintenance and updating of computer software and firmware, including such services provided over-the-air (OTA); cloud computing services; cloud hosting provider services; cloud storage services for electronic data; cloud repository services; cloud-based data protection services; user authentication services; authentication services for computer security; cloud provisioning services; technical data analysis services; software as a service (SaaS) relating to semiconductors, integrated circuits, internet of things (IoT) devices and/or power management; providing temporary use of non-downloadable computer software to enable users to collect, view, monitor, retrieve, display, transmit, process, analyse and/or manage data; providing temporary use of non-downloadable computer software to enable users to develop, test and manage prototype internet of things (IoT) devices
09 - Appareils et instruments scientifiques et électriques
35 - Publicité; Affaires commerciales
38 - Services de télécommunications
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Semiconductors; semiconductor chips; semiconductor devices; integrated circuits; power management integrated circuits; electronic circuits; radio receivers and transmitters; wireless transmitters and receivers; computer hardware; computer hardware development tools; software development kit (SDK); software development tools; downloadable computer software and computer software platforms relating to semiconductors, integrated circuits, internet of things (IoT) devices and/or power management; downloadable computer software and computer software platforms to enable users to collect, view, monitor, retrieve, display, transmit, process, analyse and/or manage data; downloadable computer software and computer software platforms to enable users to develop, test and manage prototype internet of things (IoT) devices Data management services; data collection services; business data analysis services; data processing services; computerised data verification Electronic and wireless transmission of data; transmission of data via satellite; electronic exchange of data; electronic data transmission services for the dissemination and exchange of profiles of IoT devices and systems; providing access to, and interconnectivity with, data in computer networks; providing access to, and interconnectivity with, databases; providing access to, and interconnectivity with, satellite data; providing access to, and interconnectivity with, a global positioning system used for monitoring, navigating, and locating objects and persons; providing access to, and interconnectivity with, online or offline computer database in the field of satellite data and satellite data transmission; providing access to, and interconnectivity with, internet of things (IoT) systems and devices Design and development of computer hardware, firmware and software; installation, maintenance and updating of computer software and firmware, including such services provided over-the-air (OTA); cloud computing services; cloud hosting provider services; cloud storage services for electronic data; cloud repository services; cloud-based data protection services; user authentication services; authentication services for computer security; cloud provisioning services; technical data analysis services; software as a service (SaaS) relating to semiconductors, integrated circuits, internet of things (IoT) devices and/or power management; providing temporary use of non-downloadable computer software to enable users to collect, view, monitor, retrieve, display, transmit, process, analyse and/or manage data; providing temporary use of non-downloadable computer software to enable users to develop, test and manage prototype internet of things (IoT) devices
09 - Appareils et instruments scientifiques et électriques
35 - Publicité; Affaires commerciales
38 - Services de télécommunications
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Semiconductors; semiconductor chips; semiconductor devices; integrated circuits; power management integrated circuits; electronic circuits; radio receivers and transmitters; wireless transmitters and receivers; computer hardware; computer hardware development tools; software development kit (SDK); software development tools; downloadable computer software and computer software platforms relating to semiconductors, integrated circuits, Internet of Things (IoT) devices and/or power management; downloadable computer software and computer software platforms to enable users to collect, view, monitor, retrieve, display, transmit, process, analyse and/or manage data; downloadable computer software and computer software platforms to enable users to develop, test and manage prototype Internet of Things (IoT) devices Data management services; data collection services; business data analysis services; data processing services; computerised data verification Electronic and wireless transmission of data; transmission of data via satellite; electronic exchange of data; electronic data transmission services for the dissemination and exchange of profiles of IoT devices and systems; providing access to, and interconnectivity with, data in computer networks; providing access to, and interconnectivity with, databases; providing access to, and interconnectivity with, satellite data; providing access to, and interconnectivity with, a global positioning system used for monitoring, navigating, and locating objects and persons; providing access to, and interconnectivity with, online or offline computer database in the field of satellite data and satellite data transmission; providing access to, and interconnectivity with, Internet of Things (IoT) systems and devices Design and development of computer hardware, firmware and software; installation, maintenance and updating of computer software and firmware, including such services provided over-the-air (OTA); user authentication services; authentication services for computer security; technical data analysis services; software as a service (SaaS) relating to semiconductors, integrated circuits, Internet of Things (IoT) devices and/or power management; providing temporary use of non-downloadable computer software to enable users to collect, view, monitor, retrieve, display, transmit, process, analyse and/or manage data; providing temporary use of non-downloadable computer software to enable users to develop, test and manage prototype Internet of Things (IoT) devices
A time delay circuit comprising a plurality of differential delay cells each having a respective time delay and being arranged in series. Each delay cell comprises first and second inverter sub-cells, each comprising a respective PMOS transistor and an NMOS transistor arranged in series such that their respective drain terminals are connected at a drain node. Each of the transistors has a back-gate terminal and is arranged such that a respective voltage applied to said back-gate terminal linearly controls its respective threshold voltage. The back-gate terminal of the PMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell and/or the back-gate terminal of the NMOS transistor in each inverter sub-cell is connected to the drain node of the other sub-cell. A control signal varies the time delay of the delay cell by adjusting a voltage supplied to a back-gate terminal of a transistor.
H03K 5/134 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés utilisant une chaîne de dispositifs actifs de retard avec des transistors à effet de champ
A method of digital radio communication between a central device and a peripheral device. The peripheral device transmits a repeated burst of advertising packets on a primary physical channel, each packet comprising an advertising field indicating an availability to form a connection. The advertising field comprises an address identifying the peripheral device. The peripheral device transmits a subsequent advertising packet on an auxiliary channel. The central device receives a packet from the burst of packets, decodes the advertising field and compares the address to one or more desired connection addresses to determine whether to initiate a connection to the peripheral device. If the address matches a desired connection address, the central device initiates a connection to the peripheral device. If the address does not match a desired connection address, the central device resumes listening for further advertising packets.
H04W 8/00 - Gestion de données relatives au réseau
H04W 28/18 - Négociation des paramètres de télécommunication sans fil
H04W 28/24 - Négociation de l'agrément du niveau de service [SLA Service Level Agreement]; Négociation de la qualité de service [QoS Quality of Service]
A boost converter circuit is provided comprising an input arranged to receive an input voltage; an output arranged to generate a higher, output voltage for powering a further circuit portion; a switching arrangement arranged to control generation of the output voltage; and a control circuit portion arranged to monitor the input voltage and control the switching arrangement in response to the input voltage.
H02M 1/00 - APPAREILS POUR LA TRANSFORMATION DE COURANT ALTERNATIF EN COURANT ALTERNATIF, DE COURANT ALTERNATIF EN COURANT CONTINU OU VICE VERSA OU DE COURANT CONTINU EN COURANT CONTINU ET EMPLOYÉS AVEC LES RÉSEAUX DE DISTRIBUTION D'ÉNERGIE OU DES SYSTÈMES D'ALI; TRANSFORMATION D'UNE PUISSANCE D'ENTRÉE EN COURANT CONTINU OU COURANT ALTERNATIF EN UNE PUISSANCE DE SORTIE DE CHOC; LEUR COMMANDE OU RÉGULATION - Détails d'appareils pour transformation
H02M 1/36 - Moyens pour mettre en marche ou arrêter les convertisseurs
H02M 1/42 - Circuits ou dispositions pour corriger ou ajuster le facteur de puissance dans les convertisseurs ou les onduleurs
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
According to an aspect, there is provided a solution for controlling communication in a processor arrangement, the arrangement comprising a core processor, a peripheral unit operationally connected to the core processor; a given number of input/output unit lines, the arrangement being further connectable to external peripherals. The solution comprises performing down-counting (600) utilising at least one counter of two down-counters of a given length, generating (602) an event when a counter reaches zero value and synchronizing (604) signalling on input/output unit lines and communication of core processor with external peripherals on the basis of the event.
A method of operating a digital radio transmitter device in accordance with a predetermined communication protocol defining a transmission timing tolerance. The method comprises: transmitting a plurality of first periodic transmissions in accordance with said predetermined communication protocol having a first period and an inherent timing uncertainty less than said transmission timing tolerance; performing a plurality of second periodic actions with a second period wherein said first and second periods are equal to each other or an integer multiple of each other; and adjusting a timing of one or more of the first periodic transmissions by an amount greater than said inherent timing uncertainty but less than or equal to a difference between said inherent timing uncertainty and said transmission timing tolerance so as to change said first period temporarily by an amount less than or equal to said transmission timing tolerance, thereby changing an offset between said first transmissions and said second actions.
A method and system for moving data from a source memory to a destination memory by a processor are disclosed. The processor has a plurality of registers and the source memory stores a sequence of instructions that include one or more load instructions and one or more store instructions. The processor moves the load instructions from the source memory to the destination memory. Then, the processor initiates execution of the load instructions from the destination memory in order to load the data from the source memory to one or more registers in the processor. Execution then returns to the sequence of instructions stored in the source memory, and the processor stores the data from the registers to the destination memory.
A method and system for moving data from a source memory to a destination memory by a processor is disclosed herein. The destination memory stores a sequence of instructions and the sequence of instructions comprises one or more load instructions and one or more store instructions. The processor initially moves the one or more store instructions from the destination memory to the source memory. The processor then executes the one or more load instructions from the destination memory. On executing the one or more load instructions, the data is loaded from the source memory to at least one register in the processor. The processor further initiates execution of the one or more store instructions stored in the source memory. On executing the one or more store instructions from the source memory, the processor stores the data from the at least one register to the destination memory.
15261212566) CS PMOS transistors have substantially equal transconductances. The first and second cross-coupled cascode NMOS transistors have substantially equal transconductances.
H03F 3/26 - Amplificateurs push-pull; Déphaseurs pour ceux-ci
H03F 1/22 - Modifications des amplificateurs pour réduire l'influence défavorable de l'impédance interne des éléments amplificateurs par utilisation de couplage dit "cascode", c. à d. étage avec cathode ou émetteur à la masse suivi d'un étage avec grille ou base à la masse respectivement
H03F 3/193 - Amplificateurs à haute fréquence, p.ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs comportant des dispositifs à effet de champ
A circuit portion for a radio transceiver comprises: a power amplifier for use when the transceiver operates in a transmission mode, a low-noise amplifier for use when the transceiver operates in a reception mode, a voltage control circuit portion, and a transformer. The transformer comprises a primary winding with a terminal for connecting to an antenna, and a secondary winding comprising a first terminal, a second terminal and a third terminal located between the first and second terminals. The power amplifier is connected to the secondary winding, the low-noise amplifier is connected to both the primary and secondary windings and the voltage control circuit portion is connected to the third terminal of the secondary winding. The voltage control circuit portion applies a first voltage to the third terminal when the transceiver operates in the transmission mode and applies a second, different voltage when the transceiver operates in the reception mode.
H03L 7/099 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H04B 1/18 - Circuits d'entrée, p.ex. pour le couplage à une antenne ou à une ligne de transmission
H04B 1/38 - TRANSMISSION - Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission Émetteurs-récepteurs, c. à d. dispositifs dans lesquels l'émetteur et le récepteur forment un ensemble structural et dans lesquels au moins une partie est utilisée pour des fonctions d'émission et de réception
77.
RADIO TRANSMITTER APPARATUS WITH CRYPTOGRAPHIC ENGINE
An integrated-circuit radio transmitter chip comprises a transmitter, a cryptographic engine and control circuitry for the cryptographic engine. The cryptographic engine performs a cryptographic operation by receiving input data, performing a first process to generate first result data and a second process to generate second result data. The first and second result data are used to generate output data. In response to determining that the transmitter is active, the control circuity controls the cryptographic engine to perform the first process and prevents the cryptographic engine from performing the second process while the transmitter is active. The control circuitry controls the cryptographic engine to perform the second process in response to determining that the transmitter is not active.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
A system for synchronizing communications in a radio ranging process involves transmitting calibration signals according to a predetermined schedule of nominal transmission times. Timing offsets are determined. A start time is determined for a transmission of a ranging signal. The start time is earlier than a nominal start time of the ranging signal by at least the largest timing offset. Another system for synchronization involves a radio device transmitting a calibration signal to a second radio device and receiving a calibration response signal from the second radio device. A time-of-flight value is determined in dependence on a time of departure of the calibration signal and a time of arrival of the calibration response signal. A ranging signal is transmitted at a time determined in dependence on the determined time-of-flight value. A ranging response signal is received and processed to determine a range value.
A radio receiver comprises a matched filter bank and a decision unit. The matched filter bank has a plurality of filter modules for generating correlation-strength data from a sampled radio signal, each filter module being configured to cross-correlate the sampled signal with data representing a respective filter sequence. The decision unit is configured to use the correlation-strength data to generate a sequence of decoded symbols from the sampled signal. The matched filter bank and/or decision unit are configured to determine the value of each symbol in the sequence in part based on the value of a respective earlier decoded symbol from the sequence of decoded symbols.
An integrated-circuit device (1) comprising a non-volatile memory (NVM) (15), a debug port (21), and debug-port control circuitry (17) for controlling access to the integrated- circuit device (1) through the debug port (21). The debug-port control circuitry (17) is configured to read a first bit array and a second bit array from respective predetermined locations in the NVM (15) in a single read cycle. The second bit array is distinct from the first bit array, and at least the second bit array contains a plurality of bits. The debug-port control circuitry (17) is further configured to determine whether the first bit array has a first predetermined bit pattern and whether the second bit array has a pattern other than a second predetermined bit pattern, and to control access through the debug port (21) at least partly in dependence on said determination.
G06F 21/75 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par inhibition de l’analyse de circuit ou du fonctionnement, p.ex. pour empêcher l'ingénierie inverse
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
81.
Management of power to internal subsystems within a system on chip
An electronic device comprising a system on chip and an external module. The system on chip includes a plurality of internal subsystems and a power management system including a plurality of internal voltage regulators which supply power to the plurality of internal subsystems. Each of the internal voltage regulators has an associated current limiter. The external module includes at least one external voltage regulator which can provide power to at least one of the internal subsystems. The power management system during a start-up phase enables the internal voltage regulators and the current limiters and in a subsequent phase determines an externally powered set of the internal subsystems, disables the corresponding internal voltage regulators, and disables the current limiters associated with the internal subsystems not externally powered.
G06F 1/32 - Moyens destinés à économiser de l'énergie
G06F 1/3206 - Surveillance d’événements, de dispositifs ou de paramètres initiant un changement de mode d’alimentation
G06F 1/3296 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par diminution de la tension d’alimentation ou de la tension de fonctionnement
A radio transmitter device (102) for transmitting radio signals according to an orthogonal frequency division multiplexing protocol using a plurality of frequency resources is provided. The radio transmitter device (102) is configured to transmit a plurality of reference signals (310) within a first subset (306) of said plurality of frequency resources at a first monitoring occasion (206) and a second monitoring occasion (208) and transmit paging information (302) within a second subset (304) of said plurality of frequency resources at one or more of the first and second monitoring occasions (206, 208), wherein the first subset (306) has a larger frequency span than the second subset (304).
A radio receiver device determines whether a digital radio signal includes a predetermined cyclic preamble. An input portion samples the digital radio signal and generates a plurality of samples for storage in a buffer. A first autocorrelator correlates first and second subsets of the samples to generate a first correlation metric, the second subset having been stored in the buffer earlier than said first subset by an even integer multiple of half of the preamble period. A second autocorrelator correlates first and third subsets of the plurality of samples to generate a second correlation metric, the third subset having been stored in the buffer earlier than said first subset by an odd integer multiple of half of the preamble period. A processing portion calculates a difference between the correlation metrics and determines that the radio signal includes the predetermined cyclic preamble when the difference is greater than a threshold value.
An integrated circuit (10) comprises an analog-to-digital converter (ADC) (26), wherein: the ADC (26) is configured to receive a periodic analog test signal and to convert the periodic analog test signal into a sequence of digital codes during a test period. The integrated circuit (10) is configured to generate and store, on the integrated circuit (10), count data representative of, for each of one or more codes, a respective count of how often the ADC (26) outputs the respective code during the test period. The integrated circuit (10) is configured to output the count data from the integrated circuit (10), or is configured to process the count data on the integrated circuit (10) to determine a measure of non-linearity of the ADC (26).
H03M 1/46 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p.ex. du type à approximations successives avec convertisseur numérique/analogique pour fournir des valeurs de référence au convertisseur
85.
SYSTEM TIMER WITH HIGH RESOLUTION AND ULTRA-LOW POWER OPERATION
An integrated-circuit device (1) comprises a low-resolution timer (20) and a high-resolution timer (30). The low-resolution timer (20) comprises a first oscillator (22) that outputs a first clock signal at a first frequency, and a first counter register (24) incremented by the first clock signal. The high-resolution timer (30) comprises a second oscillator (32) that outputs a second clock signal at a second frequency, greater than the first frequency, and a second counter register (34) incremented by the second clock signal. The device (1) operates in one of a plurality of states, including an active state (94) in which both the high-resolution timer (30) and the low-resolution timer (20) are enabled, and a sleep state (90) in which the high- resolution timer (30) is disabled and the low-resolution timer (20) is enabled. The device (1) transitions from the sleep state (90) to the active state (94) by writing a value to the second counter register (34) based on a value held in the first counter register (24).
G06F 1/14 - Dispositions pour le contrôle du temps, p.ex. horloge temps réel
G06F 1/04 - Génération ou distribution de signaux d'horloge ou de signaux dérivés directement de ceux-ci
G06F 1/3287 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par la mise hors tension d’une unité fonctionnelle individuelle dans un ordinateur
G06F 1/3237 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par désactivation de la génération ou de la distribution du signal d’horloge
G06F 1/3206 - Surveillance d’événements, de dispositifs ou de paramètres initiant un changement de mode d’alimentation
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
86.
SYNCHRONISED MULTI-PROCESSOR OPERATING SYSTEM TIMER
An integrated-circuit device (1) comprises a plurality of processor cores (2, 3) and a system timer (10). The system timer (10) includes a first oscillator (32) that outputs a first clock signal at a first frequency, a first counter register (34) incremented by the first clock signal and a plurality of event registers (52). Each event register (52) triggers an event when a value held therein is determined to be equal to a value held in the first counter register (34). The first counter register (34) is readable by each of the plurality of processor cores (2, 3), and each of the processor cores (2, 3) are capable of writing to at least one of the event registers (52).
G06F 1/14 - Dispositions pour le contrôle du temps, p.ex. horloge temps réel
G06F 1/04 - Génération ou distribution de signaux d'horloge ou de signaux dérivés directement de ceux-ci
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
G06F 1/3206 - Surveillance d’événements, de dispositifs ou de paramètres initiant un changement de mode d’alimentation
G06F 1/3237 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par désactivation de la génération ou de la distribution du signal d’horloge
G06F 1/3287 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par la mise hors tension d’une unité fonctionnelle individuelle dans un ordinateur
G06F 21/70 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur
An oscillator arrangement is provided, comprising a relaxation oscillator having an active state and an inactive state; a bias current circuit portion arranged to provide a bias current to the relaxation oscillator during said active state; and an electronic switch arranged to isolate said relaxation oscillator from the bias current circuit portion when in said inactive state. The oscillator arrangement is arranged to store an internal voltage value associated with said bias current and the bias current circuit portion is arranged to use the stored internal voltage value to generate the bias current when the oscillator is started up from the inactive state to the active state.
H03B 5/24 - Elément déterminant la fréquence comportant résistance, et soit capacité, soit inductance, p.ex. oscillateur à glissement de phase l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
H03K 3/014 - Modifications du générateur pour assurer le démarrage des oscillations
H03K 4/501 - Génération d'impulsions ayant comme caractéristique essentielle une pente définie ou des parties en gradins à forme triangulaire en dents de scie utilisant comme éléments actifs des dispositifs à semi-conducteurs dans laquelle la tension en dents de scie est produite à travers un condensateur le début de la période de retour étant déterminé par l'amplitude de la tension à travers le condensateur, p.ex. avec un comparateur
A clock selector circuit receives a first input clock signal (CLK1) having a first frequency, and a second input clock signal (CLK2) having a second frequency. A phase difference detector is configured to detect when a phase difference occurs, over time, between the first input clock signal (CLK1) and the second input clock signal (CLK2), determined using when a clock edge crosses zero, and to signal this zero crossing to switching circuitry. The switching circuitry is configured, in response to receiving a zero-crossing signal from the phase difference detector, to detect an edge of opposite type to the predetermined type in the first input clock signal (CLK1) or in the second input clock signal (CLK2), and, in response to detecting said edge of opposite type, to switch an output clock signal (CLK_OUT) between the first input clock signal (CLK1) and the second input clock signal (CLK2).
H03K 3/00 - Circuits pour produire des impulsions électriques; Circuits monostables, bistables ou multistables
H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p.ex. des signaux d'horloge
G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
H03K 5/26 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p.ex. la pente, l'intégrale la caractéristique étant la durée, l'intervalle, la position, la fréquence ou la séquence
A circuit portion (2) comprises a mapping module (10), a source component (6a, 6b, 6c), a destination component (6a, 6b, 6c) and a memory (12). The mapping module (10) comprises a plurality of channels that each provides a connection for connecting two components (6a, 6b, 6c) of the circuit portion (2) in a one-to-one relationship. The source component (6a, 6b, 6c) is arranged in a first clock or power domain (4a, 4b, 4c), and the destination component (6a, 6b, 6c) is arranged in a second clock or power domain (4a, 4b, 4c). In response to an assertion of an event signal (8) or an interrupt by the source component (6a, 6b, 6c), the mapping module (10) is configured to forward the event signal (8) or interrupt to the destination component (6a, 6b, 6c) via only one channel of the plurality of channels so as to cause the destination component (6a, 6b, 6c) to perform a corresponding task according to a mapping stored in the memory (12).
An electronic device (1) for processing near-field communication signals includes first and second antenna connection terminals (3a, 3b) for connection to a near-field antenna (2), a linear load (10) and a voltage clamp (8), each connected between said connection terminals (3a, 3b). A current flowing through the linear load (10) has a substantially linear, positive relationship with a voltage across the linear load, defining a conductance of the linear load (10). The conductance of the linear load (10) is adjustable. The voltage clamp (8) has an adjustable clamping voltage. The electronic device (1) also includes a peak detector (12) arranged to detect an amplitude of an incoming near-field communication signal across said antenna connection terminals (3a, 3b), and a control circuit (14) arranged to adjust the conductance of the linear load (10) and the clamping voltage of the voltage clamp (8) based on the amplitude detected by the peak detector (12), so as to regulate the voltage swing across the antenna connection terminals (3a, 3b).
H04B 5/00 - Systèmes de transmission à induction directe, p.ex. du type à boucle inductive
G01R 19/04 - Mesure des valeurs de pointe d'un courant alternatif ou des impulsions
G05F 1/10 - Régulation de la tension ou de l'intensité
H03K 5/24 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p.ex. la pente, l'intégrale la caractéristique étant l'amplitude
A method of operating a radio receiver device comprises receiving a plurality of signals with a plurality of corresponding frequencies; applying respective gains to each of the plurality of signals; and storing the gain applied to each signal and its corresponding frequency. The method comprises subsequently receiving a further signal with a further frequency; and applying a further gain to the further signal. The further gain is determined using at least one of the stored gains according to a difference between the further frequency and at least one of the plurality of corresponding frequencies.
An asynchronous circuit portion (2) for sampling an input signal (14) is provided. The asynchronous circuit portion comprises a sampling circuit portion (4) arranged to receive the input signal and to generate first and second sample signals; a first storage element (6) arranged to generate a first storage signal on a first storage output (40) on reception of the first sample signal; and a second storage element (8) arranged to generate a second storage signal on a second storage output (42) on reception of the second sample signal. A control circuit portion (10) is arranged to detect if either of said first and second storage signals has been generated, to fix the first and second storage outputs and to generate a sample ready signal. The circuit portion generates an output signal (16) corresponding to the input signal using the first storage output when the sample ready signal is generated.
The cut-off frequency of an electronic filter (10) having a nominal transfer function and a nominal cut-off frequency is estimated by: applying (104) a first signal at a first frequency to an input of the filter (10) while sampling (106) an output of the filter (10) in order to obtain a first magnitude measurement, the first frequency being less than the nominal cut-off frequency; applying a second signal (108) at a second frequency to the input of the filter (10) while sampling (110) the output of the filter (10) in order to obtain a second magnitude measurement, the second frequency being greater than the nominal cut-off frequency; and estimating (112, 114) the cut-off frequency of the filter (10) based on the nominal transfer function, the first magnitude measurement, and the second magnitude measurement.
H03H 7/01 - Réseaux à deux accès sélecteurs de fréquence
H03H 11/12 - Réseaux sélectifs en fréquence à deux accès utilisant des amplificateurs avec contre-réaction
H03H 7/46 - Réseaux pour connecter plusieurs sources ou charges, fonctionnant sur des fréquences ou dans des bandes de fréquence différentes, à une charge ou à une source commune
94.
FAST-LOCKING ALL-DIGITAL PHASE-LOCKED LOOP AND APPLICATIONS THEREOF
According to an aspect, there is provided an all-digital phase-locked loop, ADPLL, for a radio receiver, transmitter or transceiver. The ADPLL comprises a time-to-digital converter for generating a digital time signal based on an external reference clock signal and a feedback signal, a switched capacitor digitally controlled oscillator, SC-DCO, for generating a radio frequency signal used as the feed-back signal, a phase-locked loop for controlling the SC-DCO based on the digital time signal for achieving a phase and frequency lock and digital processing means. The digital processing means are configured to maintain, in at least one memory, a lookup table defining a plurality of switching configurations of the SC-DCO corresponding to a plurality of frequencies of the radio frequency signal and to cause the phase-locked loop controller to adjust the switching configuration of the SC-DCO according to the lookup table.
H03L 7/10 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase pour assurer la synchronisation initiale ou pour élargir le domaine d'accrochage
H03L 7/099 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03L 7/093 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
Analog to digital conversion circuitry has an input sampling buffer, which has an input sampling capacitor for sampling an analog signal. The conversion circuitry also has a successive-approximation-register analog to digital converter (SAR-ADC) which converts the sampled analog signal to a digital signal. The input sampling buffer has an amplifier and a gain-control capacitor, and has an amplification configuration and an error-feedback configuration. In the amplification configuration, the input sampling capacitor is coupled to the amplifier and gain-control capacitor, with the gain-control capacitor connected in feedback with the amplifier, for applying gain to the sampled analog signal. In the error-feedback configuration, the gain-control capacitor is decoupled from the input sampling capacitor and receives a residue voltage from the SAR-ADC, such that the level of the analog signal determined in the amplification configuration varies depending on the residue voltage received onto the gain-control capacitor in the error-feedback configuration.
According to an aspect, there is provided a method for transmitting a low-power radio signal, comprising: transmitting, by a radio device, a data radio signal by using binary frequency-shift-keying modulation introducing a phase change between consecutive bit intervals in the data radio signal; and transmitting, by the radio device, a wake-up radio signal using the binary frequency-shift-keying modulation where repetition coding is applied before the frequency-shift-keying to eliminate the phase change between consecutive bit intervals in the wake-up radio signal.
H04L 27/20 - Circuits de modulation; Circuits émetteurs
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H04W 4/80 - Services utilisant la communication de courte portée, p.ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
H04L 27/152 - Circuits de démodulation; Circuits récepteurs avec démodulation utilisant les propriétés spectrales du signal reçu, p.ex. en utilisant des éléments sélectifs de la fréquence ou sensibles à la fréquence utilisant des oscillateurs commandés, p.ex. dispositions PLL
A circuit portion (2) comprises a signal generator (4), clocked by a clock signal, for generating an alternating logic signal comprising a repeated sequence of alternating logic transitions. A circuit sub-portion (10) introduces a delay to the alternating logic signal. An edge-travel detector samples the delayed alternating logic signal and outputs an edge-travel signal representative of a timing of a logic transition in the alternating logic signal with respect to the clock signal. A mask block compares the edge-travel signal with a mask signal to determine whether the timing of the logic transition matches one or more candidate timings, and outputs a comparison signal in dependence on this determination.
G06F 21/75 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par inhibition de l’analyse de circuit ou du fonctionnement, p.ex. pour empêcher l'ingénierie inverse
An integrated-circuit device (10) comprises a processor (12), a program memory (16), a hardware-based key generation system (22, 26) that outputs a selectable device identity key of a plurality of predetermined device identity keys, and a one- time programmable (OTP) memory (30) for storing one or more public cryptographic keys. When a public cryptographic key is stored in the OTP memory (30), and when software is stored in the program memory (16), the device (10) uses the public cryptographic key to determine whether the software stored in the program memory (16) is validly signed by a private cryptographic key associated with the public cryptographic key, before the software is executed by the processor (12). The device (10) controls which device identity key of the plurality of predetermined device identity keys is output by the hardware-based key generation system (22, 26) at least partly in dependence on the outcome of this determination.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
According to an aspect, there is provided an apparatus comprising: a bulk-controlled switch circuit comprising a first transistor coupled to a load and having a source coupled to a source voltage and a drain coupled to a drain voltage, a second transistor and a third transistor coupled, in parallel with the first transistor, to one another in series between the source voltage and the drain voltage, wherein a bulk of the first transistor is coupled with bulks of the second transistor and the third transistor, wherein a gate of the second transistor is coupled to the source voltage via a first impedance circuit and a gate of the third transistor is coupled to the drain voltage via a second impedance circuit to form a comparator switch controlled by the source voltage and the drain voltage and to dynamically switch a greater one of the source voltage and the drain voltage to the load; a first current generator circuit and a second current generator circuit; a first current mirror circuit biased by the first current generator circuit, responsive to the source voltage, and configured to trigger the second transistor to couple the source voltage to the load when the source voltage is above the drain voltage; a second current mirror circuit biased by the second current generator circuit, responsive to the drain voltage, and configured to trigger the third transistor to couple the drain voltage to the load when the drain voltage is above the source voltage.
H02M 3/156 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
A circuit portion comprising a clock domain is disclosed. A first clock is arranged to clock components in the clock domain. An analogue to digital converter is clocked by a second clock with a duty cycle. The second clock is derived from the first clock. The analogue to digital converter is arranged to output a feedback signal upon finishing a conversion of a sample, and the feedback signal is arranged to control the duty cycle.
H03M 1/38 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p.ex. du type à approximations successives
H03K 19/17736 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels des ressources de routage
