According to an aspect, there is provided a swing-boosted differential oscillator and a method for trimming the oscillator. The oscillator comprises a switch (110) for connecting a set of capacitors (C1, C2) alternately to power supply and ground (102, 112) based on a switching control (116A, 116B), a comparator (114) configured to produce the switching control (116A, 116B) by comparing a voltage of the capacitors (C1, C2) at the inputs (VC1, VC2) of the comparator to a preset threshold voltage, and a trimmable resistor (RCAL) connecting the inputs (VC1, VC2) of the comparator, the resistor controlling the frequency of the output (118) of the oscillator.
H03B 5/24 - Elément déterminant la fréquence comportant résistance, et soit capacité, soit inductance, p.ex. oscillateur à glissement de phase l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
H03K 3/012 - Modifications du générateur pour améliorer le temps de réponse ou pour diminuer la consommation d'énergie
H03K 3/013 - Modifications du générateur en vue d'éviter l'action du bruit ou des interférences
H03K 4/502 - Génération d'impulsions ayant comme caractéristique essentielle une pente définie ou des parties en gradins à forme triangulaire en dents de scie utilisant comme éléments actifs des dispositifs à semi-conducteurs dans laquelle la tension en dents de scie est produite à travers un condensateur le début de la période de retour étant déterminé par l'amplitude de la tension à travers le condensateur, p.ex. avec un comparateur le condensateur étant chargé à partir d'une source à courant constant
According to an aspect, there is provided a swing-boosted differential oscillator (500) and a method for trimming the oscillator. The oscillator comprises a switch (110') for connecting a set of capacitors (C1, C2) alternately to power supply and ground (102', 112') based on a switching control (116A', 116B'), two comparators (502, 504) configured to produce an output signal of the oscillator (ck) and the switching control (116A', 116B') via a multiplexer (508) by comparing a voltage of the capacitors (C1, C2) at the inputs (VC1, VC2) of the comparators to a threshold voltage (VBB), where the comparators comprising back gate bias input (fig. 5: 804, fig. 8: Vbb, 804) for controlling the threshold voltage of the comparators, the threshold voltage trimming the frequency of the output signal of the oscillator.
H03K 4/502 - Génération d'impulsions ayant comme caractéristique essentielle une pente définie ou des parties en gradins à forme triangulaire en dents de scie utilisant comme éléments actifs des dispositifs à semi-conducteurs dans laquelle la tension en dents de scie est produite à travers un condensateur le début de la période de retour étant déterminé par l'amplitude de la tension à travers le condensateur, p.ex. avec un comparateur le condensateur étant chargé à partir d'une source à courant constant
H03K 19/00 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion
A radio frequency device arranged to communicate with a radio network cell of a radio network is provided. The radio frequency device is arranged to operate in a first mode in which the radio frequency device communicates with a radio network cell using a standard communication protocol; to operate in a second mode in which the radio frequency device communicates with a radio network cell using a coverage enhancement communication protocol; to operate in a third mode in which the radio frequency device is restricted from communicating with a radio network cell using the coverage enhancement communication protocol; and to transition from operating in the third mode to operating in the second mode without operating in the first mode.
H04W 4/70 - Services pour la communication de machine à machine ou la communication de type machine
H04W 48/12 - Distribution d'informations relatives aux restrictions d'accès ou aux accès, p.ex. distribution de données d'exploration utilisant un canal de commande descendant
H04W 48/18 - Sélection d'un réseau ou d'un service de télécommunications
H04W 60/00 - Rattachement à un réseau, p.ex. enregistrement; Suppression du rattachement à un réseau, p.ex. annulation de l'enregistrement
H04W 60/04 - Rattachement à un réseau, p.ex. enregistrement; Suppression du rattachement à un réseau, p.ex. annulation de l'enregistrement utilisant des événements déclenchés
H04W 68/02 - Dispositions pour augmenter l'efficacité du canal d'avertissement ou de messagerie
H04W 88/06 - Dispositifs terminaux adapté au fonctionnement dans des réseaux multiples, p.ex. terminaux multi-mode
According to an aspect, there is provided a relaxation oscillator (100) comprising first (101, 11) and second (102, 12) current sources and a comparator (103) having a first input (103-) connected to the first current source, a second input (103+) connected to the second current source and an output. One of the first and second inputs is an inverting input and other one of the first and second inputs is a non- inverting input. The relaxation oscillator further comprises a resistive circuit (110) connected between the first input of the comparator and the ground. The resistive circuit comprises at least a first resistor (R) and a capacitor charging circuit (111) connected between the second input of the comparator and the ground. The capacitor charging circuit comprises a capacitor (105, C), a second resistor (107, R0) connected in series with the capacitor and a switch (106) connected in parallel with the capacitor. The switch is configured to be controlled based on the output of the comparator.
H03K 4/502 - Génération d'impulsions ayant comme caractéristique essentielle une pente définie ou des parties en gradins à forme triangulaire en dents de scie utilisant comme éléments actifs des dispositifs à semi-conducteurs dans laquelle la tension en dents de scie est produite à travers un condensateur le début de la période de retour étant déterminé par l'amplitude de la tension à travers le condensateur, p.ex. avec un comparateur le condensateur étant chargé à partir d'une source à courant constant
A battery characterisation system for determining one or more characteristics of a battery is provided. The system comprises a controllable load arranged to be connected to a battery and a voltage sensor arranged to measure a voltage output from said battery. The battery characterisation system is arranged to receive information identifying one or more nominal properties of said battery; to select a discharge profile based on said one or more nominal properties; to control the controllable load to discharge said battery according to said discharge profile; to record the voltage output measured by the voltage sensor and a current output from the battery as the battery is being discharged; and to determine one or more characteristics of the battery using said recorded voltage output and current output.
G01R 31/36 - Dispositions pour le test, la mesure ou la surveillance de l’état électrique d’accumulateurs ou de batteries, p.ex. de la capacité ou de l’état de charge
G01R 31/3842 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p.ex. état de charge combinant des mesures de tension et de courant
A battery-powered device is disclosed comprising a battery and a voltage sensor arranged to measure a terminal voltage of the battery. The battery-powered device is arranged to: a) determine a current flowing into or out of the battery, b) predict a terminal voltage of the battery using the current and an estimated state of charge of the battery, c) measure an actual terminal voltage of the battery using the voltage sensor, d) compare the predicted terminal voltage with the actual terminal voltage and e) update the estimated state of charge of the battery based on said comparison. The battery-powered device is arranged to repeat steps (a)-(e) at one or more subsequent times, said one or more subsequent times being determined based on an operating state of the battery-powered device.
G01R 31/367 - Logiciels à cet effet, p.ex. pour le test des batteries en utilisant une modélisation ou des tables de correspondance
G01R 31/3842 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p.ex. état de charge combinant des mesures de tension et de courant
A boost converter circuit is disclosed comprising an input arranged to receive an input voltage from a battery; an output arranged to generate a higher, output voltage for powering a further circuit portion; and a switching arrangement arranged to control generation of the output voltage. The boost converter circuit compares the input voltage with a first reference input voltage and controls the switching arrangement to limit the output current of the boost converter circuit based on the comparison of the input voltage and the first reference input voltage. The boost converter circuit monitors a parameter indicative of a condition of the battery, determines a second, lower reference input voltage in response to the monitored parameter, compares the input voltage with the second reference input voltage and controls the switching arrangement to limit the output current of the boost converter circuit based on the comparison of the input voltage and the second reference input voltage.
H02M 1/00 - APPAREILS POUR LA TRANSFORMATION DE COURANT ALTERNATIF EN COURANT ALTERNATIF, DE COURANT ALTERNATIF EN COURANT CONTINU OU VICE VERSA OU DE COURANT CONTINU EN COURANT CONTINU ET EMPLOYÉS AVEC LES RÉSEAUX DE DISTRIBUTION D'ÉNERGIE OU DES SYSTÈMES D'ALI; TRANSFORMATION D'UNE PUISSANCE D'ENTRÉE EN COURANT CONTINU OU COURANT ALTERNATIF EN UNE PUISSANCE DE SORTIE DE CHOC; LEUR COMMANDE OU RÉGULATION - Détails d'appareils pour transformation
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
A receiver device is provided which is arranged to receive a data packet from a transmitter device comprising a control portion and a payload portion, said control portion comprising a feedback request indicator. The receiver device is arranged to detect the feedback request indicator, to attempt to decode the payload portion of the data packet, to transmit an acknowledgement to the transmitter device if said feedback request indicator indicates that an acknowledgement is requested for said data packet, and to process said data packet without transmitting an acknowledgement if said feedback request indicator indicates that an acknowledgement is not requested for said data packet.
H04L 1/1607 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue en utilisant un canal de retour dans lesquelles le canal de retour transporte des signaux de contrôle, p.ex. répétition de signaux de demande - Détails du signal de contrôle
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
H04L 1/1829 - Dispositions spécialement adaptées au point de réception
A receiver device comprises receiving circuitry configured to receive a radio signal modulated using frequency shift keying or phase shift keying, the radio signal comprising a plurality of successive symbol intervals, differential detector circuitry configured to multiply a signal for a current symbol interval with a first reference signal and output a first output signal for the current symbol interval, wherein the first reference signal corresponds to a conjugate of a signal for a first symbol interval preceding the current symbol interval and multiply the signal for the current symbol interval with a second reference signal and output a second output signal for the current symbol interval, wherein the second reference signal corresponds to a conjugate of a signal for a second symbol interval preceding the first symbol interval, in which the conjugate of the signal for the second symbol interval has been phase adjusted in dependence on a previous phase decision for the first symbol interval preceding the current symbol interval, combining circuitry configured to combine the first output signal for the current symbol interval and the second output signal for the current symbol interval to obtain a combined signal for the current symbol interval, and decision circuitry configured to output a phase decision for the current symbol interval in dependence upon the combined signal.
A radio device for use in a DECT-2020 mesh network is configured to transmit DECT- 2020 radio beacons of a predetermined type periodically with a first beacon period. The radio device is further configured to determine that a predetermined condition is met, and, in response to determining that the predetermined condition is met, transmit DECT-2020 radio beacons of the predetermined type with a second beacon period, different from the first beacon period.
H04W 48/12 - Distribution d'informations relatives aux restrictions d'accès ou aux accès, p.ex. distribution de données d'exploration utilisant un canal de commande descendant
H04W 84/18 - Réseaux auto-organisés, p.ex. réseaux ad hoc ou réseaux de détection
A radio communication system (100) comprises radio devices (200) configured as a radio mesh network (102). A source device transmits a message through the mesh network (102) for receipt by a destination device. The message encodes an identifier of the source device. Each of one or more intermediate devices, located sequentially along a path from the source to the destination, receives the message, encodes a respective identifier within the message, and transmits the message along the path towards the destination. The destination device receives the message and decodes the identifiers of the source and intermediate devices. It transmits a second message, for receipt by the source, that encodes the identifiers of the source and the intermediate devices. Each of the intermediate devices receives the second message, decodes an identifier of a next device along the communication path towards the source device, and uses the identifier to transmit the second message to the next device.
H04L 45/122 - Routage ou recherche de routes de paquets dans les réseaux de commutation de données Évaluation de la route la plus courte en minimisant les distances, p.ex. en sélectionnant une route avec un nombre minimal de sauts
H04W 40/22 - Sélection d'itinéraire ou de voie de communication, p.ex. routage basé sur l'énergie disponible ou le chemin le plus court utilisant la retransmission sélective en vue d'atteindre une station émettrice-réceptrice de base [BTS Base Transceiver Station] ou un point d'accès
H04W 40/24 - Gestion d'informations sur la connectabilité, p.ex. exploration de connectabilité ou mise à jour de connectabilité
A digital radio transceiver is configured to receive a downlink signal or channel addressed to the transceiver and begin transmission of an uplink signal or channel after a time gap following receipt of the downlink signal or channel. When the downlink signal or channel and the uplink signal or channel belong to a predetermined set of signals and channels, the time gap has a first value. When at least one of the downlink signal or channel and the uplink signal or channel do not belong to the predetermined set, the time gap has a second value, the second value being shorter than the first value.
A radio communication system, comprising a transmitter and a receiver wherein the transmitter is configured to transmit a multi-block request including control and timing information relating to a subsequent multi-block transmission, the receiver is configured to receive and decode said multi-block request, the transmitter is configured to subsequently transmit the multi-block transmission, wherein the multi-block transmission comprises a series of discrete blocks. Each block comprises a respective data payload and a synchronisation portion, and each synchronisation portion enables synchronisation between the transmitter and receiver when used in combination with the control and timing information, independently of receipt of other blocks in the multi-block transmission.
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H04W 4/80 - Services utilisant la communication de courte portée, p.ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
A system is provided which comprises a first circuit portion operating in a first clock domain with a first clock having a first frequency, a second circuit portion operating in a second clock domain with a second clock having a second, higher, frequency, and an interface circuit portion for transferring data from the first circuit portion to the second circuit portion. The interface circuit portion comprises a data input, a data output, a shared memory, a data storage portion, a signalling portion and a data access portion. The first circuit portion is arranged to assert data at the data input and to assert a data valid signal when asserting data at the data input. The data storage portion is configured to detect the data valid signal and to change an input data storage location of the shared memory in response to the data valid signal. The signalling portion is configured to generate an interface signal and to change a state of said interface signal in response to the data valid signal. The data access portion is configured to detect the change of state of the interface signal, to change an output data storage location of the shared memory in response to the change of state of the interface signal and to output a data ready signal to the second circuit portion in response to the change of state of the interface signal.
There is disclosed a radio system (100), and a method for operating a radio system. An orthogonal frequency-division multiple-access (OFDMA) radio signal (106) is transmitted, which has information digitally modulated onto it as OFDMA symbols on subcarriers in a first set of symbol periods. The radio signal (106) has a second set of symbol periods interleaved, with the first set of symbol periods in time, in which these subcarriers are unmodulated, so as to create a predetermined temporal pattern (221). The radio signal (106) is received on a first radio apparatus (101), which demodulates and uses information from the modulated symbol periods of the predetermined temporal pattern. A second radio apparatus (104) receives the same radio signal (106), detects the predetermined temporal pattern (221) of modulated and unmodulated symbol periods in the received radio signal, and, in response, activates its radio module (200) by generating an electrical wake-up signal.
A method and device for phase-based ranging measurement between a first radio frequency transceiver and a second radio frequency transceiver. The method comprises the steps of:transmitting a radio frequency signal from the first radio frequency transceiver to the second radio frequency transceiver;receiving, on the first radio frequency transceiver, a radio frequency signal transmitted from the second radio frequency transceiver, the frequency being the same as the frequency transmitted from the first radio frequency transceiver; shifting the frequencies of the transmitted and the received radio signals of a transceiver to a same frequency, different from the transmitted and received frequencies, prior to being input to processing modules in the transmitter and receiver signal paths of the transceiver, where the modules in these signal paths are synchronized by sharing same clock domain; after an analogue to digital conversion module, converting the analogue transmitted and received radio frequency signals to digital signals, shifting the frequencies of the digital signals to the same frequency as the frequency of the transducer's transmitted and the received radio frequency signals, and measuring the frequency response between the transmitted and reflected radio frequency signals from the resulting digital signals. The device comprises means for performing said method.
G01S 13/10 - Systèmes pour mesurer la distance uniquement utilisant la transmission de trains discontinus d'ondes modulées par impulsions
G01S 13/30 - Systèmes pour mesurer la distance uniquement utilisant la transmission de trains discontinus d'ondes modulées par impulsions utilisant plus d'une impulsion par période radar
G01S 7/35 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe - Détails de systèmes non impulsionnels
H04B 1/408 - Circuits utilisant le même oscillateur pour générer à la fois la fréquence de l’émetteur et la fréquence de l’oscillateur local du récepteur la fréquence de l’oscillateur de l’émetteur étant identique à la fréquence de l’oscillateur local du récepteur
Radio transceiver device and method is provided. The method comprising sequentially transmitting, radio frequency signals on a plurality of radio channels, each channel being non-uniformly spaced and representing a distinct continuous tone, sequentially transmitting radio frequency signals with distinct continuous tones on same channels as those received from the first radio transceiver device, as well as measured phase difference of the radio frequency signals on each radio channel received from the first radio transceiver device, creating a first set of estimate candidates, repeatedly for the plurality radio channels, determining an optimal phase unwrapping vector candidate based on the first set of estimate candidates and the measured phase differences of signals received on the first and second transceiver devices to determine a second set of candidates, and calculating the distance between the first and second radio transceiver devices using the optimal phase unwrapping vector candidate and the second set.
A method for controlled phase adjustment and coherent modulation in a radio frequency transceiver is provided. The radio frequency transceiver comprises an analogue circuitry for transmitting and receiving radio frequency signals and an all-digital phase locked loop controlled by a Phase Locked Loop, PLL, Control unit (200). The method comprises: receiving a phase shift, and based thereon, deriving a corresponding digital control signal; inputting the digital control signal to the PLL Control unit (200), the control signal defining a temporary iteration pattern of delays to be used by a configurable delay block, DTC (240); locking a radio frequency oscillator signal of a Digital Controlled Oscillator (220) in the phase locked loop to the temporary iteration pattern of delays; adjusting the phase of the frequency signal in digital circuitry, until the signal phase matches the phase shift defined by the digital control signal.
H03L 7/085 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie
G01S 13/06 - Systèmes déterminant les données relatives à la position d'une cible
H04B 1/403 - Circuits utilisant le même oscillateur pour générer à la fois la fréquence de l’émetteur et la fréquence de l’oscillateur local du récepteur
A boost converter circuit is provided comprising an input arranged to receive an input voltage; an output arranged to generate a higher, output voltage for powering a further circuit portion; a switching arrangement arranged to control generation of the output voltage; and a control circuit portion arranged to monitor the input voltage and control the switching arrangement in response to the input voltage.
H02M 1/00 - APPAREILS POUR LA TRANSFORMATION DE COURANT ALTERNATIF EN COURANT ALTERNATIF, DE COURANT ALTERNATIF EN COURANT CONTINU OU VICE VERSA OU DE COURANT CONTINU EN COURANT CONTINU ET EMPLOYÉS AVEC LES RÉSEAUX DE DISTRIBUTION D'ÉNERGIE OU DES SYSTÈMES D'ALI; TRANSFORMATION D'UNE PUISSANCE D'ENTRÉE EN COURANT CONTINU OU COURANT ALTERNATIF EN UNE PUISSANCE DE SORTIE DE CHOC; LEUR COMMANDE OU RÉGULATION - Détails d'appareils pour transformation
H02M 1/36 - Moyens pour mettre en marche ou arrêter les convertisseurs
H02M 1/42 - Circuits ou dispositions pour corriger ou ajuster le facteur de puissance dans les convertisseurs ou les onduleurs
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
According to an aspect, there is provided a solution for controlling communication in a processor arrangement, the arrangement comprising a core processor, a peripheral unit operationally connected to the core processor; a given number of input/output unit lines, the arrangement being further connectable to external peripherals. The solution comprises performing down-counting (600) utilising at least one counter of two down-counters of a given length, generating (602) an event when a counter reaches zero value and synchronizing (604) signalling on input/output unit lines and communication of core processor with external peripherals on the basis of the event.
15261212566) CS PMOS transistors have substantially equal transconductances. The first and second cross-coupled cascode NMOS transistors have substantially equal transconductances.
H03F 3/26 - Amplificateurs push-pull; Déphaseurs pour ceux-ci
H03F 1/22 - Modifications des amplificateurs pour réduire l'influence défavorable de l'impédance interne des éléments amplificateurs par utilisation de couplage dit "cascode", c. à d. étage avec cathode ou émetteur à la masse suivi d'un étage avec grille ou base à la masse respectivement
H03F 3/193 - Amplificateurs à haute fréquence, p.ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs comportant des dispositifs à effet de champ
An integrated-circuit device (1) comprising a non-volatile memory (NVM) (15), a debug port (21), and debug-port control circuitry (17) for controlling access to the integrated- circuit device (1) through the debug port (21). The debug-port control circuitry (17) is configured to read a first bit array and a second bit array from respective predetermined locations in the NVM (15) in a single read cycle. The second bit array is distinct from the first bit array, and at least the second bit array contains a plurality of bits. The debug-port control circuitry (17) is further configured to determine whether the first bit array has a first predetermined bit pattern and whether the second bit array has a pattern other than a second predetermined bit pattern, and to control access through the debug port (21) at least partly in dependence on said determination.
G06F 21/75 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par inhibition de l’analyse de circuit ou du fonctionnement, p.ex. pour empêcher l'ingénierie inverse
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
A radio transmitter device (102) for transmitting radio signals according to an orthogonal frequency division multiplexing protocol using a plurality of frequency resources is provided. The radio transmitter device (102) is configured to transmit a plurality of reference signals (310) within a first subset (306) of said plurality of frequency resources at a first monitoring occasion (206) and a second monitoring occasion (208) and transmit paging information (302) within a second subset (304) of said plurality of frequency resources at one or more of the first and second monitoring occasions (206, 208), wherein the first subset (306) has a larger frequency span than the second subset (304).
An integrated circuit (10) comprises an analog-to-digital converter (ADC) (26), wherein: the ADC (26) is configured to receive a periodic analog test signal and to convert the periodic analog test signal into a sequence of digital codes during a test period. The integrated circuit (10) is configured to generate and store, on the integrated circuit (10), count data representative of, for each of one or more codes, a respective count of how often the ADC (26) outputs the respective code during the test period. The integrated circuit (10) is configured to output the count data from the integrated circuit (10), or is configured to process the count data on the integrated circuit (10) to determine a measure of non-linearity of the ADC (26).
H03M 1/46 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p.ex. du type à approximations successives avec convertisseur numérique/analogique pour fournir des valeurs de référence au convertisseur
25.
SYSTEM TIMER WITH HIGH RESOLUTION AND ULTRA-LOW POWER OPERATION
An integrated-circuit device (1) comprises a low-resolution timer (20) and a high-resolution timer (30). The low-resolution timer (20) comprises a first oscillator (22) that outputs a first clock signal at a first frequency, and a first counter register (24) incremented by the first clock signal. The high-resolution timer (30) comprises a second oscillator (32) that outputs a second clock signal at a second frequency, greater than the first frequency, and a second counter register (34) incremented by the second clock signal. The device (1) operates in one of a plurality of states, including an active state (94) in which both the high-resolution timer (30) and the low-resolution timer (20) are enabled, and a sleep state (90) in which the high- resolution timer (30) is disabled and the low-resolution timer (20) is enabled. The device (1) transitions from the sleep state (90) to the active state (94) by writing a value to the second counter register (34) based on a value held in the first counter register (24).
G06F 1/14 - Dispositions pour le contrôle du temps, p.ex. horloge temps réel
G06F 1/04 - Génération ou distribution de signaux d'horloge ou de signaux dérivés directement de ceux-ci
G06F 1/3287 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par la mise hors tension d’une unité fonctionnelle individuelle dans un ordinateur
G06F 1/3237 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par désactivation de la génération ou de la distribution du signal d’horloge
G06F 1/3206 - Surveillance d’événements, de dispositifs ou de paramètres initiant un changement de mode d’alimentation
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
26.
SYNCHRONISED MULTI-PROCESSOR OPERATING SYSTEM TIMER
An integrated-circuit device (1) comprises a plurality of processor cores (2, 3) and a system timer (10). The system timer (10) includes a first oscillator (32) that outputs a first clock signal at a first frequency, a first counter register (34) incremented by the first clock signal and a plurality of event registers (52). Each event register (52) triggers an event when a value held therein is determined to be equal to a value held in the first counter register (34). The first counter register (34) is readable by each of the plurality of processor cores (2, 3), and each of the processor cores (2, 3) are capable of writing to at least one of the event registers (52).
G06F 1/14 - Dispositions pour le contrôle du temps, p.ex. horloge temps réel
G06F 1/04 - Génération ou distribution de signaux d'horloge ou de signaux dérivés directement de ceux-ci
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
G06F 1/3206 - Surveillance d’événements, de dispositifs ou de paramètres initiant un changement de mode d’alimentation
G06F 1/3237 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par désactivation de la génération ou de la distribution du signal d’horloge
G06F 1/3287 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par la mise hors tension d’une unité fonctionnelle individuelle dans un ordinateur
G06F 21/70 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur
27.
DEVICE AND METHOD FOR REGULATING VOLTAGE SWING ACROSS AN ANTENNA OF A NEAR-FIELD COMMUNICATIONS DEVICE
An electronic device (1) for processing near-field communication signals includes first and second antenna connection terminals (3a, 3b) for connection to a near-field antenna (2), a linear load (10) and a voltage clamp (8), each connected between said connection terminals (3a, 3b). A current flowing through the linear load (10) has a substantially linear, positive relationship with a voltage across the linear load, defining a conductance of the linear load (10). The conductance of the linear load (10) is adjustable. The voltage clamp (8) has an adjustable clamping voltage. The electronic device (1) also includes a peak detector (12) arranged to detect an amplitude of an incoming near-field communication signal across said antenna connection terminals (3a, 3b), and a control circuit (14) arranged to adjust the conductance of the linear load (10) and the clamping voltage of the voltage clamp (8) based on the amplitude detected by the peak detector (12), so as to regulate the voltage swing across the antenna connection terminals (3a, 3b).
H04B 5/00 - Systèmes de transmission à induction directe, p.ex. du type à boucle inductive
G01R 19/04 - Mesure des valeurs de pointe d'un courant alternatif ou des impulsions
G05F 1/10 - Régulation de la tension ou de l'intensité
H03K 5/24 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p.ex. la pente, l'intégrale la caractéristique étant l'amplitude
A circuit portion (2) comprises a mapping module (10), a source component (6a, 6b, 6c), a destination component (6a, 6b, 6c) and a memory (12). The mapping module (10) comprises a plurality of channels that each provides a connection for connecting two components (6a, 6b, 6c) of the circuit portion (2) in a one-to-one relationship. The source component (6a, 6b, 6c) is arranged in a first clock or power domain (4a, 4b, 4c), and the destination component (6a, 6b, 6c) is arranged in a second clock or power domain (4a, 4b, 4c). In response to an assertion of an event signal (8) or an interrupt by the source component (6a, 6b, 6c), the mapping module (10) is configured to forward the event signal (8) or interrupt to the destination component (6a, 6b, 6c) via only one channel of the plurality of channels so as to cause the destination component (6a, 6b, 6c) to perform a corresponding task according to a mapping stored in the memory (12).
An asynchronous circuit portion (2) for sampling an input signal (14) is provided. The asynchronous circuit portion comprises a sampling circuit portion (4) arranged to receive the input signal and to generate first and second sample signals; a first storage element (6) arranged to generate a first storage signal on a first storage output (40) on reception of the first sample signal; and a second storage element (8) arranged to generate a second storage signal on a second storage output (42) on reception of the second sample signal. A control circuit portion (10) is arranged to detect if either of said first and second storage signals has been generated, to fix the first and second storage outputs and to generate a sample ready signal. The circuit portion generates an output signal (16) corresponding to the input signal using the first storage output when the sample ready signal is generated.
The cut-off frequency of an electronic filter (10) having a nominal transfer function and a nominal cut-off frequency is estimated by: applying (104) a first signal at a first frequency to an input of the filter (10) while sampling (106) an output of the filter (10) in order to obtain a first magnitude measurement, the first frequency being less than the nominal cut-off frequency; applying a second signal (108) at a second frequency to the input of the filter (10) while sampling (110) the output of the filter (10) in order to obtain a second magnitude measurement, the second frequency being greater than the nominal cut-off frequency; and estimating (112, 114) the cut-off frequency of the filter (10) based on the nominal transfer function, the first magnitude measurement, and the second magnitude measurement.
H03H 7/01 - Réseaux à deux accès sélecteurs de fréquence
H03H 11/12 - Réseaux sélectifs en fréquence à deux accès utilisant des amplificateurs avec contre-réaction
H03H 7/46 - Réseaux pour connecter plusieurs sources ou charges, fonctionnant sur des fréquences ou dans des bandes de fréquence différentes, à une charge ou à une source commune
31.
FAST-LOCKING ALL-DIGITAL PHASE-LOCKED LOOP AND APPLICATIONS THEREOF
According to an aspect, there is provided an all-digital phase-locked loop, ADPLL, for a radio receiver, transmitter or transceiver. The ADPLL comprises a time-to-digital converter for generating a digital time signal based on an external reference clock signal and a feedback signal, a switched capacitor digitally controlled oscillator, SC-DCO, for generating a radio frequency signal used as the feed-back signal, a phase-locked loop for controlling the SC-DCO based on the digital time signal for achieving a phase and frequency lock and digital processing means. The digital processing means are configured to maintain, in at least one memory, a lookup table defining a plurality of switching configurations of the SC-DCO corresponding to a plurality of frequencies of the radio frequency signal and to cause the phase-locked loop controller to adjust the switching configuration of the SC-DCO according to the lookup table.
H03L 7/10 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase pour assurer la synchronisation initiale ou pour élargir le domaine d'accrochage
H03L 7/099 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03L 7/093 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
According to an aspect, there is provided a method for transmitting a low-power radio signal, comprising: transmitting, by a radio device, a data radio signal by using binary frequency-shift-keying modulation introducing a phase change between consecutive bit intervals in the data radio signal; and transmitting, by the radio device, a wake-up radio signal using the binary frequency-shift-keying modulation where repetition coding is applied before the frequency-shift-keying to eliminate the phase change between consecutive bit intervals in the wake-up radio signal.
H04L 27/20 - Circuits de modulation; Circuits émetteurs
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H04W 4/80 - Services utilisant la communication de courte portée, p.ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
H04L 27/152 - Circuits de démodulation; Circuits récepteurs avec démodulation utilisant les propriétés spectrales du signal reçu, p.ex. en utilisant des éléments sélectifs de la fréquence ou sensibles à la fréquence utilisant des oscillateurs commandés, p.ex. dispositions PLL
A circuit portion (2) comprises a signal generator (4), clocked by a clock signal, for generating an alternating logic signal comprising a repeated sequence of alternating logic transitions. A circuit sub-portion (10) introduces a delay to the alternating logic signal. An edge-travel detector samples the delayed alternating logic signal and outputs an edge-travel signal representative of a timing of a logic transition in the alternating logic signal with respect to the clock signal. A mask block compares the edge-travel signal with a mask signal to determine whether the timing of the logic transition matches one or more candidate timings, and outputs a comparison signal in dependence on this determination.
G06F 21/75 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par inhibition de l’analyse de circuit ou du fonctionnement, p.ex. pour empêcher l'ingénierie inverse
An integrated-circuit device (10) comprises a processor (12), a program memory (16), a hardware-based key generation system (22, 26) that outputs a selectable device identity key of a plurality of predetermined device identity keys, and a one- time programmable (OTP) memory (30) for storing one or more public cryptographic keys. When a public cryptographic key is stored in the OTP memory (30), and when software is stored in the program memory (16), the device (10) uses the public cryptographic key to determine whether the software stored in the program memory (16) is validly signed by a private cryptographic key associated with the public cryptographic key, before the software is executed by the processor (12). The device (10) controls which device identity key of the plurality of predetermined device identity keys is output by the hardware-based key generation system (22, 26) at least partly in dependence on the outcome of this determination.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
The invention provides an electronic device (1) and method of operating an electronic device. The device (1) is configured to store (30) a device-specific identifier for the electronic device and a local sequence value associated with an external party. The device receives (32) a cryptographically-signed message (20) including an identifier field (24), a sequence-value field (25), and a cryptographic signature (27), and determines whether the received message is valid. To determine validity the device checks that the cryptographic signature is associated with the external party (35), the cryptographic signature confirms the integrity of the identifier field and the sequence- value field, the received identifier field matches the stored identifier (33); and the received sequence-value field satisfies a sequence condition (34) determined in dependence on the stored local sequence value. In response to determining that the message is valid, the device updates (36) the stored local sequence value to correspond to the received sequence-value field.
An integrated circuit has multiple clock domains. At least one of the clock domains is a secure domain (2) including a protection clock portion (6). The protection clock portion (6) is arranged to produce a clock signal having a clock period which varies randomly over at least some cycles of operation. The clock signal is arranged to clock one or more components in the secure domain (2).
G06F 21/75 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par inhibition de l’analyse de circuit ou du fonctionnement, p.ex. pour empêcher l'ingénierie inverse
H04L 9/00 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité
An integrated circuit (2) comprises a circuit portion (6a) for detecting a low logic speed relative to a clock signal frequency. The circuit portion (6a) comprises an oscillator (10a) arranged to output a periodic clock signal (18a) and a detection circuit portion (11a) comprising a latch circuit portion (12), a delay circuit portion (14) and a comparison circuit portion (16). The latch circuit portion (12) outputs a first signal (20) that changes state once per clock cycle. The delay circuit portion (14) receives the first signal (20) and outputs a second signal (22) subject to a propagation delay compared to the first signal (20), the propagation delay being less than a period of the clock signal (18a) under normal operating conditions. The comparison circuit portion (16) compares the first signal (20) at the input and the second signal (22) at the output of the delay circuit portion (14) and outputs an error signal (24a) if the signals are indicative of low logic speed relative to the clock signal frequency.
G06F 21/75 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par inhibition de l’analyse de circuit ou du fonctionnement, p.ex. pour empêcher l'ingénierie inverse
38.
PHYSICAL SECURITY PROTECTION FOR INTEGRATED CIRCUITS
An integrated circuit comprising a detection circuit portion (102) for detecting an electromagnetic pulse attack on the integrated circuit is provided. The detection circuit portion (102) comprises a shadow flip-flop (106) comprising a clock input and a clock net (126) connected to said clock input. The detection circuit portion (102) also comprises a clock gate (124) connected to the clock net (126), wherein the clock gate (124) is controlled by an enable signal so as selectively to be in an open state in which the clock gate (124) passes a clock signal to the clock net (126) or in a closed state in which the clock gate (124) does not pass the clock signal to the clock net (126). The detection circuit portion (102) further comprises an error circuit portion (117), wherein the error circuit portion (117) is arranged to selectively output an error signal if: the shadow flip-flop (106) is clocked by a signal from the clock net (126) and the clock gate (124) is in the closed state.
G06F 21/00 - Dispositions de sécurité pour protéger les calculateurs, leurs composants, les programmes ou les données contre une activité non autorisée
A method and apparatus for transmission are disclosed. The solution comprises forming a frame for transmission, where the frame comprises a header section, a training sequence section, an address and rate section, and a payload section. The training sequence section (202) comprises a given number of first fields (300A, 300B, 300C, 300D) of equal length and a second field (302). The total length of the given number of the first fields is shorter or equal than the length of the second field, the second field (302) comprises a given symbol sequence, and the first field (300A, 300B, 300C, 300D) comprises a part of the same given symbol sequence.
PIERCEPIERCE, of an oscillator (3). The method includes acquiring (105) or determining (107) a digital representation encoding a bias current. The method also includes carrying out an algorithm (109) to update the digital representation if the oscillation amplitude is measured, by one or more peak detectors (6), to be outside of upper and lower thresholds. Also provided is an apparatus (1) arranged to control the bias current of an oscillator (3) using this method, the apparatus including one or more peak detectors (6) and a current digital to analogue converter (16).
H03B 5/12 - Eléments déterminant la fréquence comportant des inductances ou des capacités localisées l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
H03B 5/36 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique l'élément actif de l'amplificateur comportant un dispositif semi-conducteur
A method of determining device (2) locations includes receiving a set of candidate locations (S100) in an environment (4) and generating training data representing synthetic distance measurements between pairs of the candidate locations (S101, S102, S103). The synthetic distance measurements are generated by applying random variations to the geometric distances between the candidate locations (S102, S103). The training data and candidate locations are used to train a machine learning model (S104). A set of measured distances between devices (2) are input to the trained learning model (S106), which is used to determine a respective location in the environment (4) of each of the devices (S107).
A method and apparatus for transmission are disclosed. The solu-tion comprises forming a frame for transmission, where the frame comprises a header section, a training sequence section, address and rate section, and a pay-load section. The address and rate sec-tion comprises an address field (400A, 400B) indicating the ad-dress of the recipient of the frame and a rate indicator field (402) indicating data rate mode used in the payload section parts, and a cyclic redundancy check field (404). The address field comprises a first part (400A) in the beginning of the address and rate section and a second part (400B) after the cyclic redundancy check field, the second part comprising a given number of the last bits of the address of the recipient.
According to an aspect, there is provided an apparatus for power management of a system on a chip, SoC. The apparatus comprises means for performing the following. The apparatus maintains, in a memory, a knowledge-based system comprising a plurality of rules. Each rule maps a shift from a first to a second SoC state to a set of one or more sequential actions for activating a power tree configuration corresponding to said second SoC state. The apparatus receives a request for adjusting a current power tree configuration so as to match a target SoC state. The apparatus determines a set of one or more sequential actions for activating an optimal power tree configuration for the SoC based on the knowledge-based system using current and target SoC states as an input. Finally, the apparatus adjusts the current power tree configuration according to the set of one or more sequential actions.
G05F 1/56 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final
G05F 3/24 - Régulation de la tension ou du courant là où la tension ou le courant sont continus utilisant des dispositifs non commandés à caractéristiques non linéaires consistant en des dispositifs à semi-conducteurs en utilisant des combinaisons diode-transistor dans lesquelles les transistors sont uniquement du type à effet de champ
H03F 3/50 - Amplificateurs dans lesquels le signal d'entrée est appliqué — ou le signal de sortie est recueilli — sur une impédance commune aux circuits d'entrée et de sortie de l'élément amplificateur, p.ex. amplificateurs dits "cathodynes"
H03F 1/30 - Modifications des amplificateurs pour réduire l'influence des variations de la température ou de la tension d'alimentation
A circuit portion (1) is provided which is arranged to be operable in a test mode. The circuit portion includes a Successive Approximation Register Analog to Digital Converter, SAR ADC, (6) and an input (12) for a reference signal (100). The SAR ADC is arranged to generate a feedback signal (101) having a duty cycle representing a time taken for the SAR ADC to complete an analogue to digital conversion. The SAR ADC can carry out a comparison of a duty cycle of the reference signal with the duty cycle of the feedback signal, and can generate an output signal comprising a digital representation (13) of the comparison of the reference duty cycle and the feedback duty cycle.
Apparatuses, methods, and computer programs for RACH procedure are disclosed. A method comprises: generating (502) system broadcast information indicating random access channel, RACH, occasions for a RACH procedure of a legacy user apparatus capable of employing a downlink and an uplink initial bandwidth part of a base station of the cellular radio network; and causing (506) a transmission of the system broadcast information in a first downlink portion of the one or more non-overlapping portions of the downlink initial bandwidth part via the base station. The system broadcast information also indicates, for a RACH procedure of a reduced capability user apparatus capable of employing only a limited amount of each of the downlink and uplink initial bandwidth parts of the base station, i) a set of the RACH occasions for the reduced capability user apparatus that are confined to one or more non-overlapping portions of the uplink initial bandwidth part, and ii) at least one of the one or more non-overlapping portions of the downlink initial bandwidth part containing a control resource set for a random access response and/or a contention resolution of the RACH procedure of the reduced capability user apparatus (100).
11tt, 1004) connected in series with first inductor and having a plurality of tuning values corresponding to operating frequency bands of the multiband radio receiver or transceiver. The tunable capacitor is implemented in an integrated circuit. The series resonant circuit is configured to be resonant at a plurality of first subharmonics of frequencies of the operating frequency bands. Optionally the filter comprises a second capacitor (C2, 1002) and a second inductor (L2, 1010) in series between the resonant circuit to ground and the input of the LNA. The second inductor adds to impedance matcing and low pass filtering above the operating frequency bands.
An integrated-circuit device (2) comprises a resettable source register (28) in a first reset domain (104). A destination circuit (6), outside the first reset domain (104), is arranged to sample an output of the resettable source register (28). A digital logic module (82) causes a central reset controller (8) to output a reset-warning signal (40a) in response to receiving a request to reset first reset domain (104), and to reset the first domain (104) after a predetermined delay period from outputting the reset-warning signal (40a).
- 40 - Abstract A configurable radio frequency receiver (74) is provided. The receiver has at least one low noise amplifier (86a, 86b); an oscillator arrangement for producing a plurality of signals having a first number or a second number of separate phases; and multiple mixer modules (83, 85, 87, 89) having inputs connected to an output of 5 the low noise amplifier. The receiver has a configurable resistor network (76). The receiver is configured such that it can operate in a first mode (78) with said plurality of signals having said first number of phases or a second mode (80) with said plurality of signals having said second number of phases. The configurable resistor network enables the receiver to operate in the first mode in a first configuration, and 10 the second mode in a second configuration. The mixer modules are employed during the operation of the first mode and the second mode. [Figure 5]
An integrated-circuit chip (201; 401) and method of operating said chip is provided. The integrated-circuit chip includes multiple processors (211a-n; 411a-n), a system memory (230, 231) and a main system bus (202; 402) for carrying data between each of the processors and the system memory. The chip also has debug logic (203; 403), a debug port (203a, 403a) for communicating with the debug logic from outside the chip and a debug connection that connects the debug logic to the main system bus. A power management system is also included for controlling the power supplied to each of a number of power domains (429a-n) on the chip. The debug logic and each of the processors are in different respective power domains. The debug logic is configured to send a debug instruction to any of the processors. The debug instruction is communicated over the debug connection (214; 414) and over the main system bus.
A digital radio transmitter device (10, 12) operates in accordance with a predetermined communication protocol that defines a default inter-frame spacing. The device (10, 12) has a minimum inter-frame spacing that is shorter than said 5 default inter-frame spacing. The device (10, 12) is configured to: transmit (22, 54) a first data packet (92, 104) indicating that the device (10, 12) is able to support an inter-frame spacing shorter than said default inter-frame spacing; receive (30, 36, 62, 72) a second data packet (94, 102, 106, 114) from a peer device (10, 12) after said default inter-frame spacing; if said second data packet (94, 102, 106, 114)10 indicates that said peer device (10, 12) is able to support an inter-frame spacing shorter than said default inter-frame spacing, transmit a third data packet using an inter-frame spacing shorter than said default inter-frame spacing; and if said second data packet (94, 102, 106, 114) does not indicate that said peer device (10, 12) is able to support an inter-frame spacing shorter than said default inter-frame spacing, 15 transmit said third packet using said default inter-frame spacing.
H04W 28/18 - Négociation des paramètres de télécommunication sans fil
H04W 4/80 - Services utilisant la communication de courte portée, p.ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
There is disclosed an electronic device (100) and a method of operating an electronic device (100). It has peripherals (134) which each have one or more event outputs or task inputs, connected to a peripheral interconnect (140). The device also has a controller (142) for configuring the peripheral interconnect and a memory (131,132), which are communicatively coupled to a bus system (135). The peripheral interconnect (140) receives configuration data from the controller (142), which selectively connects peripheral event outputs and task inputs. The controller (142) uses the bus system (135) to access a sequence of instructions in a script (20) stored in the memory (131,132). Each instruction in the sequence identifies a peripheral task input, event output and a second peripheral event output. Each subsequent instruction in the sequence is implemented in response to detecting an event signalled from the second peripheral event output identified by the preceding instruction in the sequence.
G06F 13/12 - Commande par programme pour dispositifs périphériques utilisant des matériels indépendants du processeur central, p.ex. canal ou processeur périphérique
G06F 9/06 - Dispositions pour la commande par programme, p.ex. unités de commande utilisant des programmes stockés, c. à d. utilisant un moyen de stockage interne à l'équipement de traitement de données pour recevoir ou conserver les programmes
G06F 15/17 - Communication entre processeurs utilisant une connexion de type entrée/sortie, p.ex. canal, point d'accès entrée/sortie
This document discloses a method for determining spatial conditions between a first radio device and a second radio device, the method comprising: path loss ranging, by the first radio device, the second radio device and computing at least one path loss estimate indicating a first distance between the first radio device and the second radio device; phase ranging, by the first radio device, the second radio device and computing at least one phase ranging value indicating a second distance between the first radio device and the second radio device; computing, based on the at least one path loss estimate and the at least one phase ranging value, at least one parameter describing the spatial conditions between the first radio device and the second radio device.
G01S 7/41 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe utilisant l'analyse du signal d'écho pour la caractérisation de la cible; Signature de cible; Surface équivalente de cible
G01S 13/76 - Systèmes utilisant la reradiation d'ondes radio, p.ex. du type radar secondaire; Systèmes analogues dans lesquels des signaux de type pulsé sont transmis
G01S 13/82 - Systèmes utilisant la reradiation d'ondes radio, p.ex. du type radar secondaire; Systèmes analogues dans lesquels des signaux de type continu sont transmis
G01S 13/84 - Systèmes utilisant la reradiation d'ondes radio, p.ex. du type radar secondaire; Systèmes analogues dans lesquels des signaux de type continu sont transmis pour la détermination de distance par mesure de phase
G01S 13/00 - Systèmes utilisant la réflexion ou la reradiation d'ondes radio, p.ex. systèmes radar; Systèmes analogues utilisant la réflexion ou la reradiation d'ondes dont la nature ou la longueur d'onde sont sans importance ou non spécifiées
G01S 11/06 - Systèmes pour déterminer la distance ou la vitesse sans utiliser la réflexion ou la reradiation utilisant les ondes radioélectriques utilisant des mesures d'intensité
According to an aspect, there is provided a first radio device for performing the following. The first radio device causes wireless transmission of one or more first advertising messages at one or more advertising radio frequencies using a connectionless mode of the first radio device. The radio device receives, for at least one first advertising message, a first scan request from a second radio device and transmits, for each first scan request, a first scan response to the second radio device. Based on one or more received first scan requests, the first radio device performs bi-directional channel sounding with the second radio device at one or more sounding radio frequencies. The first radio device receives, from the second radio device, at least one first message comprising information on second channel sounding measurements and transmits, to the second radio device, at least one second message comprising information on first channel sounding measurements performed by the first radio device.
H04W 4/02 - Services utilisant des informations de localisation
H04W 4/80 - Services utilisant la communication de courte portée, p.ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
H04W 8/00 - Gestion de données relatives au réseau
There is provided a method of testing an RF transceiver circuit (2; 60) and an RF transceiver circuit arranged to be operable in a test mode comprising a transmitter circuit portion (82; 82') and a receiver circuit portion (80; 80'), the receiver circuit portion including a mixer (10; 10'). The method involves the transmitter circuit portion generating a modulated signal and the receiver circuit portion receiving a continuous radio frequency wave. The mixer mixes the modulated signal with a signal derived from the continuous radio frequency wave to produce an output. A remainder of the receiver circuit portion processes the output of the mixer.
H04B 17/14 - Surveillance; Tests d’émetteurs pour l’étalonnage de l’ensemble voie d’émission/voie de réception, p.ex. bouclage d’autotest
H04B 1/48 - Commutation transmission-réception dans des circuits pour connecter l'émetteur et le récepteur à une voie de transmission commune, p.ex. par l'énergie de l'émetteur
An amplitude regulator circuit portion (208) is arranged to supply a current to an inverter (206) in an oscillator circuit (204). The regulator (208) monitors a voltage at the input terminal of the inverter (206) and varies the current supplied to the inverter (206) in response to the monitored voltage. The amplitude regulator (208) comprises first, second, and third PMOS transistors (P1-3), and first and second NMOS transistors (N1-2) and is arranged such that an input node of the amplitude regulator (208) is connected to the input terminal of the inverter (206), a respective gate terminal of each of the first and second NMOS transistors (N1-2), and a respective drain terminal of each of the first NMOS transistor (N1) and first PMOS transistor (P1). The amplitude regulator (208) also comprises a back-bias circuit portion (212) arranged to vary a back-bias voltage at a back-gate terminal of the second NMOS transistor (N2), thereby varying a threshold voltage of said second NMOS transistor (N2), where the threshold voltage of the second NMOS transistor (N2) is lower than the threshold voltage of the first NMOS transistor (N1).
H03B 5/36 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique l'élément actif de l'amplificateur comportant un dispositif semi-conducteur
An electronic device (202) comprises an oscillator circuit portion (204) comprising an inverter (206) and a crystal oscillator connected between the input and output terminals of the inverter (XC1, XC2). An amplitude regulator circuit portion (208) is arranged to supply a current to the inverter (206). The amplitude regulator (208) monitors a voltage at the input of the inverter (206) and varies the current supplied to the inverter (206) in response to the monitored voltage. The amplitude regulator (208) comprises a trimmable resistor (R1') arranged such that the voltage at the input of the inverter (206) is set to an operating point when the supply current provided by the amplitude regulator circuit (208) is equal to a threshold value, the operating point being at least partly determined by the selected resistance of the resistor (R1'). A current monitor (210) is arranged to monitor the current supplied to the inverter (206) during operation and to determine therefrom whether the voltage at the input terminal of the inverter (206) is within a predetermined range.
H03B 5/36 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique l'élément actif de l'amplificateur comportant un dispositif semi-conducteur
A constant-gm current source (102), arranged to generate a supply current (IPIERCE) for a Pierce oscillator. First (P1) and second (N1) transistors have their source terminals connected to first (AVDD) and second (GND) supply rails respectively, and their drain terminals are connected together and to the gate terminal of the first transistor (P1). Third (P2) and fourth (N2) transistors have their source terminals are connected to the first (AVDD) and second (GND) supply rails respectively, and their drain terminals are connected together and to the gate terminal of the fourth transistor (N2). An output portion (N3, P4, P5) varies the supply current (IPIERCE) in response to a voltage at the drain terminals of the third and fourth transistors (P2, N2). The gate terminals of the first (P1) and third (P2) transistors are connected together and receive a gate voltage (vgp), and the gate terminals of the second (N1) and fourth (N2) transistors are connected together. A reference resistive element (R1') connected between the source terminal of the third transistor (P2) and the first supply rail (AVDD) has a predetermined resistance value. An auto-calibration transistor (R2, P6) has its source terminal connected to the first supply rail (AVDD) and its drain terminal connected to the source terminal of the first transistor (P1). The gate terminal of the auto-calibration transistor (R2, P6) is supplied with the gate voltage (vgp).
H03B 5/36 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique l'élément actif de l'amplificateur comportant un dispositif semi-conducteur
G05F 3/24 - Régulation de la tension ou du courant là où la tension ou le courant sont continus utilisant des dispositifs non commandés à caractéristiques non linéaires consistant en des dispositifs à semi-conducteurs en utilisant des combinaisons diode-transistor dans lesquelles les transistors sont uniquement du type à effet de champ
A circuit portion (2) comprises a DCDC converter (4) that provides current to one of a plurality of loads (S0, S1, S2) at a time. A controller (14) detects when a voltage across an under-supplied load of the plurality of loads (S0, S1, S2) is below a first threshold. Channel logic circuitry (10) provides current from the converter (4) to the under-supplied load in response to the controller (14) detecting that the voltage is below the first threshold. A voltage regulator (30a, 30b, 30c) provides current to the under-supplied load when the voltage is below a second threshold.
H02M 1/00 - APPAREILS POUR LA TRANSFORMATION DE COURANT ALTERNATIF EN COURANT ALTERNATIF, DE COURANT ALTERNATIF EN COURANT CONTINU OU VICE VERSA OU DE COURANT CONTINU EN COURANT CONTINU ET EMPLOYÉS AVEC LES RÉSEAUX DE DISTRIBUTION D'ÉNERGIE OU DES SYSTÈMES D'ALI; TRANSFORMATION D'UNE PUISSANCE D'ENTRÉE EN COURANT CONTINU OU COURANT ALTERNATIF EN UNE PUISSANCE DE SORTIE DE CHOC; LEUR COMMANDE OU RÉGULATION - Détails d'appareils pour transformation
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p.ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
A circuit portion (2) is provided which includes an energy harvesting device (4) producing a DC output; a DC-DC converter (8) having an input connected to the DC output of the energy harvesting device (4); an output for connection to a load (44, 46); and a monitoring module (18) including a non-ohmic semiconductor element (56, 68, 58, 70). The monitoring module (18) is arranged to derive information relating to an output current flowing from the DC-DC converter by measuring a current through the non-ohmic semiconductor element (56, 68, 58, 70). The monitoring module (18) is arranged to adjust one or more parameters of the DC-DC converter (8) based on the information relating to said output current flowing from the DC-DC converter (8).
H02M 1/00 - APPAREILS POUR LA TRANSFORMATION DE COURANT ALTERNATIF EN COURANT ALTERNATIF, DE COURANT ALTERNATIF EN COURANT CONTINU OU VICE VERSA OU DE COURANT CONTINU EN COURANT CONTINU ET EMPLOYÉS AVEC LES RÉSEAUX DE DISTRIBUTION D'ÉNERGIE OU DES SYSTÈMES D'ALI; TRANSFORMATION D'UNE PUISSANCE D'ENTRÉE EN COURANT CONTINU OU COURANT ALTERNATIF EN UNE PUISSANCE DE SORTIE DE CHOC; LEUR COMMANDE OU RÉGULATION - Détails d'appareils pour transformation
A circuit portion (2) is provided which includes an energy harvesting device (4) producing a DC output; an inductor-less capacitor-based DC-DC converter (8), having an input connected to the DC output of the energy harvesting device; an output connected to a battery (46); and a voltage limiting module (24). The voltage limiting module (24) includes a voltage sensor arranged to measure a voltage representative of a voltage at the battery (46) and is arranged to limit a voltage provided by the DC-DC converter (8) if the voltage representative of the voltage at the battery (46) exceeds a threshold.
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p.ex. le niveau ou la densité de l'électrolyte
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
A common-mode feedback circuit (204) for a fully differential amplifier (102) comprises first (MB), second (MTP), and third (MTN) transistors, each having a respective drain, source, gate, and back-gate terminals. The drain terminal of the first transistor (MB) and the gate terminals of the first, second, and third transistors (MB, MTP, MTN) are connected together at a bias current terminal. The drain terminals of the second and third transistors are connected together at a tail current terminal. The source terminals of the first, second, and third transistors are connected together. The back-gate terminal of the first transistor (MB) is arranged to receive a common-mode reference voltage input (VCM), the back-gate terminal of the second transistor (MTP) is arranged to receive a positive output voltage (VP) from the fully differential amplifier, and the back-gate terminal of the third transistor (MTN) is arranged to receive a negative output voltage (VN) from the fully differential amplifier (102).
A bootloader (20) comprises software instructions for execution by a processor (4) of an electronic processing device (1). The bootloader (20) comprises an interpreter (31) for interpreting a boot script (27, 28, 29) stored in a memory (8) of the processing device (1), and an integrity checker (30a) for checking the integrity of boot scripts (27, 28, 29) stored in the memory (8). The bootloader (20) comprises instructions for using the integrity checker (30a) to check the integrity of a first boot script (27, 28, 29) of a plurality of boot scripts (27, 28, 29) stored in the memory (8). The bootloader (20) also comprises instructions for using the integrity checker (30a) to check the integrity of a second boot script (27, 28, 29) of the plurality of boot scripts (27, 28, 29) stored in the memory (8), independently of the integrity of the first boot script (27, 28, 29). The interpreter (31) comprises instructions for interpreting a control-flow command in the first boot script (27, 28, 29), the control-flow command conditionally or unconditionally causing the bootloader (20) to start interpreting commands from the second boot script(27, 28, 29).
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
An electronic device (200) comprises a synchronisation system (2) that receives a signal (6) clocked by a first clock signal (50) having a first frequency and receives a second clock signal (52) having said first frequency, but offset in phase from the first clock signal (50). The signal is delayed (6a) by an adjustable delay period. It is determined whether, following a logic transition in the delayed signal (6a), the next clock edge received is an active edge or is a non-active edge. A calibration controller (36) increases the delay period when the next clock edge is a non-active edge and maintains or decreases the delay period when the next clock edge is an active edge, or decreases the delay period when the next clock edge is an active edge and maintains or increases the delay period when the next clock edge is a non-active edge.
H03K 5/26 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p.ex. la pente, l'intégrale la caractéristique étant la durée, l'intervalle, la position, la fréquence ou la séquence
A method of operating a digital radio receiver (2) is provided. The method comprises: a) receiving an incoming radio signal comprising an incoming symbol sequence (102); b) selecting a portion of the incoming symbol sequence (102); c) determining a first error between the selected portion of the incoming symbol sequence (102) and a first predetermined symbol sequence (11) using a difference metric; d) determining, using the difference metric, a set of second errors between the selected portion of the incoming symbol sequence (102) and a respective set of second predetermined symbol sequences (13), each formed by prepending different length portions of a predetermined preamble symbol sequence (104) to a beginning of the first predetermined symbol sequence (11); and e) determining a minimum error from the first error and the set of second errors. If the first error is not the minimum error, a different portion of the incoming symbol sequence (102) is selected and steps c) to e) are repeated. If the first error is the minimum error, a following portion of the incoming symbol sequence (102) is decoded to produce a data payload.
A processing apparatus (20) has a processor (200) comprising a plurality of deferred- push processor registers (214) and processor-register control circuitry (220, 222, 224, 226, 228). The processor-register control circuitry (220, 222, 224, 226, 228) comprises a plurality of status registers (226), each status register (226) corresponding to a different respective deferred-push register (214). The processor-register control circuitry (220, 222, 224, 226, 228) is configured to: detect a write of a new value to a register (214) of the deferred-push registers (214); and determine whether the status register (226) for the deferred-push register (214) has a first value, indicative of an unsaved status for the deferred-push register (214). The processor-control circuitry (220, 222, 224, 226, 228) is configured, when the status register (226) has the first value, to: read a current value from the deferred-push register (214) before the writing of the new value to the deferred-push register (214) completes; write the current value to a memory (202); and set the status register (226) for the deferred-push register (214) to a second value, indicative of a saved status for the deferred-push register (214).
A hardware accelerator (4) comprises a direct memory access (DMA) system (7, 8) and an array (20) of processing elements (PEs). Each PE (20a) comprises two data inputs (40, 41) and two data outputs (42, 43) and can perform a selectable logical or arithmetic operation. The array (20) comprises configurable interconnects (23) for selectively connecting outputs of the PEs to inputs of the PEs. A first data buffer (21) comprises two or more first-edge cyclic registers (21a), for connecting the DMA system (7, 8) to selected data inputs at a first edge of the PE array (20). A second data buffer (22) comprises two or more second-edge linear or cyclic shift registers, for connecting selected data outputs of a second edge of the PE array (20) to the DMA system.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p.ex. plusieurs processeurs de données à instruction unique
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
An apparatus (17) for demodulating a frequency-modulated signal comprises a joint frequency-offset & modulation-index estimator (34), and a signal demodulator (37, 39). The joint estimator (34) receives data representative of a preamble portion of the signal, modulated with predetermined preamble data. It jointly determines (311) a frequency-offset estimate and a modulation-index estimate by using an optimization process that minimizes a cost function that is a function of the received data and that is parameterised by a frequency-offset parameter and by a modulation-index parameter. The signal demodulator (37, 39) receives data representative of a message portion of the signal, modulated with message data, and uses the frequency-offset estimate to demodulate the message.
A method of operating a display system consisting of a plurality of light emitting diodes (LEDs) (2, 5) is disclosed. The LEDs (2, 5) are arranged in a plurality of groups and an integrated circuit (3) provides power to the LEDs (2, 5) through a plurality of output pins (L0-L7) connected to respective groups. The integrated circuit (3) selectively determines the states of the output pins (L0-L7) to illuminate the groups of LEDs (2, 5) in a repeating sequence such that each group is illuminated for a time dependent on a number of groups and a compensation factor. The compensation factor is dependent on at least a number of LEDs (2, 5) in the group.
G09G 3/32 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p.ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p.ex. utilisant des diodes électroluminescentes [LED]
G09G 3/34 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p.ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice en commandant la lumière provenant d'une source indépendante
G09G 3/12 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un seul caractère, soit en sélectionnant un seul caractère parmi plusieurs, soit en composant le caractère par combinaison d'éléments individuels, p.ex. de segments élémentaires utilisant des sources lumineuses commandées utilisant des éléments électroluminescents
G09G 3/14 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un seul caractère, soit en sélectionnant un seul caractère parmi plusieurs, soit en composant le caractère par combinaison d'éléments individuels, p.ex. de segments élémentaires utilisant des sources lumineuses commandées utilisant des éléments électroluminescents des dispositifs à semi-conducteurs, p.ex. des dispositifs à diodes
G09G 3/20 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p.ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice
H05B 45/48 - Circuits pour faire fonctionner des diodes électroluminescentes [LED] - Détails des circuits de charge à LED avec un contrôle actif à l'intérieur d'une matrice de LED ayant des LED organisées en chaînes et comportant des dispositifs de dérivation parallèles
A method of, and apparatus (17) for, demodulating a frequency-modulated signal. The method comprises: for each of a plurality of templates, performing (105, 107) a respective cross-correlation operation between the template and data representative of the frequency-modulated signal, each template comprising data representative of a signal that is frequency-modulated with predetermined preamble data using a different respective modulation index; generating (105) frequency-offset data from one or more of the cross-correlation operations, the frequency-offset data being representative of a difference between a reference frequency and a carrier frequency of the frequency- modulated signal; determining (109) a respective peak correlation-coefficient value from each of the cross-correlation operations; identifying (111) a highest peak correlation-coefficient value in the determined peak correlation-coefficient values; determining (113) a modulation index estimate in dependence on which template produced the highest peak correlation-coefficient value; and using (115, 117) the frequency-offset data and the modulation index estimate to demodulate (119) at least a portion of the frequency-modulated signal.
H04L 27/144 - Circuits de démodulation; Circuits récepteurs avec démodulation utilisant les propriétés spectrales du signal reçu, p.ex. en utilisant des éléments sélectifs de la fréquence ou sensibles à la fréquence
A receiver (15) comprises a matched filter bank (37), decision logic (39) and a frequency offset estimator (35). The matched filter bank (37) comprises an input for receiving data representative of a frequency- or phase-modulated signal. The decision logic (39) generates a sequence of demodulated symbol values from outputs of the matched filter bank (37). The frequency offset estimator (35) determines a first phase value from a first output and a second phase value from a second output of the matched filter bank (37), the second output being offset from the first by L symbol periods. It also determines a phase adjustment value from an L-symbol subsequence within the sequence of demodulated symbol values, each subsequence value being determined from values output by the matched filter bank (37) between the first and second outputs. It estimates a frequency offset based on the difference between the first phase value plus the phase adjustment value, and the second phase value.
A radio device (110) comprises a radio transceiver (105, 107), a resonator (101), a temperature measurement unit (102), a frequency synthesiser (113) and a processing system (104). A temperature signal from the temperature measurement unit (102), representative of a measured temperature of the resonator (101), is used to determine an estimated frequency offset for the resonator (101) at the measured temperature using a model stored in a memory of the processing system (104) that relates frequency offset to temperature. A periodic signal from the resonator (101) is provided to the frequency synthesizer (113), which, in dependence on the estimated frequency offset, is used to generate a periodic local signal. The radio transceiver (105, 107) receives a radio signal comprising a periodic component at a received signal frequency. An error value representative of a difference between the received signal frequency and a frequency of the periodic local signal is determined and used to update one or more parameters of the model stored in the memory.
H03L 1/02 - Stabilisation du signal de sortie du générateur contre les variations de valeurs physiques, p.ex. de l'alimentation en énergie contre les variations de température uniquement
H03L 7/18 - Synthèse de fréquence indirecte, c. à d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle
H03L 7/087 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie utilisant au moins deux détecteurs de phase ou un détecteur de fréquence et de phase dans la boucle
H03B 5/04 - Modifications du générateur pour compenser des variations dans les grandeurs physiques, p.ex. alimentation, charge, température
An Orthogonal Frequency-Division Multiplexing digital radio transmitter (110) is arranged to transmit a data packet (200) comprising a plurality of Orthogonal Frequency-Division Multiplexing symbols (304). At least one of the symbols (304) comprises a plurality of demodulation reference signals (408) in a first plurality of frequency sub-carriers (302) of the symbol (304). The transmitter (110) is arranged to transmit a physical control channel (406) at least partly distributed among a remainder of frequency sub-carriers (302) of the symbol (304) according to a calculated distribution. The transmitter (110) calculates the distribution by arranging the remainder of frequency sub-carriers (304) in a two-dimensional matrix such that said remainder of frequency sub-carriers (304) have indices which are sequential in a first dimension and have a common increment in a second dimension, and allocating a second plurality of the remainder of frequency sub-carriers (302) to the physical control channel (406) sequentially in the second direction.
A time delay circuit comprising a plurality of differential delay cells 8 each having a respective time delay and being arranged in series. Each delay cell 8 comprises first and second inverter sub-cells 2a, 2b, each comprising a respective PMOS transistor 4a, 4b and an NMOS transistor 6a, 6b arranged in series such that their respective drain terminals are connected at a drain node 10a, 10b. These transistors may be UTBB-FDSOI transistors. Each of the transistors 4a, 4b, 6a, 6b has a back-gate terminal and is arranged such that a respective voltage applied to said back-gate terminal linearly controls its respective threshold voltage. The back- gate terminal of the PMOS transistor 4a, 4b in each inverter sub-cell 2a, 2b is connected to the drain node of the other sub-cell 2a, 2b and/or the back-gate terminal of the NMOS transistor 6a, 6b in each inverter sub-cell 2a, 2b is connected to the drain node of the other sub-cell 2a, 2b. A control signal vctrl varies the time delay of the delay cell 2a, 2b by adjusting a voltage supplied to a back-gate terminal of at least one transistor.
H03K 5/134 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés utilisant une chaîne de dispositifs actifs de retard avec des transistors à effet de champ
H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe
A digital radio transmitter (110) is arranged to operate according to a predetermined communication protocol and comprises a plurality of transmit antennas (114). The transmitter (110) is arranged to transmit a data packet (200) comprising: a reference signal (408) to allow a receiver (112) to perform channel estimation, a data channel (410) comprising a payload of the data packet (200), and a control channel (406) comprising information required to decode the data channel (410). The transmitter (110) is arranged to transmit each of the reference signal (408), data channel (410) and control channel (406) using beamforming employing a common set of beamforming parameters.
H04B 7/06 - Systèmes de diversité; Systèmes à plusieurs antennes, c. à d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H04B 7/06 - Systèmes de diversité; Systèmes à plusieurs antennes, c. à d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
A method of operating a digital radio transmitter device (10, 12) in accordance with a predetermined communication protocol defining a transmission timing tolerance (30). The method comprises: transmitting a plurality of first periodic transmissions (31) in accordance with said predetermined communication protocol having a first period (39) and an inherent timing uncertainty (40) less than said transmission timing tolerance (30); performing a plurality of second periodic actions (55, 64) with a second period (39, 72) wherein said first (39) and second periods (39, 72) are equal to each other or an integer multiple of each other; and adjusting a timing of one or more of the first periodic transmissions (31) by an amount greater than said inherent timing uncertainty (40) but less than or equal to a difference (42) between said inherent timing uncertainty (40) and said transmission timing tolerance (30) so as to change said first period (39) temporarily by an amount less than or equal to said transmission timing tolerance (30), thereby changing an offset (60, 74) between said first transmissions (31) and said second actions (55, 64).
H04W 4/80 - Services utilisant la communication de courte portée, p.ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
80.
METHOD AND SYSTEM FOR OPTIMIZING DATA TRANSFER FROM ONE MEMORY TO ANOTHER MEMORY
A method and system (100) for moving data from a source memory (102) to a destination memory (104) by a processor (106) are disclosed. The processor (106) has a plurality of registers (114) and the source memory (102) stores a sequence of instructions that include one or more load instructions and one or more store instructions. The processor (106) moves the load instructions from the source memory (102) to the destination memory (104). Then, the processor (106) initiates execution of the load instructions from the destination memory (104) in order to load the data from the source memory (102) to one or more registers (114) in the processor (106). Execution then returns to the sequence of instructions stored in the source memory (102), and the processor (106) stores the data from the registers (114) to the destination memory (104).
A method and system (100) for moving data from a source memory (102) to a destination memory (104) by a processor (106) is disclosed herein. The destination memory (104) stores a sequence of instructions and the sequence of instructions comprises one or more load instructions and one or more store instructions. The processor (106) initially moves the one or more store instructions from the destination memory (104) to the source memory (102). The processor (106) then executes the one or more load instructions from the destination memory (104). On executing the one or more load instructions, the data is loaded from the source memory (102) to at least one register (114) in the processor (106). The processor (106) further initiates execution of the one or more store instructions stored in the source memory (102). On executing the one or more store instructions from the source memory (102), the processor (106) stores the data from the at least one register (114) to the destination memory (104).
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G06F 9/32 - Formation de l'adresse de l'instruction suivante, p.ex. par incrémentation du compteur ordinal
An integrated-circuit radio transmitter chip (2) comprises a transmitter (7), a cryptographic engine (12) and control circuitry (13) for the cryptographic engine. The cryptographic engine (12) performs a cryptographic operation by receiving input data, performing a first process to generate first result data and a second process to generate second result data. The first and second result data are used to generate output data. In response to determining that the transmitter (7) is active, the control circuity (13) controls the cryptographic engine (12) to perform the first process and prevents the cryptographic engine from performing the second process while the transmitter is active. The control circuitry (13) controls the cryptographic engine (12) to perform the second process in response to determining that the transmitter (7) is not active.
H04L 9/00 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité
G06F 21/75 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par inhibition de l’analyse de circuit ou du fonctionnement, p.ex. pour empêcher l'ingénierie inverse
H04B 15/00 - Suppression ou limitation du bruit ou des interférences
H04W 12/02 - Protection de la confidentialité ou de l'anonymat, p.ex. protection des informations personnellement identifiables [PII]
A method of digital radio communication between a central device (10') and a peripheral device (12', 14'). The peripheral device (12', 14') transmits a repeated burst of advertising packets (58, 60, 62) on a primary physical channel, each packet (58, 50, 62) comprising an advertising field indicating an availability to form a connection. The advertising field comprises an address identifying the peripheral device (12', 14'). The peripheral device (12', 14') transmits a subsequent advertising packet on an auxiliary channel. The central device (12') receives a packet (58, 60, 62) from the burst of packets (58, 60, 62), decodes the advertising field and compares the address to one or more desired connection addresses to determine whether to initiate a connection to the peripheral device (12', 14'). If the address matches a desired connection address, the central device (10') initiates a connection to the peripheral device (12', 14'). If the address does not match a desired connection address, the central device (10') resumes listening for further advertising packets (58, 60, 62).
H04W 4/80 - Services utilisant la communication de courte portée, p.ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
A digital radio communication system comprising a transmitter (100) and a receiver (102) is arranged to operate according to a predetermined communication protocol. The transmitter (100) is arranged to transmit a data packet (400) comprising: a data field (408); a first physical header field (408) indicating at least a transmission type, information regarding modulation and/or coding of said data field (408) and an indicator that a further physical header field is being transmitted; and a second physical header field (410) indicating at least a transmission type, information regarding modulation and/or coding of said data field (408) and an indicator as to whether a further physical header field is being transmitted.
A clock selector circuit (1) comprises a first input for receiving a first input clock signal (CLK1) having a first frequency, and a second input for receiving a second input clock signal (CLK2) having a second frequency, the second frequency differing from the first frequency by a frequency offset. The clock selector circuit (1) further comprises a clock output for outputting an output clock signal (CLK_OUT), a phase difference detector (7) and switching circuitry (5, 6). The phase difference detector (7) is configured to detect when a phase difference, over time, between the first input clock signal (CLK1) and the second input clock signal (CLK2), determined using a predetermined type of clock edge, being either a rising edge or a falling edge, crosses zero, and to signal this zero crossing to the switching circuitry (5, 6). The switching circuitry (5, 6) is configured, in response to receiving a zero-crossing signal from the phase difference detector (7), to detect an edge of opposite type to the predetermined type in the first input clock signal (CLK1) or in the second input clock signal (CLK2), and, in response to detecting said edge of opposite type, to switch the output clock signal (CLK_OUT) between the first input clock signal (CLK1) and the second input clock signal (CLK2).
An electronic device (2) comprising a system on chip (6) and an external module. The system on chip (6) includes a plurality of internal subsystems (10, 12) and a power management system (24) including a plurality of internal voltage regulators (14, 16) which supply power to the plurality of internal subsystems (10, 12). Each of the internal voltage regulators (14, 16) has an associated current limiter (30, 32). The external module includes at least one external voltage regulator (8) which can provide power to at least one of the internal subsystems (10, 12). The power management system (24) during a start-up phase enables the internal voltage regulators (14, 16) and the current limiters (30, 32) and in a subsequent phase determines an externally powered set of the internal subsystems (10, 12), disables the corresponding internal voltage regulators (14, 16), and disables the current limiters (30, 32) associated with the internal subsystems (10,12) not externally powered.
An oscillator arrangement is provided, comprising a relaxation oscillator (2) having an active state and an inactive state; a bias current circuit portion (16) arranged to provide a bias current (14) to the relaxation oscillator (2) during said active state; and an electronic switch (12) arranged to isolate said relaxation oscillator (2) from the bias current circuit portion (16) when in said inactive state. The oscillator arrangement is arranged to store an internal voltage value associated with said bias current (14) and the bias current circuit portion (16) is arranged to use the stored internal voltage value to generate the bias current (14) when the oscillator (2) is started up from the inactive state to the active state.
A microcontroller (2) comprises a processor (3) and a memory (11). The memory (11) comprises a first-stage bootloader region (41), a first second-stage bootloader region (43), a second second-stage bootloader region (45), and an application region (47) for storing an application (29). A first-stage bootloader (25) is stored in the first-stage bootloader region (41) and an active second-stage bootloader (27) is stored in an active one of the first (43) and second (45) second-stage bootloader regions. The processor (3) is configured to execute instructions from the first-stage bootloader (25) when the microcontroller (2) is reset. The first-stage bootloader (25) comprises instructions for transferring execution from the first-stage bootloader (25) to the active second-stage bootloader (27), which comprises instructions for transferring execution to an address in the application region (47), and for causing the processor (3) to write a replacement second-stage bootloader (27) to whichever of the first (43) and second (45) second-stage bootloader regions is not the active region. The first-stage bootloader (25) comprises instructions for detecting the replacement second-stage bootloader (27) in whichever of the first (43) and second (45) second-stage bootloader regions is not the active region and for transferring execution to the replacement second-stage bootloader (27) when the microcontroller (2) is next reset.
A radio receiver apparatus (2) comprises radio circuitry (4) for receiving a sequence of radio data packets, transmitted at regular intervals, wherein the sequence of radio data packets encodes a digital audio stream and each radio data packet encodes a respective number of audio samples from the digital audio stream. The apparatus (2) also comprises a digital audio interface (5) for outputting audio samples from the received digital audio stream, a controllable oscillator (24) arranged to control an output rate at which the audio samples are output from the digital audio interface (5), and a timer (20). The apparatus (2) also comprises control logic (19), configured to use the timer (20) to measure an interval between receiving each of a pair of the radio data packets, and to control the oscillator (24) to vary the output rate incrementally, in a number of steps, while outputting the audio samples from one radio data packet. The number of steps, or the size of each step, or both, depends on the measured interval.
A microcontroller system (100) comprising a master microcontroller unit (102), a further module (104, 106) and a general purpose input/output (108). In a first state the general purpose input/output is controlled by the master microcontroller unit and in a second state the general purpose input/output is controlled by the further module. The master microcontroller unit is arranged to transmit a selection signal which changes the state of the general purpose input/output.
A digital radio receiver receives an encoded digital radio signal comprising a plurality of bits. The receiver determines a plurality of soft bits representing estimates of the bits and stores the soft bits in a rate de-matching buffer (18). The receiver calculates a first linear combination of soft bits from a first subset of the buffer (18) and a second linear combination of soft bits from a second subset of the buffer (18). The receiver calculates a ratio between the first and second linear combinations and compares the ratio to an expected value. The receiver then determines its operational state based on the comparison.
A radio system comprises a radio transmitter apparatus (2) and a radio receiver apparatus (1). The radio transmitter apparatus (2) is configured to transmit a continuous-wave radio-frequency signal having a first frequency. The radio receiver 5 apparatus (1) comprises: an antenna (17) for receiving the continuous-wave radio- frequency signal; a local oscillator (6) for generating a periodic signal at a second frequency which differs from the first frequency by a frequency offset; a mixer (7) for mixing the received continuous-wave radio-frequency signal with the periodic signal to generate a down-mixed signal; and a processor or other circuitry (11) configured to 10 generate frequency-offset data from the down-mixed signal, wherein the frequency- offset data is representative of an estimate of the frequency offset. The processor or other circuitry (11) is configured to use the frequency-offset data to generate DC-offset data representative of an estimate of a DC offset component of the down-mixed signal.
H04B 1/30 - Circuits pour récepteurs homodynes ou synchrodynes
G01S 13/84 - Systèmes utilisant la reradiation d'ondes radio, p.ex. du type radar secondaire; Systèmes analogues dans lesquels des signaux de type continu sont transmis pour la détermination de distance par mesure de phase
93.
APPARATUS AND METHOD FOR REGISTERING AN APPARATUS WITH A LONG TERM EVOLUTION (LTE) CELLULAR NETWORK USING A SELECTED ACCESS TECHNOLOGY
An apparatus (1) has a radio (15) for communicating with LTE networks (30) using a first access technology and for communicating with LTE networks (31) using a second access technology. The apparatus (1) is configured to access an identity-data memory (14;19) storing received identity data. The apparatus (1) includes an access-technology-identification memory (14;19) for storing access-technology identification information that identifies an access technology associated with identity data stored in the identity-data memory (14;19). The apparatus (1) registers with an LTE cellular network (2; 30, 31), using a selected access technology. The apparatus (1) processes the access-technology identification information to determine whether the identity data stored in the identity-data memory (14;19) is associated with the selected access technology, and, when it is associated, sends the identity data to the LTE network (2; 30, 31).
A radio-frequency (RF) amplifier device (3) comprises a signal input (14) for receiving an RF electrical signal, a variable-gain amplifier (17a) for amplifying the received signal, and a signal output (7) for outputting the amplified signal. The device (3) has a binary input (19) for switching a gain of the amplifier between a first level and the custom gain level. Configuration logic (30) receives serialised data encoding a custom gain level at a serial input (19), and stores data representative of the custom gain level in a memory (32) of the device (3). Gain-control logic (30) reads the data representative of the custom gain level from the memory (32), and sets the gain of the amplifier (17a) to the first level or to the custom gain level in dependence on a state of the binary input (19).
H03F 3/68 - Combinaisons d'amplificateurs, p.ex. amplificateurs à plusieurs voies pour stéréophonie
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p.ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 3/72 - Amplificateurs commandés, c. à d. amplificateurs mis en service ou hors service au moyen d'un signal de commande
A radio device(4)receives data from a base station(7a, 7b)that transmits a first radio signal, carrying a first data block, in a first time window, and a second radio signal, also carrying the first data block, in a different, second time window. The radio device (4)comprises first and second antennas(29. 30), receive circuitry(31), and a switch (32)for selectively connecting the receive circuitry(31)to the first antenna(29)or to the second antenna(30). It(4)is configured to sample the first radio signal, received by the first antenna(29)in the first time window, to generate first sampled data; disconnect the first antenna(29)from the receive circuitry(31)and connect the second antenna(30);sample the second radio signal, received by the second antenna(30)in the second time window, to generate second sampled data; and use both the first sampled data and the second sampled data to decode the first data block.
H04B 7/06 - Systèmes de diversité; Systèmes à plusieurs antennes, c. à d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H04B 7/08 - Systèmes de diversité; Systèmes à plusieurs antennes, c. à d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station de réception
A frequency synthesiser arrangement (100) is arranged to receive a clock input signal (116) and provide an output signal (118). The frequency synthesiser arrangement (100) comprises: a frequency divider (110) arranged to divide the output signal (118) by a variable number N and output a feedback signal (120); a phase detector (102) arranged to detect a phase difference between the feedback signal (120) and the clock input signal (116); a phase alignment circuit portion (112) arranged to determine an overlap of the clock input signal (116) and the feedback signal (120); and a voltage controlled oscillator (108) which is arranged to receive either a first input derived from the phase detector or a second input from an external reference voltage (114) and to provide the output signal (118). The phase alignment circuit portion (112) is arranged to provide a control output (124) which determines whether the voltage controlled oscillator (108) receives the first or second input.
H03L 7/113 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase pour assurer la synchronisation initiale ou pour élargir le domaine d'accrochage utilisant un discriminateur de fréquence
H03L 7/10 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase pour assurer la synchronisation initiale ou pour élargir le domaine d'accrochage
A method (100) of operating a radio receiver device to monitor a paging group over a paging period. The paging group comprises one or more paging candidates, each having a respective repetition length. The method comprises: receiving (102) one or more data symbols; attempting (104) to decode said received data symbols, wherein a successful decoding attempt produces a decoded message comprising a value indicative of a respective repetition length of said decoded message (108); and, if the decoding attempt is successful (106), stopping monitoring (112) of a paging candidate having a respective repetition length greater than said value (110) before the end of the paging period.
H04W 4/70 - Services pour la communication de machine à machine ou la communication de type machine
H04W 48/12 - Distribution d'informations relatives aux restrictions d'accès ou aux accès, p.ex. distribution de données d'exploration utilisant un canal de commande descendant
A radio device (4) sends a random-access request message to a base station (7a, 7b) and receives a random-access response message from the base station (7a, 7b). A plurality of data transport blocks are thereafter transmitted in a first direction between the radio device (4) and the base station (7a, 7b), but the radio device (4) does not send a connection-setup complete message to the base station (7a, 7b) until all of the plurality of data transport blocks having been transmitted.
A method of operating a radio receiver having a normal mode in which said radio receiver is arranged to seek information by continually monitoring search space candidates and a rejection mode in which said radio receiver stops monitoring one or more of the candidates. The method comprises receiving at least one signal comprising a portion specified in the protocol for carrying a non-universal reference symbol (302); determining a first received signal strength value of said portion (306a, 306b);receiving at least one signal carrying a universal reference symbol (302);determining a second received signal strength value of said universal reference symbol(306a, 306b);comparing the first received signal strength value to a signal strength threshold based on the second received signal strength value (308);operating the radio receiver in the normal mode if the first received signal strength value exceeds the signal strength threshold; and operating the radio receiver in the rejection mode if the first received signal strength value does not exceed the signal strength threshold.
A method of communication over a cellular telecommunications network (16) using an electronic device (14) comprises communicating a session control signal between the electronic device and the cellular telecommunications network on a first radio channel (32) provided by the cellular telecommunications network. The session control signal comprises identification data that identifies a remote party (8). The cellular telecommunications network (16) uses the identification data to establish an IP-based communication session with the remote party (8). Content data for the IP-based communication session is communicated between the electronic device (14) and the cellular telecommunications network (16) on a second radio channel (34) provided by the cellular telecommunications network.