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2023
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Invention
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Atomic memory operations for address translation.
Systems and methods are disclosed for atomic m... |
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Invention
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Vector instruction cracking after scalar dispatch.
Apparatus and methods for vector instruction ... |
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Invention
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Supporting multiple vector lengths with configurable vector register file.
Systems and methods a... |
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Invention
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Fusion with destructive instructions.
Systems and methods are disclosed for fusion with destruct... |
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Invention
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Memory request combination indication.
A processor core may include circuitry that fetches a fir... |
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Invention
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Translation lookaside buffer (tlb) prefetcher with multi- level tlb prefetches and feedback archi... |
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Invention
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Load-store pipeline selection for vectors.
Systems and methods are disclosed for load-store pipe... |
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Invention
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Vector gather with a narrow datapath.
Systems and methods are disclosed for vector gather with a... |
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Invention
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Floating-point multiplier using zero counters. One or more zero counters may be configured to cou... |
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Invention
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Floating-point multiplier using zero counters.
One or more zero counters may be configured to co... |
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Invention
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Configuring a component of a processor core based on an attribute of an operating system process.... |
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Invention
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Trace encoder with event filter.
A trace circuitry may be configured to receive a selection of o... |
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Invention
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Integrated circuits as a service. Systems and methods are disclosed for automated generation of i... |
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Invention
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Generation of dynamic design flows for integrated circuits. Systems and methods are disclosed for... |
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Invention
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Data cache with prediction hints for cache hits. Described is a data cache with prediction hints ... |
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P/S
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Semiconductor chips; integrated circuits; microprocessors; microcontrollers; printed circuit boar... |
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Invention
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Checker cores for fault tolerant processing.
Systems and methods are disclosed for checker cores... |
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Invention
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Integrated circuit design using metadata. An integrated circuit design is generated for an integr... |
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Invention
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Integrated circuit design verification with signal forcing. An integrated circuit design may be g... |
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Invention
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Integrated circuit design verification with module swapping. An integrated circuit design is gene... |
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2022
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Invention
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Page table entry caches with multiple tag lengths. Systems and methods are disclosed for page tab... |
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Invention
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Logging guest physical address for memory access faults.
Systems and methods are disclosed for l... |
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Invention
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Integrated circuit generation with composable interconnect. Disclosed are systems and methods tha... |
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Invention
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Event tracing. Systems and methods are disclosed for debug event tracing. For example, an integra... |
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Invention
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Store-to-load forwarding for processor pipelines. Systems and methods are disclosed for store-to-... |
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Invention
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Prefetcher with out-of-order filtered prefetcher training queue. Described is a system and method... |
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Invention
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Cycle accurate tracing of vector instructions. Systems and methods are disclosed for cycle accura... |
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Invention
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Integrated circuit generation with improved interconnect. Disclosed are systems and methods that ... |
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Invention
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Systems and methods for clock gating. Described are systems and methods for clock gating componen... |
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Invention
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Configuring a prefetcher associated with a processor core. Disclosed are systems and methods for ... |
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Invention
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Integrated circuit generation using an integrated circuit shell.
Systems and methods are disclos... |
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Invention
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Quad narrowing operation. Systems and methods are disclosed for implementing a quad narrowing ope... |
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Invention
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Hybrid fixed-point and floating-point computations for improved neural network accuracy. Systems ... |
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Invention
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Software indirection level for address translation sharing. Systems and methods are disclosed for... |
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Invention
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Translation tagging for address translation caching. Systems and methods are disclosed for transl... |
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Invention
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Method for executing atomic memory operations when contested.
Described are methods and a system... |
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Invention
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Data cache with hybrid writeback and writethrough. Described is a data cache implementing hybrid ... |
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Invention
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Processor power management using instruction throttling.
Systems and methods are disclosed for p... |
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Invention
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Asymmetric data path operations. Executing an instruction may include loading first, second, and ... |
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Invention
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Method and apparatus for accelerated inference of machine-learning models. Accelerating interfere... |
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Invention
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Selectable and hierarchical power management. Described are systems and methods for power managem... |
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Invention
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Selectable and hierarchical power management.
Described are systems and methods for power manage... |
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Invention
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Systems and methods for power gating chip components. Described are systems and methods for power... |
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Invention
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Processor power management using instruction throttling. Systems and methods are disclosed for pr... |
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Invention
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Prefetcher aggressiveness tuning. Disclosed herein are implementations of prefetcher aggressivene... |
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Invention
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Prefetcher with multi-cache level prefetches and feedback architecture. Described is a prefetcher... |
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2021
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Invention
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Efficient processing of masked memory accesses.
Disclosed herein are systems and methods for pro... |
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Invention
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Memory protection for vector operations.
Systems and methods are disclosed for memory protection... |
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Invention
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Memory protection for gather-scatter operations.
Systems and methods are disclosed for memory pr... |
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Invention
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Register renaming for power conservation.
Systems and methods are disclosed for register renamin... |
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2020
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P/S
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Semiconductor chips; integrated circuits; microprocessors;
microcontrollers; printed circuit boa... |
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2019
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P/S
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Printed circuit boards; user-configurable circuit boards; semiconductor chips; integrated circuit... |
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P/S
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Printed circuit boards; user-configurable circuit boards;
semiconductor chips; integrated circui... |
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2016
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P/S
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Semiconductor chips; integrated circuits; microprocessors |
