VIA Alliance Semiconductor Co., Ltd.

Chine

 
Quantité totale PI 287
Rang # Quantité totale PI 4 374
Note d'activité PI 2,3/5.0    33
Rang # Activité PI 23 323

Brevets

Marques

238 0
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49 0
0
 
Dernier brevet 2021 - Methods for compressing and deco...
Premier brevet 2013 - Microprocessor mechanism for dec...

Derniers inventions, produits et services

2021 Invention Methods for compressing and decompressing texture tiles and apparatuses using the same. The inven...
2019 Invention Switch and data accessing method thereof. A data accessing method of a switch for transmitting da...
2018 Invention Chipset and server system using the same. A chipset implemented in a server node of a server syst...
2017 Invention Methods for accelerating hash-based compression and apparatuses using the same. The invention int...
Invention Processor with secure hash algorithm and digital signal processing method with secure hash algori...
Invention Chip package array, and chip package. A chip package array including a plurality of chip packages...
Invention Electronic structure, and electronic structure array. An electronic structure is provided with a ...
Invention Chip package process. A chip package process includes the following steps. A supporting structure...
Invention Electronic structure process. An electronic structure process includes the following steps. A red...
Invention Refreshing of dynamic random access memory. A schedule for refreshing a dynamic random access mem...
Invention Controller and control method for dynamic random access memory. A schedule for refreshing a dynam...
Invention Pre-driver and replica circuit and driver system with the same. A pre-driver includes a first inv...
Invention Processor with memory controller including dynamically programmable functional unit. A processor ...
Invention Processing system and method for data strobe signal. A processing system and method for a data st...
Invention Methods for calculating floating-point operands and apparatuses using the same. The invention int...
Invention Interpolator. An interpolator includes a first delay circuit, a second delay circuit, and a tunab...
Invention Methods for executing a computer instruction and apparatuses using the same. The invention introd...
2016 Invention Neural network unit with segmentable array width rotator. First/second memories hold rows of N we...
Invention Neural network unit with re-shapeable memory. 2 D bits and an extra bit. Each of N processing uni...
Invention Neural network unit with segmentable array width rotator and re-shapeable weight memory to match ...
Invention Neural network unit with mixed data and weight size computation capability. In a neural network u...
Invention Methods for prefetching data and apparatuses using the same. The invention introduces a method fo...
Invention Neural network unit that performs efficient 3-dimensional convolutions. A neural network unit con...
Invention Processor with memory array operable as either last level cache slice or neural network unit memo...
Invention Neural network unit with neural memory and array of neural processing units that collectively per...
Invention Processor with memory array operable as either cache memory or neural network unit memory. A proc...
Invention Neural network unit with memory layout to perform efficient 3-dimensional convolutions. A neural ...
Invention Processor with memory array operable as either victim cache or neural network unit memory. A proc...
Invention Methods for compressing and decompressing texture tiles and apparatuses using the same. The inve...
Invention Efficient random number generation for update events in multi-bank conditional branch predictor. ...
Invention Processor with instruction cache that performs zero clock retires. A method of operating a proces...
Invention Scannable data synchronizer. A scannable data synchronizer including an input circuit, first and ...
Invention Processor with instruction cache that performs zero clock retires. A method of retiring cache lin...
Invention Apparatuses and methods for trusted module execution. A computer system including a processor and...
Invention Apparatuses and methods for trusted module execution. Apparatuses and methods for trusted module ...
Invention System and method of automatic power control system and bias current control circuit. A bias-curr...
Invention Branch predictor that uses multiple byte offsets in hash of instruction block fetch address and b...
Invention Pipelined processor with multi-issue microcode unit having local branch decoder. A processor has ...
Invention Switch and data accessing method thereof. A switch for transmitting data packets between at least...
Invention Processing denormal numbers in fma hardware. A microprocessor includes FMA execution logic that d...
Invention Processor with improved alias queue and store collision detection to reduce memory violations and...
Invention System and method of merging partial write result during retire phase. A processor including a ph...
Invention Processor with slave free list that handles overflow of recycled physical registers and method of...
Invention Multi-threading processor and a scheduling method thereof. A processor includes an execution unit...
Invention Single ended-to-differential converter. A single-ended-to-differential converter for driving an L...
Invention System and method of determining memory ownership on cache line basis for detecting self-modifyin...
2014 Invention Cache memory budgeted by ways based on memory access type. A set associative cache memory, compri...