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2024
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Invention
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Device with embedded high-bandwidth, high-capacity memory using wafer bonding.
An electronic dev... |
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Invention
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3-dimensional nor memory array with very fine pitch: device and method.
A method to ease the fab... |
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Invention
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High capacity memory circuit with low effective latency.
A first circuit formed on a first semic... |
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Invention
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Three-dimensional nor memory array of thin-film ferroelectric memory transistors implementing par... |
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Invention
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Memory array of three-dimensional nor memory strings with word line select device. A memory circu... |
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Invention
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Memory array of three-dimensional nor memory strings with word line select device.
A memory circ... |
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P/S
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Semiconductor devices; Semiconductor chipsets; integrated circuits and integrated circuit modules |
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Invention
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Vertical thin-film transistor and application as bit-line connector for 3-dimensional memory arra... |
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Invention
|
Quasi-volatile memory device with a back-channel usage.
A quasi-volatile memory (QV memory) stac... |
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Invention
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Memory circuit, system and method for rapid retrieval of data sets.
A 3-dimensional array of NOR... |
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Invention
|
Fabrication method for a three-dimensional memory array of thin-film ferroelectric transistors us... |
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P/S
|
Semiconductor devices, namely, semiconductor memory chips and storage chips; Semiconductor chipse... |
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2023
|
Invention
|
Methods for forming multi-layer vertical nor-type memory string arrays. A method for forming 3-di... |
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Invention
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Methods for reducing disturb errors by refreshing data alongside programming or erase operations.... |
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Invention
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Three-dimensional memory string array of thin-film ferroelectric transistors. Thin-film Ferroelec... |
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Invention
|
Multi-gate nor flash thin-film transistor strings arranged in stacked horizontal active strips wi... |
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Invention
|
Fabrication method for a three-dimensional memory array of thin-film ferroelectric transistors fo... |
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Invention
|
Memory centric computational memory system.
A memory structure including three-dimensional NOR m... |
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Invention
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Dynamic random-access memory (dram) configured for block transfers and method thereof.
A method ... |
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Invention
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Wear-level control circuit for memory module.
A memory device includes: (a) one or more memory c... |
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Invention
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Memory controller for a high capacity memory circuit with large number of independently accessibl... |
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Invention
|
Three-dimensional vertical nor flash thin film transistor strings.
A memory structure, includes ... |
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Invention
|
Memory controller for a high capacity memory circuit using virtual bank addressing.
A memory sys... |
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|
Invention
|
Three-dimensional vertical nor flash thin-film transistor strings.
A memory structure, includes ... |
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P/S
|
Semiconductor devices; semiconductor chips; semiconductor chipsets; integrated circuits and integ... |
|
|
Invention
|
High capacity memory circuit with low effective latency. A first circuit formed on a first semico... |
|
|
Invention
|
Device with embedded high-bandwidth, high-capacity memory using wafer bonding. An electronic devi... |
|
|
Invention
|
Memory structure including high density three-dimensional nor memory strings of junctionless ferr... |
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Invention
|
Memory structure including three-dimensional nor memory strings and method of fabrication.
A mem... |
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P/S
|
Semiconductor devices; semiconductor chipsets; integrated circuits and integrated circuit modules |
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|
Invention
|
Memory device and method for manufacturing therefor.
A memory device includes a stacked body of ... |
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Invention
|
Memory structure including three-dimensional nor memory strings of junctionless ferroelectric sto... |
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2022
|
Invention
|
Quasi-volatile system-level memory. A high-capacity system memory may be built from both quasi-vo... |
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Invention
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Memory system implementing write abort operation for reduced read latency. A memory system includ... |
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Invention
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Memory system implementing write abort operation for reduced read latency.
A memory system inclu... |
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Invention
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Memory device including arrangement of independently and concurrently operable tiles of memory tr... |
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Invention
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Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film tra... |
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|
Invention
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Staggered word line architecture for reduced disturb in 3-dimensional nor memory arrays. A stagge... |
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Invention
|
Cool electron erasing in thin-film storage transistors.
A storage transistor has a tunnel dielec... |
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Invention
|
Memory centric system incorporating computational memory. Semiconductor memory systems and archit... |
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|
Invention
|
Memory structure including three-dimensional nor memory strings of junctionless ferroelectric mem... |
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|
Invention
|
Memory structure of three-dimensional nor memory strings of junctionless ferroelectric memory tra... |
|
|
Invention
|
Memory circuit, system and method for rapid retrieval of data sets. A 3-dimensional array of NOR ... |
|
|
Invention
|
Three-dimensional memory string array of thin-film ferroelectric transistors formed with an oxide... |
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|
Invention
|
Three-dimensional nor memory string arrays of thin-film ferroelectric transistors.
A memory stru... |
|
|
Invention
|
Three-dimensional nor memory string arrays of thin-film ferroelectric transistors. A memory struc... |
|
|
Invention
|
3-dimensional memory string array of thin-film ferroelectric transistors. Thin-film Ferroelectric... |
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2021
|
Invention
|
Process for a 3-dimensional array of horizontal nor-type memory strings. In the highly efficient ... |
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Invention
|
Methods for fabricating a 3-dimensional memory structure of nor memory strings. A process for bui... |
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2020
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P/S
|
Semiconductors, namely, semiconductor memory and storage
chips; interfaces for computers, mobile... |
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P/S
|
Semiconductors, namely, semiconductor memory and storage chips; Electronic display interfaces for... |
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2019
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P/S
|
Semiconductors, namely, memory and storage chips. Licensing of technology and intellectual proper... |
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P/S
|
Semiconductors, namely, semiconductor memory and storage chips |
