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2023
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Invention
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Bonded semiconductor die assembly containing through-stack via structures and methods for making ... |
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Invention
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Three-dimensional memory device including discrete charge storage elements and methods of forming... |
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Invention
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Modelling and prediction system with auto machine learning in the production of memory devices. ... |
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2022
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Invention
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Three dimensional memory device containing resonant tunneling barrier and high mobility channel a... |
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Invention
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Wafer surface chemical distribution sensing system and methods for operating the same. A CMP syst... |
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Invention
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Non-volatile memory with staggered ramp down at the end of pre-charging. In order to inhibit memo... |
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Invention
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Soft erase process during programming of non-volatile memory. Programming a plurality of non-vola... |
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Invention
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Three-dimensional memory device with word-line etch stop liners and method of making thereof. A t... |
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Invention
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Three-dimensional memory device with orthogonal memory opening and support opening arrays and met... |
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Invention
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High aspect ratio via fill process employing selective metal deposition and structures formed by ... |
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Invention
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Field effect transistors with reduced gate fringe area and method of making the same. A semicondu... |
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Invention
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Non-volatile memory with adjusted bit line voltage during verify. A control circuit connected to ... |
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2021
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Invention
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Memory device that is optimized for operation at different temperatures.
A plurality of memory p... |
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Invention
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Three-dimensional memory device and method of making the same using differential thinning of vert... |
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Invention
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Soft erase process during programming of non-volatile memory.
Programming a plurality of non-vol... |
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Invention
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Techniques for erasing the memory cells of edge word lines.
A method of erasing memory cells in ... |
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Invention
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Wafer surface chemical distribution sensing system and methods for operating the same.
A CMP sys... |
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Invention
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Field effect transistors with reduced gate fringe area and method of making the same.
A semicond... |
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Invention
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Non-volatile memory with staggered ramp down at the end of pre-charging.
In order to inhibit mem... |
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Invention
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Three-dimensional memory device with word-line etch stop liners and method of making thereof.
A ... |
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Invention
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Systems and methods for staggering read operation of sub-blocks.
A memory device with one or mor... |
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Invention
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Edge word line data retention improvement for memory apparatus with on-pitch semi-circle drain si... |
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Invention
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Proactive edge word line leak detection for memory apparatus with on-pitch semi-circle drain side... |
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Invention
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Adaptive semi-circle select gate bias.
A memory apparatus and method of operation are provided. ... |
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Invention
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Data conversion with data path circuits for use in double sense amp architecture with fractional ... |
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Invention
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Systems and methods for retaining inflight data during a power loss event.
Memory devices, or me... |
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Invention
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Pseudo multi-plane read methods and apparatus for non-volatile memory devices.
An apparatus incl... |
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Invention
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Systems and methods for dynamically sensing a memory block.
A memory device that dynamically adj... |
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Invention
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Computation of discrete fourier transformation (dft) using non-volatile memory arrays.
A non-vol... |
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Invention
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Transfer latch tiers.
Read and write circuitry, described herein, comprises data latches, each d... |
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Invention
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Positive tco voltage to dummy select transistors in 3d memory.
Technology is disclosed for apply... |
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Invention
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Three-dimensional memory device with discrete charge storage elements and methods for forming the... |
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Invention
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Non-volatile memory with adjusted bit line voltage during verify.
A control circuit connected to... |
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Invention
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Variable programming voltage step size control during programming of a memory device.
The memory... |
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Invention
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Smart re-use of parity buffer.
Technology is disclosed herein for efficient use of volatile memo... |
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Invention
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Double sense amp and fractional bit assignment in non-volatile memory structures.
A method for p... |
