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2020
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Invention
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Single process for liner and metal fill. After forming a contact opening in a dielectric material... |
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2019
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Invention
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Wimpy device by selective laser annealing. A device having co-integrated wimpy and nominal transi... |
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Invention
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Indium gallium arsenide metal oxide semiconductor field effect transistor having a low contact re... |
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Invention
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Fabrication of a vertical transistor with self-aligned bottom source/drain.
A method of forming ... |
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Invention
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Heat pipe and vapor chamber heat dissipation. The present invention provides a heat dissipation d... |
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Invention
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Self-forming spacers using oxidation. A method of forming a self-forming spacer using oxidation. ... |
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Invention
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Well and punch through stopper formation using conformal doping. A method for doping fins include... |
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Invention
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Patterned gate dielectrics for iii-v-based cmos circuits.
Semiconductor devices and methods of m... |
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Invention
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Removal of trilayer resist without damage to underlying structure. A method for semiconductor pro... |
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Invention
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Dual silicide liner flow for enabling low contact resistance. A method for fabricating a semicond... |
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Invention
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Local wiring in between stacked devices.
Semiconductor devices and methods are provided to fabri... |
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Invention
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Vertical transport fets having a gradient threshold voltage. Vertical transport field effect tran... |
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Invention
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Conductive contacts in semiconductor on insulator substrate. A semiconductor device includes a ga... |
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Invention
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Porous silicon relaxation medium for dislocation free cmos devices. A method for forming CMOS dev... |
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Invention
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Techniques for vertical fet gate length control. Techniques for VFET gate length control are prov... |
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Invention
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Package assembly for thin wafer shipping and method of use. A package assembly for thin wafer shi... |
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Invention
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Semiconductor structure with integrated passive structures.
A metal-oxide-semiconductor field-ef... |
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Invention
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Semiconductor devices with sidewall spacers of equal thickness.
Semiconductor structures with di... |
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Invention
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Enhancement of iso-via reliability. A semiconductor structure and a process for forming a semicon... |
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Invention
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Forming on-chip metal-insulator-semiconductor capacitor.
A method is presented for forming a sem... |
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Invention
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Semiconductor device with self-aligned carbon nanotube gate. A method of forming a semiconductor ... |
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Invention
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Charge carrier transport facilitated by strain.
A semiconductor structure and formation thereof.... |
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Invention
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Semiconductor structures having low resistance paths throughout a wafer.
A semiconductor structu... |
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Invention
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Beol embedded high density vertical resistor structure. Embedded resistors which have tunable res... |
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Invention
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Self-limiting fin spike removal. Provided is a method for forming a semiconductor structure. In e... |
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Invention
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Sacrificial cap for forming semiconductor contact. A method for forming a semiconductor device in... |
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Invention
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Forming a combination of long channel devices and vertical transport fin field effect transistors... |
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Invention
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Transistor with asymmetric spacers. A field-effect transistor device including an asymmetric spac... |
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Invention
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Lateral bipolar junction transistor with abrupt junction and compound buried oxide.
A lateral bi... |
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Invention
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Electronic devices having spiral conductive structures. Techniques for generating enhanced induct... |
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Invention
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Conformal capacitor structure formed by a single process. A capacitor structure is provided that ... |
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Invention
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Field effect transistor devices having gate contacts formed in active region overlapping source/d... |
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Invention
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Vertical field effect transistor (vfet) programmable complementary metal oxide semiconductor inve... |
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Invention
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Integrated gate driver. A method is presented for forming a semiconductor device. The method may ... |
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Invention
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Self-aligned trench metal-alloying for iii-v nfets.
After forming source/drain contact openings ... |
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Invention
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High density programmable e-fuse co-integrated with vertical fets. A method for integrating verti... |
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Invention
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Wafer stacking for integrated circuit manufacturing.
A method of manufacturing integrated device... |
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Invention
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Implementing a hybrid finfet device and nanowire device utilizing selective sgoi.
A silicon-on-i... |
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Invention
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Simultaneously fabricating a high voltage transistor and a finfet. Forming a semiconductor layer ... |
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Invention
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Spacer for trench epitaxial structures. The disclosure relates to a structure and methods of form... |
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Invention
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Substrate with a fin region comprising a stepped height structure.
A method of forming a semicon... |
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Invention
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Inverse tone direct print euv lithography enabled by selective material deposition.
Various meth... |
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Invention
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Transistor with asymmetric source/drain overlap.
An asymmetric field-effect transistor having di... |
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Invention
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Transistor with asymmetric source/drain overlap. An asymmetric field-effect transistor having dif... |
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Invention
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Tunnel transistor. A tunnel field-effect transistor having source and drain contacts made from di... |
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2018
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Invention
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Structure and method for improving access resistance in u-channel etsoi. The present invention pr... |
