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2023
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Invention
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Doped polar layers and semiconductor device incorporating same.
The disclosed technology general... |
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Invention
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Integration of ferroelectric memory devices having stacked electrodes with transistors.
Approach... |
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Invention
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Method of forming 3d stacked compute and memory with copper pillars.
Described is a packaging te... |
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2022
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Invention
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Manganese or scandium doped multi-element non-linear polar material gain memory bit-cell. A high-... |
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Invention
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Write disturb mitigation for non-linear polar material based multi-capacitor bit-cell.
A disturb... |
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Invention
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Majority or minority logic gate with non-linear input capacitors without reset. A class of comple... |
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Invention
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Multi-element gain memory bit-cell having stacked and folded planar memory elements with and with... |
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Invention
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Multi-element ferroelectric gain memory bit-cell having stacked and folded non-planar capacitors.... |
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Invention
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Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors. A c... |
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Invention
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Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors with... |
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Invention
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Computer-aided design tool for inverter minimization. A computer-aided design (CAD) tool is provi... |
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Invention
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Asynchronous completion tree circuit using multi-function threshold gate with input based adaptiv... |
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Invention
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Asynchronous consensus circuit with stacked ferroelectric planar capacitors. Asynchronous circuit... |
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Invention
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Asynchronous validity tree circuit using multi-function threshold gate with input based adaptive ... |
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Invention
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Asynchronous consensus circuit with stacked linear or paraelectric non-planar capacitors. Asynchr... |
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Invention
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Asynchronous consensus circuit using multi-function threshold gate with input based adaptive thre... |
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2021
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Invention
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Asynchronous circuit with multi-input threshold gate logic and 1-input threshold gate. 2 (e.g., 2... |
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Invention
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Integrated trench and via electrode for memory device applications and methods of fabrication. A ... |
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Invention
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Multi-level hydrogen barrier layers for memory applications. A device includes, in a first region... |
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Invention
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Integrated trench and via electrode for memory device applications. A device includes, in a first... |
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Invention
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Conductive and insulative hydrogen barrier layer for memory devices. A device includes, in a firs... |
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Invention
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Dual hydrogen barrier layer for memory devices integrated with low density film for logic structu... |
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Invention
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High density dual encapsulation materials for capacitors and methods of fabrication. A device inc... |
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Invention
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Integrated via and bridge electrodes for memory array applications and methods of fabrication. A ... |
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Invention
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Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic stru... |
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Invention
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Reading scheme for 1tnc ferroelectric memory bit-cell with plate-line parallel to bit-line and wi... |
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Invention
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Writing scheme for multi-element gain ferroelectric memory bit-cell with plate-lines parallel to ... |
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Invention
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Computer-aided design tool for minimum gate count initialization. A computer-aided design (CAD) t... |
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Invention
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Common mode compensation for non-linear polar material based differential memory bit-cell having ... |
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Invention
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Common mode compensation for differential multi-element non-linear polar material based gain memo... |
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Invention
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Method of forming a stack of planar capacitors including capacitors with non-linear polar materia... |
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Invention
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Computer-aided design tool for gate pruning. A computer-aided design (CAD) tool is provided for l... |
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Invention
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Low power non-linear polar material based threshold logic gate multiplier. A new class of multipl... |
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Invention
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Computer-aided design tool for wide-input logic initialization. A computer-aided design (CAD) too... |
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Invention
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Method and apparatus for cycle-by-cycle clock gating of ferroelectric or paraelectric logic and c... |
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Invention
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Computer-aided design tool for circuit logic initialization. A computer-aided design (CAD) tool i... |
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Invention
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Non-linear polar material based low power multiplier with nor and nand gate based reset mechanism... |
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Invention
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Computer-aided design tool for majority or minority inverter graph synthesis. A computer-aided de... |
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Invention
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Method and apparatus to process an instruction for a distributed logic having tightly coupled acc... |
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Invention
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Method to segregate logic and memory into separate dies for thermal management in a multi-dimensi... |
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Invention
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High density ferroelectric random access memory (feram) devices and methods of fabrication. Non l... |
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Invention
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Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensi... |
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Invention
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Apparatus and method for endurance of non-volatile memory banks via multi-level wear leveling. En... |
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Invention
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Apparatus and method for endurance of non-volatile memory banks via wear leveling in a round robi... |
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Invention
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Process integration flow for embedded memory with multi-pocket masks for decoupling processing of... |
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Invention
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Embedded memory with encapsulation layer adjacent to a memory stack. A process integration and pa... |
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Invention
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Apparatus and method for endurance of non-volatile memory banks via outlier compensation. Enduran... |
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Invention
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High-density low voltage ferroelectric differential memory bit-cell with shared plate-line.
Desc... |
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Invention
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Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging. A ferroelectric ... |
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2020
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Invention
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Low latency and high bandwidth artificial intelligence processor. Matrix multiplication process i... |
