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2023
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P/S
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Accelerated data processors; accelerated video processors; downloadable audio and video graphics ... |
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Invention
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Distributed geometry.
Systems, apparatuses, and methods for performing geometry work in parallel... |
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Invention
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Compiler directed fine grained power management.
Systems, methods, devices, and computer-impleme... |
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Invention
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Accelerating neural networks with one shot skip layer pruning.
Systems, methods, and devices for... |
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Invention
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Alternative protocol over physical layer.
A link controller includes a Peripheral Component Inte... |
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Invention
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Platform power manager for rack level power and thermal constraints.
Platform power management i... |
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Invention
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Memory calibration system and method.
A method for performing stutter of dynamic random access m... |
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Invention
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Pipeline delay elimination with parallel two level primitive batch binning. A technique for rende... |
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Invention
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Device and method for efficient transitioning to and from reduced power state.
A processing devi... |
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Invention
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Dynamic cache bypass for power savings. A technique for operating a cache is disclosed. The techn... |
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Invention
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Method and apparatus for a page-local delta-based prefetcher.
A method includes recording a firs... |
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P/S
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Downloadable computer software for media and design content creation; downloadable computer softw... |
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Invention
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Suppressing cache line modification.
Disclosed is a system and method for use in a cache for sup... |
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P/S
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Semiconductor devices; semiconductor chips; semiconductors; integrated circuits; integrated circu... |
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Invention
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Real time workload-based system adjustment. Real time workload-based system adjustment is describ... |
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Invention
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Method and apparatus for controlling cache line storage in cache memory.
A method and apparatus ... |
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Invention
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Method and apparatus of integrating memory stacks.
An apparatus and method for performing memory... |
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Invention
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Cross-chiplet performance data streaming. Methods and systems are disclosed for cross-chiplet per... |
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Invention
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Core activation and deactivation for a multi-core processor. Core activation and deactivation for... |
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P/S
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semiconductor chips; semiconductor devices; semiconductors; accelerated data processors; accelera... |
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2022
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Invention
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Pipeline delay elimination with parallel two level primitive batch binning.
A technique for rend... |
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P/S
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Semiconductors; Integrated Circuits; multi-core heterogeneous compute platforms; field programmab... |
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P/S
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Semiconductors; Integrated Circuits; multi-core
heterogeneous compute platforms; field programma... |
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P/S
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Integrated circuits; programmable integrated circuits; integrated circuits in the nature of integ... |
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Invention
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Mixed signal feedback design for verification.
Techniques for implementing a mixed signal feedba... |
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Invention
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Method and apparatus for performing high speed parallel locally order clustering for a bounding v... |
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Invention
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Write hardware training acceleration. A memory includes a link training circuit with a pseudo-ran... |
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Invention
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Split-scan sense amplifier flip-flop. A method includes generating a functional clock signal, a s... |
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P/S
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Semiconductors; Integrated Circuits; multi-core heterogeneous computer hardware platforms; field ... |
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Invention
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Sharing package pins in a multi-chip module (mcm).
A semiconductor package includes multiple die... |
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Invention
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Approach for skipping near-memory processing commands.
An approach is provided for skipping, i.e... |
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Invention
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Performing operations for handling data using processor in memory circuitry in a high bandwidth m... |
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Invention
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Real time profile switching for memory overclocking.
Profile switching for memory overclocking i... |
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Invention
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Real time workload-based system adjustment.
Real time workload-based system adjustment is descri... |
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Invention
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Identifying memory system sensitivity to timing parameters.
Various timing parameter values for ... |
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Invention
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Dynamic cache bypass for power savings.
A technique for operating a cache is disclosed. The tech... |
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P/S
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Integrated circuits, namely, graphics, video and multimedia integrated circuits; integrated circu... |
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Invention
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Memory bit cell with homogeneous layout pattern of base layers for high density memory macros.
A... |
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Invention
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Design of an integrated circuit using multiple and different process corners.
A system and metho... |
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Invention
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Reducing probe filter accesses for processing in memory requests.
Systems, apparatuses, and meth... |
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Invention
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Memory encryption.
A memory controller includes encryption circuits for encrypting write data to... |
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Invention
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Cross-chiplet performance data streaming.
Methods and systems are disclosed for cross-chiplet pe... |
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Invention
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Detecting personal-space violations in artificial intelligence based non-player characters.
Syst... |
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Invention
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Object distance estimation with camera lens focus calibration.
Systems, apparatuses, and methods... |
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Invention
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Using a hardware-based controller for power state management.
Methods and systems are disclosed ... |
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Invention
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Managing large tage histories.
A tagged geometric (TAGE) branch predictor for managing large TAG... |
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Invention
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Enforcing consistency across redundant tagged geometric (tage) branch histories.
Enforcing consi... |
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Invention
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Dynamic register renaming in hardware to reduce bank conflicts in parallel processor architecture... |
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Invention
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Fusing no-op (nop) instructions.
A method of fusing no-op (NOP) instructions includes receiving ... |
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Invention
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Hybrid parallelized tagged geometric (tage) branch prediction.
Hybrid parallelized tagged geomet... |
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Invention
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Core activation and deactivation for a multi-core processor.
Core activation and deactivation fo... |
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Invention
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Lid carveouts for processor lighting.
Package lids with carveouts configured to expose lights di... |
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Invention
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User configurable hardware settings for overclocking.
User configurable hardware settings for ov... |
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Invention
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Lid carveouts for processor connection and alignment.
Package lids with carveouts configured for... |
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Invention
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Electronic device including dies and an interconnect coupled to the dies and processes of forming... |
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Invention
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Error-tolerant memory system for machine learning systems.
A memory system uses error detection ... |
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Invention
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Page swapping to protect memory devices.
A page swapping memory protection system tracks accesse... |
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P/S
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Integrated circuit chip sets; cards containing integrated circuits; integrated circuit chips; sem... |
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P/S
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Integrated circuit chip sets; cards containing integrated circuits; integrated circuit chips; s... |
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P/S
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Downloadable computer software development tools and utilities; downloadable open source software... |
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2021
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P/S
|
Accelerated data processors; accelerated video processors; audio and video graphics for real time... |
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P/S
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Downloadable computer software development tools and downloadable software utilities for high-res... |
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P/S
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Downloadable computer software, namely, proprietary implementation of software stack and applicat... |
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P/S
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Semiconductor chips; semiconductor devices; semiconductors; accelerated data processors; accelera... |
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P/S
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Semiconductor devices; semiconductor chips; semiconductors; computer hardware; microprocessor mod... |
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P/S
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Platform as a service (PAAS) featuring computer software platforms for purchasing computing power... |
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P/S
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Computer servers; computer hardware for use in proxying and managing communications between local... |
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P/S
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Computer servers; computer hardware for use in managing network-enabled devices and Internet-of-T... |
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P/S
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Downloadable computer software, namely, being a proprietary implementation of downloadable softwa... |
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2020
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P/S
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Computer hardware; Recorded computer software; Downloadable computer software; Recorded computer ... |
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2019
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Invention
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Protection against branch target buffer poisoning by a management layer. A processing system incl... |
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Invention
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Performing store-to-load forwarding of a return address for a return instruction. A load/store un... |
