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2023
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P/S
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Accelerated data processors; accelerated video processors; downloadable audio and video graphics ... |
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P/S
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Downloadable computer software for media and design content creation; downloadable computer softw... |
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P/S
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Semiconductor devices; semiconductor chips; semiconductors; integrated circuits; integrated circu... |
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Invention
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Compression aware prefetch.
Methods, devices, and systems for prefetching data. First data is lo... |
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Invention
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Flexible dictionary sharing for compressed caches.
Systems, apparatuses, and methods for impleme... |
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P/S
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semiconductor chips; semiconductor devices; semiconductors; accelerated data processors; accelera... |
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Invention
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Method and apparatus for providing wear leveling.
Exemplary embodiments provide wear spreading a... |
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Invention
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Dynamic graphical processing unit register allocation.
Systems, apparatuses, and methods for dyn... |
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Invention
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Method and apparatus for providing thermal wear leveling.
Exemplary embodiments provide thermal ... |
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Invention
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Low latency wireless virtual reality systems and methods.
Virtual Reality (VR) processing device... |
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2022
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Invention
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Gaming super resolution.
A processing device is provided which includes memory and a processor. ... |
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Invention
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Error recovery for non-volatile memory modules.
A memory controller includes a command queue, a ... |
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P/S
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Semiconductors; Integrated Circuits; multi-core heterogeneous compute platforms; field programmab... |
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P/S
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Semiconductors; Integrated Circuits; multi-core
heterogeneous compute platforms; field programma... |
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P/S
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Integrated circuits; programmable integrated circuits; integrated circuits in the nature of integ... |
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Invention
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Hierarchical asymmetric core attribute detection. Within a processing system, thread count asymme... |
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Invention
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Computer processing devices with dynamic shared cache line copy retention policy selection. Syste... |
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Invention
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Error pin training with graphics ddr memory. A receiver is trained for receiving a signal over a ... |
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Invention
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Hardware management of direct memory access commands. A method for hardware management of DMA tra... |
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Invention
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Performance management during power supply voltage droop. A method for controlling a data process... |
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Invention
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Compensation methods for voltage and temperature (vt) drift of memory interfaces. A data processi... |
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Invention
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Throttling hull shaders based on tessellation factors in a graphics pipeline.
A processing syste... |
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Invention
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Reducing latency in highly scalable hpc applications via accelerator-resident runtime management.... |
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Invention
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Using chiplet-level performance information for configuring chiplets in a processor. A processor ... |
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Invention
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Three-dimensional semiconductor package having a stacked passive device. A three-dimensional semi... |
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Invention
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Cache line coherence state upgrade. Techniques for performing cache operations are provided. The ... |
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Invention
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History-based selective cache line invalidation requests. Techniques for performing cache operati... |
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Invention
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Cache line coherence state downgrade. Techniques for performing cache operations are provided. Th... |
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Invention
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Combination scheme for baseline wander, direct current level shifting, and receiver linear equali... |
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Invention
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Memory system with region-specific memory access scheduling.
An integrated circuit device includ... |
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Invention
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Error pin training with graphics ddr memory.
A receiver is trained for receiving a signal over a... |
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Invention
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Compensation methods for voltage and temperature (vt) drift of memory interfaces.
A data process... |
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Invention
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Combining quantum states of qubits on a quantum processor.
An electronic device includes a quant... |
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P/S
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Semiconductors; Integrated Circuits; multi-core heterogeneous computer hardware platforms; field ... |
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P/S
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Integrated circuits, namely, graphics, video and multimedia integrated circuits; integrated circu... |
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P/S
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Integrated circuit chip sets; cards containing integrated circuits; integrated circuit chips; sem... |
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P/S
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Integrated circuit chip sets; cards containing integrated circuits; integrated circuit chips; s... |
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P/S
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integrated circuit chip sets; cards containing integrated circuits; integrated circuit chips; sem... |
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P/S
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Downloadable computer software development tools and utilities; downloadable open source software... |
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2021
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Invention
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Secure testing mode.
A technique for operating a processing device is disclosed. The method incl... |
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Invention
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Repairable latch array. An integrated circuit includes a latch array including a plurality of lat... |
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Invention
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Data as compute.
A method includes storing a function representing a set of data elements stored... |
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Invention
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Hierarchical asymmetric core attribute detection.
Within a processing system, thread count asymm... |
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Invention
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Job scheduling using reinforcement learning.
Systems, methods, and techniques utilize reinforcem... |
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Invention
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Semiconductor chip having stepped conductive pillars.
In an implementation, a semiconductor chip... |
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Invention
|
Chiplet-level performance information for configuring chiplets in a processor.
A processor inclu... |
|
|
Invention
|
Computer processing devices with dynamic shared cache line copy retention policy selection.
Syst... |
|
|
Invention
|
Performance management during power supply voltage droop.
A method for controlling a data proces... |
|
|
Invention
|
Hardware management of direct memory access commands.
A method for hardware management of DMA tr... |
|
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Invention
|
Clock frequency divider circuit.
A system and method for efficiently generating clock signals ar... |
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Invention
|
Cache line coherence state downgrade.
Techniques for performing cache operations are provided. T... |
|
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Invention
|
Cache line coherence state upgrade.
Techniques for performing cache operations are provided. The... |
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Invention
|
Inverse performance driven program analysis.
An approach is provided for a program profiler to i... |
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Invention
|
History-based selective cache line invalidation requests.
Techniques for performing cache operat... |
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Invention
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Error detection at layers of a neural network.
A processing system performs error detection at e... |
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Invention
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Providing data from portions of a memory to processors in memory (pims) in an electronic device. ... |
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Invention
|
Three-dimensional semiconductor package having a stacked passive device.
A three-dimensional sem... |
|
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Invention
|
High voltage tolerant capacitors.
A system and method for fabricating on-die metal-insulator-met... |
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Invention
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Dynamic random-access memory (dram) training acceleration.
A method for performing read training... |
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Invention
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On-die power supply monitor design.
A system and method for efficiently measuring on-die power s... |
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Invention
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Platform resource selction for upscaler operations.
Compound processing of an upscaler operation... |
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P/S
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Accelerated data processors; accelerated video processors; audio and video graphics for real time... |
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P/S
|
Downloadable computer software development tools and downloadable software utilities for high-res... |
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P/S
|
Downloadable computer software, namely, proprietary implementation of software stack and applicat... |
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P/S
|
Semiconductor chips; semiconductor devices; semiconductors; accelerated data processors; accelera... |
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P/S
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Semiconductor devices; semiconductor chips; semiconductors; computer hardware; microprocessor mod... |
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P/S
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Platform as a service (PAAS) featuring computer software platforms for purchasing computing power... |
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P/S
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Computer servers; computer hardware for use in proxying and managing communications between local... |
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P/S
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Computer servers; computer hardware for use in managing network-enabled devices and Internet-of-T... |
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P/S
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Downloadable computer software, namely, being a proprietary implementation of downloadable softwa... |
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2020
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P/S
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Computer hardware; Recorded computer software; Downloadable computer software; Recorded computer ... |
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P/S
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Computer hardware; recorded computer software; downloadable computer software; recorded computer ... |
